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ad_ip_jesd204_tpl_dac: Fix PN generator reset state 

Only the N (where N is the size of the PN sequence) MSB bits of the reset
state of the PN generator should be set to 1. All other bits should be
initialized following the PN generator sequence.

Otherwise the first set of samples contain an incorrect PN sequence.

This does not increase the complexity of the PN generator, all reset values
are still constant.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2018-08-08 10:17:06 +02:00 committed by Lars-Peter Clausen
parent 5af80e79b3
commit 0be4a5c10e
1 changed files with 10 additions and 2 deletions
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12
library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_channel.v
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@ -71,18 +71,26 @@ module ad_ip_jesd204_tpl_dac_channel #(
wire [DW:0] pn15; wire [DW:0] pn15;
wire [DW+15:0] pn15_full_state; wire [DW+15:0] pn15_full_state;
wire [DW:0] dac_pn15_data_s; wire [DW:0] dac_pn15_data_s;
wire [DW:0] pn15_reset;
wire [DW:0] pn7; wire [DW:0] pn7;
wire [DW+7:0] pn7_full_state; wire [DW+7:0] pn7_full_state;
wire [DW:0] dac_pn7_data_s; wire [DW:0] dac_pn7_data_s;
wire [DW:0] pn7_reset;
// PN15 x^15 + x^14 + 1 // PN15 x^15 + x^14 + 1
assign pn15 = pn15_full_state[15+:DW+1] ^ pn15_full_state[14+:DW+1]; assign pn15 = pn15_full_state[15+:DW+1] ^ pn15_full_state[14+:DW+1];
assign pn15_full_state = {dac_pn15_data[14:0],pn15}; assign pn15_full_state = {dac_pn15_data[14:0],pn15};
assign pn15_reset[DW-:15] = {15{1'b1}};
assign pn15_reset[DW-15:0] = pn15_reset[DW:15] ^ pn15_reset[DW-1:14];
// PN7 x^7 + x^6 + 1 // PN7 x^7 + x^6 + 1
assign pn7 = pn7_full_state[7+:DW+1] ^ pn7_full_state[6+:DW+1]; assign pn7 = pn7_full_state[7+:DW+1] ^ pn7_full_state[6+:DW+1];
assign pn7_full_state = {dac_pn7_data[6:0],pn7}; assign pn7_full_state = {dac_pn7_data[6:0],pn7};
assign pn7_reset[DW-:7] = {7{1'b1}};
assign pn7_reset[DW-7:0] = pn7_reset[DW:7] ^ pn7_reset[DW-1:6];
generate generate
genvar i; genvar i;
for (i = 0; i < DATA_PATH_WIDTH; i = i + 1) begin: g_pn_swizzle for (i = 0; i < DATA_PATH_WIDTH; i = i + 1) begin: g_pn_swizzle
@ -114,8 +122,8 @@ module ad_ip_jesd204_tpl_dac_channel #(
always @(posedge clk) begin always @(posedge clk) begin
if (dac_data_sync == 1'b1) begin if (dac_data_sync == 1'b1) begin
dac_pn15_data <= {DW+1{1'd1}}; dac_pn15_data <= pn15_reset;
dac_pn7_data <= {DW+1{1'd1}}; dac_pn7_data <= pn7_reset;
end else begin end else begin
dac_pn15_data <= pn15; dac_pn15_data <= pn15;
dac_pn7_data <= pn7; dac_pn7_data <= pn7;