diff --git a/library/ad463x_data_capture/ad463x_data_capture.v b/library/ad463x_data_capture/ad463x_data_capture.v
index 6a857c009..72191ddb0 100644
--- a/library/ad463x_data_capture/ad463x_data_capture.v
+++ b/library/ad463x_data_capture/ad463x_data_capture.v
@@ -44,7 +44,6 @@ module ad463x_data_capture #(
   parameter NUM_OF_LANES = 2,
   parameter DATA_WIDTH = 32
 ) (
-
   input                                     clk,          // core clock of the SPIE
   input                                     csn,          // CSN (chip select)
   input                                     echo_sclk,    // BUSY/SCLKOUT
@@ -53,82 +52,80 @@ module ad463x_data_capture #(
   output [(NUM_OF_LANES * DATA_WIDTH)-1:0]  m_axis_data,  // parallel data lines
   output                                    m_axis_valid, // data validation
   input                                     m_axis_ready  // NOTE: back pressure is ignored
-
 );
 
-reg csn_d;
+  reg csn_d;
 
-wire reset;
+  wire reset;
 
-always @(posedge clk) begin
-  csn_d <= csn;
-end
+  always @(posedge clk) begin
+    csn_d <= csn;
+  end
 
-// negative edge resets the shift registers
-assign reset = ~csn & csn_d;
+  // negative edge resets the shift registers
+  assign reset = ~csn & csn_d;
 
-// CSN positive edge validates the output data
-// WARNING: there isn't any buffering for data, if the sink module is not
-// ready, the data will be discarded
-assign m_axis_valid = csn & ~csn_d & m_axis_ready;
+  // CSN positive edge validates the output data
+  // WARNING: there isn't any buffering for data, if the sink module is not
+  // ready, the data will be discarded
+  assign m_axis_valid = csn & ~csn_d & m_axis_ready;
 
-genvar i, j;
-generate
-if (DDR_EN) // Double Data Rate mode
-begin
+  genvar i, j;
+  generate
+  if (DDR_EN) // Double Data Rate mode
+  begin
 
-  for (i=0; i<NUM_OF_LANES; i=i+1) begin
+    for (i=0; i<NUM_OF_LANES; i=i+1) begin
 
-    reg [DATA_WIDTH-1:0] data_shift_p;
-    reg [DATA_WIDTH-1:0] data_shift_n;
+      reg [DATA_WIDTH-1:0] data_shift_p;
+      reg [DATA_WIDTH-1:0] data_shift_n;
 
-    // shift register for positive edge
-    always @(negedge echo_sclk or posedge reset) begin
-      if (reset) begin
-        data_shift_n <= 0;
-      end else begin
-        data_shift_n <= {data_shift_n, data_in[i]};
+      // shift register for positive edge
+      always @(negedge echo_sclk or posedge reset) begin
+        if (reset) begin
+          data_shift_n <= 0;
+        end else begin
+          data_shift_n <= {data_shift_n, data_in[i]};
+        end
       end
-    end
 
-    // shift register for positive edge
-    always @(posedge echo_sclk or posedge reset) begin
-      if (reset) begin
-        data_shift_p <= 0;
-      end else begin
-        data_shift_p <= {data_shift_p, data_in[i]};
+      // shift register for positive edge
+      always @(posedge echo_sclk or posedge reset) begin
+        if (reset) begin
+          data_shift_p <= 0;
+        end else begin
+          data_shift_p <= {data_shift_p, data_in[i]};
+        end
       end
-    end
 
-    // DDR output logic - only the first 16 bits are forwarded
-    for (j=0; j<DATA_WIDTH/2; j=j+1) begin
-      assign m_axis_data[DATA_WIDTH*i+(j*2)+:2] = {data_shift_p[j], data_shift_n[j]};
-    end
-
-  end /* for loop */
-
-end else begin  // Single Data Rate mode
-
-  for (i=0; i<NUM_OF_LANES; i=i+1) begin
-
-    reg [DATA_WIDTH-1:0] data_shift_n;
-
-    // shift register for positive edge
-    always @(negedge echo_sclk or posedge reset) begin
-      if (reset) begin
-        data_shift_n <= 0;
-      end else begin
-        data_shift_n <= {data_shift_n, data_in[i]};
+      // DDR output logic - only the first 16 bits are forwarded
+      for (j=0; j<DATA_WIDTH/2; j=j+1) begin
+        assign m_axis_data[DATA_WIDTH*i+(j*2)+:2] = {data_shift_p[j], data_shift_n[j]};
       end
-    end
 
-    // SDR output logic
-    assign m_axis_data[DATA_WIDTH*i+:DATA_WIDTH] = data_shift_n;
+    end /* for loop */
 
-  end /* for loop */
+  end else begin  // Single Data Rate mode
 
-end
-endgenerate
+    for (i=0; i<NUM_OF_LANES; i=i+1) begin
+
+      reg [DATA_WIDTH-1:0] data_shift_n;
+
+      // shift register for positive edge
+      always @(negedge echo_sclk or posedge reset) begin
+        if (reset) begin
+          data_shift_n <= 0;
+        end else begin
+          data_shift_n <= {data_shift_n, data_in[i]};
+        end
+      end
+
+      // SDR output logic
+      assign m_axis_data[DATA_WIDTH*i+:DATA_WIDTH] = data_shift_n;
+
+    end /* for loop */
+
+  end
+  endgenerate
 
 endmodule
-
diff --git a/library/axi_ad5766/axi_ad5766.v b/library/axi_ad5766/axi_ad5766.v
index f89ee47d0..652ca347d 100644
--- a/library/axi_ad5766/axi_ad5766.v
+++ b/library/axi_ad5766/axi_ad5766.v
@@ -43,7 +43,8 @@ module axi_ad5766 #(
   parameter   DEV_PACKAGE = 0,
   parameter   ASYNC_SPI_CLK = 0,
   parameter   CMD_MEM_ADDRESS_WIDTH = 4,
-  parameter   SDO_MEM_ADDRESS_WIDTH = 4)(
+  parameter   SDO_MEM_ADDRESS_WIDTH = 4
+) (
 
   // Slave AXI interface
 
@@ -107,7 +108,8 @@ module axi_ad5766 #(
 
   input                                 ctrl_enable,
   output                                ctrl_enabled,
-  input                                 ctrl_mem_reset);
+  input                                 ctrl_mem_reset
+);
 
   // internal wires
 
@@ -192,35 +194,32 @@ module axi_ad5766 #(
         spi_enabled <= spi_enable_s | spi_active;
     end
 
-    sync_bits # (
-        .NUM_OF_BITS(1),
-        .ASYNC_CLK(1)
+    sync_bits #(
+      .NUM_OF_BITS(1),
+      .ASYNC_CLK(1)
     ) i_sync_enable (
-        .in_bits(ctrl_do_enable),
-        .out_clk(spi_clk),
-        .out_resetn(1'b1),
-        .out_bits(spi_enable_s)
-    );
+      .in_bits(ctrl_do_enable),
+      .out_clk(spi_clk),
+      .out_resetn(1'b1),
+      .out_bits(spi_enable_s));
 
-    sync_bits # (
-        .NUM_OF_BITS(1),
-        .ASYNC_CLK(1)
+    sync_bits #(
+      .NUM_OF_BITS(1),
+      .ASYNC_CLK(1)
     ) i_sync_enabled (
-        .in_bits(spi_enabled),
-        .out_clk(ctrl_clk),
-        .out_resetn(1'b1),
-        .out_bits(ctrl_is_enabled)
-    );
+      .in_bits(spi_enabled),
+      .out_clk(ctrl_clk),
+      .out_resetn(1'b1),
+      .out_bits(ctrl_is_enabled));
 
-    sync_bits # (
-        .NUM_OF_BITS(1),
-        .ASYNC_CLK(1)
+    sync_bits #(
+      .NUM_OF_BITS(1),
+      .ASYNC_CLK(1)
     ) i_sync_mem_reset (
-        .in_bits(ctrl_mem_reset),
-        .out_clk(spi_clk),
-        .out_resetn(1'b1),
-        .out_bits(spi_mem_reset_s)
-    );
+      .in_bits(ctrl_mem_reset),
+      .out_clk(spi_clk),
+      .out_resetn(1'b1),
+      .out_bits(spi_mem_reset_s));
 
   end else begin
     assign spi_enable_s = ctrl_enable;
@@ -299,14 +298,15 @@ module axi_ad5766 #(
   // rate controller
 
   assign dac_rstn_s = ~dac_rst_s;
-  util_pulse_gen #(.PULSE_WIDTH(1)) i_trigger_gen (
+  util_pulse_gen #(
+    .PULSE_WIDTH(1)
+  ) i_trigger_gen (
     .clk (spi_clk),
     .rstn (dac_rstn_s),
     .pulse_width (1'b1),
     .pulse_period (pulse_period_s),
     .load_config (1'b1),
-    .pulse (trigger_s)
-  );
+    .pulse (trigger_s));
 
   // offset of the sequencer registers are 8'h40
 
@@ -327,8 +327,8 @@ module axi_ad5766 #(
   assign pulse_period_s = {16'h0, dac_datarate_s};
 
   up_ad5766_sequencer #(
-    .SEQ_ID(4))
-  i_sequencer (
+    .SEQ_ID(4)
+  ) i_sequencer (
     .sequence_clk (spi_clk),
     .sequence_rst (spi_mem_reset_s),
     .sequence_req (dma_valid),
@@ -397,7 +397,6 @@ module axi_ad5766 #(
     .up_rdata (up_rdata_s[0]),
     .up_rack (up_rack_s[0]));
 
-
   // AXI wrapper
 
   up_axi #(
diff --git a/library/axi_ad5766/up_ad5766_sequencer.v b/library/axi_ad5766/up_ad5766_sequencer.v
index 97ecb9adf..4fef14560 100644
--- a/library/axi_ad5766/up_ad5766_sequencer.v
+++ b/library/axi_ad5766/up_ad5766_sequencer.v
@@ -37,8 +37,8 @@
 
 module up_ad5766_sequencer #(
 
-  parameter   SEQ_ID = 0)(
-
+  parameter   SEQ_ID = 0
+) (
   input                 sequence_clk,
   input                 sequence_rst,
   input                 sequence_req,
@@ -54,8 +54,8 @@ module up_ad5766_sequencer #(
   input                 up_rreq,
   input         [13:0]  up_raddr,
   output  reg   [31:0]  up_rdata,
-  output  reg           up_rack);
-
+  output  reg           up_rack
+);
 
   // registers
 
@@ -214,7 +214,9 @@ module up_ad5766_sequencer #(
 
   // CDC
 
-  up_xfer_cntrl #(.DATA_WIDTH(132)) i_xfer_cntrl (
+  up_xfer_cntrl #(
+    .DATA_WIDTH(132)
+  ) i_xfer_cntrl (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_data_cntrl ({up_endof_seq,
diff --git a/library/axi_ad7616/axi_ad7616.v b/library/axi_ad7616/axi_ad7616.v
index 9acfc45de..6bd2c1ad0 100644
--- a/library/axi_ad7616/axi_ad7616.v
+++ b/library/axi_ad7616/axi_ad7616.v
@@ -38,7 +38,8 @@
 module axi_ad7616 #(
 
   parameter       ID = 0,
-  parameter       IF_TYPE = 1) (
+  parameter       IF_TYPE = 1
+) (
 
   // physical data interface
 
@@ -88,8 +89,8 @@ module axi_ad7616 #(
   output      [15:0]      adc_data,
   output                  adc_sync,
 
-  output                  irq);
-
+  output                  irq
+);
 
   localparam      NUM_OF_SDI = 2;
   localparam      SERIAL = 0;
@@ -368,8 +369,7 @@ module axi_ad7616 #(
       .fifo_wr_en(adc_valid),
       .fifo_wr_data(adc_data),
       .fifo_wr_sync(adc_sync),
-      .fifo_wr_xfer_req(1'b1)
-    );
+      .fifo_wr_xfer_req(1'b1));
 
   end
   endgenerate
@@ -402,8 +402,7 @@ module axi_ad7616 #(
       .wr_req (wr_req_s),
       .wr_data (wr_data_s),
       .rd_data (rd_data_s),
-      .rd_valid (rd_valid_s)
-    );
+      .rd_valid (rd_valid_s));
 
   end
   endgenerate
@@ -466,6 +465,3 @@ module axi_ad7616 #(
     .up_rack (up_rack));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_ad7616/axi_ad7616_control.v b/library/axi_ad7616/axi_ad7616_control.v
index 2d3cc01c6..c2d87e997 100644
--- a/library/axi_ad7616/axi_ad7616_control.v
+++ b/library/axi_ad7616/axi_ad7616_control.v
@@ -38,7 +38,8 @@
 module axi_ad7616_control #(
 
   parameter   ID = 0,
-  parameter   IF_TYPE = 0) (
+  parameter   IF_TYPE = 0
+) (
 
   // control signals
 
@@ -68,7 +69,6 @@ module axi_ad7616_control #(
   output  reg             up_rack
 );
 
-
   localparam  PCORE_VERSION = 'h00001002;
   localparam  POS_EDGE = 0;
   localparam  NEG_EDGE = 1;
@@ -170,8 +170,7 @@ module axi_ad7616_control #(
     .clk (up_clk),
     .rst (up_rst),
     .signal_in (busy),
-    .signal_out (end_of_conv)
-  );
+    .signal_out (end_of_conv));
 
   // convertion start generator
   // NOTE: + The minimum convertion cycle is 1 us
@@ -208,4 +207,3 @@ module axi_ad7616_control #(
   assign cnvst = (up_cnvst_en == 1'b1) ? cnvst_buf : 1'b0;
 
 endmodule
-
diff --git a/library/axi_ad7616/axi_ad7616_maxis2wrfifo.v b/library/axi_ad7616/axi_ad7616_maxis2wrfifo.v
index 4573cd44a..7e091d143 100644
--- a/library/axi_ad7616/axi_ad7616_maxis2wrfifo.v
+++ b/library/axi_ad7616/axi_ad7616_maxis2wrfifo.v
@@ -37,8 +37,8 @@
 
 module axi_ad7616_maxis2wrfifo #(
 
-  parameter   DATA_WIDTH = 16) (
-
+  parameter   DATA_WIDTH = 16
+) (
   input                   clk,
   input                   rstn,
   input                   sync_in,
@@ -58,7 +58,6 @@ module axi_ad7616_maxis2wrfifo #(
   input                   fifo_wr_xfer_req
 );
 
-
   always @(posedge clk) begin
     if (rstn == 1'b0) begin
       m_axis_ready <= 1'b0;
diff --git a/library/axi_ad7616/axi_ad7616_pif.v b/library/axi_ad7616/axi_ad7616_pif.v
index 2750ea10d..f84d7d144 100644
--- a/library/axi_ad7616/axi_ad7616_pif.v
+++ b/library/axi_ad7616/axi_ad7616_pif.v
@@ -37,7 +37,8 @@
 
 module axi_ad7616_pif #(
 
-  parameter UP_ADDRESS_WIDTH = 14) (
+  parameter UP_ADDRESS_WIDTH = 14
+) (
 
   // physical interface
 
@@ -67,8 +68,8 @@ module axi_ad7616_pif #(
   input                   wr_req,
   input       [15:0]      wr_data,
   output  reg [15:0]      rd_data,
-  output  reg             rd_valid);
-
+  output  reg             rd_valid
+);
 
   // state registers
 
@@ -212,4 +213,3 @@ module axi_ad7616_pif #(
   end
 
 endmodule
-
diff --git a/library/axi_ad9122/axi_ad9122.v b/library/axi_ad9122/axi_ad9122.v
index 1b7c2de7e..4a479ea42 100644
--- a/library/axi_ad9122/axi_ad9122.v
+++ b/library/axi_ad9122/axi_ad9122.v
@@ -53,7 +53,8 @@ module axi_ad9122 #(
   parameter   DAC_DDS_TYPE = 1,
   parameter   DAC_DDS_CORDIC_DW = 20,
   parameter   DAC_DDS_CORDIC_PHASE_DW = 18,
-  parameter   IO_DELAY_GROUP = "dev_if_delay_group") (
+  parameter   IO_DELAY_GROUP = "dev_if_delay_group"
+) (
 
   // dac interface
 
@@ -104,8 +105,8 @@ module axi_ad9122 #(
   output      [ 1:0]      s_axi_rresp,
   input                   s_axi_rready,
   input       [ 2:0]      s_axi_awprot,
-  input       [ 2:0]      s_axi_arprot);
-
+  input       [ 2:0]      s_axi_arprot
+);
 
   // internal clocks and resets
 
@@ -164,8 +165,8 @@ module axi_ad9122 #(
     .MMCM_VCO_DIV (MMCM_VCO_DIV),
     .MMCM_VCO_MUL (MMCM_VCO_MUL),
     .MMCM_CLK0_DIV (MMCM_CLK0_DIV),
-    .MMCM_CLK1_DIV (MMCM_CLK1_DIV))
-  i_if (
+    .MMCM_CLK1_DIV (MMCM_CLK1_DIV)
+  ) i_if (
     .dac_clk_in_p (dac_clk_in_p),
     .dac_clk_in_n (dac_clk_in_n),
     .dac_clk_out_p (dac_clk_out_p),
@@ -216,8 +217,8 @@ module axi_ad9122 #(
     .DAC_DDS_TYPE (DAC_DDS_TYPE),
     .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
     .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
-    .DATAPATH_DISABLE(DAC_DATAPATH_DISABLE))
-  i_core (
+    .DATAPATH_DISABLE(DAC_DATAPATH_DISABLE)
+  ) i_core (
     .dac_div_clk (dac_div_clk),
     .dac_rst (dac_rst),
     .dac_frame_i0 (dac_frame_i0_s),
@@ -297,6 +298,3 @@ module axi_ad9122 #(
     .up_rack (up_rack_s));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_ad9122/axi_ad9122_channel.v b/library/axi_ad9122/axi_ad9122_channel.v
index 73b8f9282..622b6f753 100644
--- a/library/axi_ad9122/axi_ad9122_channel.v
+++ b/library/axi_ad9122/axi_ad9122_channel.v
@@ -41,7 +41,8 @@ module axi_ad9122_channel #(
   parameter DAC_DDS_TYPE = 1,
   parameter DAC_DDS_CORDIC_DW = 16,
   parameter DAC_DDS_CORDIC_PHASE_DW = 16,
-  parameter DATAPATH_DISABLE = 0) (
+  parameter DATAPATH_DISABLE = 0
+) (
 
   // dac interface
 
@@ -69,7 +70,8 @@ module axi_ad9122_channel #(
   input                   up_rreq,
   input       [13:0]      up_raddr,
   output      [31:0]      up_rdata,
-  output                  up_rack);
+  output                  up_rack
+);
 
   // internal signals
 
@@ -110,8 +112,8 @@ module axi_ad9122_channel #(
     .DDS_TYPE (DAC_DDS_TYPE),
     .CORDIC_DW (DAC_DDS_CORDIC_DW),
     .CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
-    .CLK_RATIO (4))
-  i_dds (
+    .CLK_RATIO (4)
+  ) i_dds (
     .clk (dac_clk),
     .dac_dds_format (dac_dds_format),
     .dac_data_sync (dac_data_sync),
@@ -131,8 +133,8 @@ module axi_ad9122_channel #(
     .CHANNEL_ID(CHANNEL_ID),
     .DDS_DISABLE (0),
     .USERPORTS_DISABLE (0),
-    .IQCORRECTION_DISABLE (0))
-  i_up_dac_channel (
+    .IQCORRECTION_DISABLE (0)
+  ) i_up_dac_channel (
     .dac_clk (dac_div_clk),
     .dac_rst (dac_rst),
     .dac_dds_scale_1 (dac_dds_scale_1_s),
@@ -174,6 +176,3 @@ module axi_ad9122_channel #(
     .up_rack (up_rack));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_ad9122/axi_ad9122_core.v b/library/axi_ad9122/axi_ad9122_core.v
index 6cd8e95c5..951a59480 100644
--- a/library/axi_ad9122/axi_ad9122_core.v
+++ b/library/axi_ad9122/axi_ad9122_core.v
@@ -45,7 +45,8 @@ module axi_ad9122_core #(
   parameter   DAC_DDS_TYPE = 1,
   parameter   DAC_DDS_CORDIC_DW = 16,
   parameter   DAC_DDS_CORDIC_PHASE_DW = 16,
-  parameter   DATAPATH_DISABLE = 0) (
+  parameter   DATAPATH_DISABLE = 0
+) (
 
   // dac interface
 
@@ -109,8 +110,8 @@ module axi_ad9122_core #(
   input                   up_rreq,
   input       [13:0]      up_raddr,
   output  reg [31:0]      up_rdata,
-  output  reg             up_rack);
-
+  output  reg             up_rack
+);
 
   // internal registers
 
@@ -159,8 +160,8 @@ module axi_ad9122_core #(
     .DAC_DDS_TYPE (DAC_DDS_TYPE),
     .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
     .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
-    .DATAPATH_DISABLE(DATAPATH_DISABLE))
-  i_channel_0 (
+    .DATAPATH_DISABLE(DATAPATH_DISABLE)
+  ) i_channel_0 (
     .dac_div_clk (dac_div_clk),
     .dac_rst (dac_rst),
     .dac_enable (dac_enable_0),
@@ -188,8 +189,8 @@ module axi_ad9122_core #(
     .DAC_DDS_TYPE (DAC_DDS_TYPE),
     .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
     .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
-    .DATAPATH_DISABLE(DATAPATH_DISABLE))
-  i_channel_1 (
+    .DATAPATH_DISABLE(DATAPATH_DISABLE)
+  ) i_channel_1 (
     .dac_div_clk (dac_div_clk),
     .dac_rst (dac_rst),
     .dac_enable (dac_enable_1),
@@ -223,8 +224,8 @@ module axi_ad9122_core #(
     .COMMON_ID (6'h10),
     .DRP_DISABLE (6'h00),
     .USERPORTS_DISABLE (0),
-    .GPIO_DISABLE (0))
-  i_up_dac_common (
+    .GPIO_DISABLE (0)
+  ) i_up_dac_common (
     .mmcm_rst (mmcm_rst),
     .dac_clk (dac_div_clk),
     .dac_rst (dac_rst),
@@ -266,6 +267,3 @@ module axi_ad9122_core #(
     .up_rack (up_rack_s));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_ad9122/axi_ad9122_if.v b/library/axi_ad9122/axi_ad9122_if.v
index 482467658..4ab3f756f 100644
--- a/library/axi_ad9122/axi_ad9122_if.v
+++ b/library/axi_ad9122/axi_ad9122_if.v
@@ -47,7 +47,8 @@ module axi_ad9122_if #(
   parameter   MMCM_VCO_MUL = 12,
   parameter   MMCM_CLK0_DIV = 2,
   parameter   MMCM_CLK1_DIV = 8,
-  parameter   IO_DELAY_GROUP = "dac_if_delay_group") (
+  parameter   IO_DELAY_GROUP = "dac_if_delay_group"
+) (
 
   // dac interface
 
@@ -101,8 +102,8 @@ module axi_ad9122_if #(
   input       [31:0]      up_drp_wdata,
   output      [31:0]      up_drp_rdata,
   output                  up_drp_ready,
-  output                  up_drp_locked);
-
+  output                  up_drp_locked
+);
 
   // internal registers
 
@@ -130,8 +131,8 @@ module axi_ad9122_if #(
   ad_serdes_out #(
     .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
     .DDR_OR_SDR_N (SERDES_OR_DDR_N),
-    .DATA_WIDTH (16))
-  i_serdes_out_data (
+    .DATA_WIDTH (16)
+  ) i_serdes_out_data (
     .rst (dac_rst),
     .clk (dac_clk),
     .div_clk (dac_div_clk),
@@ -154,8 +155,8 @@ module axi_ad9122_if #(
   ad_serdes_out #(
     .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
     .DDR_OR_SDR_N (SERDES_OR_DDR_N),
-    .DATA_WIDTH (1))
-  i_serdes_out_frame (
+    .DATA_WIDTH (1)
+  ) i_serdes_out_frame (
     .rst (dac_rst),
     .clk (dac_clk),
     .div_clk (dac_div_clk),
@@ -178,8 +179,8 @@ module axi_ad9122_if #(
   ad_serdes_out #(
     .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
     .DDR_OR_SDR_N (SERDES_OR_DDR_N),
-    .DATA_WIDTH (1))
-  i_serdes_out_clk (
+    .DATA_WIDTH (1)
+  ) i_serdes_out_clk (
     .rst (dac_rst),
     .clk (dac_clk),
     .div_clk (dac_div_clk),
@@ -207,8 +208,8 @@ module axi_ad9122_if #(
     .MMCM_VCO_DIV (MMCM_VCO_DIV),
     .MMCM_VCO_MUL (MMCM_VCO_MUL),
     .MMCM_CLK0_DIV (MMCM_CLK0_DIV),
-    .MMCM_CLK1_DIV (MMCM_CLK1_DIV))
-  i_serdes_clk (
+    .MMCM_CLK1_DIV (MMCM_CLK1_DIV)
+  ) i_serdes_clk (
     .rst (mmcm_rst),
     .clk_in_p (dac_clk_in_p),
     .clk_in_n (dac_clk_in_n),
@@ -228,6 +229,3 @@ module axi_ad9122_if #(
     .up_drp_locked (up_drp_locked));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_ad9250/axi_ad9250.v b/library/axi_ad9250/axi_ad9250.v
index c4c70b0e6..5f83637fb 100644
--- a/library/axi_ad9250/axi_ad9250.v
+++ b/library/axi_ad9250/axi_ad9250.v
@@ -85,7 +85,8 @@ module axi_ad9250 #(
   output                  s_axi_rvalid,
   output      [31:0]      s_axi_rdata,
   output      [ 1:0]      s_axi_rresp,
-  input                   s_axi_rready);
+  input                   s_axi_rready
+);
 
   assign adc_clk = rx_clk;
 
@@ -135,7 +136,6 @@ module axi_ad9250 #(
     .s_axi_rvalid (s_axi_rvalid),
     .s_axi_rready (s_axi_rready),
     .s_axi_rresp (s_axi_rresp),
-    .s_axi_rdata (s_axi_rdata)
-  );
+    .s_axi_rdata (s_axi_rdata));
 
 endmodule
diff --git a/library/axi_ad9265/axi_ad9265.v b/library/axi_ad9265/axi_ad9265.v
index f1dadb242..7ed89302e 100644
--- a/library/axi_ad9265/axi_ad9265.v
+++ b/library/axi_ad9265/axi_ad9265.v
@@ -43,7 +43,8 @@ module axi_ad9265 #(
   parameter SPEED_GRADE = 0,
   parameter DEV_PACKAGE = 0,
   parameter ADC_DATAPATH_DISABLE = 0,
-  parameter IO_DELAY_GROUP = "adc_if_delay_group") (
+  parameter IO_DELAY_GROUP = "adc_if_delay_group"
+) (
 
   // adc interface (clk, data, over-range)
 
@@ -89,8 +90,8 @@ module axi_ad9265 #(
   output      [31:0]      s_axi_rdata,
   input                   s_axi_rready,
   input       [ 2:0]      s_axi_awprot,
-  input       [ 2:0]      s_axi_arprot);
-
+  input       [ 2:0]      s_axi_arprot
+);
 
   // internal registers
 
@@ -157,8 +158,8 @@ module axi_ad9265 #(
 
   axi_ad9265_channel #(
     .CHANNEL_ID(0),
-    .DATAPATH_DISABLE (ADC_DATAPATH_DISABLE))
-  i_channel (
+    .DATAPATH_DISABLE (ADC_DATAPATH_DISABLE)
+  ) i_channel (
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
     .adc_data (adc_data_s),
@@ -184,8 +185,8 @@ module axi_ad9265 #(
 
   axi_ad9265_if #(
     .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
-    .IO_DELAY_GROUP (IO_DELAY_GROUP))
-  i_if (
+    .IO_DELAY_GROUP (IO_DELAY_GROUP)
+  ) i_if (
     .adc_clk_in_p (adc_clk_in_p),
     .adc_clk_in_n (adc_clk_in_n),
     .adc_data_in_p (adc_data_in_p),
@@ -206,7 +207,10 @@ module axi_ad9265 #(
 
   // adc delay control
 
-  up_delay_cntrl #(.DATA_WIDTH(9), .BASE_ADDRESS(6'h02)) i_delay_cntrl (
+  up_delay_cntrl #(
+    .DATA_WIDTH(9),
+    .BASE_ADDRESS(6'h02)
+  ) i_delay_cntrl (
     .delay_clk (delay_clk),
     .delay_rst (delay_rst),
     .delay_locked (delay_locked_s),
@@ -237,8 +241,8 @@ module axi_ad9265 #(
     .DRP_DISABLE (6'h00),
     .USERPORTS_DISABLE (0),
     .GPIO_DISABLE (0),
-    .START_CODE_DISABLE(0))
-  i_up_adc_common (
+    .START_CODE_DISABLE(0)
+  ) i_up_adc_common (
     .mmcm_rst (),
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
@@ -313,7 +317,3 @@ module axi_ad9265 #(
     .up_rack (up_rack));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
-
diff --git a/library/axi_ad9265/axi_ad9265_channel.v b/library/axi_ad9265/axi_ad9265_channel.v
index aa3f4370c..aa9287979 100644
--- a/library/axi_ad9265/axi_ad9265_channel.v
+++ b/library/axi_ad9265/axi_ad9265_channel.v
@@ -39,7 +39,8 @@
 module axi_ad9265_channel #(
 
   parameter CHANNEL_ID = 0,
-  parameter DATAPATH_DISABLE = 0) (
+  parameter DATAPATH_DISABLE = 0
+) (
 
   // adc interface
 
@@ -68,8 +69,8 @@ module axi_ad9265_channel #(
   input                   up_rreq,
   input       [13:0]      up_raddr,
   output      [31:0]      up_rdata,
-  output                  up_rack);
-
+  output                  up_rack
+);
 
   // internal signals
 
@@ -97,7 +98,9 @@ module axi_ad9265_channel #(
   if (DATAPATH_DISABLE == 1) begin
   assign adc_dfmt_data_s = adc_data;
   end else begin
-  ad_datafmt #(.DATA_WIDTH(16)) i_ad_datafmt (
+  ad_datafmt #(
+    .DATA_WIDTH(16)
+  ) i_ad_datafmt (
     .clk (adc_clk),
     .valid (1'b1),
     .data (adc_data),
@@ -131,8 +134,8 @@ module axi_ad9265_channel #(
     .USERPORTS_DISABLE (0),
     .DATAFORMAT_DISABLE (0),
     .DCFILTER_DISABLE (0),
-    .IQCORRECTION_DISABLE (0))
-  i_up_adc_channel (
+    .IQCORRECTION_DISABLE (0)
+  ) i_up_adc_channel (
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
     .adc_enable (adc_enable),
@@ -179,6 +182,3 @@ module axi_ad9265_channel #(
     .up_rack (up_rack));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_ad9265/axi_ad9265_if.v b/library/axi_ad9265/axi_ad9265_if.v
index e7b09b56e..bdb6735ac 100644
--- a/library/axi_ad9265/axi_ad9265_if.v
+++ b/library/axi_ad9265/axi_ad9265_if.v
@@ -41,7 +41,8 @@ module axi_ad9265_if #(
 
   parameter   FPGA_TECHNOLOGY = 0,
   parameter   IO_DELAY_GROUP = "adc_if_delay_group",
-  parameter   DELAY_REFCLK_FREQUENCY = 200) (
+  parameter   DELAY_REFCLK_FREQUENCY = 200
+) (
 
   // adc interface (clk, data, over-range)
   // nominal clock 125 MHz, up to 300 MHz
@@ -68,8 +69,8 @@ module axi_ad9265_if #(
   output      [44:0]      up_drdata,
   input                   delay_clk,
   input                   delay_rst,
-  output                  delay_locked);
-
+  output                  delay_locked
+);
 
   // internal registers
 
@@ -102,8 +103,8 @@ module axi_ad9265_if #(
     .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
     .IODELAY_CTRL (0),
     .IODELAY_GROUP (IO_DELAY_GROUP),
-    .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
-  i_adc_data (
+    .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
+  ) i_adc_data (
     .rx_clk (adc_clk),
     .rx_data_in_p (adc_data_in_p[l_inst]),
     .rx_data_in_n (adc_data_in_n[l_inst]),
@@ -125,8 +126,8 @@ module axi_ad9265_if #(
     .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
     .IODELAY_CTRL (1),
     .IODELAY_GROUP (IO_DELAY_GROUP),
-    .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
-  i_adc_or (
+    .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
+  ) i_adc_or (
     .rx_clk (adc_clk),
     .rx_data_in_p (adc_or_in_p),
     .rx_data_in_n (adc_or_in_n),
@@ -142,8 +143,7 @@ module axi_ad9265_if #(
 
   // clock
 
-  ad_data_clk
-  i_adc_clk (
+  ad_data_clk i_adc_clk (
     .rst (1'b0),
     .locked (),
     .clk_in_p (adc_clk_in_p),
@@ -151,6 +151,3 @@ module axi_ad9265_if #(
     .clk (adc_clk));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_ad9265/axi_ad9265_pnmon.v b/library/axi_ad9265/axi_ad9265_pnmon.v
index f3e1a89e3..a57b3195a 100644
--- a/library/axi_ad9265/axi_ad9265_pnmon.v
+++ b/library/axi_ad9265/axi_ad9265_pnmon.v
@@ -47,7 +47,8 @@ module axi_ad9265_pnmon (
 
   output                  adc_pn_oos,
   output                  adc_pn_err,
-  input       [ 3:0]      adc_pnseq_sel);
+  input       [ 3:0]      adc_pnseq_sel
+);
 
   // internal registers
 
@@ -161,7 +162,9 @@ module axi_ad9265_pnmon (
 
   // pn oos & pn err
 
-  ad_pnmon #(.DATA_WIDTH(32)) i_pnmon (
+  ad_pnmon #(
+    .DATA_WIDTH(32)
+  ) i_pnmon (
     .adc_clk (adc_clk),
     .adc_valid_in (adc_valid_in),
     .adc_data_in (adc_pn_data_in),
@@ -170,7 +173,3 @@ module axi_ad9265_pnmon (
     .adc_pn_err (adc_pn_err));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
-
diff --git a/library/axi_ad9361/axi_ad9361.v b/library/axi_ad9361/axi_ad9361.v
index eaf06382e..4066c5149 100644
--- a/library/axi_ad9361/axi_ad9361.v
+++ b/library/axi_ad9361/axi_ad9361.v
@@ -69,7 +69,8 @@ module axi_ad9361 #(
   parameter   MIMO_ENABLE = 0,
   parameter   USE_SSI_CLK = 1,
   parameter   DELAY_REFCLK_FREQUENCY = 200,
-  parameter   RX_NODPA = 0) (
+  parameter   RX_NODPA = 0
+) (
 
   // physical interface (receive-lvds)
 
@@ -192,7 +193,8 @@ module axi_ad9361 #(
   input   [31:0]  up_dac_gpio_in,
   output  [31:0]  up_dac_gpio_out,
   input   [31:0]  up_adc_gpio_in,
-  output  [31:0]  up_adc_gpio_out);
+  output  [31:0]  up_adc_gpio_out
+);
 
   // derived parameters
 
@@ -339,8 +341,8 @@ module axi_ad9361 #(
     .IODELAY_CTRL (IODELAY_CTRL),
     .CLK_DESKEW (MIMO_ENABLE),
     .USE_SSI_CLK (USE_SSI_CLK),
-    .DELAY_REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
-  i_dev_if (
+    .DELAY_REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
+  ) i_dev_if (
     .rx_clk_in (rx_clk_in),
     .rx_frame_in (rx_frame_in),
     .rx_data_in (rx_data_in),
@@ -405,8 +407,8 @@ module axi_ad9361 #(
     .CLK_DESKEW (MIMO_ENABLE),
     .USE_SSI_CLK (USE_SSI_CLK),
     .DELAY_REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY),
-    .RX_NODPA (RX_NODPA))
-  i_dev_if (
+    .RX_NODPA (RX_NODPA)
+  ) i_dev_if (
     .rx_clk_in_p (rx_clk_in_p),
     .rx_clk_in_n (rx_clk_in_n),
     .rx_frame_in_p (rx_frame_in_p),
@@ -521,7 +523,9 @@ module axi_ad9361 #(
 
   generate
   if (TDD_DISABLE == 0) begin
-  axi_ad9361_tdd_if #(.LEVEL_OR_PULSE_N(1)) i_tdd_if (
+  axi_ad9361_tdd_if #(
+    .LEVEL_OR_PULSE_N(1)
+  ) i_tdd_if (
     .clk (clk),
     .rst (rst),
     .tdd_rx_vco_en (tdd_rx_vco_en_s),
@@ -599,8 +603,8 @@ module axi_ad9361 #(
     .USERPORTS_DISABLE (ADC_USERPORTS_DISABLE_INT),
     .DATAFORMAT_DISABLE (ADC_DATAFORMAT_DISABLE_INT),
     .DCFILTER_DISABLE (ADC_DCFILTER_DISABLE_INT),
-    .IQCORRECTION_DISABLE (ADC_IQCORRECTION_DISABLE_INT))
-  i_rx (
+    .IQCORRECTION_DISABLE (ADC_IQCORRECTION_DISABLE_INT)
+  ) i_rx (
     .mmcm_rst (mmcm_rst),
     .adc_rst (rst),
     .adc_clk (clk),
@@ -672,8 +676,8 @@ module axi_ad9361 #(
     .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
     .USERPORTS_DISABLE (DAC_USERPORTS_DISABLE_INT),
     .DELAYCNTRL_DISABLE (DAC_DELAYCNTRL_DISABLE_INT),
-    .IQCORRECTION_DISABLE (DAC_IQCORRECTION_DISABLE_INT))
-  i_tx (
+    .IQCORRECTION_DISABLE (DAC_IQCORRECTION_DISABLE_INT)
+  ) i_tx (
     .dac_clk (clk),
     .dac_valid (dac_valid_s),
     .dac_data (dac_data_s),
@@ -750,6 +754,3 @@ module axi_ad9361 #(
     .up_rack (up_rack));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_ad9361/axi_ad9361_rx.v b/library/axi_ad9361/axi_ad9361_rx.v
index d4d34e86a..f7554bd05 100644
--- a/library/axi_ad9361/axi_ad9361_rx.v
+++ b/library/axi_ad9361/axi_ad9361_rx.v
@@ -52,7 +52,8 @@ module axi_ad9361_rx #(
   parameter   USERPORTS_DISABLE = 0,
   parameter   DATAFORMAT_DISABLE = 0,
   parameter   DCFILTER_DISABLE = 0,
-  parameter   IQCORRECTION_DISABLE = 0) (
+  parameter   IQCORRECTION_DISABLE = 0
+) (
 
   // common
 
@@ -126,7 +127,8 @@ module axi_ad9361_rx #(
   output   [31:0] up_drp_wdata,
   input    [31:0] up_drp_rdata,
   input           up_drp_ready,
-  input           up_drp_locked);
+  input           up_drp_locked
+);
 
   // configuration settings
 
@@ -194,8 +196,8 @@ module axi_ad9361_rx #(
     .USERPORTS_DISABLE (USERPORTS_DISABLE),
     .DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
     .DCFILTER_DISABLE (DCFILTER_DISABLE),
-    .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
-  i_rx_channel_0 (
+    .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)
+  ) i_rx_channel_0 (
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
     .adc_valid (adc_valid),
@@ -231,8 +233,8 @@ module axi_ad9361_rx #(
     .USERPORTS_DISABLE (USERPORTS_DISABLE),
     .DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
     .DCFILTER_DISABLE (DCFILTER_DISABLE),
-    .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
-  i_rx_channel_1 (
+    .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)
+  ) i_rx_channel_1 (
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
     .adc_valid (adc_valid),
@@ -268,8 +270,8 @@ module axi_ad9361_rx #(
     .USERPORTS_DISABLE (USERPORTS_DISABLE),
     .DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
     .DCFILTER_DISABLE (DCFILTER_DISABLE),
-    .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
-  i_rx_channel_2 (
+    .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)
+  ) i_rx_channel_2 (
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
     .adc_valid (adc_valid),
@@ -305,8 +307,8 @@ module axi_ad9361_rx #(
     .USERPORTS_DISABLE (USERPORTS_DISABLE),
     .DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
     .DCFILTER_DISABLE (DCFILTER_DISABLE),
-    .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
-  i_rx_channel_3 (
+    .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)
+  ) i_rx_channel_3 (
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
     .adc_valid (adc_valid),
@@ -345,8 +347,8 @@ module axi_ad9361_rx #(
     .DRP_DISABLE (1),
     .USERPORTS_DISABLE (USERPORTS_DISABLE),
     .GPIO_DISABLE (0),
-    .START_CODE_DISABLE (0))
-  i_up_adc_common (
+    .START_CODE_DISABLE (0)
+  ) i_up_adc_common (
     .mmcm_rst (mmcm_rst),
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
@@ -397,8 +399,8 @@ module axi_ad9361_rx #(
   up_delay_cntrl #(
     .INIT_DELAY (INIT_DELAY),
     .DATA_WIDTH (13),
-    .BASE_ADDRESS (6'h02))
-  i_delay_cntrl (
+    .BASE_ADDRESS (6'h02)
+  ) i_delay_cntrl (
     .delay_clk (delay_clk),
     .delay_rst (delay_rst),
     .delay_locked (delay_locked),
@@ -417,7 +419,3 @@ module axi_ad9361_rx #(
     .up_rack (up_rack_s[5]));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
-
diff --git a/library/axi_ad9361/axi_ad9361_rx_channel.v b/library/axi_ad9361/axi_ad9361_rx_channel.v
index 1f247d50f..32adfb49e 100644
--- a/library/axi_ad9361/axi_ad9361_rx_channel.v
+++ b/library/axi_ad9361/axi_ad9361_rx_channel.v
@@ -45,7 +45,8 @@ module axi_ad9361_rx_channel #(
   parameter   USERPORTS_DISABLE = 0,
   parameter   DATAFORMAT_DISABLE = 0,
   parameter   DCFILTER_DISABLE = 0,
-  parameter   IQCORRECTION_DISABLE = 0) (
+  parameter   IQCORRECTION_DISABLE = 0
+) (
 
   // adc interface
 
@@ -79,7 +80,8 @@ module axi_ad9361_rx_channel #(
   input           up_rreq,
   input   [13:0]  up_raddr,
   output  [31:0]  up_rdata,
-  output          up_rack);
+  output          up_rack
+);
 
   // internal signals
 
@@ -129,8 +131,8 @@ module axi_ad9361_rx_channel #(
 
   axi_ad9361_rx_pnmon #(
     .Q_OR_I_N (Q_OR_I_N),
-    .PRBS_SEL (CHANNEL_ID))
-  i_rx_pnmon (
+    .PRBS_SEL (CHANNEL_ID)
+  )  i_rx_pnmon (
     .adc_clk (adc_clk),
     .adc_valid (adc_valid),
     .adc_data_i (adc_data),
@@ -141,8 +143,8 @@ module axi_ad9361_rx_channel #(
 
   ad_datafmt #(
     .DATA_WIDTH (12),
-    .DISABLE (DATAFORMAT_DISABLE))
-  i_ad_datafmt (
+    .DISABLE (DATAFORMAT_DISABLE)
+  ) i_ad_datafmt (
     .clk (adc_clk),
     .valid (adc_valid),
     .data (adc_data_s),
@@ -153,8 +155,8 @@ module axi_ad9361_rx_channel #(
     .dfmt_se (adc_dfmt_se_s));
 
   ad_dcfilter #(
-    .DISABLE (DCFILTER_DISABLE))
-  i_ad_dcfilter (
+    .DISABLE (DCFILTER_DISABLE)
+  ) i_ad_dcfilter (
     .clk (adc_clk),
     .valid (adc_dfmt_valid_s),
     .data (adc_dfmt_data_s),
@@ -166,8 +168,8 @@ module axi_ad9361_rx_channel #(
 
   ad_iqcor #(
     .Q_OR_I_N (Q_OR_I_N),
-    .DISABLE (IQCORRECTION_DISABLE))
-  i_ad_iqcor (
+    .DISABLE (IQCORRECTION_DISABLE)
+  ) i_ad_iqcor (
     .clk (adc_clk),
     .valid (adc_dcfilter_valid_s),
     .data_in (adc_dcfilter_data_s),
@@ -183,8 +185,8 @@ module axi_ad9361_rx_channel #(
     .USERPORTS_DISABLE (USERPORTS_DISABLE),
     .DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
     .DCFILTER_DISABLE (DCFILTER_DISABLE),
-    .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
-  i_up_adc_channel (
+    .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)
+  ) i_up_adc_channel (
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
     .adc_enable (adc_enable),
@@ -232,9 +234,4 @@ module axi_ad9361_rx_channel #(
 
   end
   endgenerate
-
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
-
diff --git a/library/axi_ad9361/axi_ad9361_rx_pnmon.v b/library/axi_ad9361/axi_ad9361_rx_pnmon.v
index 20779e9a7..393dff5c3 100644
--- a/library/axi_ad9361/axi_ad9361_rx_pnmon.v
+++ b/library/axi_ad9361/axi_ad9361_rx_pnmon.v
@@ -39,7 +39,8 @@
 module axi_ad9361_rx_pnmon #(
 
   parameter   Q_OR_I_N     = 0,
-  parameter   PRBS_SEL  = 0) (
+  parameter   PRBS_SEL  = 0
+) (
 
   // adc interface
 
@@ -52,7 +53,8 @@ module axi_ad9361_rx_pnmon #(
 
   input       [ 3:0]      adc_pnseq_sel,
   output                  adc_pn_oos,
-  output                  adc_pn_err);
+  output                  adc_pn_err
+);
 
   localparam  PRBS_P09  = 0;
   localparam  PRBS_P11  = 1;
@@ -287,7 +289,9 @@ module axi_ad9361_rx_pnmon #(
 
   // pn oos & pn err
 
-  ad_pnmon #(.DATA_WIDTH(24)) i_pnmon (
+  ad_pnmon #(
+    .DATA_WIDTH(24)
+  ) i_pnmon (
     .adc_clk (adc_clk),
     .adc_valid_in (adc_pn_valid_in),
     .adc_data_in (adc_pn_data_in),
@@ -297,7 +301,3 @@ module axi_ad9361_rx_pnmon #(
     .adc_pn_err (adc_pn_err));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
-
diff --git a/library/axi_ad9361/axi_ad9361_tdd.v b/library/axi_ad9361/axi_ad9361_tdd.v
index ea528def3..d1ae5b271 100644
--- a/library/axi_ad9361/axi_ad9361_tdd.v
+++ b/library/axi_ad9361/axi_ad9361_tdd.v
@@ -75,7 +75,8 @@ module axi_ad9361_tdd (
   input                   up_rreq,
   input       [13:0]      up_raddr,
   output      [31:0]      up_rdata,
-  output                  up_rack);
+  output                  up_rack
+);
 
   // internal signals
 
@@ -152,7 +153,7 @@ module axi_ad9361_tdd (
 
   // instantiations
 
-  up_tdd_cntrl i_up_tdd_cntrl(
+  up_tdd_cntrl i_up_tdd_cntrl (
     .clk(clk),
     .rst(rst),
     .tdd_enable(tdd_enable_s),
@@ -206,8 +207,8 @@ module axi_ad9361_tdd (
 
   ad_tdd_control #(
     .TX_DATA_PATH_DELAY(),
-    .CONTROL_PATH_DELAY())
-  i_tdd_control(
+    .CONTROL_PATH_DELAY()
+  ) i_tdd_control(
     .clk(clk),
     .rst(rst),
     .tdd_enable(tdd_enable_s),
diff --git a/library/axi_ad9361/axi_ad9361_tdd_if.v b/library/axi_ad9361/axi_ad9361_tdd_if.v
index 334738bd1..7cfe46d8c 100644
--- a/library/axi_ad9361/axi_ad9361_tdd_if.v
+++ b/library/axi_ad9361/axi_ad9361_tdd_if.v
@@ -35,12 +35,9 @@
 
 `timescale 1ns/1ps
 
-module axi_ad9361_tdd_if#(
-
-  parameter       LEVEL_OR_PULSE_N = 0) (
-
-  // clock
-
+module axi_ad9361_tdd_if #(
+  parameter       LEVEL_OR_PULSE_N = 0
+) (
   input                   clk,
   input                   rst,
 
@@ -58,15 +55,14 @@ module axi_ad9361_tdd_if#(
 
   // interface status
 
-  output      [ 7:0]      ad9361_tdd_status);
-
+  output      [ 7:0]      ad9361_tdd_status
+);
 
   localparam      PULSE_MODE = 0;
   localparam      LEVEL_MODE = 1;
 
   // internal registers
 
-
   reg             tdd_vco_overlap = 1'b0;
   reg             tdd_rf_overlap = 1'b0;
 
@@ -91,7 +87,7 @@ module axi_ad9361_tdd_if#(
   endgenerate
 
   always @(posedge clk) begin
-    if(rst == 1'b1) begin
+    if (rst == 1'b1) begin
       tdd_vco_overlap <= 1'b0;
       tdd_rf_overlap <= 1'b0;
     end else begin
@@ -106,4 +102,3 @@ module axi_ad9361_tdd_if#(
   assign ad9361_enable = ad9361_enable_s;
 
 endmodule
-
diff --git a/library/axi_ad9361/axi_ad9361_tx.v b/library/axi_ad9361/axi_ad9361_tx.v
index 6105f9001..e33acbbc6 100644
--- a/library/axi_ad9361/axi_ad9361_tx.v
+++ b/library/axi_ad9361/axi_ad9361_tx.v
@@ -55,7 +55,8 @@ module axi_ad9361_tx #(
   parameter   DAC_DDS_CORDIC_PHASE_DW = 13,
   parameter   USERPORTS_DISABLE = 0,
   parameter   DELAYCNTRL_DISABLE = 0,
-  parameter   IQCORRECTION_DISABLE = 0) (
+  parameter   IQCORRECTION_DISABLE = 0
+) (
 
   // dac interface
 
@@ -119,7 +120,8 @@ module axi_ad9361_tx #(
   input           up_rreq,
   input   [13:0]  up_raddr,
   output  [31:0]  up_rdata,
-  output          up_rack);
+  output          up_rack
+);
 
   // configuration settings
 
@@ -227,8 +229,8 @@ module axi_ad9361_tx #(
     .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
     .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
     .USERPORTS_DISABLE (USERPORTS_DISABLE),
-    .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
-  i_tx_channel_0 (
+    .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)
+  ) i_tx_channel_0 (
     .dac_clk (dac_clk),
     .dac_rst (dac_rst),
     .dac_valid (dac_valid_int),
@@ -262,8 +264,8 @@ module axi_ad9361_tx #(
     .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
     .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
     .USERPORTS_DISABLE (USERPORTS_DISABLE),
-    .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
-  i_tx_channel_1 (
+    .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)
+  ) i_tx_channel_1 (
     .dac_clk (dac_clk),
     .dac_rst (dac_rst),
     .dac_valid (dac_valid_int),
@@ -297,8 +299,8 @@ module axi_ad9361_tx #(
     .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
     .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
     .USERPORTS_DISABLE (USERPORTS_DISABLE),
-    .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
-  i_tx_channel_2 (
+    .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)
+  ) i_tx_channel_2 (
     .dac_clk (dac_clk),
     .dac_rst (dac_rst),
     .dac_valid (dac_valid_int),
@@ -332,8 +334,8 @@ module axi_ad9361_tx #(
     .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
     .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
     .USERPORTS_DISABLE (USERPORTS_DISABLE),
-    .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
-  i_tx_channel_3 (
+    .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)
+  ) i_tx_channel_3 (
     .dac_clk (dac_clk),
     .dac_rst (dac_rst),
     .dac_valid (dac_valid_int),
@@ -368,8 +370,8 @@ module axi_ad9361_tx #(
     .CLK_EDGE_SEL (CLK_EDGE_SEL),
     .DRP_DISABLE (1),
     .USERPORTS_DISABLE (USERPORTS_DISABLE),
-    .GPIO_DISABLE (0))
-  i_up_dac_common (
+    .GPIO_DISABLE (0)
+  ) i_up_dac_common (
     .mmcm_rst (),
     .dac_clk (dac_clk),
     .dac_rst (dac_rst),
@@ -419,8 +421,8 @@ module axi_ad9361_tx #(
     .DISABLE (DELAYCNTRL_DISABLE),
     .INIT_DELAY (INIT_DELAY),
     .DATA_WIDTH(16),
-    .BASE_ADDRESS(6'h12))
-  i_delay_cntrl (
+    .BASE_ADDRESS(6'h12)
+  ) i_delay_cntrl (
     .delay_clk (delay_clk),
     .delay_rst (delay_rst),
     .delay_locked (delay_locked),
@@ -439,6 +441,3 @@ module axi_ad9361_tx #(
     .up_rack (up_rack_s[5]));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_ad9361/axi_ad9361_tx_channel.v b/library/axi_ad9361/axi_ad9361_tx_channel.v
index f85d7588f..f66c2af42 100644
--- a/library/axi_ad9361/axi_ad9361_tx_channel.v
+++ b/library/axi_ad9361/axi_ad9361_tx_channel.v
@@ -47,7 +47,8 @@ module axi_ad9361_tx_channel #(
   parameter   DAC_DDS_CORDIC_DW = 14,
   parameter   DAC_DDS_CORDIC_PHASE_DW = 13,
   parameter   USERPORTS_DISABLE = 0,
-  parameter   IQCORRECTION_DISABLE = 0) (
+  parameter   IQCORRECTION_DISABLE = 0
+) (
 
   // dac interface
 
@@ -77,7 +78,8 @@ module axi_ad9361_tx_channel #(
   input           up_rreq,
   input   [13:0]  up_raddr,
   output  [31:0]  up_rdata,
-  output          up_rack);
+  output          up_rack
+);
 
   // parameters
 
@@ -258,8 +260,8 @@ module axi_ad9361_tx_channel #(
 
   ad_iqcor #(
     .Q_OR_I_N (Q_OR_I_N),
-    .DISABLE (IQCORRECTION_DISABLE))
-  i_ad_iqcor (
+    .DISABLE (IQCORRECTION_DISABLE)
+  ) i_ad_iqcor (
     .clk (dac_clk),
     .valid (dac_valid),
     .data_in ({dac_data_out_int, 4'd0}),
@@ -323,8 +325,8 @@ module axi_ad9361_tx_channel #(
     .DDS_TYPE (DAC_DDS_TYPE),
     .CORDIC_DW (DAC_DDS_CORDIC_DW),
     .CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
-    .CLK_RATIO (1))
-  i_dds (
+    .CLK_RATIO (1)
+  ) i_dds (
     .clk (dac_clk),
     .dac_dds_format (dac_dds_format),
     .dac_data_sync (dac_data_sync),
@@ -348,8 +350,8 @@ module axi_ad9361_tx_channel #(
     .CHANNEL_ID (CHANNEL_ID),
     .DDS_DISABLE (DAC_DDS_DISABLE),
     .USERPORTS_DISABLE (USERPORTS_DISABLE),
-    .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
-  i_up_dac_channel (
+    .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)
+  ) i_up_dac_channel (
     .dac_clk (dac_clk),
     .dac_rst (dac_rst),
     .dac_dds_scale_1 (dac_dds_scale_1_s),
@@ -391,6 +393,3 @@ module axi_ad9361_tx_channel #(
     .up_rack (up_rack_s));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_ad9361/intel/axi_ad9361_alt_lvds_rx.v b/library/axi_ad9361/intel/axi_ad9361_alt_lvds_rx.v
index dd26c3496..01b3cdff1 100644
--- a/library/axi_ad9361/intel/axi_ad9361_alt_lvds_rx.v
+++ b/library/axi_ad9361/intel/axi_ad9361_alt_lvds_rx.v
@@ -54,7 +54,8 @@ module axi_ad9361_alt_lvds_rx (
   output  [ 5:0]  rx_data_1,
   output  [ 5:0]  rx_data_2,
   output  [ 5:0]  rx_data_3,
-  output          rx_locked);
+  output          rx_locked
+);
 
   // internal signals
 
diff --git a/library/axi_ad9361/intel/axi_ad9361_alt_lvds_tx.v b/library/axi_ad9361/intel/axi_ad9361_alt_lvds_tx.v
index ad6aac865..5a8aa3a78 100644
--- a/library/axi_ad9361/intel/axi_ad9361_alt_lvds_tx.v
+++ b/library/axi_ad9361/intel/axi_ad9361_alt_lvds_tx.v
@@ -55,7 +55,8 @@ module axi_ad9361_alt_lvds_tx (
   input   [ 5:0]  tx_data_1,
   input   [ 5:0]  tx_data_2,
   input   [ 5:0]  tx_data_3,
-  output          tx_locked);
+  output          tx_locked
+);
 
   // internal registers
 
diff --git a/library/axi_ad9361/intel/axi_ad9361_cmos_if.v b/library/axi_ad9361/intel/axi_ad9361_cmos_if.v
index b95e6e9f9..138eba27d 100644
--- a/library/axi_ad9361/intel/axi_ad9361_cmos_if.v
+++ b/library/axi_ad9361/intel/axi_ad9361_cmos_if.v
@@ -45,7 +45,8 @@ module axi_ad9361_cmos_if #(
   // Dummy parameters, required keep the code consistency(used on Xilinx)
   parameter   IO_DELAY_GROUP = "dev_if_delay_group",
   parameter   IODELAY_CTRL = 1,
-  parameter   DELAY_REFCLK_FREQUENCY = 0) (
+  parameter   DELAY_REFCLK_FREQUENCY = 0
+) (
 
   // physical interface (receive)
 
@@ -116,7 +117,8 @@ module axi_ad9361_cmos_if #(
   input   [31:0]      up_drp_wdata,
   output  [31:0]      up_drp_rdata,
   output              up_drp_ready,
-  output              up_drp_locked);
+  output              up_drp_locked
+);
 
   // cmos is not supported on intel platforms yet.
 
@@ -137,6 +139,3 @@ module axi_ad9361_cmos_if #(
   assign up_drp_locked = 1'd0;
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_ad9361/intel/axi_ad9361_lvds_if.v b/library/axi_ad9361/intel/axi_ad9361_lvds_if.v
index 573fc915e..68d494d17 100644
--- a/library/axi_ad9361/intel/axi_ad9361_lvds_if.v
+++ b/library/axi_ad9361/intel/axi_ad9361_lvds_if.v
@@ -46,7 +46,8 @@ module axi_ad9361_lvds_if #(
   parameter   IO_DELAY_GROUP = "dev_if_delay_group",
   parameter   IODELAY_CTRL = 1,
   parameter   DELAY_REFCLK_FREQUENCY = 0,
-  parameter   RX_NODPA = 0) (
+  parameter   RX_NODPA = 0
+) (
 
   // physical interface (receive)
 
@@ -123,7 +124,8 @@ module axi_ad9361_lvds_if #(
   input   [31:0]      up_drp_wdata,
   output  [31:0]      up_drp_rdata,
   output              up_drp_ready,
-  output              up_drp_locked);
+  output              up_drp_locked
+);
 
   // internal registers
 
@@ -218,7 +220,7 @@ module axi_ad9361_lvds_if #(
     end
 
   end
-endgenerate
+  endgenerate
 
   // frame check
 
@@ -531,8 +533,8 @@ endgenerate
   generate
   if (FPGA_TECHNOLOGY == ARRIA10) begin
   axi_ad9361_lvds_if_10 #(
-    .RX_NODPA (RX_NODPA))
-  i_axi_ad9361_lvds_if_10 (
+    .RX_NODPA (RX_NODPA)
+  ) i_axi_ad9361_lvds_if_10 (
     .rx_clk_in_p (rx_clk_in_p),
     .rx_clk_in_n (rx_clk_in_n),
     .rx_frame_in_p (rx_frame_in_p),
@@ -567,6 +569,3 @@ endgenerate
   endgenerate
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_ad9361/intel/axi_ad9361_lvds_if_10.v b/library/axi_ad9361/intel/axi_ad9361_lvds_if_10.v
index 830d97b03..b546f3da9 100644
--- a/library/axi_ad9361/intel/axi_ad9361_lvds_if_10.v
+++ b/library/axi_ad9361/intel/axi_ad9361_lvds_if_10.v
@@ -37,7 +37,8 @@
 
 module axi_ad9361_lvds_if_10  #(
 
-  parameter   RX_NODPA = 0) (
+  parameter   RX_NODPA = 0
+) (
 
   // physical interface (receive)
 
@@ -91,7 +92,8 @@ module axi_ad9361_lvds_if_10  #(
   // delay interface
 
   input               up_clk,
-  input               up_rstn);
+  input               up_rstn
+);
 
   // internal registers
 
@@ -236,7 +238,7 @@ module axi_ad9361_lvds_if_10  #(
         .data_s_export (rx_data_s[27:24]),
         .delay_locked_export (rx_delay_locked_s[6]));
 
-     assign rx_clk = rx_clk_in_p;
+      assign rx_clk = rx_clk_in_p;
 
     end else begin
 
@@ -302,6 +304,3 @@ module axi_ad9361_lvds_if_10  #(
     .ls_clk_clk (clk));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_ad9361/intel/axi_ad9361_lvds_if_c5.v b/library/axi_ad9361/intel/axi_ad9361_lvds_if_c5.v
index cc811bf8c..8af649fe6 100644
--- a/library/axi_ad9361/intel/axi_ad9361_lvds_if_c5.v
+++ b/library/axi_ad9361/intel/axi_ad9361_lvds_if_c5.v
@@ -89,7 +89,8 @@ module axi_ad9361_lvds_if_c5 (
   // delay interface
 
   input               up_clk,
-  input               up_rstn);
+  input               up_rstn
+);
 
   // internal registers
 
@@ -392,6 +393,3 @@ module axi_ad9361_lvds_if_c5 (
     .sset (1'b0));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_ad9361/xilinx/axi_ad9361_cmos_if.v b/library/axi_ad9361/xilinx/axi_ad9361_cmos_if.v
index 2d912e92b..e7a5cac4e 100644
--- a/library/axi_ad9361/xilinx/axi_ad9361_cmos_if.v
+++ b/library/axi_ad9361/xilinx/axi_ad9361_cmos_if.v
@@ -43,7 +43,8 @@ module axi_ad9361_cmos_if #(
   parameter   IODELAY_CTRL = 1,
   parameter   CLK_DESKEW = 0,
   parameter   USE_SSI_CLK = 1,
-  parameter   DELAY_REFCLK_FREQUENCY = 200) (
+  parameter   DELAY_REFCLK_FREQUENCY = 200
+) (
 
   // physical interface (receive)
 
@@ -114,7 +115,8 @@ module axi_ad9361_cmos_if #(
   input   [31:0]      up_drp_wdata,
   output  [31:0]      up_drp_rdata,
   output              up_drp_ready,
-  output              up_drp_locked);
+  output              up_drp_locked
+);
 
   // internal registers
 
@@ -439,8 +441,8 @@ module axi_ad9361_cmos_if #(
     .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
     .IODELAY_CTRL (0),
     .IODELAY_GROUP (IO_DELAY_GROUP),
-    .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
-  i_rx_data (
+    .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
+  ) i_rx_data (
     .rx_clk (l_clk),
     .rx_data_in_p (rx_data_in[i]),
     .rx_data_in_n (1'd0),
@@ -463,8 +465,8 @@ module axi_ad9361_cmos_if #(
     .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
     .IODELAY_CTRL (IODELAY_CTRL),
     .IODELAY_GROUP (IO_DELAY_GROUP),
-    .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
-  i_rx_frame (
+    .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
+  ) i_rx_frame (
     .rx_clk (l_clk),
     .rx_data_in_p (rx_frame_in),
     .rx_data_in_n (1'd0),
@@ -488,8 +490,8 @@ module axi_ad9361_cmos_if #(
     .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
     .IODELAY_CTRL (0),
     .IODELAY_GROUP (IO_DELAY_GROUP),
-    .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
-  i_tx_data (
+    .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
+  ) i_tx_data (
     .tx_clk (l_clk),
     .tx_data_p (tx_data_1[i]),
     .tx_data_n (tx_data_0[i]),
@@ -513,8 +515,8 @@ module axi_ad9361_cmos_if #(
     .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
     .IODELAY_CTRL (0),
     .IODELAY_GROUP (IO_DELAY_GROUP),
-    .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
-  i_tx_frame (
+    .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
+  ) i_tx_frame (
     .tx_clk (l_clk),
     .tx_data_p (tx_frame[1]),
     .tx_data_n (tx_frame[0]),
@@ -536,8 +538,8 @@ module axi_ad9361_cmos_if #(
     .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
     .IODELAY_CTRL (0),
     .IODELAY_GROUP (IO_DELAY_GROUP),
-    .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
-  i_tx_clk (
+    .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
+  ) i_tx_clk (
     .tx_clk (l_clk),
     .tx_data_p (tx_clk[1]),
     .tx_data_n (tx_clk[0]),
@@ -559,8 +561,8 @@ module axi_ad9361_cmos_if #(
     .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
     .IODELAY_CTRL (0),
     .IODELAY_GROUP (IO_DELAY_GROUP),
-    .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
-  i_enable (
+    .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
+  ) i_enable (
     .tx_clk (l_clk),
     .tx_data_p (enable_int_p),
     .tx_data_n (enable_int_p),
@@ -582,8 +584,8 @@ module axi_ad9361_cmos_if #(
     .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
     .IODELAY_CTRL (0),
     .IODELAY_GROUP (IO_DELAY_GROUP),
-    .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
-  i_txnrx (
+    .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
+  ) i_txnrx (
     .tx_clk (l_clk),
     .tx_data_p (txnrx_int_p),
     .tx_data_n (txnrx_int_p),
@@ -601,8 +603,8 @@ module axi_ad9361_cmos_if #(
 
   generate if (USE_SSI_CLK == 1) begin
   ad_data_clk #(
-    .SINGLE_ENDED (1))
-  i_clk (
+    .SINGLE_ENDED (1)
+  ) i_clk (
     .rst (1'd0),
     .locked (),
     .clk_in_p (rx_clk_in),
@@ -614,6 +616,3 @@ module axi_ad9361_cmos_if #(
   endgenerate
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v b/library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v
index 7ab781910..ec772f6cc 100644
--- a/library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v
+++ b/library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v
@@ -44,7 +44,8 @@ module axi_ad9361_lvds_if #(
   parameter   CLK_DESKEW = 0,
   parameter   USE_SSI_CLK = 1,
   parameter   DELAY_REFCLK_FREQUENCY = 200,
-  parameter   RX_NODPA = 0) (
+  parameter   RX_NODPA = 0
+) (
 
   // physical interface (receive)
 
@@ -121,7 +122,8 @@ module axi_ad9361_lvds_if #(
   input   [31:0]      up_drp_wdata,
   output  [31:0]      up_drp_rdata,
   output              up_drp_ready,
-  output              up_drp_locked);
+  output              up_drp_locked
+);
 
   // internal registers
 
@@ -213,7 +215,6 @@ module axi_ad9361_lvds_if #(
 
   // frame check
 
-
   // delineation
   reg             rx_error_r1 = 'd0;
   reg             rx_error_r2 = 'd0;
@@ -454,8 +455,8 @@ module axi_ad9361_lvds_if #(
     .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
     .IODELAY_CTRL (0),
     .IODELAY_GROUP (IO_DELAY_GROUP),
-    .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
-  i_rx_data (
+    .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
+  ) i_rx_data (
     .rx_clk (l_clk),
     .rx_data_in_p (rx_data_in_p[i]),
     .rx_data_in_n (rx_data_in_n[i]),
@@ -477,8 +478,8 @@ module axi_ad9361_lvds_if #(
     .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
     .IODELAY_CTRL (IODELAY_CTRL),
     .IODELAY_GROUP (IO_DELAY_GROUP),
-    .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
-  i_rx_frame (
+    .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
+  ) i_rx_frame (
     .rx_clk (l_clk),
     .rx_data_in_p (rx_frame_in_p),
     .rx_data_in_n (rx_frame_in_n),
@@ -501,8 +502,8 @@ module axi_ad9361_lvds_if #(
     .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
     .IODELAY_CTRL (0),
     .IODELAY_GROUP (IO_DELAY_GROUP),
-    .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
-  i_tx_data (
+    .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
+  ) i_tx_data (
     .tx_clk (l_clk),
     .tx_data_p (tx_data_1[i]),
     .tx_data_n (tx_data_0[i]),
@@ -525,8 +526,8 @@ module axi_ad9361_lvds_if #(
     .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
     .IODELAY_CTRL (0),
     .IODELAY_GROUP (IO_DELAY_GROUP),
-    .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
-  i_tx_frame (
+    .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
+  ) i_tx_frame (
     .tx_clk (l_clk),
     .tx_data_p (tx_frame),
     .tx_data_n (tx_frame),
@@ -547,8 +548,8 @@ module axi_ad9361_lvds_if #(
     .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
     .IODELAY_CTRL (0),
     .IODELAY_GROUP (IO_DELAY_GROUP),
-    .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
-  i_tx_clk (
+    .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
+  ) i_tx_clk (
     .tx_clk (l_clk),
     .tx_data_p (tx_clk[1]),
     .tx_data_n (tx_clk[0]),
@@ -570,8 +571,8 @@ module axi_ad9361_lvds_if #(
     .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
     .IODELAY_CTRL (0),
     .IODELAY_GROUP (IO_DELAY_GROUP),
-    .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
-  i_enable (
+    .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
+  ) i_enable (
     .tx_clk (l_clk),
     .tx_data_p (enable_int_p),
     .tx_data_n (enable_int_p),
@@ -593,8 +594,8 @@ module axi_ad9361_lvds_if #(
     .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
     .IODELAY_CTRL (0),
     .IODELAY_GROUP (IO_DELAY_GROUP),
-    .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
-  i_txnrx (
+    .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
+  ) i_txnrx (
     .tx_clk (l_clk),
     .tx_data_p (txnrx_int_p),
     .tx_data_n (txnrx_int_p),
@@ -610,8 +611,7 @@ module axi_ad9361_lvds_if #(
 
   // device clock interface (receive clock)
   generate if (USE_SSI_CLK == 1) begin
-  ad_data_clk
-  i_clk (
+  ad_data_clk i_clk (
     .rst (1'd0),
     .locked (),
     .clk_in_p (rx_clk_in_p),
@@ -623,6 +623,3 @@ module axi_ad9361_lvds_if #(
   endgenerate
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_ad9434/axi_ad9434.v b/library/axi_ad9434/axi_ad9434.v
index 15980fd1b..232220501 100644
--- a/library/axi_ad9434/axi_ad9434.v
+++ b/library/axi_ad9434/axi_ad9434.v
@@ -43,7 +43,8 @@ module axi_ad9434 #(
   parameter FPGA_FAMILY = 0,
   parameter SPEED_GRADE = 0,
   parameter DEV_PACKAGE = 0,
-  parameter IO_DELAY_GROUP = "dev_if_delay_group") (
+  parameter IO_DELAY_GROUP = "dev_if_delay_group"
+) (
 
   // physical interface
   input                   adc_clk_in_p,
@@ -84,7 +85,8 @@ module axi_ad9434 #(
   output      [31:0]      s_axi_rdata,
   input                   s_axi_rready,
   input       [ 2:0]      s_axi_awprot,
-  input       [ 2:0]      s_axi_arprot);
+  input       [ 2:0]      s_axi_arprot
+);
 
   // internal clocks & resets
   wire            adc_rst;
@@ -131,8 +133,8 @@ module axi_ad9434 #(
 
   axi_ad9434_if #(
     .FPGA_TECHNOLOGY(FPGA_TECHNOLOGY),
-    .IO_DELAY_GROUP(IO_DELAY_GROUP))
-  i_if(
+    .IO_DELAY_GROUP(IO_DELAY_GROUP)
+  ) i_if (
     .adc_clk_in_p(adc_clk_in_p),
     .adc_clk_in_n(adc_clk_in_n),
     .adc_data_in_p(adc_data_in_p),
diff --git a/library/axi_ad9434/axi_ad9434_core.v b/library/axi_ad9434/axi_ad9434_core.v
index 182edc429..2a1eb26a8 100644
--- a/library/axi_ad9434/axi_ad9434_core.v
+++ b/library/axi_ad9434/axi_ad9434_core.v
@@ -41,7 +41,8 @@ module axi_ad9434_core #(
   parameter FPGA_TECHNOLOGY = 0,
   parameter FPGA_FAMILY = 0,
   parameter SPEED_GRADE = 0,
-  parameter DEV_PACKAGE = 0) (
+  parameter DEV_PACKAGE = 0
+) (
 
   // device interface
 
@@ -92,7 +93,8 @@ module axi_ad9434_core #(
   output                  mmcm_rst,
   output                  adc_rst,
   output                  adc_enable,
-  input                   adc_status);
+  input                   adc_status
+);
 
   // internal signals
   wire            up_status_pn_err_s;
@@ -122,17 +124,17 @@ module axi_ad9434_core #(
   genvar n;
   generate
   for (n = 0; n < 4; n = n + 1) begin: g_ad_dfmt
-   ad_datafmt # (
-    .DATA_WIDTH(12))
-  i_datafmt (
-    .clk (adc_clk),
-    .valid (1'b1),
-    .data (adc_data[n*12+11:n*12]),
-    .valid_out (dma_dvalid),
-    .data_out (dma_data[n*16+15:n*16]),
-    .dfmt_enable (adc_dfmt_enable_s),
-    .dfmt_type (adc_dfmt_type_s),
-    .dfmt_se (adc_dfmt_se_s));
+    ad_datafmt #(
+      .DATA_WIDTH(12)
+    ) i_datafmt (
+      .clk (adc_clk),
+      .valid (1'b1),
+      .data (adc_data[n*12+11:n*12]),
+      .valid_out (dma_dvalid),
+      .data_out (dma_data[n*16+15:n*16]),
+      .dfmt_enable (adc_dfmt_enable_s),
+      .dfmt_type (adc_dfmt_type_s),
+      .dfmt_se (adc_dfmt_se_s));
   end
   endgenerate
 
@@ -161,8 +163,8 @@ module axi_ad9434_core #(
     .DRP_DISABLE(0),
     .USERPORTS_DISABLE(1),
     .GPIO_DISABLE(1),
-    .START_CODE_DISABLE(1))
-  i_adc_common(
+    .START_CODE_DISABLE(1)
+  ) i_adc_common(
     .mmcm_rst (mmcm_rst),
 
     .adc_clk (adc_clk),
@@ -216,8 +218,8 @@ module axi_ad9434_core #(
     .USERPORTS_DISABLE(1),
     .DATAFORMAT_DISABLE(0),
     .DCFILTER_DISABLE(1),
-    .IQCORRECTION_DISABLE(1))
-  i_adc_channel(
+    .IQCORRECTION_DISABLE(1)
+  ) i_adc_channel(
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
     .adc_enable (adc_enable),
@@ -265,7 +267,10 @@ module axi_ad9434_core #(
 
   // adc delay control
 
-  up_delay_cntrl #(.DATA_WIDTH(13), .BASE_ADDRESS(6'h02)) i_delay_cntrl (
+  up_delay_cntrl #(
+    .DATA_WIDTH(13),
+    .BASE_ADDRESS(6'h02)
+  ) i_delay_cntrl (
     .delay_clk (delay_clk),
     .delay_rst (delay_rst),
     .delay_locked (delay_locked),
diff --git a/library/axi_ad9434/axi_ad9434_if.v b/library/axi_ad9434/axi_ad9434_if.v
index 5dbd05f66..ea42a59ca 100644
--- a/library/axi_ad9434/axi_ad9434_if.v
+++ b/library/axi_ad9434/axi_ad9434_if.v
@@ -38,7 +38,8 @@
 module axi_ad9434_if #(
 
   parameter FPGA_TECHNOLOGY = 0,
-  parameter IO_DELAY_GROUP = "dev_if_delay_group") (
+  parameter IO_DELAY_GROUP = "dev_if_delay_group"
+) (
 
   // device interface
   input                   adc_clk_in_p,
@@ -77,8 +78,8 @@ module axi_ad9434_if #(
   input       [31:0]      up_drp_wdata,
   output      [31:0]      up_drp_rdata,
   output                  up_drp_ready,
-  output                  up_drp_locked);
-
+  output                  up_drp_locked
+);
 
   localparam SDR = 0;
 
@@ -105,8 +106,8 @@ module axi_ad9434_if #(
     .IODELAY_GROUP(IO_DELAY_GROUP),
     .DDR_OR_SDR_N(SDR),
     .DATA_WIDTH(12),
-    .SERDES_FACTOR(4))
-  i_adc_data (
+    .SERDES_FACTOR(4)
+  ) i_adc_data (
     .rst(adc_rst),
     .clk(adc_clk_in),
     .div_clk(adc_div_clk),
@@ -138,8 +139,8 @@ module axi_ad9434_if #(
     .IODELAY_GROUP(IO_DELAY_GROUP),
     .DDR_OR_SDR_N(SDR),
     .DATA_WIDTH(1),
-    .SERDES_FACTOR(4))
-  i_adc_or (
+    .SERDES_FACTOR(4)
+  ) i_adc_or (
     .rst(adc_rst),
     .clk(adc_clk_in),
     .div_clk(adc_div_clk),
@@ -174,8 +175,8 @@ module axi_ad9434_if #(
     .MMCM_VCO_MUL (12),
     .MMCM_CLK0_DIV (2),
     .MMCM_CLK1_DIV (8),
-    .SERDES_FACTOR(4))
-  i_serdes_clk (
+    .SERDES_FACTOR(4)
+  ) i_serdes_clk (
     .rst (mmcm_rst),
     .clk_in_p (adc_clk_in_p),
     .clk_in_n (adc_clk_in_n),
diff --git a/library/axi_ad9434/axi_ad9434_pnmon.v b/library/axi_ad9434/axi_ad9434_pnmon.v
index 20abc7a35..2fcbaac2b 100644
--- a/library/axi_ad9434/axi_ad9434_pnmon.v
+++ b/library/axi_ad9434/axi_ad9434_pnmon.v
@@ -44,7 +44,8 @@ module axi_ad9434_pnmon (
   // pn interface
   input       [ 3:0]      adc_pnseq_sel,
   output                  adc_pn_err,
-  output                  adc_pn_oos);
+  output                  adc_pn_oos
+);
 
   // internal registers
   reg     [47:0]  adc_pn_data_pn = 'd0;
@@ -181,7 +182,9 @@ module axi_ad9434_pnmon (
   end
 
   // pn oos & pn err
-  ad_pnmon #(.DATA_WIDTH(48)) i_pnmon (
+  ad_pnmon #(
+    .DATA_WIDTH(48)
+  ) i_pnmon (
     .adc_clk (adc_clk),
     .adc_valid_in (1'b1),
     .adc_data_in (adc_data_inv_s),
diff --git a/library/axi_ad9467/axi_ad9467.v b/library/axi_ad9467/axi_ad9467.v
index 9cd004c31..f82021ddd 100644
--- a/library/axi_ad9467/axi_ad9467.v
+++ b/library/axi_ad9467/axi_ad9467.v
@@ -43,7 +43,8 @@ module axi_ad9467#(
   parameter   SPEED_GRADE = 0,
   parameter   DEV_PACKAGE = 0,
   parameter   IO_DELAY_GROUP = "dev_if_delay_group",
-  parameter   DELAY_REFCLK_FREQUENCY = 200) (
+  parameter   DELAY_REFCLK_FREQUENCY = 200
+) (
 
   // physical interface
 
@@ -88,8 +89,8 @@ module axi_ad9467#(
   output                  s_axi_rvalid,
   output      [ 1:0]      s_axi_rresp,
   output      [31:0]      s_axi_rdata,
-  input                   s_axi_rready);
-
+  input                   s_axi_rready
+);
 
   // internal registers
 
@@ -150,8 +151,8 @@ module axi_ad9467#(
   axi_ad9467_if #(
     .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
     .IO_DELAY_GROUP (IO_DELAY_GROUP),
-    .DELAY_REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
-  i_if (
+    .DELAY_REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
+  ) i_if (
     .adc_clk_in_p (adc_clk_in_p),
     .adc_clk_in_n (adc_clk_in_n),
     .adc_data_in_p (adc_data_in_p),
@@ -172,7 +173,9 @@ module axi_ad9467#(
 
   // channel
 
-  axi_ad9467_channel #(.CHANNEL_ID(0)) i_channel (
+  axi_ad9467_channel #(
+    .CHANNEL_ID(0)
+  ) i_channel (
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
     .adc_data (adc_data_s),
@@ -195,7 +198,10 @@ module axi_ad9467#(
 
   // adc delay control
 
-  up_delay_cntrl #(.DATA_WIDTH(9), .BASE_ADDRESS(6'h02)) i_delay_cntrl (
+  up_delay_cntrl #(
+    .DATA_WIDTH(9),
+    .BASE_ADDRESS(6'h02)
+  ) i_delay_cntrl (
     .delay_clk (delay_clk),
     .delay_rst (delay_rst),
     .delay_locked (delay_locked_s),
@@ -226,8 +232,8 @@ module axi_ad9467#(
     .DRP_DISABLE (6'h00),
     .USERPORTS_DISABLE (0),
     .GPIO_DISABLE (0),
-    .START_CODE_DISABLE(0))
-  i_up_adc_common (
+    .START_CODE_DISABLE(0)
+  ) i_up_adc_common (
     .mmcm_rst (),
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
@@ -305,6 +311,3 @@ module axi_ad9467#(
     .up_rack (up_rack));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_ad9467/axi_ad9467_channel.v b/library/axi_ad9467/axi_ad9467_channel.v
index 5c94affa1..a3ff337eb 100644
--- a/library/axi_ad9467/axi_ad9467_channel.v
+++ b/library/axi_ad9467/axi_ad9467_channel.v
@@ -37,7 +37,8 @@
 
 module axi_ad9467_channel#(
 
-  parameter CHANNEL_ID = 0) (
+  parameter CHANNEL_ID = 0
+) (
 
   // adc interface
 
@@ -65,8 +66,8 @@ module axi_ad9467_channel#(
   input                   up_rreq,
   input       [13:0]      up_raddr,
   output      [31:0]      up_rdata,
-  output                  up_rack);
-
+  output                  up_rack
+);
 
   // internal signals
 
@@ -86,7 +87,9 @@ module axi_ad9467_channel#(
     .adc_pn_err (adc_pn_err_s),
     .adc_pnseq_sel (adc_pnseq_sel_s));
 
-  ad_datafmt #(.DATA_WIDTH(16)) i_datafmt (
+  ad_datafmt #(
+    .DATA_WIDTH(16)
+  ) i_datafmt (
     .clk(adc_clk),
     .valid(1'b1),
     .data(adc_data),
@@ -102,8 +105,8 @@ module axi_ad9467_channel#(
     .USERPORTS_DISABLE (0),
     .DATAFORMAT_DISABLE (0),
     .DCFILTER_DISABLE (0),
-    .IQCORRECTION_DISABLE (0))
-  i_up_adc_channel (
+    .IQCORRECTION_DISABLE (0)
+  ) i_up_adc_channel (
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
     .adc_enable (adc_enable),
@@ -150,6 +153,3 @@ module axi_ad9467_channel#(
     .up_rack (up_rack));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_ad9467/axi_ad9467_if.v b/library/axi_ad9467/axi_ad9467_if.v
index b5256a5ec..b370abcbb 100644
--- a/library/axi_ad9467/axi_ad9467_if.v
+++ b/library/axi_ad9467/axi_ad9467_if.v
@@ -40,7 +40,8 @@ module axi_ad9467_if #(
 
   parameter FPGA_TECHNOLOGY = 0,
   parameter IO_DELAY_GROUP = "dev_if_delay_group",
-  parameter DELAY_REFCLK_FREQUENCY = 200) (
+  parameter DELAY_REFCLK_FREQUENCY = 200
+) (
 
   // adc interface (clk, data, over-range)
 
@@ -69,8 +70,8 @@ module axi_ad9467_if #(
   output      [44:0]      up_drdata,
   input                   delay_clk,
   input                   delay_rst,
-  output                  delay_locked);
-
+  output                  delay_locked
+);
 
   // internal registers
 
@@ -132,8 +133,8 @@ module axi_ad9467_if #(
     .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
     .IODELAY_CTRL (0),
     .IODELAY_GROUP (IO_DELAY_GROUP),
-    .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
-  i_adc_data (
+    .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
+  ) i_adc_data (
     .rx_clk (adc_clk),
     .rx_data_in_p (adc_data_in_p[l_inst]),
     .rx_data_in_n (adc_data_in_n[l_inst]),
@@ -155,8 +156,8 @@ module axi_ad9467_if #(
     .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
     .IODELAY_CTRL (1),
     .IODELAY_GROUP (IO_DELAY_GROUP),
-    .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
-  i_adc_or (
+    .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
+  ) i_adc_or (
     .rx_clk (adc_clk),
     .rx_data_in_p (adc_or_in_p),
     .rx_data_in_n (adc_or_in_n),
@@ -172,8 +173,7 @@ module axi_ad9467_if #(
 
   // clock
 
-  ad_data_clk
-  i_adc_clk (
+  ad_data_clk i_adc_clk (
     .rst (1'b0),
     .locked (),
     .clk_in_p (adc_clk_in_p),
@@ -181,6 +181,3 @@ module axi_ad9467_if #(
     .clk (adc_clk));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_ad9467/axi_ad9467_pnmon.v b/library/axi_ad9467/axi_ad9467_pnmon.v
index 5b059baaf..ecb39d317 100644
--- a/library/axi_ad9467/axi_ad9467_pnmon.v
+++ b/library/axi_ad9467/axi_ad9467_pnmon.v
@@ -47,7 +47,8 @@ module axi_ad9467_pnmon (
 
   output                  adc_pn_oos,
   output                  adc_pn_err,
-  input       [ 3:0]      adc_pnseq_sel);
+  input       [ 3:0]      adc_pnseq_sel
+);
 
   // internal registers
 
@@ -161,7 +162,9 @@ module axi_ad9467_pnmon (
 
   // pn oos & pn err
 
-  ad_pnmon #(.DATA_WIDTH(32)) i_pnmon (
+  ad_pnmon #(
+    .DATA_WIDTH(32)
+  ) i_pnmon (
     .adc_clk (adc_clk),
     .adc_valid_in (adc_valid_in),
     .adc_data_in (adc_pn_data_in),
@@ -171,7 +174,3 @@ module axi_ad9467_pnmon (
     .adc_pn_err (adc_pn_err));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
-
diff --git a/library/axi_ad9625/axi_ad9625.v b/library/axi_ad9625/axi_ad9625.v
index f272254a3..53f6be507 100644
--- a/library/axi_ad9625/axi_ad9625.v
+++ b/library/axi_ad9625/axi_ad9625.v
@@ -42,7 +42,8 @@ module axi_ad9625 #(
   parameter FPGA_FAMILY = 0,
   parameter SPEED_GRADE = 0,
   parameter DEV_PACKAGE = 0,
-  parameter DELAY_REFCLK_FREQUENCY = 200) (
+  parameter DELAY_REFCLK_FREQUENCY = 200
+) (
 
   // jesd interface
   // rx_clk is (line-rate/40)
@@ -87,7 +88,8 @@ module axi_ad9625 #(
   output      [ 31:0]     s_axi_rdata,
   input                   s_axi_rready,
   input       [  2:0]     s_axi_awprot,
-  input       [  2:0]     s_axi_arprot);
+  input       [  2:0]     s_axi_arprot
+);
 
   // internal registers
 
@@ -143,8 +145,8 @@ module axi_ad9625 #(
   assign adc_valid = 1'b1;
 
   axi_ad9625_if #(
-    .ID (ID))
-  i_if (
+    .ID (ID)
+  ) i_if (
     .rx_clk (rx_clk),
     .rx_sof (rx_sof),
     .rx_data (rx_data),
@@ -194,8 +196,8 @@ module axi_ad9625 #(
     .DRP_DISABLE(1),
     .USERPORTS_DISABLE(1),
     .GPIO_DISABLE(1),
-    .START_CODE_DISABLE(1))
-  i_up_adc_common (
+    .START_CODE_DISABLE(1)
+  ) i_up_adc_common (
     .mmcm_rst (),
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
@@ -270,7 +272,3 @@ module axi_ad9625 #(
     .up_rack (up_rack));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
-
diff --git a/library/axi_ad9625/axi_ad9625_channel.v b/library/axi_ad9625/axi_ad9625_channel.v
index f06774add..bc1fa5d7c 100644
--- a/library/axi_ad9625/axi_ad9625_channel.v
+++ b/library/axi_ad9625/axi_ad9625_channel.v
@@ -63,7 +63,8 @@ module axi_ad9625_channel (
   input                   up_rreq,
   input       [ 13:0]     up_raddr,
   output      [ 31:0]     up_rdata,
-  output                  up_rack);
+  output                  up_rack
+);
 
   // internal signals
 
@@ -86,7 +87,9 @@ module axi_ad9625_channel (
   genvar n;
   generate
   for (n = 0; n < 16; n = n + 1) begin: g_ad_datafmt_1
-  ad_datafmt #(.DATA_WIDTH(12)) i_ad_datafmt (
+  ad_datafmt #(
+    .DATA_WIDTH(12)
+  ) i_ad_datafmt (
     .clk (adc_clk),
     .valid (1'b1),
     .data (adc_data[n*12+11:n*12]),
@@ -104,8 +107,8 @@ module axi_ad9625_channel (
     .USERPORTS_DISABLE(1),
     .DATAFORMAT_DISABLE(0),
     .DCFILTER_DISABLE(1),
-    .IQCORRECTION_DISABLE(1))
-  i_up_adc_channel (
+    .IQCORRECTION_DISABLE(1)
+  ) i_up_adc_channel (
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
     .adc_enable (adc_enable),
@@ -152,7 +155,3 @@ module axi_ad9625_channel (
     .up_rack (up_rack));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
-
diff --git a/library/axi_ad9625/axi_ad9625_if.v b/library/axi_ad9625/axi_ad9625_if.v
index a79e996d3..49de21a7b 100644
--- a/library/axi_ad9625/axi_ad9625_if.v
+++ b/library/axi_ad9625/axi_ad9625_if.v
@@ -37,7 +37,9 @@
 
 module axi_ad9625_if #(
 
-  parameter   ID = 0) (
+  parameter   ID = 0
+) (
+
   // jesd interface
   // rx_clk is (line-rate/40)
 
@@ -55,7 +57,8 @@ module axi_ad9625_if #(
   output      [ 15:0]     adc_sref,
   input                   adc_sref_sync,
   input       [  3:0]     adc_raddr_in,
-  output      [  3:0]     adc_raddr_out);
+  output      [  3:0]     adc_raddr_out
+);
 
   // internal registers
 
@@ -207,7 +210,10 @@ module axi_ad9625_if #(
 
   // alignment fifo
 
-  ad_mem #(.ADDRESS_WIDTH(4), .DATA_WIDTH(192)) i_mem (
+  ad_mem #(
+    .ADDRESS_WIDTH(4),
+    .DATA_WIDTH(192)
+  ) i_mem (
     .clka (rx_clk),
     .wea (1'b1),
     .addra (adc_waddr),
@@ -232,7 +238,3 @@ module axi_ad9625_if #(
   endgenerate
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
-
diff --git a/library/axi_ad9625/axi_ad9625_pnmon.v b/library/axi_ad9625/axi_ad9625_pnmon.v
index 3bd7f2be9..fcd2b1327 100644
--- a/library/axi_ad9625/axi_ad9625_pnmon.v
+++ b/library/axi_ad9625/axi_ad9625_pnmon.v
@@ -49,7 +49,8 @@ module axi_ad9625_pnmon (
 
   // processor interface PN9 (0x0), PN23 (0x1)
 
-  input       [  3:0]     adc_pnseq_sel);
+  input       [  3:0]     adc_pnseq_sel
+);
 
   // internal registers
 
@@ -494,7 +495,9 @@ module axi_ad9625_pnmon (
 
   // pn oos & pn error
 
-  ad_pnmon #(.DATA_WIDTH(192)) i_pnmon (
+  ad_pnmon #(
+    .DATA_WIDTH(192)
+  ) i_pnmon (
     .adc_clk (adc_clk),
     .adc_valid_in (1'b1),
     .adc_data_in (adc_pn_data_in),
@@ -503,7 +506,3 @@ module axi_ad9625_pnmon (
     .adc_pn_err (adc_pn_err));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
-
diff --git a/library/axi_ad9671/axi_ad9671.v b/library/axi_ad9671/axi_ad9671.v
index 93fb747f9..fb6e8c5d8 100644
--- a/library/axi_ad9671/axi_ad9671.v
+++ b/library/axi_ad9671/axi_ad9671.v
@@ -42,7 +42,8 @@ module axi_ad9671 #(
   parameter   FPGA_FAMILY = 0,
   parameter   SPEED_GRADE = 0,
   parameter   DEV_PACKAGE = 0,
-  parameter QUAD_OR_DUAL_N = 1) (
+  parameter QUAD_OR_DUAL_N = 1
+) (
 
   // jesd interface
   // rx_clk is (line-rate/40)
@@ -87,8 +88,8 @@ module axi_ad9671 #(
   output                  s_axi_rvalid,
   output      [ 1:0]      s_axi_rresp,
   output      [ 31:0]     s_axi_rdata,
-  input                   s_axi_rready);
-
+  input                   s_axi_rready
+);
 
   // internal registers
 
@@ -159,8 +160,8 @@ module axi_ad9671 #(
 
   axi_ad9671_if #(
     .QUAD_OR_DUAL_N (QUAD_OR_DUAL_N),
-    .ID (ID))
-  i_if (
+    .ID (ID)
+  )  i_if (
     .rx_clk (rx_clk),
     .rx_data (rx_data),
     .rx_sof (rx_sof),
@@ -197,7 +198,9 @@ module axi_ad9671 #(
   genvar n;
   generate
   for (n = 0; n < 8; n = n + 1) begin: g_channel
-  axi_ad9671_channel #(.CHANNEL_ID(n)) i_channel (
+  axi_ad9671_channel #(
+    .CHANNEL_ID(n)
+  ) i_channel (
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
     .adc_valid (adc_valid_s),
@@ -302,6 +305,3 @@ module axi_ad9671 #(
     .up_rack (up_rack));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_ad9671/axi_ad9671_channel.v b/library/axi_ad9671/axi_ad9671_channel.v
index 45ce9883d..d36e90d69 100644
--- a/library/axi_ad9671/axi_ad9671_channel.v
+++ b/library/axi_ad9671/axi_ad9671_channel.v
@@ -38,7 +38,8 @@
 
 module axi_ad9671_channel #(
 
-  parameter CHANNEL_ID = 0) (
+  parameter CHANNEL_ID = 0
+) (
 
   // adc interface
 
@@ -68,8 +69,8 @@ module axi_ad9671_channel #(
   input                   up_rreq,
   input       [13:0]      up_raddr,
   output      [31:0]      up_rdata,
-  output                  up_rack);
-
+  output                  up_rack
+);
 
   // internal signals
 
@@ -90,7 +91,9 @@ module axi_ad9671_channel #(
     .adc_pn_err (adc_pn_err_s),
     .adc_pnseq_sel (adc_pnseq_sel_s));
 
-  ad_datafmt #(.DATA_WIDTH(16)) i_ad_datafmt (
+  ad_datafmt #(
+    .DATA_WIDTH(16)
+  ) i_ad_datafmt (
     .clk (adc_clk),
     .valid (adc_valid),
     .data (adc_data),
@@ -100,7 +103,9 @@ module axi_ad9671_channel #(
     .dfmt_type (adc_dfmt_type_s),
     .dfmt_se (adc_dfmt_se_s));
 
-  up_adc_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel (
+  up_adc_channel #(
+    .CHANNEL_ID(CHANNEL_ID)
+  ) i_up_adc_channel (
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
     .adc_enable (adc_enable),
@@ -147,7 +152,3 @@ module axi_ad9671_channel #(
     .up_rack (up_rack));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
-
diff --git a/library/axi_ad9671/axi_ad9671_if.v b/library/axi_ad9671/axi_ad9671_if.v
index 5f5abd926..d3d5a64aa 100644
--- a/library/axi_ad9671/axi_ad9671_if.v
+++ b/library/axi_ad9671/axi_ad9671_if.v
@@ -38,7 +38,8 @@
 module axi_ad9671_if #(
 
   parameter QUAD_OR_DUAL_N = 1,
-  parameter ID = 0) (
+  parameter ID = 0
+) (
 
   // jesd interface
   // rx_clk is (line-rate/40)
@@ -75,8 +76,8 @@ module axi_ad9671_if #(
   output  reg             adc_sync_status,
   output  reg             adc_status,
   input       [ 3:0]      adc_raddr_in,
-  output  reg [ 3:0]      adc_raddr_out);
-
+  output  reg [ 3:0]      adc_raddr_out
+);
 
   // internal wires
 
@@ -184,7 +185,10 @@ module axi_ad9671_if #(
     end
   end
 
-  ad_mem #(.ADDRESS_WIDTH(4), .DATA_WIDTH(128)) i_mem (
+  ad_mem #(
+    .ADDRESS_WIDTH(4),
+    .DATA_WIDTH(128)
+  ) i_mem (
     .clka(rx_clk),
     .wea(int_valid),
     .addra(adc_waddr),
@@ -210,7 +214,3 @@ module axi_ad9671_if #(
   endgenerate
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
-
diff --git a/library/axi_ad9671/axi_ad9671_pnmon.v b/library/axi_ad9671/axi_ad9671_pnmon.v
index 850abaa28..b67f09553 100644
--- a/library/axi_ad9671/axi_ad9671_pnmon.v
+++ b/library/axi_ad9671/axi_ad9671_pnmon.v
@@ -48,7 +48,8 @@ module axi_ad9671_pnmon (
 
   output                  adc_pn_oos,
   output                  adc_pn_err,
-  input       [ 3:0]      adc_pnseq_sel);
+  input       [ 3:0]      adc_pnseq_sel
+);
 
   // internal registers
 
@@ -166,7 +167,9 @@ module axi_ad9671_pnmon (
 
   // pn oos & pn err
 
-  ad_pnmon #(.DATA_WIDTH(32)) i_pnmon (
+  ad_pnmon #(
+    .DATA_WIDTH(32)
+  ) i_pnmon (
     .adc_clk (adc_clk),
     .adc_valid_in (adc_pn_valid_s),
     .adc_data_in (adc_pn_data_in),
@@ -175,7 +178,3 @@ module axi_ad9671_pnmon (
     .adc_pn_err (adc_pn_err));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
-
diff --git a/library/axi_ad9684/axi_ad9684.v b/library/axi_ad9684/axi_ad9684.v
index bb8de7093..b36339dce 100644
--- a/library/axi_ad9684/axi_ad9684.v
+++ b/library/axi_ad9684/axi_ad9684.v
@@ -43,7 +43,8 @@ module axi_ad9684 #(
   parameter SPEED_GRADE = 0,
   parameter DEV_PACKAGE = 0,
   parameter IO_DELAY_GROUP = "dev_if_delay_group",
-  parameter OR_STATUS = 1) (
+  parameter OR_STATUS = 1
+) (
 
   // device interface ports
 
@@ -92,8 +93,8 @@ module axi_ad9684 #(
   output                  s_axi_rvalid,
   output      [ 1:0]      s_axi_rresp,
   output      [31:0]      s_axi_rdata,
-  input                   s_axi_rready);
-
+  input                   s_axi_rready
+);
 
   // internal registers
 
@@ -168,8 +169,8 @@ module axi_ad9684 #(
   axi_ad9684_if #(
     .FPGA_TECHNOLOGY(FPGA_TECHNOLOGY),
     .IO_DELAY_GROUP(IO_DELAY_GROUP),
-    .OR_STATUS (OR_STATUS))
-  i_ad9684_if (
+    .OR_STATUS (OR_STATUS)
+  ) i_ad9684_if (
     .adc_clk_in_p (adc_clk_in_p),
     .adc_clk_in_n (adc_clk_in_n),
     .adc_data_in_p (adc_data_in_p),
@@ -217,8 +218,8 @@ module axi_ad9684 #(
     .DRP_DISABLE (6'h00),
     .USERPORTS_DISABLE (0),
     .GPIO_DISABLE (0),
-    .START_CODE_DISABLE(0))
-  i_up_adc_common (
+    .START_CODE_DISABLE(0)
+  ) i_up_adc_common (
     .mmcm_rst (rst_s),
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
@@ -265,8 +266,8 @@ module axi_ad9684 #(
 
   axi_ad9684_channel #(
     .CHANNEL_ID (0),
-    .Q_OR_I_N (0))
-  i_channel_0 (
+    .Q_OR_I_N (0)
+  ) i_channel_0 (
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
     .adc_data (adc_rawdata_0_s),
@@ -293,8 +294,8 @@ module axi_ad9684 #(
 
   axi_ad9684_channel #(
     .CHANNEL_ID (1),
-    .Q_OR_I_N (1))
-  i_channel_1 (
+    .Q_OR_I_N (1)
+  ) i_channel_1 (
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
     .adc_data (adc_rawdata_1_s),
@@ -320,8 +321,8 @@ module axi_ad9684 #(
   // adc delay control instance
 
   up_delay_cntrl #(
-    .DATA_WIDTH(15))
-  i_delay_cntrl (
+    .DATA_WIDTH(15)
+  ) i_delay_cntrl (
     .delay_clk (delay_clk),
     .delay_rst (delay_rst),
     .delay_locked (delay_locked_s),
diff --git a/library/axi_ad9684/axi_ad9684_channel.v b/library/axi_ad9684/axi_ad9684_channel.v
index e566f55e5..040bdd2d2 100644
--- a/library/axi_ad9684/axi_ad9684_channel.v
+++ b/library/axi_ad9684/axi_ad9684_channel.v
@@ -39,7 +39,8 @@ module axi_ad9684_channel #(
 
   parameter Q_OR_I_N = 0,
   parameter CHANNEL_ID = 0,
-  parameter DATAPATH_DISABLE = 0) (
+  parameter DATAPATH_DISABLE = 0
+) (
 
   // adc data interface
 
@@ -69,8 +70,8 @@ module axi_ad9684_channel #(
   input                   up_rreq,
   input       [13:0]      up_raddr,
   output      [31:0]      up_rdata,
-  output                  up_rack);
-
+  output                  up_rack
+);
 
   // internal signals
 
@@ -94,7 +95,9 @@ module axi_ad9684_channel #(
   genvar n;
   generate
   for (n = 0; n < 2; n = n + 1) begin: g_ad_datafmt_1
-  ad_datafmt #(.DATA_WIDTH(14)) i_ad_datafmt (
+  ad_datafmt #(
+    .DATA_WIDTH(14)
+  ) i_ad_datafmt (
     .clk (adc_clk),
     .valid (1'b1),
     .data (adc_data[n*14+13:n*14]),
@@ -114,8 +117,8 @@ module axi_ad9684_channel #(
     .USERPORTS_DISABLE (0),
     .DATAFORMAT_DISABLE (0),
     .DCFILTER_DISABLE (0),
-    .IQCORRECTION_DISABLE (0))
-  i_up_adc_channel (
+    .IQCORRECTION_DISABLE (0)
+  ) i_up_adc_channel (
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
     .adc_enable (adc_enable),
@@ -162,4 +165,3 @@ module axi_ad9684_channel #(
     .up_rack (up_rack));
 
 endmodule
-
diff --git a/library/axi_ad9684/axi_ad9684_if.v b/library/axi_ad9684/axi_ad9684_if.v
index b74520e4b..4cbac9ae4 100644
--- a/library/axi_ad9684/axi_ad9684_if.v
+++ b/library/axi_ad9684/axi_ad9684_if.v
@@ -39,7 +39,8 @@ module axi_ad9684_if #(
 
   parameter FPGA_TECHNOLOGY = 0,
   parameter IO_DELAY_GROUP = "dev_if_delay_group",
-  parameter OR_STATUS = 0) (
+  parameter OR_STATUS = 0
+) (
 
   // device interface
   input                   adc_clk_in_p,
@@ -78,8 +79,8 @@ module axi_ad9684_if #(
   input       [31:0]      up_drp_wdata,
   output      [31:0]      up_drp_rdata,
   output                  up_drp_ready,
-  output                  up_drp_locked);
-
+  output                  up_drp_locked
+);
 
   localparam DDR_OR_SDR_N = 1;
 
@@ -110,8 +111,8 @@ module axi_ad9684_if #(
     .IODELAY_CTRL(1),
     .IODELAY_GROUP(IO_DELAY_GROUP),
     .DDR_OR_SDR_N(DDR_OR_SDR_N),
-    .DATA_WIDTH(14))
-  i_adc_data (
+    .DATA_WIDTH(14)
+  ) i_adc_data (
     .rst(adc_rst),
     .clk(adc_clk_in),
     .div_clk(adc_div_clk),
@@ -143,8 +144,8 @@ module axi_ad9684_if #(
       .IODELAY_CTRL(0),
       .IODELAY_GROUP(IO_DELAY_GROUP),
       .DDR_OR_SDR_N(DDR_OR_SDR_N),
-      .DATA_WIDTH(1))
-    i_adc_or (
+      .DATA_WIDTH(1)
+    ) i_adc_or (
       .rst(adc_rst),
       .clk(adc_clk_in),
       .div_clk(adc_div_clk),
@@ -188,8 +189,8 @@ module axi_ad9684_if #(
     .MMCM_VCO_DIV (6),
     .MMCM_VCO_MUL (12),
     .MMCM_CLK0_DIV (2),
-    .MMCM_CLK1_DIV (4))
-  i_serdes_clk (
+    .MMCM_CLK1_DIV (4)
+  ) i_serdes_clk (
     .rst (rst),
     .clk_in_p (adc_clk_in_p),
     .clk_in_n (adc_clk_in_n),
diff --git a/library/axi_ad9684/axi_ad9684_pnmon.v b/library/axi_ad9684/axi_ad9684_pnmon.v
index 7c22b436c..6934e3d40 100644
--- a/library/axi_ad9684/axi_ad9684_pnmon.v
+++ b/library/axi_ad9684/axi_ad9684_pnmon.v
@@ -50,7 +50,8 @@ module axi_ad9684_pnmon (
 
   // processor interface PN9 (0x0), PN23 (0x1)
 
-  input       [ 3:0]      adc_pnseq_sel);
+  input       [ 3:0]      adc_pnseq_sel
+);
 
   // internal registers
 
@@ -159,7 +160,9 @@ module axi_ad9684_pnmon (
 
   // pn oos & pn err
 
-  ad_pnmon #(.DATA_WIDTH(28)) i_pnmon (
+  ad_pnmon #(
+    .DATA_WIDTH(28)
+  ) i_pnmon (
     .adc_clk (adc_clk),
     .adc_valid_in (1'b1),
     .adc_data_in (adc_pn_data_in),
@@ -168,7 +171,3 @@ module axi_ad9684_pnmon (
     .adc_pn_err (adc_pn_err));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
-
diff --git a/library/axi_ad9739a/axi_ad9739a.v b/library/axi_ad9739a/axi_ad9739a.v
index 621360b7c..1de09e42b 100644
--- a/library/axi_ad9739a/axi_ad9739a.v
+++ b/library/axi_ad9739a/axi_ad9739a.v
@@ -48,7 +48,8 @@ module axi_ad9739a #(
   parameter   DAC_DDS_CORDIC_DW = 16,
   parameter   DAC_DDS_CORDIC_PHASE_DW = 16,
   parameter   DAC_DATAPATH_DISABLE = 0,
-  parameter   IO_DELAY_GROUP = "dev_if_delay_group") (
+  parameter   IO_DELAY_GROUP = "dev_if_delay_group"
+) (
 
   // dac interface
 
@@ -91,8 +92,8 @@ module axi_ad9739a #(
   output      [ 1:0]      s_axi_rresp,
   input                   s_axi_rready,
   input       [ 2:0]      s_axi_awprot,
-  input       [ 2:0]      s_axi_arprot);
-
+  input       [ 2:0]      s_axi_arprot
+);
 
   // internal clocks and resets
 
@@ -135,7 +136,9 @@ module axi_ad9739a #(
 
   // device interface
 
-  axi_ad9739a_if #(.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY)) i_if (
+  axi_ad9739a_if #(
+    .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY)
+  ) i_if (
     .dac_clk_in_p (dac_clk_in_p),
     .dac_clk_in_n (dac_clk_in_n),
     .dac_clk_out_p (dac_clk_out_p),
@@ -176,8 +179,8 @@ module axi_ad9739a #(
     .DAC_DDS_TYPE (DAC_DDS_TYPE),
     .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
     .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
-    .DATAPATH_DISABLE(DAC_DATAPATH_DISABLE))
-  i_core (
+    .DATAPATH_DISABLE(DAC_DATAPATH_DISABLE)
+  ) i_core (
     .dac_div_clk (dac_div_clk),
     .dac_rst (dac_rst),
     .dac_data_00 (dac_data_00_s),
@@ -244,6 +247,3 @@ module axi_ad9739a #(
     .up_rack (up_rack_s));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_ad9739a/axi_ad9739a_channel.v b/library/axi_ad9739a/axi_ad9739a_channel.v
index 5d89cc2fd..1f9ee7da9 100644
--- a/library/axi_ad9739a/axi_ad9739a_channel.v
+++ b/library/axi_ad9739a/axi_ad9739a_channel.v
@@ -41,7 +41,8 @@ module axi_ad9739a_channel #(
   parameter DAC_DDS_TYPE = 1,
   parameter DAC_DDS_CORDIC_DW = 16,
   parameter DAC_DDS_CORDIC_PHASE_DW = 16,
-  parameter DATAPATH_DISABLE = 0) (
+  parameter DATAPATH_DISABLE = 0
+) (
 
   // dac interface
 
@@ -82,8 +83,8 @@ module axi_ad9739a_channel #(
   input                   up_rreq,
   input       [ 13:0]     up_raddr,
   output      [ 31:0]     up_rdata,
-  output                  up_rack);
-
+  output                  up_rack
+);
 
   // internal signals
 
@@ -169,8 +170,8 @@ module axi_ad9739a_channel #(
     .DDS_TYPE (DAC_DDS_TYPE),
     .CORDIC_DW (DAC_DDS_CORDIC_DW),
     .CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
-    .CLK_RATIO (16))
-  i_dds (
+    .CLK_RATIO (16)
+  ) i_dds (
     .clk (dac_div_clk),
     .dac_dds_format (dac_dds_format),
     .dac_data_sync (dac_data_sync),
@@ -185,7 +186,9 @@ module axi_ad9739a_channel #(
 
   // single channel processor
 
-  up_dac_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel (
+  up_dac_channel #(
+    .CHANNEL_ID(CHANNEL_ID)
+  ) i_up_dac_channel (
     .dac_clk (dac_div_clk),
     .dac_rst (dac_rst),
     .dac_dds_scale_1 (dac_dds_scale_1_s),
@@ -227,6 +230,3 @@ module axi_ad9739a_channel #(
     .up_rack (up_rack));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_ad9739a/axi_ad9739a_core.v b/library/axi_ad9739a/axi_ad9739a_core.v
index e0e858d44..e0f4bb505 100644
--- a/library/axi_ad9739a/axi_ad9739a_core.v
+++ b/library/axi_ad9739a/axi_ad9739a_core.v
@@ -45,7 +45,8 @@ module axi_ad9739a_core #(
   parameter   DAC_DDS_TYPE = 1,
   parameter   DAC_DDS_CORDIC_DW = 16,
   parameter   DAC_DDS_CORDIC_PHASE_DW = 16,
-  parameter   DATAPATH_DISABLE = 0) (
+  parameter   DATAPATH_DISABLE = 0
+) (
 
   // dac interface
 
@@ -87,8 +88,8 @@ module axi_ad9739a_core #(
   input                   up_rreq,
   input       [ 13:0]     up_raddr,
   output  reg [ 31:0]     up_rdata,
-  output  reg             up_rack);
-
+  output  reg             up_rack
+);
 
   // internal registers
 
@@ -128,8 +129,8 @@ module axi_ad9739a_core #(
     .DAC_DDS_TYPE (DAC_DDS_TYPE),
     .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
     .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
-    .DATAPATH_DISABLE(DATAPATH_DISABLE))
-  i_channel_0 (
+    .DATAPATH_DISABLE(DATAPATH_DISABLE)
+  ) i_channel_0 (
     .dac_div_clk (dac_div_clk),
     .dac_rst (dac_rst),
     .dac_enable (dac_enable),
@@ -213,6 +214,3 @@ module axi_ad9739a_core #(
     .up_rack (up_rack_s));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_ad9739a/axi_ad9739a_if.v b/library/axi_ad9739a/axi_ad9739a_if.v
index a4ca862f1..b12dbaff2 100644
--- a/library/axi_ad9739a/axi_ad9739a_if.v
+++ b/library/axi_ad9739a/axi_ad9739a_if.v
@@ -39,7 +39,8 @@
 
 module axi_ad9739a_if #(
 
-  parameter   FPGA_TECHNOLOGY = 0) (
+  parameter   FPGA_TECHNOLOGY = 0
+) (
 
   // dac interface
 
@@ -76,8 +77,8 @@ module axi_ad9739a_if #(
   input       [15:0]      dac_data_12,
   input       [15:0]      dac_data_13,
   input       [15:0]      dac_data_14,
-  input       [15:0]      dac_data_15);
-
+  input       [15:0]      dac_data_15
+);
 
   // internal registers
 
@@ -102,8 +103,8 @@ module axi_ad9739a_if #(
     .DDR_OR_SDR_N(1),
     .DATA_WIDTH(14),
     .SERDES_FACTOR(8),
-    .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY))
-  i_serdes_out_data_a (
+    .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY)
+  ) i_serdes_out_data_a (
     .rst (dac_rst),
     .clk (dac_clk),
     .div_clk (dac_div_clk),
@@ -127,8 +128,8 @@ module axi_ad9739a_if #(
     .DDR_OR_SDR_N(1),
     .DATA_WIDTH(14),
     .SERDES_FACTOR(8),
-    .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY))
-  i_serdes_out_data_b (
+    .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY)
+  ) i_serdes_out_data_b (
     .rst (dac_rst),
     .clk (dac_clk),
     .div_clk (dac_div_clk),
@@ -152,8 +153,8 @@ module axi_ad9739a_if #(
     .DDR_OR_SDR_N(1),
     .DATA_WIDTH(1),
     .SERDES_FACTOR(8),
-    .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY))
-  i_serdes_out_clk (
+    .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY)
+  ) i_serdes_out_clk (
     .rst (dac_rst),
     .clk (dac_clk),
     .div_clk (dac_div_clk),
@@ -182,7 +183,9 @@ module axi_ad9739a_if #(
     .I (dac_clk_in_s),
     .O (dac_clk));
 
-  BUFR #(.BUFR_DIVIDE("4")) i_dac_div_clk_rbuf (
+  BUFR #(
+    .BUFR_DIVIDE("4")
+  ) i_dac_div_clk_rbuf (
     .CLR (1'b0),
     .CE (1'b1),
     .I (dac_clk_in_s),
@@ -193,6 +196,3 @@ module axi_ad9739a_if #(
     .O (dac_div_clk));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_ad9783/axi_ad9783.v b/library/axi_ad9783/axi_ad9783.v
index 1ecd85e86..762257eb3 100755
--- a/library/axi_ad9783/axi_ad9783.v
+++ b/library/axi_ad9783/axi_ad9783.v
@@ -45,7 +45,8 @@ module axi_ad9783 #(
   parameter   DAC_DDS_TYPE = 2,
   parameter   DAC_DDS_CORDIC_DW = 16,
   parameter   DAC_DDS_CORDIC_PHASE_DW = 16,
-  parameter   DAC_DATAPATH_DISABLE = 0) (
+  parameter   DAC_DATAPATH_DISABLE = 0
+) (
 
   // dac interface
   // from dco1_p
@@ -92,8 +93,8 @@ module axi_ad9783 #(
   output      [  1:0]     s_axi_rresp,
   input                   s_axi_rready,
   input       [  2:0]     s_axi_awprot,
-  input       [  2:0]     s_axi_arprot);
-
+  input       [  2:0]     s_axi_arprot
+);
 
   // internal clocks and resets
 
@@ -130,8 +131,8 @@ module axi_ad9783 #(
   // device interface
 
   axi_ad9783_if #(
-    .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY))
-  i_if (
+    .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY)
+  ) i_if (
     .dac_clk_in_p (dac_clk_in_p),
     .dac_clk_in_n (dac_clk_in_n),
     .dac_clk_out_p (dac_clk_out_p),
@@ -161,8 +162,8 @@ module axi_ad9783 #(
     .DAC_DDS_TYPE (DAC_DDS_TYPE),
     .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
     .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
-    .DATAPATH_DISABLE(DAC_DATAPATH_DISABLE))
-  i_core (
+    .DATAPATH_DISABLE(DAC_DATAPATH_DISABLE)
+  ) i_core (
     .dac_div_clk (dac_div_clk),
     .dac_rst (dac_rst_s),
     .dac_data_a0 (dac_data_a0_s),
@@ -223,6 +224,3 @@ module axi_ad9783 #(
     .up_rack (up_rack_s));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_ad9783/axi_ad9783_channel.v b/library/axi_ad9783/axi_ad9783_channel.v
index e89c465ae..222d5956c 100755
--- a/library/axi_ad9783/axi_ad9783_channel.v
+++ b/library/axi_ad9783/axi_ad9783_channel.v
@@ -41,7 +41,8 @@ module axi_ad9783_channel #(
   parameter DAC_DDS_TYPE = 1,
   parameter DAC_DDS_CORDIC_DW = 16,
   parameter DAC_DDS_CORDIC_PHASE_DW = 16,
-  parameter DATAPATH_DISABLE = 0) (
+  parameter DATAPATH_DISABLE = 0
+) (
 
   // dac interface
 
@@ -70,8 +71,8 @@ module axi_ad9783_channel #(
   input                   up_rreq,
   input        [13:0]     up_raddr,
   output       [31:0]     up_rdata,
-  output                  up_rack);
-
+  output                  up_rack
+);
 
   // internal signals
 
@@ -89,7 +90,6 @@ module axi_ad9783_channel #(
   reg     [23:0]   dac_prbs_data = 'd0;
   reg     [15:0]   dac_prbs_counter = 'd0;
 
-
   // pn23 function
   function [23:0] pn23;
     input [23:0] din;
@@ -155,8 +155,8 @@ module axi_ad9783_channel #(
     .DDS_TYPE (DAC_DDS_TYPE),
     .CORDIC_DW (DAC_DDS_CORDIC_DW),
     .CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
-    .CLK_RATIO (4))
-  i_dds (
+    .CLK_RATIO (4)
+  ) i_dds (
     .clk (dac_div_clk),
     .dac_dds_format (dac_dds_format),
     .dac_data_sync (dac_data_sync),
@@ -172,8 +172,8 @@ module axi_ad9783_channel #(
   // single channel processor
 
   up_dac_channel #(
-    .CHANNEL_ID(CHANNEL_ID))
-  i_up_dac_channel (
+    .CHANNEL_ID(CHANNEL_ID)
+  ) i_up_dac_channel (
     .dac_clk (dac_div_clk),
     .dac_rst (dac_rst),
     .dac_dds_scale_1 (dac_dds_scale_1_s),
@@ -215,6 +215,3 @@ module axi_ad9783_channel #(
     .up_rack (up_rack));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_ad9783/axi_ad9783_core.v b/library/axi_ad9783/axi_ad9783_core.v
index 9b26714c4..81e901ec1 100755
--- a/library/axi_ad9783/axi_ad9783_core.v
+++ b/library/axi_ad9783/axi_ad9783_core.v
@@ -45,7 +45,8 @@ module axi_ad9783_core #(
   parameter   DAC_DDS_TYPE = 1,
   parameter   DAC_DDS_CORDIC_DW = 16,
   parameter   DAC_DDS_CORDIC_PHASE_DW = 16,
-  parameter   DATAPATH_DISABLE = 0) (
+  parameter   DATAPATH_DISABLE = 0
+) (
 
   // dac interface
 
@@ -81,8 +82,8 @@ module axi_ad9783_core #(
   input                   up_rreq,
   input       [ 13:0]     up_raddr,
   output reg  [ 31:0]     up_rdata,
-  output reg              up_rack);
-
+  output reg              up_rack
+);
 
   // internal registers
 
@@ -129,8 +130,8 @@ module axi_ad9783_core #(
     .DAC_DDS_TYPE (DAC_DDS_TYPE),
     .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
     .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
-    .DATAPATH_DISABLE(DATAPATH_DISABLE))
-  i_channel_0 (
+    .DATAPATH_DISABLE(DATAPATH_DISABLE)
+  ) i_channel_0 (
     .dac_div_clk (dac_div_clk),
     .dac_rst (dac_rst),
     .dac_enable (dac_enable_0_reg),
@@ -157,8 +158,8 @@ module axi_ad9783_core #(
     .DAC_DDS_TYPE (DAC_DDS_TYPE),
     .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
     .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
-    .DATAPATH_DISABLE(DATAPATH_DISABLE))
-  i_channel_1 (
+    .DATAPATH_DISABLE(DATAPATH_DISABLE)
+  ) i_channel_1 (
     .dac_div_clk (dac_div_clk),
     .dac_rst (dac_rst),
     .dac_enable (dac_enable_1_reg),
@@ -187,8 +188,8 @@ module axi_ad9783_core #(
     .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
     .FPGA_FAMILY (FPGA_FAMILY),
     .SPEED_GRADE (SPEED_GRADE),
-    .DEV_PACKAGE (DEV_PACKAGE))
-  i_up_dac_common (
+    .DEV_PACKAGE (DEV_PACKAGE)
+  ) i_up_dac_common (
     .mmcm_rst (),
     .dac_clk (dac_div_clk),
     .dac_rst (dac_rst),
@@ -230,6 +231,3 @@ module axi_ad9783_core #(
     .up_rack (up_rack_s));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_ad9783/axi_ad9783_if.v b/library/axi_ad9783/axi_ad9783_if.v
index cb6bd94a1..77d0d0824 100755
--- a/library/axi_ad9783/axi_ad9783_if.v
+++ b/library/axi_ad9783/axi_ad9783_if.v
@@ -39,7 +39,8 @@
 
 module axi_ad9783_if #(
 
-  parameter   FPGA_TECHNOLOGY = 0) (
+  parameter   FPGA_TECHNOLOGY = 0
+) (
 
   // dac interface
 
@@ -65,8 +66,8 @@ module axi_ad9783_if #(
   input   [15:0]   dac_data_b0,
   input   [15:0]   dac_data_b1,
   input   [15:0]   dac_data_b2,
-  input   [15:0]   dac_data_b3);
-
+  input   [15:0]   dac_data_b3
+);
 
   // internal registers
 
@@ -92,8 +93,8 @@ module axi_ad9783_if #(
     .DDR_OR_SDR_N(1),
     .DATA_WIDTH(16),
     .SERDES_FACTOR(8),
-    .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY))
-  i_serdes_out_data (
+    .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY)
+  ) i_serdes_out_data (
     .rst (dac_rst),
     .clk (dac_clk_s),
     .div_clk (dac_div_clk),
@@ -117,8 +118,8 @@ module axi_ad9783_if #(
     .DDR_OR_SDR_N(1),
     .DATA_WIDTH(1),
     .SERDES_FACTOR(8),
-    .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY))
-  i_serdes_out_clk (
+    .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY)
+  ) i_serdes_out_clk (
     .rst (dac_rst),
     .clk (dac_clk_s),
     .div_clk (dac_div_clk),
@@ -147,8 +148,8 @@ module axi_ad9783_if #(
     .BUFGCE_DIVIDE (4),
     .IS_CE_INVERTED (1'b0),
     .IS_CLR_INVERTED (1'b0),
-    .IS_I_INVERTED (1'b0))
-  i_dac_div_clk_rbuf (
+    .IS_I_INVERTED (1'b0)
+  ) i_dac_div_clk_rbuf (
     .O (dac_div_clk_s),
     .CE (1'b1),
     .CLR (1'b0),
@@ -159,6 +160,3 @@ module axi_ad9783_if #(
     .O (dac_div_clk));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_ad9963/axi_ad9963.v b/library/axi_ad9963/axi_ad9963.v
index 6389d1b5c..93655c15e 100644
--- a/library/axi_ad9963/axi_ad9963.v
+++ b/library/axi_ad9963/axi_ad9963.v
@@ -56,7 +56,8 @@ module axi_ad9963 #(
   parameter   ADC_DCFILTER_DISABLE = 0,
   parameter   ADC_IQCORRECTION_DISABLE = 0,
   parameter   ADC_SCALECORRECTION_ONLY = 1,
-  parameter   DELAY_REFCLK_FREQUENCY = 200) (
+  parameter   DELAY_REFCLK_FREQUENCY = 200
+) (
 
   // physical interface (receive)
 
@@ -130,7 +131,8 @@ module axi_ad9963 #(
   output          s_axi_rvalid,
   output  [31:0]  s_axi_rdata,
   output  [ 1:0]  s_axi_rresp,
-  input           s_axi_rready);
+  input           s_axi_rready
+);
 
   // internal registers
 
@@ -189,8 +191,8 @@ module axi_ad9963 #(
     .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
     .ADC_IODELAY_ENABLE (ADC_IODELAY_ENABLE),
     .IO_DELAY_GROUP (IO_DELAY_GROUP),
-    .DELAY_REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
-  i_dev_if (
+    .DELAY_REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
+  ) i_dev_if (
     .trx_clk (trx_clk),
     .trx_iq (trx_iq),
     .trx_data (trx_data),
@@ -274,8 +276,8 @@ module axi_ad9963 #(
     .DAC_DDS_TYPE (DAC_DDS_TYPE),
     .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
     .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
-    .DATAPATH_DISABLE (DAC_DATAPATH_DISABLE))
-  i_tx (
+    .DATAPATH_DISABLE (DAC_DATAPATH_DISABLE)
+  ) i_tx (
     .dac_clk (dac_clk),
     .dac_rst (dac_rst),
     .dac_data (dac_data_s),
@@ -337,6 +339,3 @@ module axi_ad9963 #(
     .up_rack (up_rack));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_ad9963/axi_ad9963_if.v b/library/axi_ad9963/axi_ad9963_if.v
index df1599893..7c71bb103 100644
--- a/library/axi_ad9963/axi_ad9963_if.v
+++ b/library/axi_ad9963/axi_ad9963_if.v
@@ -42,7 +42,8 @@ module axi_ad9963_if #(
   parameter   FPGA_TECHNOLOGY = 0,
   parameter   ADC_IODELAY_ENABLE = 0,
   parameter   IO_DELAY_GROUP = "dev_if_delay_group",
-  parameter   DELAY_REFCLK_FREQUENCY = 200) (
+  parameter   DELAY_REFCLK_FREQUENCY = 200
+) (
 
   // physical interface (receive)
 
@@ -86,7 +87,8 @@ module axi_ad9963_if #(
   output      [64:0]  up_adc_drdata,
   input               delay_clk,
   input               delay_rst,
-  output              delay_locked);
+  output              delay_locked
+);
 
   // internal registers
 
@@ -149,21 +151,19 @@ module axi_ad9963_if #(
   // device clock interface (receive clock)
 
   BUFGCTRL #(
-      .INIT_OUT(0),
-      .PRESELECT_I0("FALSE"),
-      .PRESELECT_I1("FALSE")
-      )
-  bufgctrl_adc (
-      .O(adc_clk),
-      .CE0(1'b1),
-      .CE1(1'b0),
-      .I0(trx_clk),
-      .I1(1'b0),
-      .IGNORE0(1'b0),
-      .IGNORE1(1'b0),
-      .S0(up_adc_ce),
-      .S1(1'b0)
-      );
+    .INIT_OUT(0),
+    .PRESELECT_I0("FALSE"),
+    .PRESELECT_I1("FALSE")
+  ) bufgctrl_adc (
+    .O(adc_clk),
+    .CE0(1'b1),
+    .CE1(1'b0),
+    .I0(trx_clk),
+    .I1(1'b0),
+    .IGNORE0(1'b0),
+    .IGNORE1(1'b0),
+    .S0(up_adc_ce),
+    .S1(1'b0));
 
   // receive data interface, ibuf -> idelay -> iddr
 
@@ -175,8 +175,8 @@ module axi_ad9963_if #(
     .IODELAY_ENABLE (ADC_IODELAY_ENABLE),
     .IODELAY_CTRL (0),
     .IODELAY_GROUP (IO_DELAY_GROUP),
-    .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
-  i_rx_data (
+    .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
+  ) i_rx_data (
     .rx_clk (adc_clk),
     .rx_data_in_p (trx_data[l_inst]),
     .rx_data_in_n (1'b0),
@@ -199,8 +199,8 @@ module axi_ad9963_if #(
     .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
     .IODELAY_ENABLE (ADC_IODELAY_ENABLE),
     .IODELAY_CTRL (1),
-    .IODELAY_GROUP (IO_DELAY_GROUP))
-  i_rx_iq (
+    .IODELAY_GROUP (IO_DELAY_GROUP)
+  ) i_rx_iq (
     .rx_clk (adc_clk),
     .rx_data_in_p (trx_iq),
     .rx_data_in_n (1'b0),
@@ -216,7 +216,9 @@ module axi_ad9963_if #(
 
   // transmit data interface
 
-  BUFR #(.BUFR_DIVIDE(2)) i_div_clk_buf (
+  BUFR #(
+    .BUFR_DIVIDE(2)
+  ) i_div_clk_buf (
     .CLR (1'b0),
     .CE (1'b1),
     .I (tx_clk),
@@ -226,8 +228,7 @@ module axi_ad9963_if #(
     .INIT_OUT(0),
     .PRESELECT_I0("FALSE"),
     .PRESELECT_I1("FALSE")
-    )
-  bufgctrl_dac (
+  ) bufgctrl_dac (
     .O(dac_clk),
     .CE0(1'b1),
     .CE1(1'b0),
@@ -236,16 +237,15 @@ module axi_ad9963_if #(
     .IGNORE0(1'b0),
     .IGNORE1(1'b0),
     .S0(up_dac_ce),
-    .S1(1'b0)
-    );
+    .S1(1'b0));
 
   generate
   for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin: g_tx_data
   ODDR #(
     .DDR_CLK_EDGE ("SAME_EDGE"),
     .INIT (1'b0),
-    .SRTYPE ("SYNC"))
-  i_tx_data_oddr (
+    .SRTYPE ("SYNC")
+  ) i_tx_data_oddr (
     .CE (1'b1),
     .R (dac_rst),
     .S (1'b0),
@@ -259,8 +259,8 @@ module axi_ad9963_if #(
   ODDR #(
     .DDR_CLK_EDGE ("SAME_EDGE"),
     .INIT (1'b0),
-    .SRTYPE ("SYNC"))
-  i_tx_data_oddr (
+    .SRTYPE ("SYNC")
+  ) i_tx_data_oddr (
     .CE (1'b1),
     .R (dac_rst),
     .S (1'b0),
@@ -270,6 +270,3 @@ module axi_ad9963_if #(
     .Q (tx_iq));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_ad9963/axi_ad9963_rx.v b/library/axi_ad9963/axi_ad9963_rx.v
index c9c5577b1..5840ef0da 100644
--- a/library/axi_ad9963/axi_ad9963_rx.v
+++ b/library/axi_ad9963/axi_ad9963_rx.v
@@ -49,7 +49,8 @@ module axi_ad9963_rx #(
   parameter FPGA_TECHNOLOGY = 0,
   parameter FPGA_FAMILY = 0,
   parameter SPEED_GRADE = 0,
-  parameter DEV_PACKAGE = 0) (
+  parameter DEV_PACKAGE = 0
+) (
 
   // adc interface
 
@@ -91,7 +92,8 @@ module axi_ad9963_rx #(
   input               up_rreq,
   input       [13:0]  up_raddr,
   output reg  [31:0]  up_rdata,
-  output reg          up_rack);
+  output reg          up_rack
+);
 
  // configuration settings
 
@@ -148,8 +150,8 @@ module axi_ad9963_rx #(
     .DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
     .DCFILTER_DISABLE (DCFILTER_DISABLE),
     .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
-    .SCALECORRECTION_ONLY (SCALECORRECTION_ONLY))
-  i_rx_channel_0 (
+    .SCALECORRECTION_ONLY (SCALECORRECTION_ONLY)
+  ) i_rx_channel_0 (
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
     .adc_valid (adc_valid),
@@ -183,8 +185,8 @@ module axi_ad9963_rx #(
     .DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
     .DCFILTER_DISABLE (DCFILTER_DISABLE),
     .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
-    .SCALECORRECTION_ONLY (SCALECORRECTION_ONLY))
-  i_rx_channel_1 (
+    .SCALECORRECTION_ONLY (SCALECORRECTION_ONLY)
+  ) i_rx_channel_1 (
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
     .adc_valid (adc_valid),
@@ -273,7 +275,10 @@ module axi_ad9963_rx #(
 
   generate if (IODELAY_ENABLE == 1) begin
 
-  up_delay_cntrl #(.DATA_WIDTH(13), .BASE_ADDRESS(6'h02)) i_delay_cntrl (
+  up_delay_cntrl #(
+    .DATA_WIDTH(13),
+    .BASE_ADDRESS(6'h02)
+  ) i_delay_cntrl (
     .delay_clk (delay_clk),
     .delay_rst (delay_rst),
     .delay_locked (delay_locked),
@@ -302,7 +307,3 @@ module axi_ad9963_rx #(
   endgenerate
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
-
diff --git a/library/axi_ad9963/axi_ad9963_rx_channel.v b/library/axi_ad9963/axi_ad9963_rx_channel.v
index ccc650c83..405b04638 100644
--- a/library/axi_ad9963/axi_ad9963_rx_channel.v
+++ b/library/axi_ad9963/axi_ad9963_rx_channel.v
@@ -45,7 +45,8 @@ module axi_ad9963_rx_channel #(
   parameter DATAFORMAT_DISABLE = 0,
   parameter DCFILTER_DISABLE = 0,
   parameter IQCORRECTION_DISABLE = 0,
-  parameter SCALECORRECTION_ONLY = 1) (
+  parameter SCALECORRECTION_ONLY = 1
+) (
 
   // adc interface
 
@@ -77,7 +78,8 @@ module axi_ad9963_rx_channel #(
   input           up_rreq,
   input   [13:0]  up_raddr,
   output  [31:0]  up_rdata,
-  output          up_rack);
+  output          up_rack
+);
 
   // internal signals
 
@@ -116,7 +118,9 @@ module axi_ad9963_rx_channel #(
   assign adc_dfmt_valid_s = adc_valid;
   assign adc_dfmt_data_s = {{4{adc_data[11]}}, adc_data};
   end else begin
-  ad_datafmt #(.DATA_WIDTH (12)) i_ad_datafmt (
+  ad_datafmt #(
+    .DATA_WIDTH (12)
+  ) i_ad_datafmt (
     .clk (adc_clk),
     .valid (adc_valid),
     .data (adc_data),
@@ -145,10 +149,11 @@ module axi_ad9963_rx_channel #(
   end
   endgenerate
 
-  ad_iqcor #(.Q_OR_I_N (Q_OR_I_N),
-             .DISABLE(IQCORRECTION_DISABLE == 1),
-             .SCALE_ONLY(SCALECORRECTION_ONLY))
-    i_ad_iqcor (
+  ad_iqcor #(
+    .Q_OR_I_N (Q_OR_I_N),
+    .DISABLE(IQCORRECTION_DISABLE == 1),
+    .SCALE_ONLY(SCALECORRECTION_ONLY)
+  ) i_ad_iqcor (
     .clk (adc_clk),
     .valid (adc_dcfilter_valid_s),
     .data_in (adc_dcfilter_data_s),
@@ -213,7 +218,3 @@ module axi_ad9963_rx_channel #(
     .up_rack (up_rack));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
-
diff --git a/library/axi_ad9963/axi_ad9963_rx_pnmon.v b/library/axi_ad9963/axi_ad9963_rx_pnmon.v
index 9d514a463..0bb66becd 100644
--- a/library/axi_ad9963/axi_ad9963_rx_pnmon.v
+++ b/library/axi_ad9963/axi_ad9963_rx_pnmon.v
@@ -48,7 +48,8 @@ module axi_ad9963_rx_pnmon (
 
   input   [ 3:0]  adc_pnseq_sel,
   output          adc_pn_oos,
-  output          adc_pn_err);
+  output          adc_pn_err
+);
 
   // internal registers
 
@@ -83,7 +84,7 @@ module axi_ad9963_rx_pnmon (
 
   // standard prbs functions
 
- function [23:0] pn23;
+  function [23:0] pn23;
     input [23:0] din;
     reg   [23:0] dout;
     begin
@@ -96,16 +97,18 @@ module axi_ad9963_rx_pnmon (
 
   assign adc_pn_data_pn_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in : adc_pn_data_pn;
 
- always @(posedge adc_clk) begin
-   if(adc_valid == 1'b1) begin
-     adc_pn_data_in <= {adc_pn_data_in[22:11], adc_data};
-     adc_pn_data_pn <= pn23(adc_pn_data_pn_s);
-   end
- end
+  always @(posedge adc_clk) begin
+    if(adc_valid == 1'b1) begin
+      adc_pn_data_in <= {adc_pn_data_in[22:11], adc_data};
+      adc_pn_data_pn <= pn23(adc_pn_data_pn_s);
+    end
+  end
 
   // pn oos & pn err
 
-  ad_pnmon #(.DATA_WIDTH(24)) i_pnmon (
+  ad_pnmon #(
+    .DATA_WIDTH(24)
+  ) i_pnmon (
     .adc_clk (adc_clk),
     .adc_valid_in (adc_valid),
     .adc_data_in (adc_pn_data_in),
@@ -115,6 +118,3 @@ module axi_ad9963_rx_pnmon (
     .adc_pn_err (adc_pn_err));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_ad9963/axi_ad9963_tx.v b/library/axi_ad9963/axi_ad9963_tx.v
index 1accfc755..490475392 100644
--- a/library/axi_ad9963/axi_ad9963_tx.v
+++ b/library/axi_ad9963/axi_ad9963_tx.v
@@ -47,7 +47,8 @@ module axi_ad9963_tx #(
   parameter   DAC_DDS_TYPE = 1,
   parameter   DAC_DDS_CORDIC_DW = 14,
   parameter   DAC_DDS_CORDIC_PHASE_DW = 13,
-  parameter   DATAPATH_DISABLE = 0) (
+  parameter   DATAPATH_DISABLE = 0
+) (
 
   // dac interface
 
@@ -88,7 +89,8 @@ module axi_ad9963_tx #(
   input               up_rreq,
   input       [13:0]  up_raddr,
   output reg  [31:0]  up_rdata,
-  output reg          up_rack);
+  output reg          up_rack
+);
 
   // internal signals
 
@@ -131,8 +133,8 @@ module axi_ad9963_tx #(
     .DAC_DDS_TYPE (DAC_DDS_TYPE),
     .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
     .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
-    .DATAPATH_DISABLE (DATAPATH_DISABLE))
-  i_tx_channel_0 (
+    .DATAPATH_DISABLE (DATAPATH_DISABLE)
+  ) i_tx_channel_0 (
     .dac_clk (dac_clk),
     .dac_rst (dac_rst),
     .dac_valid (dac_valid_i),
@@ -165,8 +167,8 @@ module axi_ad9963_tx #(
     .DAC_DDS_TYPE (DAC_DDS_TYPE),
     .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
     .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
-    .DATAPATH_DISABLE (DATAPATH_DISABLE))
-  i_tx_channel_1 (
+    .DATAPATH_DISABLE (DATAPATH_DISABLE)
+  ) i_tx_channel_1 (
     .dac_clk (dac_clk),
     .dac_rst (dac_rst),
     .dac_valid (dac_valid_q),
@@ -250,6 +252,3 @@ module axi_ad9963_tx #(
     .up_rack (up_rack_s[2]));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_ad9963/axi_ad9963_tx_channel.v b/library/axi_ad9963/axi_ad9963_tx_channel.v
index fa2d3719d..17081973f 100644
--- a/library/axi_ad9963/axi_ad9963_tx_channel.v
+++ b/library/axi_ad9963/axi_ad9963_tx_channel.v
@@ -44,7 +44,8 @@ module axi_ad9963_tx_channel #(
   parameter   DAC_DDS_TYPE = 1,
   parameter   DAC_DDS_CORDIC_DW = 14,
   parameter   DAC_DDS_CORDIC_PHASE_DW = 13,
-  parameter   DATAPATH_DISABLE = 0) (
+  parameter   DATAPATH_DISABLE = 0
+) (
 
   // dac interface
 
@@ -76,7 +77,8 @@ module axi_ad9963_tx_channel #(
   input               up_rreq,
   input       [13:0]  up_raddr,
   output      [31:0]  up_rdata,
-  output              up_rack);
+  output              up_rack
+);
 
   localparam  PRBS_SEL = CHANNEL_ID;
   localparam  PRBS_P09 = 0;
@@ -128,7 +130,9 @@ module axi_ad9963_tx_channel #(
   assign dac_iqcor_valid_s = data_source_valid;
   assign dac_iqcor_data_s = {dac_data_out, 4'd0};
   end else begin
-  ad_iqcor #(.Q_OR_I_N (Q_OR_I_N)) i_ad_iqcor (
+  ad_iqcor #(
+    .Q_OR_I_N (Q_OR_I_N)
+  ) i_ad_iqcor (
     .clk (dac_clk),
     .valid (data_source_valid),
     .data_in ({dac_data_out, 4'd0}),
@@ -156,7 +160,7 @@ module axi_ad9963_tx_channel #(
     dma_valid_m <= dma_valid;
   end
 
- function [23:0] pn23;
+  function [23:0] pn23;
     input [23:0] din;
     reg   [23:0] dout;
     begin
@@ -205,8 +209,8 @@ module axi_ad9963_tx_channel #(
     .DDS_TYPE (DAC_DDS_TYPE),
     .CORDIC_DW (DAC_DDS_CORDIC_DW),
     .CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
-    .CLK_RATIO (1))
-  i_dds (
+    .CLK_RATIO (1)
+  ) i_dds (
     .clk (dac_clk),
     .dac_dds_format (dac_dds_format),
     .dac_data_sync (dac_data_sync),
@@ -269,6 +273,3 @@ module axi_ad9963_tx_channel #(
     .up_rack (up_rack));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_adaq8092/axi_adaq8092.v b/library/axi_adaq8092/axi_adaq8092.v
index cf57fa84e..d811185da 100644
--- a/library/axi_adaq8092/axi_adaq8092.v
+++ b/library/axi_adaq8092/axi_adaq8092.v
@@ -45,7 +45,8 @@ module axi_adaq8092 #(
   parameter ADC_DATAPATH_DISABLE = 0,
   parameter IO_DELAY_GROUP = "adc_if_delay_group",
   parameter OUTPUT_MODE = 0,
-  parameter   [27:0] POLARITY_MASK ='hfffffff) (
+  parameter   [27:0] POLARITY_MASK ='hfffffff
+) (
 
   // adc interface (clk, data, over-range)
 
@@ -99,10 +100,11 @@ module axi_adaq8092 #(
   output      [31:0]      s_axi_rdata,
   input                   s_axi_rready,
   input       [ 2:0]      s_axi_awprot,
-  input       [ 2:0]      s_axi_arprot);
-  
+  input       [ 2:0]      s_axi_arprot
+);
+
   // configuration settings
-  
+
   localparam CONFIG = (OUTPUT_MODE * 128);
 
   // internal registers
@@ -111,7 +113,7 @@ module axi_adaq8092 #(
   reg     [31:0]  up_rdata = 'd0;
   reg             up_wack = 'd0;
   reg             up_rack = 'd0;
-  
+
   // internal clocks & resets
 
   wire            up_rstn;
@@ -122,16 +124,16 @@ module axi_adaq8092 #(
 
   wire            adc_or_s;
   wire    [27:0]  adc_data_s;
-  wire    [1:0]   up_status_or_s;      
+  wire    [1:0]   up_status_or_s;
   wire            adc_status_s;
   wire    [29:0]  up_dld_s;
   wire    [149:0] up_dwdata_s;
   wire    [149:0] up_drdata_s;
   wire            delay_locked_s;
   wire    [13:0]  up_raddr_s;
-  wire    [31:0]  up_rdata_s[0:3];     
-  wire    [3:0]   up_rack_s ;          
-  wire    [3:0]   up_wack_s;          
+  wire    [31:0]  up_rdata_s[0:3];
+  wire    [3:0]   up_rack_s;
+  wire    [3:0]   up_wack_s;
   wire            up_wreq_s;
   wire    [13:0]  up_waddr_s;
   wire    [31:0]  up_wdata_s;
@@ -147,7 +149,7 @@ module axi_adaq8092 #(
   assign up_clk = s_axi_aclk;
   assign up_rstn = s_axi_aresetn;
   assign adc_valid = 1'b1;
- 
+
   // processor read interface
 
   always @(negedge up_rstn or posedge up_clk) begin
@@ -159,12 +161,12 @@ module axi_adaq8092 #(
     end else begin
       up_status_or <= up_status_or_s[0] | up_status_or_s[1];
       up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | up_rdata_s[3];
-      up_rack <=   up_rack_s[0] | up_rack_s[1]  | up_rack_s[2]  | up_rack_s[3];
-      up_wack <=   up_wack_s[0] | up_wack_s[1]  | up_wack_s[2]  | up_wack_s[3]; 
+      up_rack  <=  up_rack_s[0] | up_rack_s[1]  | up_rack_s[2]  | up_rack_s[3];
+      up_wack  <=  up_wack_s[0] | up_wack_s[1]  | up_wack_s[2]  | up_wack_s[3];
     end
   end
 
-  // ADC channel 1  
+  // ADC channel 1
 
   axi_adaq8092_channel #(
     .CHANNEL_ID(0),
@@ -189,7 +191,7 @@ module axi_adaq8092 #(
     .up_rdata (up_rdata_s[0]),
     .up_rack (up_rack_s[0]));
 
-  // ADC channel 2 
+  // ADC channel 2
 
   axi_adaq8092_channel #(
     .CHANNEL_ID(1),
@@ -215,19 +217,19 @@ module axi_adaq8092 #(
     .up_rack (up_rack_s[1]));
 
   // ADC interface
-  
+
   axi_adaq8092_rand_decode i_rand (
     .adc_data(adc_data_s),
     .adc_clk(adc_clk),
     .adc_rand_enb(adc_custom_control_s[0]),
     .adc_data_decoded(adc_part_decoded_data_s));
-            
+
   axi_adaq8092_apb_decode i_apb (
     .adc_data(adc_part_decoded_data_s),
     .adc_clk(adc_clk),
     .adc_abp_enb(adc_custom_control_s[1]),
     .adc_data_decoded({adc_decoded_data_s_2,adc_decoded_data_s_1}));
-  
+
   axi_adaq8092_if #(
     .OUTPUT_MODE(OUTPUT_MODE),
     .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
@@ -259,7 +261,7 @@ module axi_adaq8092 #(
   // adc delay control
 
   up_delay_cntrl #(
-    .DATA_WIDTH(30), 
+    .DATA_WIDTH(30),
     .BASE_ADDRESS(6'h02)
   ) i_delay_cntrl (
     .delay_clk (delay_clk),
diff --git a/library/axi_adaq8092/axi_adaq8092_apb_decode.v b/library/axi_adaq8092/axi_adaq8092_apb_decode.v
index 30a77dc1d..33f250835 100644
--- a/library/axi_adaq8092/axi_adaq8092_apb_decode.v
+++ b/library/axi_adaq8092/axi_adaq8092_apb_decode.v
@@ -32,7 +32,7 @@
 //
 // ***************************************************************************
 // ***************************************************************************
-// ADC ALTERNATE BIT POLARITY DECODE 
+// ADC ALTERNATE BIT POLARITY DECODE
 
 `timescale 1ns/100ps
 
@@ -41,23 +41,24 @@ module axi_adaq8092_apb_decode (
   input      [27:0]      adc_data,
   input                  adc_clk,
   input                  adc_abp_enb,
-  output     [27:0]      adc_data_decoded);
+  output     [27:0]      adc_data_decoded
+);
+
+  // internal registers
 
-  // internal registers 
- 
   reg        [27:0]      adc_data_decoded_s;
 
   // internal variable
 
-  integer i; 
+  integer i;
 
   assign adc_data_decoded = adc_abp_enb ? adc_data_decoded_s : adc_data ;
 
-  always @(posedge adc_clk) begin 
+  always @(posedge adc_clk) begin
     for (i = 0; i <= 13; i = i + 1) begin
       adc_data_decoded_s[2*i+1] = ~adc_data[2*i+1];
       adc_data_decoded_s[2*i] = adc_data[2*i];
     end
-  end  
+  end
 
 endmodule
diff --git a/library/axi_adaq8092/axi_adaq8092_channel.v b/library/axi_adaq8092/axi_adaq8092_channel.v
index f38446353..803992d3b 100644
--- a/library/axi_adaq8092/axi_adaq8092_channel.v
+++ b/library/axi_adaq8092/axi_adaq8092_channel.v
@@ -39,7 +39,8 @@
 module axi_adaq8092_channel #(
 
   parameter CHANNEL_ID = 0,
-  parameter DATAPATH_DISABLE = 0) (
+  parameter DATAPATH_DISABLE = 0
+) (
 
   // adc interface
 
@@ -66,7 +67,8 @@ module axi_adaq8092_channel #(
   input                   up_rreq,
   input       [13:0]      up_raddr,
   output      [31:0]      up_rdata,
-  output                  up_rack);
+  output                  up_rack
+);
 
   // internal signals
 
@@ -77,7 +79,7 @@ module axi_adaq8092_channel #(
   wire            adc_dfmt_enable_s;
   wire    [15:0]  adc_dcfilt_offset_s;
   wire    [15:0]  adc_dcfilt_coeff_s;
-      
+
   generate
     if (DATAPATH_DISABLE == 1) begin
       assign adc_dfmt_data_s = {2'b0 , adc_data};
@@ -110,8 +112,8 @@ module axi_adaq8092_channel #(
         .dcfilt_coeff (adc_dcfilt_coeff_s),
         .dcfilt_offset (adc_dcfilt_offset_s));
     end
-  endgenerate 
-  
+  endgenerate
+
   up_adc_channel #(
     .COMMON_ID (6'h01),
     .CHANNEL_ID(CHANNEL_ID),
diff --git a/library/axi_adaq8092/axi_adaq8092_if.v b/library/axi_adaq8092/axi_adaq8092_if.v
index 608af9081..681cb7d17 100644
--- a/library/axi_adaq8092/axi_adaq8092_if.v
+++ b/library/axi_adaq8092/axi_adaq8092_if.v
@@ -43,7 +43,8 @@ module axi_adaq8092_if #(
   parameter          IO_DELAY_GROUP = "adc_if_delay_group",
   parameter          DELAY_REFCLK_FREQUENCY = 200,
   parameter   [27:0] POLARITY_MASK ='hfffffff,
-  parameter          OUTPUT_MODE = 0) (
+  parameter          OUTPUT_MODE = 0
+) (
 
   // adc interface (clk, data, over-range)
   // nominal clock 80 MHz, up to 105 MHz
@@ -60,14 +61,14 @@ module axi_adaq8092_if #(
   input                    cmos_adc_data_or_1,
   input                    cmos_adc_data_or_2,
 
-  // up control SDR or DDR 
+  // up control SDR or DDR
 
   input                    sdr_or_ddr,
-  
+
   // interface outputs
 
   output                  adc_clk,
-  output  reg [27:0]      adc_data, 
+  output  reg [27:0]      adc_data,
   output  reg             adc_or,
   output  reg             adc_status,
 
@@ -79,7 +80,8 @@ module axi_adaq8092_if #(
   output      [149:0]     up_drdata,
   input                   delay_clk,
   input                   delay_rst,
-  output                  delay_locked);
+  output                  delay_locked
+);
 
   // internal registers
 
@@ -105,73 +107,73 @@ module axi_adaq8092_if #(
 
   localparam LVDS =  0;
   localparam CMOS =  1;
-  
+
   always @(posedge adc_clk) begin
 
     adc_status <= 1'b1;
-    
-    if (OUTPUT_MODE == LVDS) begin         
-    
+
+    if (OUTPUT_MODE == LVDS) begin
+
       adc_or <= adc_or_s_1 | adc_or_s_2;
-      adc_data <= POLARITY_MASK ^ adc_data_s; 
-      adc_data_s <= { lvds_adc_data_n_s[13], lvds_adc_data_p_s[13], 
-                      lvds_adc_data_n_s[12], lvds_adc_data_p_s[12], 
-                      lvds_adc_data_n_s[11], lvds_adc_data_p_s[11], 
-                      lvds_adc_data_n_s[10], lvds_adc_data_p_s[10], 
-                      lvds_adc_data_n_s[9],  lvds_adc_data_p_s[9], 
-                      lvds_adc_data_n_s[8],  lvds_adc_data_p_s[8], 
-                      lvds_adc_data_n_s[7],  lvds_adc_data_p_s[7], 
-                      lvds_adc_data_n_s[6],  lvds_adc_data_p_s[6], 
-                      lvds_adc_data_n_s[5],  lvds_adc_data_p_s[5], 
-                      lvds_adc_data_n_s[4],  lvds_adc_data_p_s[4], 
-                      lvds_adc_data_n_s[3],  lvds_adc_data_p_s[3], 
-                      lvds_adc_data_n_s[2],  lvds_adc_data_p_s[2], 
-                      lvds_adc_data_n_s[1],  lvds_adc_data_p_s[1], 
+      adc_data <= POLARITY_MASK ^ adc_data_s;
+      adc_data_s <= { lvds_adc_data_n_s[13], lvds_adc_data_p_s[13],
+                      lvds_adc_data_n_s[12], lvds_adc_data_p_s[12],
+                      lvds_adc_data_n_s[11], lvds_adc_data_p_s[11],
+                      lvds_adc_data_n_s[10], lvds_adc_data_p_s[10],
+                      lvds_adc_data_n_s[9],  lvds_adc_data_p_s[9],
+                      lvds_adc_data_n_s[8],  lvds_adc_data_p_s[8],
+                      lvds_adc_data_n_s[7],  lvds_adc_data_p_s[7],
+                      lvds_adc_data_n_s[6],  lvds_adc_data_p_s[6],
+                      lvds_adc_data_n_s[5],  lvds_adc_data_p_s[5],
+                      lvds_adc_data_n_s[4],  lvds_adc_data_p_s[4],
+                      lvds_adc_data_n_s[3],  lvds_adc_data_p_s[3],
+                      lvds_adc_data_n_s[2],  lvds_adc_data_p_s[2],
+                      lvds_adc_data_n_s[1],  lvds_adc_data_p_s[1],
                       lvds_adc_data_n_s[0],  lvds_adc_data_p_s[0]};
-    
-    end else if (OUTPUT_MODE == CMOS) begin  
+
+    end else if (OUTPUT_MODE == CMOS) begin
       adc_data <= adc_data_s;
       if (sdr_or_ddr == 0) begin            //DDR_CMOS
         adc_or <= adc_or_s_1_p | adc_or_s_1_n;
-        adc_data_s <= { cmos_adc_data_n_s[27], cmos_adc_data_p_s[27], 
-                        cmos_adc_data_n_s[25], cmos_adc_data_p_s[25], 
-                        cmos_adc_data_n_s[23], cmos_adc_data_p_s[23], 
-                        cmos_adc_data_n_s[21], cmos_adc_data_p_s[21], 
-                        cmos_adc_data_n_s[19], cmos_adc_data_p_s[19], 
-                        cmos_adc_data_n_s[17], cmos_adc_data_p_s[17], 
-                        cmos_adc_data_n_s[15], cmos_adc_data_p_s[15], 
-                        cmos_adc_data_n_s[13], cmos_adc_data_p_s[13], 
-                        cmos_adc_data_n_s[11], cmos_adc_data_p_s[11], 
-                        cmos_adc_data_n_s[9],  cmos_adc_data_p_s[9], 
-                        cmos_adc_data_n_s[7],  cmos_adc_data_p_s[7], 
-                        cmos_adc_data_n_s[5],  cmos_adc_data_p_s[5], 
-                        cmos_adc_data_n_s[3],  cmos_adc_data_p_s[3], 
+        adc_data_s <= { cmos_adc_data_n_s[27], cmos_adc_data_p_s[27],
+                        cmos_adc_data_n_s[25], cmos_adc_data_p_s[25],
+                        cmos_adc_data_n_s[23], cmos_adc_data_p_s[23],
+                        cmos_adc_data_n_s[21], cmos_adc_data_p_s[21],
+                        cmos_adc_data_n_s[19], cmos_adc_data_p_s[19],
+                        cmos_adc_data_n_s[17], cmos_adc_data_p_s[17],
+                        cmos_adc_data_n_s[15], cmos_adc_data_p_s[15],
+                        cmos_adc_data_n_s[13], cmos_adc_data_p_s[13],
+                        cmos_adc_data_n_s[11], cmos_adc_data_p_s[11],
+                        cmos_adc_data_n_s[9],  cmos_adc_data_p_s[9],
+                        cmos_adc_data_n_s[7],  cmos_adc_data_p_s[7],
+                        cmos_adc_data_n_s[5],  cmos_adc_data_p_s[5],
+                        cmos_adc_data_n_s[3],  cmos_adc_data_p_s[3],
                         cmos_adc_data_n_s[1],  cmos_adc_data_p_s[1]};
       end else if (sdr_or_ddr == 1) begin    //SDR_CMOS
         adc_or <= adc_or_s_1_p | adc_or_s_2_p;
-        adc_data_s <= { cmos_adc_data_p_s[27], cmos_adc_data_p_s[26], 
-                        cmos_adc_data_p_s[25], cmos_adc_data_p_s[24], 
-                        cmos_adc_data_p_s[23], cmos_adc_data_p_s[22], 
-                        cmos_adc_data_p_s[21], cmos_adc_data_p_s[20], 
-                        cmos_adc_data_p_s[19], cmos_adc_data_p_s[18], 
-                        cmos_adc_data_p_s[17], cmos_adc_data_p_s[16], 
-                        cmos_adc_data_p_s[15], cmos_adc_data_p_s[14], 
-                        cmos_adc_data_p_s[13], cmos_adc_data_p_s[12], 
-                        cmos_adc_data_p_s[11], cmos_adc_data_p_s[10], 
-                        cmos_adc_data_p_s[9],  cmos_adc_data_p_s[8], 
-                        cmos_adc_data_p_s[7],  cmos_adc_data_p_s[6], 
-                        cmos_adc_data_p_s[5],  cmos_adc_data_p_s[4], 
-                        cmos_adc_data_p_s[3],  cmos_adc_data_p_s[2], 
-                        cmos_adc_data_p_s[1],  cmos_adc_data_p_s[0]}; 
+        adc_data_s <= { cmos_adc_data_p_s[27], cmos_adc_data_p_s[26],
+                        cmos_adc_data_p_s[25], cmos_adc_data_p_s[24],
+                        cmos_adc_data_p_s[23], cmos_adc_data_p_s[22],
+                        cmos_adc_data_p_s[21], cmos_adc_data_p_s[20],
+                        cmos_adc_data_p_s[19], cmos_adc_data_p_s[18],
+                        cmos_adc_data_p_s[17], cmos_adc_data_p_s[16],
+                        cmos_adc_data_p_s[15], cmos_adc_data_p_s[14],
+                        cmos_adc_data_p_s[13], cmos_adc_data_p_s[12],
+                        cmos_adc_data_p_s[11], cmos_adc_data_p_s[10],
+                        cmos_adc_data_p_s[9],  cmos_adc_data_p_s[8],
+                        cmos_adc_data_p_s[7],  cmos_adc_data_p_s[6],
+                        cmos_adc_data_p_s[5],  cmos_adc_data_p_s[4],
+                        cmos_adc_data_p_s[3],  cmos_adc_data_p_s[2],
+                        cmos_adc_data_p_s[1],  cmos_adc_data_p_s[0]};
       end
-    end 
+    end
   end
 
   // data interface
 
   generate
     if (OUTPUT_MODE == LVDS) begin
-      for (l_inst = 0; l_inst <= 13; l_inst = l_inst + 1) begin : lvds_adc_if  // DDR LVDS INTERFACE 
+      for (l_inst = 0; l_inst <= 13; l_inst = l_inst + 1) begin : lvds_adc_if  // DDR LVDS INTERFACE
         ad_data_in #(
           .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
           .IODELAY_CTRL (0),
@@ -191,10 +193,10 @@ module axi_adaq8092_if #(
           .delay_clk (delay_clk),
           .delay_rst (delay_rst),
           .delay_locked ());
-      end          
+      end
     end else if (OUTPUT_MODE == CMOS) begin
 
-       for (l_inst = 0; l_inst <= 27; l_inst = l_inst + 1) begin : cmos_adc_if  //  CMOS INTERFACE 
+       for (l_inst = 0; l_inst <= 27; l_inst = l_inst + 1) begin : cmos_adc_if  //  CMOS INTERFACE
         ad_data_in #(
           .SINGLE_ENDED(1),
           .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
@@ -215,8 +217,8 @@ module axi_adaq8092_if #(
           .delay_clk (delay_clk),
           .delay_rst (delay_rst),
           .delay_locked ());
-      end 
-    end       
+      end
+    end
   endgenerate
 
   // over-range interface
@@ -262,7 +264,7 @@ module axi_adaq8092_if #(
       .delay_clk (delay_clk),
       .delay_rst (delay_rst),
       .delay_locked ());
-    
+
     ad_data_in #(
       .SINGLE_ENDED(1),
       .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
@@ -284,7 +286,7 @@ module axi_adaq8092_if #(
       .delay_rst (delay_rst),
       .delay_locked ());
   end
-  
+
   // clock
 
   ad_data_clk i_adc_clk (
@@ -293,5 +295,5 @@ module axi_adaq8092_if #(
     .clk_in_p (adc_clk_in_p),
     .clk_in_n (adc_clk_in_n),
     .clk (adc_clk));
-    
+
 endmodule
diff --git a/library/axi_adaq8092/axi_adaq8092_rand_decode.v b/library/axi_adaq8092/axi_adaq8092_rand_decode.v
index 2431fb1b9..3c76c5dc7 100644
--- a/library/axi_adaq8092/axi_adaq8092_rand_decode.v
+++ b/library/axi_adaq8092/axi_adaq8092_rand_decode.v
@@ -32,20 +32,21 @@
 //
 // ***************************************************************************
 // ***************************************************************************
-// ADC DIGITAL OUTPUT RANDOMIZE DECODE 
+// ADC DIGITAL OUTPUT RANDOMIZE DECODE
 
 `timescale 1ns/100ps
 
 module axi_adaq8092_rand_decode (
 
-  // data interface 
+  // data interface
 
   input       [27:0]      adc_data,
   input                   adc_clk,
   input                   adc_rand_enb,
-  output      [27:0]      adc_data_decoded);
-  
-  // internal register 
+  output      [27:0]      adc_data_decoded
+);
+
+  // internal register
 
   reg [27:0] adc_data_decoded_s;
 
@@ -55,7 +56,7 @@ module axi_adaq8092_rand_decode (
 
   // DATA DECODING
 
-  always @(posedge adc_clk) begin 
+  always @(posedge adc_clk) begin
     for (i = 1; i <= 13; i = i + 1) begin
       adc_data_decoded_s[i] = adc_data[i] ^ adc_data[0];
     end
@@ -63,8 +64,8 @@ module axi_adaq8092_rand_decode (
       adc_data_decoded_s[i] = adc_data[i] ^ adc_data[14];
     end
 
-    adc_data_decoded_s[0] = adc_data[0];  
+    adc_data_decoded_s[0] = adc_data[0];
     adc_data_decoded_s[14] = adc_data[14];
   end
-    
+
 endmodule
diff --git a/library/axi_adc_decimate/axi_adc_decimate.v b/library/axi_adc_decimate/axi_adc_decimate.v
index 1a7f791f2..b2a29b0d1 100644
--- a/library/axi_adc_decimate/axi_adc_decimate.v
+++ b/library/axi_adc_decimate/axi_adc_decimate.v
@@ -37,8 +37,8 @@
 
 module axi_adc_decimate #(
 
-  parameter CORRECTION_DISABLE = 1) (
-
+  parameter CORRECTION_DISABLE = 1
+) (
   input                 adc_clk,
   input                 adc_rst,
 
@@ -76,7 +76,8 @@ module axi_adc_decimate #(
   output                s_axi_rvalid,
   output      [31:0]    s_axi_rdata,
   output      [ 1:0]    s_axi_rresp,
-  input                 s_axi_rready);
+  input                 s_axi_rready
+);
 
   // internal signals
 
@@ -130,7 +131,6 @@ module axi_adc_decimate #(
     .adc_dec_valid_b(adc_dec_valid_b));
 
   axi_adc_decimate_reg axi_adc_decimate_reg (
-
     .clk (adc_clk),
 
     .adc_decimation_ratio (decimation_ratio),
@@ -152,9 +152,9 @@ module axi_adc_decimate #(
     .up_rdata (up_rdata),
     .up_rack (up_rack));
 
- up_axi #(
+  up_axi #(
     .AXI_ADDRESS_WIDTH(7)
- ) i_up_axi (
+  ) i_up_axi (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_axi_awvalid (s_axi_awvalid),
@@ -184,6 +184,3 @@ module axi_adc_decimate #(
     .up_rack (up_rack));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_adc_decimate/axi_adc_decimate_filter.v b/library/axi_adc_decimate/axi_adc_decimate_filter.v
index f78bf6bc4..9cba878c9 100644
--- a/library/axi_adc_decimate/axi_adc_decimate_filter.v
+++ b/library/axi_adc_decimate/axi_adc_decimate_filter.v
@@ -35,11 +35,10 @@
 
 `timescale 1ns/100ps
 
-
 module axi_adc_decimate_filter #(
 
-  parameter CORRECTION_DISABLE = 1) (
-
+  parameter CORRECTION_DISABLE = 1
+) (
   input                 adc_clk,
   input                 adc_rst,
 
@@ -122,7 +121,8 @@ module axi_adc_decimate_filter #(
     .filter_out(adc_fir_data_b),
     .ce_out(adc_fir_valid_b));
 
-  ad_iqcor #(.Q_OR_I_N (0),
+  ad_iqcor #(
+    .Q_OR_I_N (0),
     .DISABLE(CORRECTION_DISABLE),
     .SCALE_ONLY(1)
   ) i_scale_correction_a (
@@ -136,7 +136,8 @@ module axi_adc_decimate_filter #(
     .iqcor_coeff_1 (adc_correction_coefficient_a),
     .iqcor_coeff_2 (16'h0));
 
-  ad_iqcor #(.Q_OR_I_N (0),
+  ad_iqcor #(
+    .Q_OR_I_N (0),
     .DISABLE(CORRECTION_DISABLE),
     .SCALE_ONLY(1)
   ) i_scale_correction_b (
@@ -172,7 +173,7 @@ module axi_adc_decimate_filter #(
       default: adc_dec_valid_a_filter = adc_fir_valid_a;
     endcase
 
-     case (filter_enable[0])
+    case (filter_enable[0])
       1'b0: adc_dec_data_b_r = {{4{adc_data_b[11]}},adc_data_b};
       default adc_dec_data_b_r = {adc_fir_data_b[25], adc_fir_data_b[25:11]};
     endcase
diff --git a/library/axi_adc_decimate/axi_adc_decimate_reg.v b/library/axi_adc_decimate/axi_adc_decimate_reg.v
index efe5a0006..507b2f6d7 100644
--- a/library/axi_adc_decimate/axi_adc_decimate_reg.v
+++ b/library/axi_adc_decimate/axi_adc_decimate_reg.v
@@ -58,7 +58,8 @@ module axi_adc_decimate_reg(
   input               up_rreq,
   input       [ 4:0]  up_raddr,
   output  reg [31:0]  up_rdata,
-  output  reg         up_rack);
+  output  reg         up_rack
+);
 
   // internal registers
 
@@ -129,7 +130,9 @@ module axi_adc_decimate_reg(
     end
   end
 
-   up_xfer_cntrl #(.DATA_WIDTH(69)) i_xfer_cntrl (
+  up_xfer_cntrl #(
+    .DATA_WIDTH (69)
+  ) i_xfer_cntrl (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_data_cntrl ({ up_config[1],                 // 1
@@ -150,7 +153,3 @@ module axi_adc_decimate_reg(
                       adc_filter_mask}));           // 3
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
-
diff --git a/library/axi_adc_decimate/cic_decim.v b/library/axi_adc_decimate/cic_decim.v
index f97b9654f..daf847a3e 100644
--- a/library/axi_adc_decimate/cic_decim.v
+++ b/library/axi_adc_decimate/cic_decim.v
@@ -44,7 +44,7 @@ module cic_decim (
   input [2:0] rate_sel,
   output [11:0] filter_out,
   output ce_out
-  );
+);
 
   localparam NUM_STAGES = 6;
   localparam DATA_WIDTH = 106;
@@ -110,8 +110,7 @@ module cic_decim (
         .clk(clk),
         .ce(enable),
         .data_in(data_stage[i]),
-        .data_out(data_stage[i+1])
-      );
+        .data_out(data_stage[i+1]));
     end
   endgenerate
 
@@ -125,8 +124,7 @@ module cic_decim (
     .ce(ce_comb),
     .enable(filter_enable),
     .data_in(data_stage[6]),
-    .data_out(data_stage[11])
-  );
+    .data_out(data_stage[11]));
 
   cic_comb #(
     .DATA_WIDTH(DATA_WIDTH),
@@ -138,8 +136,7 @@ module cic_decim (
     .ce(ce_comb),
     .enable(filter_enable),
     .data_in(data_stage[11]),
-    .data_out(data_stage[12])
-  );
+    .data_out(data_stage[12]));
 
   assign data_final_stage = data_stage[2*NUM_STAGES];
 
diff --git a/library/axi_adc_trigger/axi_adc_trigger.v b/library/axi_adc_trigger/axi_adc_trigger.v
index bdd6368a8..4a738744a 100644
--- a/library/axi_adc_trigger/axi_adc_trigger.v
+++ b/library/axi_adc_trigger/axi_adc_trigger.v
@@ -40,7 +40,8 @@ module axi_adc_trigger #(
   // parameters
 
   parameter SIGN_BITS = 2,
-  parameter OUT_PIN_HOLD_N = 100000) (
+  parameter OUT_PIN_HOLD_N = 100000
+) (
 
   // interface
 
@@ -89,8 +90,8 @@ module axi_adc_trigger #(
   output                s_axi_rvalid,
   output      [31:0]    s_axi_rdata,
   output      [ 1:0]    s_axi_rresp,
-  input                 s_axi_rready);
-
+  input                 s_axi_rready
+);
 
   localparam DW = 15 - SIGN_BITS;
 
@@ -211,7 +212,6 @@ module axi_adc_trigger #(
   reg                   trigger_out_hold;
   reg                   trigger_out_ack;
 
-
   // signal name changes
 
   assign up_clk = s_axi_aclk;
@@ -278,7 +278,6 @@ module axi_adc_trigger #(
     trigger_o[1] <= (trig_o_hold_cnt_1 == 'd0) ? trigger_o_m[1] : trig_o_hold_1;
   end
 
-
   // 1. keep data in sync with the trigger. The trigger bypasses the variable
   // fifo. The data goes through and it is delayed with 4 clock cycles)
   // 2. For non max sample rate of the ADC, the trigger signal that originates
@@ -344,7 +343,6 @@ module axi_adc_trigger #(
     end
   end
 
-
   always @(posedge clk) begin
     if (trigger_delay == 0) begin
       if (streaming == 1'b1 && data_valid_a == 1'b1 && trigger_out_holdoff == 1'b1) begin
@@ -470,7 +468,7 @@ module axi_adc_trigger #(
       (trigger_b_any_edge & any_edge[1]));
   end
 
-   always @(*) begin
+  always @(*) begin
     case(trigger_out_control[3:0])
       4'h0: trigger_out_mixed = trigger_a;
       4'h1: trigger_out_mixed = trigger_b;
@@ -569,54 +567,53 @@ module axi_adc_trigger #(
   assign comp_low_b_s = !comp_high_b;
 
   axi_adc_trigger_reg adc_trigger_registers (
+    .clk(clk),
 
-  .clk(clk),
+    .io_selection(io_selection),
+    .trigger_o(trigger_up_o_s),
+    .triggered(up_triggered),
 
-  .io_selection(io_selection),
-  .trigger_o(trigger_up_o_s),
-  .triggered(up_triggered),
+    .low_level(low_level),
+    .high_level(high_level),
+    .any_edge(any_edge),
+    .rise_edge(rise_edge),
+    .fall_edge(fall_edge),
 
-  .low_level(low_level),
-  .high_level(high_level),
-  .any_edge(any_edge),
-  .rise_edge(rise_edge),
-  .fall_edge(fall_edge),
+    .limit_a(limit_a),
+    .function_a(function_a),
+    .hysteresis_a(hysteresis_a),
+    .trigger_l_mix_a(trigger_l_mix_a),
 
-  .limit_a(limit_a),
-  .function_a(function_a),
-  .hysteresis_a(hysteresis_a),
-  .trigger_l_mix_a(trigger_l_mix_a),
+    .limit_b(limit_b),
+    .function_b(function_b),
+    .hysteresis_b(hysteresis_b),
+    .trigger_l_mix_b(trigger_l_mix_b),
 
-  .limit_b(limit_b),
-  .function_b(function_b),
-  .hysteresis_b(hysteresis_b),
-  .trigger_l_mix_b(trigger_l_mix_b),
+    .trigger_out_control(trigger_out_control),
+    .trigger_delay(trigger_delay),
+    .trigger_holdoff (trigger_holdoff),
+    .trigger_out_hold_pins (trigger_out_hold_pins),
 
-  .trigger_out_control(trigger_out_control),
-  .trigger_delay(trigger_delay),
-  .trigger_holdoff (trigger_holdoff),
-  .trigger_out_hold_pins (trigger_out_hold_pins),
+    .fifo_depth(fifo_depth),
 
-  .fifo_depth(fifo_depth),
+    .streaming(streaming),
 
-  .streaming(streaming),
+    // bus interface
 
-  // bus interface
+    .up_rstn(up_rstn),
+    .up_clk(up_clk),
+    .up_wreq(up_wreq),
+    .up_waddr(up_waddr),
+    .up_wdata(up_wdata),
+    .up_wack(up_wack),
+    .up_rreq(up_rreq),
+    .up_raddr(up_raddr),
+    .up_rdata(up_rdata),
+    .up_rack(up_rack));
 
-  .up_rstn(up_rstn),
-  .up_clk(up_clk),
-  .up_wreq(up_wreq),
-  .up_waddr(up_waddr),
-  .up_wdata(up_wdata),
-  .up_wack(up_wack),
-  .up_rreq(up_rreq),
-  .up_raddr(up_raddr),
-  .up_rdata(up_rdata),
-  .up_rack(up_rack));
-
- up_axi #(
+  up_axi #(
     .AXI_ADDRESS_WIDTH(7)
- ) i_up_axi (
+  ) i_up_axi (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_axi_awvalid (s_axi_awvalid),
@@ -646,6 +643,3 @@ module axi_adc_trigger #(
     .up_rack (up_rack));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_adc_trigger/axi_adc_trigger_reg.v b/library/axi_adc_trigger/axi_adc_trigger_reg.v
index 9338ab948..eeb11a966 100644
--- a/library/axi_adc_trigger/axi_adc_trigger_reg.v
+++ b/library/axi_adc_trigger/axi_adc_trigger_reg.v
@@ -67,7 +67,7 @@ module axi_adc_trigger_reg (
 
   output              streaming,
 
- // bus interface
+  // bus interface
 
   input               up_rstn,
   input               up_clk,
@@ -78,7 +78,8 @@ module axi_adc_trigger_reg (
   input               up_rreq,
   input       [ 4:0]  up_raddr,
   output reg  [31:0]  up_rdata,
-  output reg          up_rack);
+  output reg          up_rack
+);
 
   localparam DEFAULT_OUT_HOLD = 100000; // 1ms
 
@@ -239,7 +240,9 @@ module axi_adc_trigger_reg (
     end
   end
 
-   up_xfer_cntrl #(.DATA_WIDTH(262)) i_xfer_cntrl (
+  up_xfer_cntrl #(
+    .DATA_WIDTH(262)
+  ) i_xfer_cntrl (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_data_cntrl ({ up_streaming,             // 1
@@ -259,7 +262,6 @@ module axi_adc_trigger_reg (
                       up_trigger_holdoff,       // 32
                       up_trigger_out_hold_pins, // 20
                       up_trigger_delay}),       // 32
-
     .up_xfer_done (),
     .d_rst (1'b0),
     .d_clk (clk),
@@ -282,7 +284,3 @@ module axi_adc_trigger_reg (
                       trigger_delay}));      // 32
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
-
diff --git a/library/axi_adrv9001/adrv9001_pack.v b/library/axi_adrv9001/adrv9001_pack.v
index 410178fbb..981ccdd96 100644
--- a/library/axi_adrv9001/adrv9001_pack.v
+++ b/library/axi_adrv9001/adrv9001_pack.v
@@ -51,7 +51,7 @@
 
 module adrv9001_pack #(
   parameter WIDTH = 8
-)(
+) (
   input                      clk,    // Input clock
   input                      rst,
   input                      sof,    // Start of frame indicator marking the MS Beat
diff --git a/library/axi_adrv9001/adrv9001_rx.v b/library/axi_adrv9001/adrv9001_rx.v
index 7ea217829..37aee935f 100644
--- a/library/axi_adrv9001/adrv9001_rx.v
+++ b/library/axi_adrv9001/adrv9001_rx.v
@@ -44,6 +44,7 @@ module adrv9001_rx #(
   parameter USE_BUFG = 0,
   parameter IO_DELAY_GROUP = "dev_if_delay_group"
 ) (
+
   // device interface
   input                   rx_dclk_in_n_NC,
   input                   rx_dclk_in_p_dclk_in,
@@ -114,8 +115,8 @@ module adrv9001_rx #(
     .DDR_OR_SDR_N (DDR_OR_SDR_N),
     .DATA_WIDTH (NUM_LANES),
     .DRP_WIDTH (DRP_WIDTH),
-    .SERDES_FACTOR (8))
-  i_serdes (
+    .SERDES_FACTOR (8)
+  ) i_serdes (
     .rst (adc_rst|ssi_rst),
     .clk (adc_clk_in_fast),
     .div_clk (adc_clk_div),
@@ -196,7 +197,9 @@ module adrv9001_rx #(
       .I (clk_in_s),
       .O (adc_clk_in_fast));
 
-    BUFR #(.BUFR_DIVIDE("4")) i_div_clk_buf (
+    BUFR #(
+      .BUFR_DIVIDE("4")
+    ) i_div_clk_buf (
       .CLR (mssi_sync),
       .CE (1'b1),
       .I (clk_in_s),
@@ -205,24 +208,19 @@ module adrv9001_rx #(
     if (USE_BUFG == 1) begin
       BUFG I_bufg (
         .I (adc_clk_div_s),
-        .O (adc_clk_div)
-      );
+        .O (adc_clk_div));
     end else begin
       assign adc_clk_div = adc_clk_div_s;
     end
 
-    xpm_cdc_async_rst
-    # (
-       .DEST_SYNC_FF    (10), // DECIMAL; range: 2-10
-       .INIT_SYNC_FF    ( 0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
-       .RST_ACTIVE_HIGH ( 1)  // DECIMAL; 0=active low reset, 1=active high reset
-      )
-    rst_syncro
-    (
-     .src_arst (mssi_sync  ),
-     .dest_clk (adc_clk_div),
-     .dest_arst(ssi_rst    )
-    );
+    xpm_cdc_async_rst #(
+      .DEST_SYNC_FF    (10), // DECIMAL; range: 2-10
+      .INIT_SYNC_FF    ( 0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
+      .RST_ACTIVE_HIGH ( 1)  // DECIMAL; 0=active low reset, 1=active high reset
+    ) rst_syncro (
+      .src_arst (mssi_sync),
+      .dest_clk (adc_clk_div),
+      .dest_arst(ssi_rst));
 
   end else begin
     wire adc_clk_in;
@@ -248,26 +246,24 @@ module adrv9001_rx #(
     assign adc_clk_in = clk_in_s;
 
     BUFGCE #(
-       .CE_TYPE ("SYNC"),
-       .IS_CE_INVERTED (1'b0),
-       .IS_I_INVERTED (1'b0)
+      .CE_TYPE ("SYNC"),
+      .IS_CE_INVERTED (1'b0),
+      .IS_I_INVERTED (1'b0)
     ) i_clk_buf_fast (
-       .O (adc_clk_in_fast),
-       .CE (1'b1),
-       .I (adc_clk_in)
-    );
+      .O (adc_clk_in_fast),
+      .CE (1'b1),
+      .I (adc_clk_in));
 
     BUFGCE_DIV #(
-       .BUFGCE_DIVIDE (4),
-       .IS_CE_INVERTED (1'b0),
-       .IS_CLR_INVERTED (1'b0),
-       .IS_I_INVERTED (1'b0)
+      .BUFGCE_DIVIDE (4),
+      .IS_CE_INVERTED (1'b0),
+      .IS_CLR_INVERTED (1'b0),
+      .IS_I_INVERTED (1'b0)
     ) i_div_clk_buf (
-       .O (adc_clk_div),
-       .CE (1'b1),
-       .CLR (ssi_rst),
-       .I (adc_clk_in)
-    );
+      .O (adc_clk_div),
+      .CE (1'b1),
+      .CLR (ssi_rst),
+      .I (adc_clk_in));
 
     assign ssi_rst = ssi_rst_pos;
 
diff --git a/library/axi_adrv9001/adrv9001_rx_link.v b/library/axi_adrv9001/adrv9001_rx_link.v
index bf96482b9..34c76a80a 100644
--- a/library/axi_adrv9001/adrv9001_rx_link.v
+++ b/library/axi_adrv9001/adrv9001_rx_link.v
@@ -38,7 +38,6 @@
 module adrv9001_rx_link #(
   parameter CMOS_LVDS_N = 0
 ) (
-
   input         adc_rst,
   input         adc_clk_div,
   input   [7:0] adc_data_0,
@@ -107,8 +106,7 @@ module adrv9001_rx_link #(
       .idata (sdr_data_0),
       .ivalid (adc_valid),
       .strobe (sdr_data_strobe),
-      .odata (sdr_data_0_aligned)
-    );
+      .odata (sdr_data_0_aligned));
 
     adrv9001_aligner4 i_rx_aligner4_1 (
       .clk (adc_clk_div),
@@ -116,8 +114,7 @@ module adrv9001_rx_link #(
       .idata (sdr_data_1),
       .ivalid (adc_valid),
       .strobe (sdr_data_strobe),
-      .odata (sdr_data_1_aligned)
-    );
+      .odata (sdr_data_1_aligned));
 
     adrv9001_aligner4 i_rx_aligner4_2 (
       .clk (adc_clk_div),
@@ -125,8 +122,7 @@ module adrv9001_rx_link #(
       .idata (sdr_data_2),
       .ivalid (adc_valid),
       .strobe (sdr_data_strobe),
-      .odata (sdr_data_2_aligned)
-    );
+      .odata (sdr_data_2_aligned));
 
     adrv9001_aligner4 i_rx_aligner4_3 (
       .clk (adc_clk_div),
@@ -134,8 +130,7 @@ module adrv9001_rx_link #(
       .idata (sdr_data_3),
       .ivalid (adc_valid),
       .strobe (sdr_data_strobe),
-      .odata (sdr_data_3_aligned)
-    );
+      .odata (sdr_data_3_aligned));
 
     adrv9001_aligner4 i_rx_aligner4_strobe (
       .clk (adc_clk_div),
@@ -144,8 +139,7 @@ module adrv9001_rx_link #(
       .ivalid (adc_valid),
       .strobe (sdr_data_strobe),
       .ovalid (aligner4_ovalid),
-      .odata (sdr_data_strobe_aligned)
-    );
+      .odata (sdr_data_strobe_aligned));
 
     adrv9001_pack #(
       .WIDTH(4)
@@ -156,8 +150,7 @@ module adrv9001_rx_link #(
       .ivalid (aligner4_ovalid),
       .sof (sdr_data_strobe_aligned[3]),
       .odata (sdr_data_0_packed),
-      .ovalid (sdr_data_valid)
-    );
+      .ovalid (sdr_data_valid));
 
     adrv9001_pack #(
       .WIDTH(4)
@@ -168,8 +161,7 @@ module adrv9001_rx_link #(
       .ivalid (aligner4_ovalid),
       .sof (sdr_data_strobe_aligned[3]),
       .odata (sdr_data_1_packed),
-      .ovalid ()
-    );
+      .ovalid ());
 
     adrv9001_pack #(
       .WIDTH(4)
@@ -179,8 +171,7 @@ module adrv9001_rx_link #(
       .ivalid (aligner4_ovalid),
       .sof (sdr_data_strobe_aligned[3]),
       .odata (sdr_data_2_packed),
-      .ovalid ()
-    );
+      .ovalid ());
 
     adrv9001_pack #(
       .WIDTH(4)
@@ -191,8 +182,7 @@ module adrv9001_rx_link #(
       .ivalid (aligner4_ovalid),
       .sof (sdr_data_strobe_aligned[3]),
       .odata (sdr_data_3_packed),
-      .ovalid ()
-    );
+      .ovalid ());
 
     adrv9001_pack #(
       .WIDTH(4)
@@ -203,8 +193,8 @@ module adrv9001_rx_link #(
       .ivalid (aligner4_ovalid),
       .sof (sdr_data_strobe_aligned[3]),
       .odata (sdr_data_strobe_packed),
-      .ovalid ()
-    );
+      .ovalid ());
+
     assign data_0 = rx_sdr_ddr_n ? sdr_data_0_packed : adc_data_0;
     assign data_1 = rx_sdr_ddr_n ? sdr_data_1_packed : adc_data_1;
     assign data_2 = rx_sdr_ddr_n ? sdr_data_2_packed : adc_data_2;
@@ -241,54 +231,50 @@ module adrv9001_rx_link #(
   wire [31:0] rx_data32_0_packed;
   wire        rx_data32_0_packed_valid;
 
-  adrv9001_aligner8 i_rx_aligner8_0(
+  adrv9001_aligner8 i_rx_aligner8_0 (
     .clk (adc_clk_div),
     .rst (adc_rst),
     .idata (data_0),
     .ivalid (data_valid),
     .strobe (data_strobe),
     .odata (rx_data8_0_aligned),
-    .ovalid (rx_data8_0_aligned_valid)
-  );
+    .ovalid (rx_data8_0_aligned_valid));
 
-  adrv9001_aligner8 i_rx_aligner8_1(
+  adrv9001_aligner8 i_rx_aligner8_1 (
     .clk (adc_clk_div),
     .rst (adc_rst),
     .ivalid (data_valid),
     .idata (data_1),
     .strobe (data_strobe),
     .odata (rx_data8_1_aligned),
-    .ovalid (rx_data8_1_aligned_valid)
-  );
+    .ovalid (rx_data8_1_aligned_valid));
 
   generate if (CMOS_LVDS_N) begin : cmos_aligner8
-    adrv9001_aligner8 i_rx_aligner8_2(
+    adrv9001_aligner8 i_rx_aligner8_2 (
       .clk (adc_clk_div),
       .rst (adc_rst),
       .idata (data_2),
       .ivalid (data_valid),
       .strobe (data_strobe),
-      .odata (rx_data8_2_aligned)
-    );
+      .odata (rx_data8_2_aligned));
+
     adrv9001_aligner8 i_rx_aligner8_3(
       .clk (adc_clk_div),
       .rst (adc_rst),
       .idata (data_3),
       .ivalid (data_valid),
       .strobe (data_strobe),
-      .odata (rx_data8_3_aligned)
-    );
+      .odata (rx_data8_3_aligned));
   end
   endgenerate
 
-  adrv9001_aligner8 i_rx_strobe_aligner(
+  adrv9001_aligner8 i_rx_strobe_aligner (
     .clk (adc_clk_div),
     .rst (adc_rst),
     .idata (data_strobe),
     .ivalid (data_valid),
     .strobe (data_strobe),
-    .odata (rx_data8_strobe_aligned)
-  );
+    .odata (rx_data8_strobe_aligned));
 
   adrv9001_pack #(
     .WIDTH (8)
@@ -300,8 +286,7 @@ module adrv9001_rx_link #(
     .sof (rx_data8_strobe_aligned[7]),
     .odata (rx_data16_0_packed),
     .ovalid (rx_data16_0_packed_valid),
-    .osof (rx_data16_0_packed_osof)
-  );
+    .osof (rx_data16_0_packed_osof));
 
   adrv9001_pack #(
     .WIDTH (8)
@@ -313,8 +298,7 @@ module adrv9001_rx_link #(
     .sof (rx_data8_strobe_aligned[7]),
     .odata (rx_data16_1_packed),
     .ovalid (rx_data16_1_paked_valid),
-    .osof (rx_data16_1_packed_osof)
-  );
+    .osof (rx_data16_1_packed_osof));
 
   adrv9001_pack #(
     .WIDTH (16)
@@ -326,15 +310,14 @@ module adrv9001_rx_link #(
     .sof (rx_data16_0_packed_osof),
     .odata (rx_data32_0_packed),
     .ovalid (rx_data32_0_packed_valid),
-    .osof (rx_data32_0_packed_osof)
-  );
+    .osof (rx_data32_0_packed_osof));
 
   generate if (CMOS_LVDS_N) begin
     assign rx_data_i = ~rx_single_lane ? {rx_data8_1_aligned,rx_data8_0_aligned} :
                                          (rx_symb_op ? rx_data16_0_packed : rx_data32_0_packed[31:16]);
     assign rx_data_q = ~rx_single_lane ? {rx_data8_3_aligned,rx_data8_2_aligned} :
                                          (rx_symb_op ? 'b0 : rx_data32_0_packed[15:0]);
-    assign rx_data_valid = ~rx_single_lane ? rx_data8_0_aligned_valid : 
+    assign rx_data_valid = ~rx_single_lane ? rx_data8_0_aligned_valid :
                                              (rx_symb_op ? (rx_symb_8_16b ? rx_data8_0_aligned_valid : rx_data16_0_packed_valid) : rx_data32_0_packed_valid);
   end else begin
     assign rx_data_i = ~rx_single_lane ? rx_data16_0_packed :
diff --git a/library/axi_adrv9001/adrv9001_tx.v b/library/axi_adrv9001/adrv9001_tx.v
index 9d679bd1f..48f1aea44 100644
--- a/library/axi_adrv9001/adrv9001_tx.v
+++ b/library/axi_adrv9001/adrv9001_tx.v
@@ -103,8 +103,8 @@ module adrv9001_tx #(
     .DDR_OR_SDR_N(1),
     .DATA_WIDTH(NUM_LANES),
     .SERDES_FACTOR(8),
-    .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY))
-  i_serdes (
+    .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY)
+  ) i_serdes (
     .rst (dac_rst|ssi_rst),
     .clk (dac_fast_clk),
     .div_clk (dac_clk_div),
@@ -184,7 +184,9 @@ module adrv9001_tx #(
         .O (dac_fast_clk));
 
       // SERDES slow clock
-      BUFR #(.BUFR_DIVIDE("4")) i_dac_div_clk_rbuf (
+      BUFR #(
+        .BUFR_DIVIDE("4")
+      ) i_dac_div_clk_rbuf (
         .CLR (mssi_sync),
         .CE (1'b1),
         .I (tx_dclk_in_s),
@@ -192,25 +194,20 @@ module adrv9001_tx #(
 
       if (USE_BUFG == 1) begin
         BUFG I_bufg (
-         .I (dac_clk_div_s),
-         .O (dac_clk_div)
-        );
+          .I (dac_clk_div_s),
+          .O (dac_clk_div));
       end else begin
         assign dac_clk_div = dac_clk_div_s;
       end
 
-      xpm_cdc_async_rst
-      # (
-         .DEST_SYNC_FF    (10), // DECIMAL; range: 2-10
-         .INIT_SYNC_FF    ( 0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
-         .RST_ACTIVE_HIGH ( 1)  // DECIMAL; 0=active low reset, 1=active high reset
-        )
-      rst_syncro
-      (
-       .src_arst (mssi_sync  ),
-       .dest_clk (dac_clk_div),
-       .dest_arst(ssi_rst    )
-      );
+      xpm_cdc_async_rst #(
+        .DEST_SYNC_FF    (10), // DECIMAL; range: 2-10
+        .INIT_SYNC_FF    ( 0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
+        .RST_ACTIVE_HIGH ( 1)  // DECIMAL; 0=active low reset, 1=active high reset
+      ) rst_syncro (
+        .src_arst (mssi_sync),
+        .dest_clk (dac_clk_div),
+        .dest_arst(ssi_rst));
 
     end else begin
 
@@ -222,26 +219,24 @@ module adrv9001_tx #(
       end
 
       BUFGCE #(
-         .CE_TYPE ("SYNC"),
-         .IS_CE_INVERTED (1'b0),
-         .IS_I_INVERTED (1'b0)
+        .CE_TYPE ("SYNC"),
+        .IS_CE_INVERTED (1'b0),
+        .IS_I_INVERTED (1'b0)
       ) i_dac_clk_in_gbuf (
-         .O (dac_fast_clk),
-         .CE (1'b1),
-         .I (tx_dclk_in_s)
-      );
+        .O (dac_fast_clk),
+        .CE (1'b1),
+        .I (tx_dclk_in_s));
 
       BUFGCE_DIV #(
-         .BUFGCE_DIVIDE (4),
-         .IS_CE_INVERTED (1'b0),
-         .IS_CLR_INVERTED (1'b0),
-         .IS_I_INVERTED (1'b0)
+        .BUFGCE_DIVIDE (4),
+        .IS_CE_INVERTED (1'b0),
+        .IS_CLR_INVERTED (1'b0),
+        .IS_I_INVERTED (1'b0)
       ) i_dac_div_clk_rbuf (
-         .O (dac_clk_div),
-         .CE (1'b1),
-         .CLR (mssi_sync_2d),
-         .I (tx_dclk_in_s)
-      );
+        .O (dac_clk_div),
+        .CE (1'b1),
+        .CLR (mssi_sync_2d),
+        .I (tx_dclk_in_s));
 
       assign ssi_rst = mssi_sync_2d;
 
diff --git a/library/axi_adrv9001/adrv9001_tx_link.v b/library/axi_adrv9001/adrv9001_tx_link.v
index d5915f04d..cd9b0d358 100644
--- a/library/axi_adrv9001/adrv9001_tx_link.v
+++ b/library/axi_adrv9001/adrv9001_tx_link.v
@@ -58,9 +58,9 @@ module adrv9001_tx_link  #(
   // Config interface
   input          tx_sdr_ddr_n,
   input          tx_single_lane,
-  input          tx_symb_op,                
-  input          tx_symb_8_16b                 
-);                                                           
+  input          tx_symb_op,
+  input          tx_symb_8_16b
+);
 
   assign tx_clk = dac_clk_div;
 
@@ -74,7 +74,7 @@ module adrv9001_tx_link  #(
   wire [7:0] data8sdr_2;
   wire [7:0] data8sdr_3;
   wire [7:0] strobe8sdr;
-  
+
   wire       ld_next;
 
   reg [31:0] data32 = 32'b0;
@@ -122,15 +122,15 @@ module adrv9001_tx_link  #(
       data16_1 <= tx_data_q;
       strobe16 <= {1'b1,15'b0};
     end else if (ld_next) begin
-     if(tx_sdr_ddr_n) begin
-       data16_0 <= {data16_0,4'b0};
-       data16_1 <= {data16_1,4'b0};
-       strobe16 <= {strobe16,4'b0};
-     end else begin
-       data16_0 <= {data16_0,8'b0};
-       data16_1 <= {data16_1,8'b0};
-       strobe16 <= {strobe16,8'b0};
-     end
+      if(tx_sdr_ddr_n) begin
+        data16_0 <= {data16_0,4'b0};
+        data16_1 <= {data16_1,4'b0};
+        strobe16 <= {strobe16,4'b0};
+      end else begin
+        data16_0 <= {data16_0,8'b0};
+        data16_1 <= {data16_1,8'b0};
+        strobe16 <= {strobe16,8'b0};
+      end
     end
   end
 
@@ -138,7 +138,7 @@ module adrv9001_tx_link  #(
   assign data16sdr_0 = {data16_0[15],data16_0[15],
                         data16_0[14],data16_0[14],
                         data16_0[13],data16_0[13],
-                        data16_0[12],data16_0[12]}; 
+                        data16_0[12],data16_0[12]};
   assign strobe16sdr = {strobe16[15],strobe16[15],
                         strobe16[14],strobe16[14],
                         strobe16[13],strobe16[13],
@@ -198,7 +198,7 @@ module adrv9001_tx_link  #(
   assign dac_data_3 = tx_single_lane ? 'b0 :
                            (CMOS_LVDS_N ? (tx_sdr_ddr_n ? data8sdr_3 : data8_3) :
                            1'b0);
- 
+
   assign dac_data_strobe = tx_single_lane ? (tx_symb_op ? (tx_symb_8_16b ? (tx_sdr_ddr_n ? strobe8sdr : strobe8) :
                            (tx_sdr_ddr_n ? strobe16sdr : strobe16[15-:8])):
                            (tx_sdr_ddr_n ? strobe32sdr : strobe32[31-:8])) :
@@ -215,6 +215,6 @@ module adrv9001_tx_link  #(
       valid_gen <= {valid_gen[2:0],valid_gen[3]};
     end
   end
- assign ld_next = (CLK_DIV_IS_FAST_CLK == 0) ? 1'b1 : valid_gen[2];
+  assign ld_next = (CLK_DIV_IS_FAST_CLK == 0) ? 1'b1 : valid_gen[2];
 
 endmodule
diff --git a/library/axi_adrv9001/axi_adrv9001.v b/library/axi_adrv9001/axi_adrv9001.v
index cdde36d84..8649c4456 100644
--- a/library/axi_adrv9001/axi_adrv9001.v
+++ b/library/axi_adrv9001/axi_adrv9001.v
@@ -286,7 +286,7 @@ module axi_adrv9001 #(
     .DISABLE_RX2_SSI (DISABLE_RX2_SSI),
     .DISABLE_TX2_SSI (DISABLE_TX2_SSI),
     .USE_RX_CLK_FOR_TX (USE_RX_CLK_FOR_TX)
-  ) i_if(
+  ) i_if (
 
     //
     // Physical interface
@@ -404,8 +404,7 @@ module axi_adrv9001 #(
     .tx2_single_lane (tx2_single_lane),
     .tx2_sdr_ddr_n (tx2_sdr_ddr_n),
     .tx2_symb_op (tx2_symb_op),
-    .tx2_symb_8_16b (tx2_symb_8_16b)
-  );
+    .tx2_symb_8_16b (tx2_symb_8_16b));
 
   // common processor control
   axi_adrv9001_core #(
@@ -551,8 +550,7 @@ module axi_adrv9001 #(
     .up_rreq (up_rreq_s),
     .up_raddr (up_raddr_s),
     .up_rdata (up_rdata_s),
-    .up_rack (up_rack_s)
-  );
+    .up_rack (up_rack_s));
 
   assign adc_1_valid_i0 = adc_1_valid;
   assign adc_1_valid_q0 = adc_1_valid;
@@ -576,7 +574,7 @@ module axi_adrv9001 #(
   // up bus interface
   up_axi #(
     .AXI_ADDRESS_WIDTH(15)
-    ) i_up_axi (
+  ) i_up_axi (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_axi_awvalid (s_axi_awvalid),
@@ -603,8 +601,7 @@ module axi_adrv9001 #(
     .up_wack (up_wack_s),
     .up_raddr (up_raddr_s[12:0]),
     .up_rreq (up_rreq_s),
-    .up_rack (up_rack_s)
-  );
+    .up_rack (up_rack_s));
 
   // Alias Rx/Tx peripherals @ 0x8000
   assign up_raddr_s[13] = 1'b0;
diff --git a/library/axi_adrv9001/axi_adrv9001_core.v b/library/axi_adrv9001/axi_adrv9001_core.v
index 13e50d5e8..5fc21cb9a 100644
--- a/library/axi_adrv9001/axi_adrv9001_core.v
+++ b/library/axi_adrv9001/axi_adrv9001_core.v
@@ -57,6 +57,7 @@ module axi_adrv9001_core #(
   parameter DAC_DDS_CORDIC_DW = 20,
   parameter DAC_DDS_CORDIC_PHASE_DW = 18
 ) (
+
   // ADC interface
   input                   rx1_clk,
   output                  rx1_rst,
@@ -245,8 +246,8 @@ module axi_adrv9001_core #(
 
   sync_bits #(
     .NUM_OF_BITS (6),
-    .ASYNC_CLK (1))
-  i_rx1_ctrl_sync (
+    .ASYNC_CLK (1)
+  ) i_rx1_ctrl_sync (
     .in_bits ({up_rx1_r1_mode,rx1_symb_op,rx1_symb_8_16b,rx1_sdr_ddr_n,rx1_single_lane,rx1_rst}),
     .out_clk (rx2_clk),
     .out_resetn (1'b1),
@@ -254,8 +255,8 @@ module axi_adrv9001_core #(
 
   sync_bits #(
     .NUM_OF_BITS (6),
-    .ASYNC_CLK (1))
-  i_tx1_ctrl_sync (
+    .ASYNC_CLK (1)
+  ) i_tx1_ctrl_sync (
     .in_bits ({up_tx1_r1_mode,tx1_symb_op,tx1_symb_8_16b,tx1_sdr_ddr_n,tx1_single_lane,tx1_rst}),
     .out_clk (tx2_clk),
     .out_resetn (1'b1),
@@ -324,8 +325,8 @@ module axi_adrv9001_core #(
 
   sync_event #(
     .NUM_OF_EVENTS (1),
-    .ASYNC_CLK (1))
-  i_rx_external_sync (
+    .ASYNC_CLK (1)
+  ) i_rx_external_sync (
     .in_clk (ref_clk),
     .in_event (adc_sync_in),
     .out_clk (rx1_clk),
@@ -352,8 +353,8 @@ module axi_adrv9001_core #(
 
   sync_event #(
     .NUM_OF_EVENTS (1),
-    .ASYNC_CLK (1))
-  i_tx_external_sync (
+    .ASYNC_CLK (1)
+  ) i_tx_external_sync (
     .in_clk (ref_clk),
     .in_event (dac_sync_in),
     .out_clk (tx1_clk),
@@ -388,8 +389,8 @@ module axi_adrv9001_core #(
     .DEV_PACKAGE (DEV_PACKAGE),
     .DATAFORMAT_DISABLE (0),
     .DCFILTER_DISABLE (1),
-    .IQCORRECTION_DISABLE (1))
-  i_rx1 (
+    .IQCORRECTION_DISABLE (1)
+  ) i_rx1 (
     .adc_rst (rx1_rst),
     .adc_clk (rx1_clk),
     .adc_valid_A (rx1_data_valid & tdd_rx1_valid & sync_adc_valid),
@@ -453,8 +454,8 @@ module axi_adrv9001_core #(
     .DEV_PACKAGE (DEV_PACKAGE),
     .DATAFORMAT_DISABLE (0),
     .DCFILTER_DISABLE (1),
-    .IQCORRECTION_DISABLE (1))
-  i_rx2 (
+    .IQCORRECTION_DISABLE (1)
+  ) i_rx2 (
     .adc_rst (rx2_rst_loc),
     .adc_clk (rx2_clk),
     .adc_valid_A (rx2_data_valid & tdd_rx2_valid & sync_adc_valid),
@@ -515,8 +516,8 @@ module axi_adrv9001_core #(
     .IQCORRECTION_DISABLE (1),
     .DAC_DDS_TYPE (DAC_DDS_TYPE),
     .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
-    .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
-  i_tx1 (
+    .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW)
+  ) i_tx1 (
     .dac_rst (tx1_rst),
     .dac_clk (tx1_clk),
     .dac_data_valid_A (tx1_data_valid_A),
@@ -573,8 +574,8 @@ module axi_adrv9001_core #(
     .IQCORRECTION_DISABLE (1),
     .DAC_DDS_TYPE (DAC_DDS_TYPE),
     .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
-    .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
-  i_tx2 (
+    .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW)
+  ) i_tx2 (
     .dac_rst (tx2_rst_loc),
     .dac_clk (tx2_clk),
     .dac_data_valid_A (tx2_data_valid_A),
@@ -616,8 +617,8 @@ module axi_adrv9001_core #(
   up_delay_cntrl #(
     .DATA_WIDTH(NUM_LANES),
     .DRP_WIDTH(DRP_WIDTH),
-    .BASE_ADDRESS(6'h02))
-  i_delay_cntrl_rx1 (
+    .BASE_ADDRESS(6'h02)
+  ) i_delay_cntrl_rx1 (
     .delay_clk (delay_clk),
     .delay_rst (delay_rx1_rst),
     .delay_locked (delay_rx1_locked),
@@ -639,8 +640,8 @@ module axi_adrv9001_core #(
     .DATA_WIDTH(NUM_LANES),
     .DRP_WIDTH(DRP_WIDTH),
     .DISABLE(DISABLE_RX2_SSI),
-    .BASE_ADDRESS(6'h06))
-  i_delay_cntrl_rx2 (
+    .BASE_ADDRESS(6'h06)
+  ) i_delay_cntrl_rx2 (
     .delay_clk (delay_clk),
     .delay_rst (delay_rx2_rst),
     .delay_locked (delay_rx2_locked),
@@ -723,4 +724,3 @@ module axi_adrv9001_core #(
   assign tdd_sync_cntr = tdd_sync_cntr1 | tdd_sync_cntr2;
 
 endmodule
-
diff --git a/library/axi_adrv9001/axi_adrv9001_if.v b/library/axi_adrv9001/axi_adrv9001_if.v
index 790c51174..a4c15e4c7 100644
--- a/library/axi_adrv9001/axi_adrv9001_if.v
+++ b/library/axi_adrv9001/axi_adrv9001_if.v
@@ -267,8 +267,7 @@ module axi_adrv9001_if #(
     .rx_single_lane (rx1_single_lane),
     .rx_sdr_ddr_n (rx1_sdr_ddr_n),
     .rx_symb_op (rx1_symb_op),
-    .rx_symb_8_16b (rx1_symb_8_16b)
-  );
+    .rx_symb_8_16b (rx1_symb_8_16b));
 
   generate if (DISABLE_RX2_SSI == 0) begin
     adrv9001_rx
@@ -332,8 +331,7 @@ module axi_adrv9001_if #(
       .rx_single_lane (rx2_single_lane),
       .rx_sdr_ddr_n (rx2_sdr_ddr_n),
       .rx_symb_op (rx2_symb_op),
-      .rx_symb_8_16b (rx2_symb_8_16b)
-    );
+      .rx_symb_8_16b (rx2_symb_8_16b));
   end else begin
     assign delay_rx2_locked = 1'b1;
     assign up_rx2_drdata = 'h0;
@@ -345,48 +343,46 @@ module axi_adrv9001_if #(
   endgenerate
 
   adrv9001_tx #(
-   .CMOS_LVDS_N (CMOS_LVDS_N),
-   .NUM_LANES (TX_NUM_LANES),
-   .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
-   .USE_BUFG (TX_USE_BUFG),
-   .USE_RX_CLK_FOR_TX (USE_RX_CLK_FOR_TX)
+    .CMOS_LVDS_N (CMOS_LVDS_N),
+    .NUM_LANES (TX_NUM_LANES),
+    .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
+    .USE_BUFG (TX_USE_BUFG),
+    .USE_RX_CLK_FOR_TX (USE_RX_CLK_FOR_TX)
   ) i_tx_1_phy (
+    .ref_clk (ref_clk),
+    .up_clk (up_clk),
 
-   .ref_clk (ref_clk),
-   .up_clk (up_clk),
+    .tx_output_enable(tx_output_enable),
 
-   .tx_output_enable(tx_output_enable),
+    .tx_dclk_out_n_NC (tx1_dclk_out_n_NC),
+    .tx_dclk_out_p_dclk_out (tx1_dclk_out_p_dclk_out),
+    .tx_dclk_in_n_NC (tx1_dclk_in_n_NC),
+    .tx_dclk_in_p_dclk_in (tx1_dclk_in_p_dclk_in),
+    .tx_idata_out_n_idata0 (tx1_idata_out_n_idata0),
+    .tx_idata_out_p_idata1 (tx1_idata_out_p_idata1),
+    .tx_qdata_out_n_qdata2 (tx1_qdata_out_n_qdata2),
+    .tx_qdata_out_p_qdata3 (tx1_qdata_out_p_qdata3),
+    .tx_strobe_out_n_NC (tx1_strobe_out_n_NC),
+    .tx_strobe_out_p_strobe_out (tx1_strobe_out_p_strobe_out),
 
-   .tx_dclk_out_n_NC (tx1_dclk_out_n_NC),
-   .tx_dclk_out_p_dclk_out (tx1_dclk_out_p_dclk_out),
-   .tx_dclk_in_n_NC (tx1_dclk_in_n_NC),
-   .tx_dclk_in_p_dclk_in (tx1_dclk_in_p_dclk_in),
-   .tx_idata_out_n_idata0 (tx1_idata_out_n_idata0),
-   .tx_idata_out_p_idata1 (tx1_idata_out_p_idata1),
-   .tx_qdata_out_n_qdata2 (tx1_qdata_out_n_qdata2),
-   .tx_qdata_out_p_qdata3 (tx1_qdata_out_p_qdata3),
-   .tx_strobe_out_n_NC (tx1_strobe_out_n_NC),
-   .tx_strobe_out_p_strobe_out (tx1_strobe_out_p_strobe_out),
+    .rx_clk_div (adc_1_clk_div),
+    .rx_clk (adc_1_clk),
+    .rx_ssi_rst (adc_1_ssi_rst),
 
-   .rx_clk_div (adc_1_clk_div),
-   .rx_clk (adc_1_clk),
-   .rx_ssi_rst (adc_1_ssi_rst),
+    .dac_rst (tx1_rst),
+    .dac_clk_div (dac_1_clk_div),
 
-   .dac_rst (tx1_rst),
-   .dac_clk_div (dac_1_clk_div),
+    .dac_data_0 (dac_1_data_0),
+    .dac_data_1 (dac_1_data_1),
+    .dac_data_2 (dac_1_data_2),
+    .dac_data_3 (dac_1_data_3),
+    .dac_data_strb (dac_1_data_strobe),
+    .dac_data_clk (dac_1_data_clk),
+    .dac_data_valid (dac_1_data_valid),
 
-   .dac_data_0 (dac_1_data_0),
-   .dac_data_1 (dac_1_data_1),
-   .dac_data_2 (dac_1_data_2),
-   .dac_data_3 (dac_1_data_3),
-   .dac_data_strb (dac_1_data_strobe),
-   .dac_data_clk (dac_1_data_clk),
-   .dac_data_valid (dac_1_data_valid),
+    .dac_clk_ratio (dac_clk_ratio),
 
-   .dac_clk_ratio (dac_clk_ratio),
-
-   .mssi_sync (mssi_sync)
-  );
+    .mssi_sync (mssi_sync));
 
   adrv9001_tx_link #(
     .CMOS_LVDS_N (CMOS_LVDS_N),
@@ -409,51 +405,48 @@ module axi_adrv9001_if #(
     .tx_sdr_ddr_n (tx1_sdr_ddr_n),
     .tx_single_lane (tx1_single_lane),
     .tx_symb_op (tx1_symb_op),
-    .tx_symb_8_16b (tx1_symb_8_16b)
-  );
+    .tx_symb_8_16b (tx1_symb_8_16b));
 
   generate if (DISABLE_TX2_SSI == 0) begin
     adrv9001_tx #(
-     .CMOS_LVDS_N (CMOS_LVDS_N),
-     .NUM_LANES (TX_NUM_LANES),
-     .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
-     .USE_BUFG (TX_USE_BUFG),
-     .USE_RX_CLK_FOR_TX (USE_RX_CLK_FOR_TX)
+      .CMOS_LVDS_N (CMOS_LVDS_N),
+      .NUM_LANES (TX_NUM_LANES),
+      .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
+      .USE_BUFG (TX_USE_BUFG),
+      .USE_RX_CLK_FOR_TX (USE_RX_CLK_FOR_TX)
     ) i_tx_2_phy (
+      .ref_clk (ref_clk),
+      .up_clk (up_clk),
 
-     .ref_clk (ref_clk),
-     .up_clk (up_clk),
+      .tx_output_enable(tx_output_enable),
 
-     .tx_output_enable(tx_output_enable),
+      .tx_dclk_out_n_NC (tx2_dclk_out_n_NC),
+      .tx_dclk_out_p_dclk_out (tx2_dclk_out_p_dclk_out),
+      .tx_dclk_in_n_NC (tx2_dclk_in_n_NC),
+      .tx_dclk_in_p_dclk_in (tx2_dclk_in_p_dclk_in),
+      .tx_idata_out_n_idata0 (tx2_idata_out_n_idata0),
+      .tx_idata_out_p_idata1 (tx2_idata_out_p_idata1),
+      .tx_qdata_out_n_qdata2 (tx2_qdata_out_n_qdata2),
+      .tx_qdata_out_p_qdata3 (tx2_qdata_out_p_qdata3),
+      .tx_strobe_out_n_NC (tx2_strobe_out_n_NC),
+      .tx_strobe_out_p_strobe_out (tx2_strobe_out_p_strobe_out),
 
-     .tx_dclk_out_n_NC (tx2_dclk_out_n_NC),
-     .tx_dclk_out_p_dclk_out (tx2_dclk_out_p_dclk_out),
-     .tx_dclk_in_n_NC (tx2_dclk_in_n_NC),
-     .tx_dclk_in_p_dclk_in (tx2_dclk_in_p_dclk_in),
-     .tx_idata_out_n_idata0 (tx2_idata_out_n_idata0),
-     .tx_idata_out_p_idata1 (tx2_idata_out_p_idata1),
-     .tx_qdata_out_n_qdata2 (tx2_qdata_out_n_qdata2),
-     .tx_qdata_out_p_qdata3 (tx2_qdata_out_p_qdata3),
-     .tx_strobe_out_n_NC (tx2_strobe_out_n_NC),
-     .tx_strobe_out_p_strobe_out (tx2_strobe_out_p_strobe_out),
+      .rx_clk_div (adc_2_clk_div),
+      .rx_clk (adc_2_clk),
+      .rx_ssi_rst (adc_2_ssi_rst),
 
-     .rx_clk_div (adc_2_clk_div),
-     .rx_clk (adc_2_clk),
-     .rx_ssi_rst (adc_2_ssi_rst),
+      .dac_rst (tx2_rst),
+      .dac_clk_div (dac_2_clk_div),
 
-     .dac_rst (tx2_rst),
-     .dac_clk_div (dac_2_clk_div),
+      .dac_data_0 (dac_2_data_0),
+      .dac_data_1 (dac_2_data_1),
+      .dac_data_2 (dac_2_data_2),
+      .dac_data_3 (dac_2_data_3),
+      .dac_data_strb (dac_2_data_strobe),
+      .dac_data_clk (dac_2_data_clk),
+      .dac_data_valid (dac_2_data_valid),
 
-     .dac_data_0 (dac_2_data_0),
-     .dac_data_1 (dac_2_data_1),
-     .dac_data_2 (dac_2_data_2),
-     .dac_data_3 (dac_2_data_3),
-     .dac_data_strb (dac_2_data_strobe),
-     .dac_data_clk (dac_2_data_clk),
-     .dac_data_valid (dac_2_data_valid),
-
-     .mssi_sync (mssi_sync)
-    );
+      .mssi_sync (mssi_sync));
 
     adrv9001_tx_link #(
       .CMOS_LVDS_N (CMOS_LVDS_N),
@@ -476,8 +469,7 @@ module axi_adrv9001_if #(
       .tx_sdr_ddr_n (tx2_sdr_ddr_n),
       .tx_single_lane (tx2_single_lane),
       .tx_symb_op (tx2_symb_op),
-      .tx_symb_8_16b (tx2_symb_8_16b)
-    );
+      .tx_symb_8_16b (tx2_symb_8_16b));
   end else begin
     assign tx2_clk = 1'b0;
     assign tx2_dclk_out_n_NC = 1'b0;
@@ -492,4 +484,3 @@ module axi_adrv9001_if #(
   endgenerate
 
 endmodule
-
diff --git a/library/axi_adrv9001/axi_adrv9001_rx.v b/library/axi_adrv9001/axi_adrv9001_rx.v
index ce832abe8..6b329243a 100644
--- a/library/axi_adrv9001/axi_adrv9001_rx.v
+++ b/library/axi_adrv9001/axi_adrv9001_rx.v
@@ -50,6 +50,7 @@ module axi_adrv9001_rx #(
   parameter   DCFILTER_DISABLE = 0,
   parameter   IQCORRECTION_DISABLE = 1
 ) (
+
   // adc interface
   output                  adc_rst,
   input                   adc_clk,
@@ -108,303 +109,300 @@ module axi_adrv9001_rx #(
   output  reg             up_rack
 );
 
-generate
-if (ENABLED == 0) begin : core_disabled
+  generate
+  if (ENABLED == 0) begin : core_disabled
 
-  assign adc_rst = 1'b0;
-  assign adc_single_lane = 1'b0;
-  assign adc_sdr_ddr_n = 1'b0;
-  assign adc_symb_op = 1'b0;
-  assign adc_symb_8_16b = 1'b0;
-  assign up_adc_r1_mode = 1'b0;
-  assign adc_valid = 1'b0;
-  assign adc_enable_i0 = 1'b0;
-  assign adc_data_i0 = 16'b0;
-  assign adc_enable_q0 = 1'b0;
-  assign adc_data_q0 = 16'b0;
-  assign adc_enable_i1 = 1'b0;
-  assign adc_data_i1 = 16'b0;
-  assign adc_enable_q1 = 1'b0;
-  assign adc_data_q1 = 16'b0;
+    assign adc_rst = 1'b0;
+    assign adc_single_lane = 1'b0;
+    assign adc_sdr_ddr_n = 1'b0;
+    assign adc_symb_op = 1'b0;
+    assign adc_symb_8_16b = 1'b0;
+    assign up_adc_r1_mode = 1'b0;
+    assign adc_valid = 1'b0;
+    assign adc_enable_i0 = 1'b0;
+    assign adc_data_i0 = 16'b0;
+    assign adc_enable_q0 = 1'b0;
+    assign adc_data_q0 = 16'b0;
+    assign adc_enable_i1 = 1'b0;
+    assign adc_data_i1 = 16'b0;
+    assign adc_enable_q1 = 1'b0;
+    assign adc_data_q1 = 16'b0;
 
-  always @(*) begin
-    up_wack = 1'b0;
-    up_rdata = 32'b0;
-    up_rack = 1'b0;
-  end
-
-end else begin : core_enabled
-
-  // configuration settings
-
-  localparam  CONFIG =  (CMOS_LVDS_N * 128) +
-                        (MODE_R1 * 16) +
-                        (DATAFORMAT_DISABLE * 4) +
-                        (DCFILTER_DISABLE * 2) +
-                        (IQCORRECTION_DISABLE * 1);
-
-  // internal registers
-
-  reg               up_status_pn_err = 'd0;
-  reg               up_status_pn_oos = 'd0;
-  reg               up_status_or = 'd0;
-
-  // internal signals
-
-  wire    [ 15:0]   adc_data_iq_i0_s;
-  wire    [ 15:0]   adc_data_iq_q0_s;
-  wire    [ 15:0]   adc_data_iq_i1_s;
-  wire    [ 15:0]   adc_data_iq_q1_s;
-  wire    [  4:0]   adc_num_lanes;
-  wire    [  3:0]   up_adc_pn_err_s;
-  wire    [  3:0]   up_adc_pn_oos_s;
-  wire    [  3:0]   up_adc_or_s;
-  wire    [  4:0]   up_wack_s;
-  wire    [  4:0]   up_rack_s;
-  wire    [ 31:0]   up_rdata_s[0:4];
-  wire              adc_valid_out_i0;
-  wire              adc_valid_out_i1;
-
-  // processor read interface
-
-  always @(negedge up_rstn or posedge up_clk) begin
-    if (up_rstn == 0) begin
-      up_status_pn_err <= 'd0;
-      up_status_pn_oos <= 'd0;
-      up_status_or <= 'd0;
-      up_wack <= 'd0;
-      up_rack <= 'd0;
-      up_rdata <= 'd0;
-    end else begin
-      up_status_pn_err <= up_adc_r1_mode ? | up_adc_pn_err_s[1:0] : | up_adc_pn_err_s[3:0];
-      up_status_pn_oos <= up_adc_r1_mode ? | up_adc_pn_oos_s[1:0] : | up_adc_pn_oos_s[3:0];
-      up_status_or <= | up_adc_or_s;
-      up_wack <= | up_wack_s;
-      up_rack <= | up_rack_s;
-      up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] |
-                  up_rdata_s[3] | up_rdata_s[4];
+    always @(*) begin
+      up_wack = 1'b0;
+      up_rdata = 32'b0;
+      up_rack = 1'b0;
     end
+
+  end else begin : core_enabled
+
+    // configuration settings
+
+    localparam  CONFIG =  (CMOS_LVDS_N * 128) +
+                          (MODE_R1 * 16) +
+                          (DATAFORMAT_DISABLE * 4) +
+                          (DCFILTER_DISABLE * 2) +
+                          (IQCORRECTION_DISABLE * 1);
+
+    // internal registers
+
+    reg               up_status_pn_err = 'd0;
+    reg               up_status_pn_oos = 'd0;
+    reg               up_status_or = 'd0;
+
+    // internal signals
+
+    wire    [ 15:0]   adc_data_iq_i0_s;
+    wire    [ 15:0]   adc_data_iq_q0_s;
+    wire    [ 15:0]   adc_data_iq_i1_s;
+    wire    [ 15:0]   adc_data_iq_q1_s;
+    wire    [  4:0]   adc_num_lanes;
+    wire    [  3:0]   up_adc_pn_err_s;
+    wire    [  3:0]   up_adc_pn_oos_s;
+    wire    [  3:0]   up_adc_or_s;
+    wire    [  4:0]   up_wack_s;
+    wire    [  4:0]   up_rack_s;
+    wire    [ 31:0]   up_rdata_s[0:4];
+    wire              adc_valid_out_i0;
+    wire              adc_valid_out_i1;
+
+    // processor read interface
+
+    always @(negedge up_rstn or posedge up_clk) begin
+      if (up_rstn == 0) begin
+        up_status_pn_err <= 'd0;
+        up_status_pn_oos <= 'd0;
+        up_status_or <= 'd0;
+        up_wack <= 'd0;
+        up_rack <= 'd0;
+        up_rdata <= 'd0;
+      end else begin
+        up_status_pn_err <= up_adc_r1_mode ? | up_adc_pn_err_s[1:0] : | up_adc_pn_err_s[3:0];
+        up_status_pn_oos <= up_adc_r1_mode ? | up_adc_pn_oos_s[1:0] : | up_adc_pn_oos_s[3:0];
+        up_status_or <= | up_adc_or_s;
+        up_wack <= | up_wack_s;
+        up_rack <= | up_rack_s;
+        up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] |
+                    up_rdata_s[3] | up_rdata_s[4];
+      end
+    end
+
+    // channel width is 32 bits
+
+    assign adc_valid = adc_enable_i0 ? adc_valid_out_i0 : adc_valid_out_i1;
+
+    // channel 0 (i)
+
+    axi_adrv9001_rx_channel #(
+      .Q_OR_I_N (0),
+      .COMMON_ID (CHANNEL_BASE_ADDR),
+      .DISABLE (0),
+      .DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
+      .DCFILTER_DISABLE (DCFILTER_DISABLE),
+      .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
+      .DATA_WIDTH (16)
+    ) i_rx_channel_0 (
+      .adc_clk (adc_clk),
+      .adc_rst (adc_rst),
+      .adc_valid_in (adc_valid_A),
+      .adc_data_in (adc_data_i_A[15:0]),
+      .adc_valid_out (adc_valid_out_i0),
+      .adc_data_out (adc_data_i0),
+      .adc_data_iq_in (adc_data_iq_q0_s),
+      .adc_data_iq_out (adc_data_iq_i0_s),
+      .adc_enable (adc_enable_i0),
+      .dac_valid_in (dac_data_valid_A),
+      .dac_data_in (dac_data_i_A),
+      .up_adc_pn_err (up_adc_pn_err_s[0]),
+      .up_adc_pn_oos (up_adc_pn_oos_s[0]),
+      .up_adc_or (up_adc_or_s[0]),
+      .up_rstn (up_rstn),
+      .up_clk (up_clk),
+      .up_wreq (up_wreq),
+      .up_waddr (up_waddr),
+      .up_wdata (up_wdata),
+      .up_wack (up_wack_s[0]),
+      .up_rreq (up_rreq),
+      .up_raddr (up_raddr),
+      .up_rdata (up_rdata_s[0]),
+      .up_rack (up_rack_s[0]));
+
+    // channel 1 (q)
+
+    axi_adrv9001_rx_channel #(
+      .Q_OR_I_N (1),
+      .COMMON_ID (CHANNEL_BASE_ADDR),
+      .CHANNEL_ID (1),
+      .DISABLE (0),
+      .DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
+      .DCFILTER_DISABLE (DCFILTER_DISABLE),
+      .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
+      .DATA_WIDTH (16)
+    ) i_rx_channel_1 (
+      .adc_clk (adc_clk),
+      .adc_rst (adc_rst),
+      .adc_valid_in (adc_valid_A),
+      .adc_data_in (adc_data_q_A[15:0]),
+      .adc_valid_out (),
+      .adc_data_out (adc_data_q0),
+      .adc_data_iq_in (adc_data_iq_i0_s),
+      .adc_data_iq_out (adc_data_iq_q0_s),
+      .adc_enable (adc_enable_q0),
+      .dac_valid_in (dac_data_valid_A),
+      .dac_data_in (dac_data_q_A),
+      .up_adc_pn_err (up_adc_pn_err_s[1]),
+      .up_adc_pn_oos (up_adc_pn_oos_s[1]),
+      .up_adc_or (up_adc_or_s[1]),
+      .up_rstn (up_rstn),
+      .up_clk (up_clk),
+      .up_wreq (up_wreq),
+      .up_waddr (up_waddr),
+      .up_wdata (up_wdata),
+      .up_wack (up_wack_s[1]),
+      .up_rreq (up_rreq),
+      .up_raddr (up_raddr),
+      .up_rdata (up_rdata_s[1]),
+      .up_rack (up_rack_s[1]));
+
+    // channel 2 (i)
+
+    axi_adrv9001_rx_channel #(
+      .Q_OR_I_N (0),
+      .COMMON_ID (CHANNEL_BASE_ADDR),
+      .CHANNEL_ID (2),
+      .DISABLE (MODE_R1),
+      .DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
+      .DCFILTER_DISABLE (DCFILTER_DISABLE),
+      .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
+      .DATA_WIDTH (16)
+    ) i_rx_channel_2 (
+      .adc_clk (adc_clk),
+      .adc_rst (adc_rst),
+      .adc_valid_in (adc_valid_B),
+      .adc_data_in (adc_data_i_B[15:0]),
+      .adc_valid_out (adc_valid_out_i1),
+      .adc_data_out (adc_data_i1),
+      .adc_data_iq_in (adc_data_iq_q1_s),
+      .adc_data_iq_out (adc_data_iq_i1_s),
+      .adc_enable (adc_enable_i1),
+      .dac_valid_in (dac_data_valid_B),
+      .dac_data_in (dac_data_i_B),
+      .up_adc_pn_err (up_adc_pn_err_s[2]),
+      .up_adc_pn_oos (up_adc_pn_oos_s[2]),
+      .up_adc_or (up_adc_or_s[2]),
+      .up_rstn (up_rstn),
+      .up_clk (up_clk),
+      .up_wreq (up_wreq),
+      .up_waddr (up_waddr),
+      .up_wdata (up_wdata),
+      .up_wack (up_wack_s[2]),
+      .up_rreq (up_rreq),
+      .up_raddr (up_raddr),
+      .up_rdata (up_rdata_s[2]),
+      .up_rack (up_rack_s[2]));
+
+    // channel 3 (q)
+
+    axi_adrv9001_rx_channel #(
+      .Q_OR_I_N (1),
+      .COMMON_ID (CHANNEL_BASE_ADDR),
+      .CHANNEL_ID (3),
+      .DISABLE (MODE_R1),
+      .DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
+      .DCFILTER_DISABLE (DCFILTER_DISABLE),
+      .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
+      .DATA_WIDTH (16)
+    ) i_rx_channel_3 (
+      .adc_clk (adc_clk),
+      .adc_rst (adc_rst),
+      .adc_valid_in (adc_valid_B),
+      .adc_data_in (adc_data_q_B[15:0]),
+      .adc_valid_out (),
+      .adc_data_out (adc_data_q1),
+      .adc_data_iq_in (adc_data_iq_i1_s),
+      .adc_data_iq_out (adc_data_iq_q1_s),
+      .adc_enable (adc_enable_q1),
+      .dac_valid_in (dac_data_valid_B),
+      .dac_data_in (dac_data_q_B),
+      .up_adc_pn_err (up_adc_pn_err_s[3]),
+      .up_adc_pn_oos (up_adc_pn_oos_s[3]),
+      .up_adc_or (up_adc_or_s[3]),
+      .up_rstn (up_rstn),
+      .up_clk (up_clk),
+      .up_wreq (up_wreq),
+      .up_waddr (up_waddr),
+      .up_wdata (up_wdata),
+      .up_wack (up_wack_s[3]),
+      .up_rreq (up_rreq),
+      .up_raddr (up_raddr),
+      .up_rdata (up_rdata_s[3]),
+      .up_rack (up_rack_s[3]));
+
+    // common processor control
+
+    up_adc_common #(
+      .ID (ID),
+      .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
+      .FPGA_FAMILY (FPGA_FAMILY),
+      .SPEED_GRADE (SPEED_GRADE),
+      .DEV_PACKAGE (DEV_PACKAGE),
+      .COMMON_ID (COMMON_BASE_ADDR),
+      .CONFIG(CONFIG),
+      .DRP_DISABLE(1),
+      .USERPORTS_DISABLE(1),
+      .GPIO_DISABLE(1),
+      .START_CODE_DISABLE(1)
+    ) i_up_adc_common (
+      .mmcm_rst (),
+      .adc_clk (adc_clk),
+      .adc_rst (adc_rst),
+      .adc_r1_mode (),
+      .adc_ddr_edgesel (),
+      .adc_pin_mode (),
+      .adc_status (1'b1),
+      .adc_sync_status (1'd0),
+      .adc_status_ovf (adc_dovf),
+      .adc_clk_ratio (adc_clk_ratio),
+      .adc_start_code (),
+      .adc_sref_sync (),
+      .adc_sync (adc_sync),
+      .adc_num_lanes (adc_num_lanes),
+      .adc_sdr_ddr_n (adc_sdr_ddr_n),
+      .adc_symb_op (adc_symb_op),
+      .adc_symb_8_16b (adc_symb_8_16b),
+      .up_pps_rcounter(32'h0),
+      .up_pps_status(1'b0),
+      .up_pps_irq_mask(),
+      .up_adc_r1_mode (up_adc_r1_mode),
+      .up_adc_ce (),
+      .up_status_pn_err (up_status_pn_err),
+      .up_status_pn_oos (up_status_pn_oos),
+      .up_status_or (up_status_or),
+      .up_drp_sel (),
+      .up_drp_wr (),
+      .up_drp_addr (),
+      .up_drp_wdata (),
+      .up_drp_rdata (32'd0),
+      .up_drp_ready (1'd0),
+      .up_drp_locked (1'd1),
+      .up_usr_chanmax_out (),
+      .up_usr_chanmax_in (8'd3),
+      .up_adc_gpio_in (32'd0),
+      .up_adc_gpio_out (),
+      .up_rstn (up_rstn),
+      .up_clk (up_clk),
+      .up_wreq (up_wreq),
+      .up_waddr (up_waddr),
+      .up_wdata (up_wdata),
+      .up_wack (up_wack_s[4]),
+      .up_rreq (up_rreq),
+      .up_raddr (up_raddr),
+      .up_rdata (up_rdata_s[4]),
+      .up_rack (up_rack_s[4]));
+
+    assign adc_single_lane = adc_num_lanes[0];
+
   end
-
-  // channel width is 32 bits
-
-  assign adc_valid = adc_enable_i0 ? adc_valid_out_i0 : adc_valid_out_i1;
-
-  // channel 0 (i)
-
-  axi_adrv9001_rx_channel #(
-    .Q_OR_I_N (0),
-    .COMMON_ID (CHANNEL_BASE_ADDR),
-    .DISABLE (0),
-    .DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
-    .DCFILTER_DISABLE (DCFILTER_DISABLE),
-    .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
-    .DATA_WIDTH (16))
-  i_rx_channel_0 (
-    .adc_clk (adc_clk),
-    .adc_rst (adc_rst),
-    .adc_valid_in (adc_valid_A),
-    .adc_data_in (adc_data_i_A[15:0]),
-    .adc_valid_out (adc_valid_out_i0),
-    .adc_data_out (adc_data_i0),
-    .adc_data_iq_in (adc_data_iq_q0_s),
-    .adc_data_iq_out (adc_data_iq_i0_s),
-    .adc_enable (adc_enable_i0),
-    .dac_valid_in (dac_data_valid_A),
-    .dac_data_in (dac_data_i_A),
-    .up_adc_pn_err (up_adc_pn_err_s[0]),
-    .up_adc_pn_oos (up_adc_pn_oos_s[0]),
-    .up_adc_or (up_adc_or_s[0]),
-    .up_rstn (up_rstn),
-    .up_clk (up_clk),
-    .up_wreq (up_wreq),
-    .up_waddr (up_waddr),
-    .up_wdata (up_wdata),
-    .up_wack (up_wack_s[0]),
-    .up_rreq (up_rreq),
-    .up_raddr (up_raddr),
-    .up_rdata (up_rdata_s[0]),
-    .up_rack (up_rack_s[0]));
-
-  // channel 1 (q)
-
-  axi_adrv9001_rx_channel #(
-    .Q_OR_I_N (1),
-    .COMMON_ID (CHANNEL_BASE_ADDR),
-    .CHANNEL_ID (1),
-    .DISABLE (0),
-    .DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
-    .DCFILTER_DISABLE (DCFILTER_DISABLE),
-    .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
-    .DATA_WIDTH (16))
-  i_rx_channel_1 (
-    .adc_clk (adc_clk),
-    .adc_rst (adc_rst),
-    .adc_valid_in (adc_valid_A),
-    .adc_data_in (adc_data_q_A[15:0]),
-    .adc_valid_out (),
-    .adc_data_out (adc_data_q0),
-    .adc_data_iq_in (adc_data_iq_i0_s),
-    .adc_data_iq_out (adc_data_iq_q0_s),
-    .adc_enable (adc_enable_q0),
-    .dac_valid_in (dac_data_valid_A),
-    .dac_data_in (dac_data_q_A),
-    .up_adc_pn_err (up_adc_pn_err_s[1]),
-    .up_adc_pn_oos (up_adc_pn_oos_s[1]),
-    .up_adc_or (up_adc_or_s[1]),
-    .up_rstn (up_rstn),
-    .up_clk (up_clk),
-    .up_wreq (up_wreq),
-    .up_waddr (up_waddr),
-    .up_wdata (up_wdata),
-    .up_wack (up_wack_s[1]),
-    .up_rreq (up_rreq),
-    .up_raddr (up_raddr),
-    .up_rdata (up_rdata_s[1]),
-    .up_rack (up_rack_s[1]));
-
-  // channel 2 (i)
-
-  axi_adrv9001_rx_channel #(
-    .Q_OR_I_N (0),
-    .COMMON_ID (CHANNEL_BASE_ADDR),
-    .CHANNEL_ID (2),
-    .DISABLE (MODE_R1),
-    .DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
-    .DCFILTER_DISABLE (DCFILTER_DISABLE),
-    .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
-    .DATA_WIDTH (16))
-  i_rx_channel_2 (
-    .adc_clk (adc_clk),
-    .adc_rst (adc_rst),
-    .adc_valid_in (adc_valid_B),
-    .adc_data_in (adc_data_i_B[15:0]),
-    .adc_valid_out (adc_valid_out_i1),
-    .adc_data_out (adc_data_i1),
-    .adc_data_iq_in (adc_data_iq_q1_s),
-    .adc_data_iq_out (adc_data_iq_i1_s),
-    .adc_enable (adc_enable_i1),
-    .dac_valid_in (dac_data_valid_B),
-    .dac_data_in (dac_data_i_B),
-    .up_adc_pn_err (up_adc_pn_err_s[2]),
-    .up_adc_pn_oos (up_adc_pn_oos_s[2]),
-    .up_adc_or (up_adc_or_s[2]),
-    .up_rstn (up_rstn),
-    .up_clk (up_clk),
-    .up_wreq (up_wreq),
-    .up_waddr (up_waddr),
-    .up_wdata (up_wdata),
-    .up_wack (up_wack_s[2]),
-    .up_rreq (up_rreq),
-    .up_raddr (up_raddr),
-    .up_rdata (up_rdata_s[2]),
-    .up_rack (up_rack_s[2]));
-
-  // channel 3 (q)
-
-  axi_adrv9001_rx_channel #(
-    .Q_OR_I_N (1),
-    .COMMON_ID (CHANNEL_BASE_ADDR),
-    .CHANNEL_ID (3),
-    .DISABLE (MODE_R1),
-    .DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
-    .DCFILTER_DISABLE (DCFILTER_DISABLE),
-    .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
-    .DATA_WIDTH (16))
-  i_rx_channel_3 (
-    .adc_clk (adc_clk),
-    .adc_rst (adc_rst),
-    .adc_valid_in (adc_valid_B),
-    .adc_data_in (adc_data_q_B[15:0]),
-    .adc_valid_out (),
-    .adc_data_out (adc_data_q1),
-    .adc_data_iq_in (adc_data_iq_i1_s),
-    .adc_data_iq_out (adc_data_iq_q1_s),
-    .adc_enable (adc_enable_q1),
-    .dac_valid_in (dac_data_valid_B),
-    .dac_data_in (dac_data_q_B),
-    .up_adc_pn_err (up_adc_pn_err_s[3]),
-    .up_adc_pn_oos (up_adc_pn_oos_s[3]),
-    .up_adc_or (up_adc_or_s[3]),
-    .up_rstn (up_rstn),
-    .up_clk (up_clk),
-    .up_wreq (up_wreq),
-    .up_waddr (up_waddr),
-    .up_wdata (up_wdata),
-    .up_wack (up_wack_s[3]),
-    .up_rreq (up_rreq),
-    .up_raddr (up_raddr),
-    .up_rdata (up_rdata_s[3]),
-    .up_rack (up_rack_s[3]));
-
-  // common processor control
-
-  up_adc_common #(
-    .ID (ID),
-    .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
-    .FPGA_FAMILY (FPGA_FAMILY),
-    .SPEED_GRADE (SPEED_GRADE),
-    .DEV_PACKAGE (DEV_PACKAGE),
-    .COMMON_ID (COMMON_BASE_ADDR),
-    .CONFIG(CONFIG),
-    .DRP_DISABLE(1),
-    .USERPORTS_DISABLE(1),
-    .GPIO_DISABLE(1),
-    .START_CODE_DISABLE(1))
-  i_up_adc_common (
-    .mmcm_rst (),
-    .adc_clk (adc_clk),
-    .adc_rst (adc_rst),
-    .adc_r1_mode (),
-    .adc_ddr_edgesel (),
-    .adc_pin_mode (),
-    .adc_status (1'b1),
-    .adc_sync_status (1'd0),
-    .adc_status_ovf (adc_dovf),
-    .adc_clk_ratio (adc_clk_ratio),
-    .adc_start_code (),
-    .adc_sref_sync (),
-    .adc_sync (adc_sync),
-    .adc_num_lanes (adc_num_lanes),
-    .adc_sdr_ddr_n (adc_sdr_ddr_n),
-    .adc_symb_op (adc_symb_op),
-    .adc_symb_8_16b (adc_symb_8_16b),
-    .up_pps_rcounter(32'h0),
-    .up_pps_status(1'b0),
-    .up_pps_irq_mask(),
-    .up_adc_r1_mode (up_adc_r1_mode),
-    .up_adc_ce (),
-    .up_status_pn_err (up_status_pn_err),
-    .up_status_pn_oos (up_status_pn_oos),
-    .up_status_or (up_status_or),
-    .up_drp_sel (),
-    .up_drp_wr (),
-    .up_drp_addr (),
-    .up_drp_wdata (),
-    .up_drp_rdata (32'd0),
-    .up_drp_ready (1'd0),
-    .up_drp_locked (1'd1),
-    .up_usr_chanmax_out (),
-    .up_usr_chanmax_in (8'd3),
-    .up_adc_gpio_in (32'd0),
-    .up_adc_gpio_out (),
-    .up_rstn (up_rstn),
-    .up_clk (up_clk),
-    .up_wreq (up_wreq),
-    .up_waddr (up_waddr),
-    .up_wdata (up_wdata),
-    .up_wack (up_wack_s[4]),
-    .up_rreq (up_rreq),
-    .up_raddr (up_raddr),
-    .up_rdata (up_rdata_s[4]),
-    .up_rack (up_rack_s[4]));
-
-  assign adc_single_lane = adc_num_lanes[0];
-
-end
-endgenerate
+  endgenerate
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_adrv9001/axi_adrv9001_rx_channel.v b/library/axi_adrv9001/axi_adrv9001_rx_channel.v
index 2d6285381..d238f033e 100644
--- a/library/axi_adrv9001/axi_adrv9001_rx_channel.v
+++ b/library/axi_adrv9001/axi_adrv9001_rx_channel.v
@@ -45,6 +45,7 @@ module axi_adrv9001_rx_channel #(
   parameter   IQCORRECTION_DISABLE = 0,
   parameter   DATA_WIDTH = 16
 ) (
+
   // adc interface
   input                           adc_clk,
   input                           adc_rst,
@@ -145,7 +146,9 @@ module axi_adrv9001_rx_channel #(
   assign adc_dfmt_valid_s[n] = adc_valid_in_s;
   assign adc_dfmt_data_s[((16*n)+15):(16*n)] = adc_data_in_s[((16*n)+15):(16*n)];
   end else begin
-  ad_datafmt #(.DATA_WIDTH (16)) i_ad_datafmt (
+  ad_datafmt #(
+    .DATA_WIDTH (16)
+  ) i_ad_datafmt (
     .clk (adc_clk),
     .valid (adc_valid_in_s),
     .data (adc_data_in_s[((16*n)+15):(16*n)]),
@@ -182,7 +185,9 @@ module axi_adrv9001_rx_channel #(
   assign adc_valid_out_s[n] = adc_dcfilter_valid_s[n];
   assign adc_data_out[((16*n)+15):(16*n)] = adc_dcfilter_data_s[((16*n)+15):(16*n)];
   end else begin
-  ad_iqcor #(.Q_OR_I_N (Q_OR_I_N)) i_ad_iqcor (
+  ad_iqcor #(
+    .Q_OR_I_N (Q_OR_I_N)
+  ) i_ad_iqcor (
     .clk (adc_clk),
     .valid (adc_dcfilter_valid_s[n]),
     .data_in (adc_dcfilter_data_s[((16*n)+15):(16*n)]),
@@ -211,31 +216,29 @@ module axi_adrv9001_rx_channel #(
     .POL_MASK ( (1<<7) | (1<<6) ),
     .POL_W (7),
     .DW (16)
-    ) PN7_gen (
+  ) PN7_gen (
     .clk (adc_clk),
     .reset (adc_rst),
     .clk_en (adc_valid_in_s),
     .pn_init (adc_pn_oos_s),
     .pn_data_in (adc_data_in_s),
-    .pn_data_out (pn7_data)
-  );
+    .pn_data_out (pn7_data));
 
   // PN15 x^15 + x^14 + 1
   ad_pngen  #(
     .POL_MASK ( (1<<15) | (1<<14) ),
     .POL_W (15),
     .DW (16)
-    ) PN15_gen (
+  ) PN15_gen (
     .clk (adc_clk),
     .reset (adc_rst),
     .clk_en (adc_valid_in_s),
     .pn_init (adc_pn_oos_s),
     .pn_data_in (adc_data_in_s),
-    .pn_data_out (pn15_data)
-  );
+    .pn_data_out (pn15_data));
 
   // reference nibble ramp and full ramp generator
-  // next value is always the currently received value incremented 
+  // next value is always the currently received value incremented
   always @(posedge adc_clk) begin
     if (adc_valid_in_s) begin
       full_ramp_counter <= adc_data_in_s + 16'd1;
@@ -246,7 +249,7 @@ module axi_adrv9001_rx_channel #(
                         adc_pnseq_sel == 4'd5 ? pn15_data :
                         adc_pnseq_sel == 4'd10 ? {4{full_ramp_counter[3:0]}} :
                         adc_pnseq_sel == 4'd11 ? full_ramp_counter : 'h0;
-  assign valid_seq_sel = adc_pnseq_sel == 4'd4 || adc_pnseq_sel == 4'd5 || 
+  assign valid_seq_sel = adc_pnseq_sel == 4'd4 || adc_pnseq_sel == 4'd5 ||
                          adc_pnseq_sel == 4'd10 || adc_pnseq_sel == 4'd11;
 
   ad_pnmon #(
@@ -260,8 +263,7 @@ module axi_adrv9001_rx_channel #(
     .adc_data_pn (adc_data_pn),
     .adc_pattern_has_zero (adc_pnseq_sel[3]),
     .adc_pn_oos (adc_pn_oos_s),
-    .adc_pn_err (adc_pn_err_s)
-  );
+    .adc_pn_err (adc_pn_err_s));
 
   up_adc_channel #(
     .COMMON_ID (COMMON_ID),
@@ -269,8 +271,8 @@ module axi_adrv9001_rx_channel #(
     .USERPORTS_DISABLE(1),
     .DATAFORMAT_DISABLE(DATAFORMAT_DISABLE),
     .DCFILTER_DISABLE(DCFILTER_DISABLE),
-    .IQCORRECTION_DISABLE(IQCORRECTION_DISABLE))
-  i_up_adc_channel (
+    .IQCORRECTION_DISABLE(IQCORRECTION_DISABLE)
+  ) i_up_adc_channel (
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
     .adc_enable (adc_enable),
@@ -319,7 +321,3 @@ module axi_adrv9001_rx_channel #(
   endgenerate
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
-
diff --git a/library/axi_adrv9001/axi_adrv9001_tdd.v b/library/axi_adrv9001/axi_adrv9001_tdd.v
index fc5be38fe..0e700cd93 100644
--- a/library/axi_adrv9001/axi_adrv9001_tdd.v
+++ b/library/axi_adrv9001/axi_adrv9001_tdd.v
@@ -79,7 +79,8 @@ module axi_adrv9001_tdd #(
   input                   up_rreq,
   input       [13:0]      up_raddr,
   output      [31:0]      up_rdata,
-  output                  up_rack);
+  output                  up_rack
+);
 
   generate
   if (ENABLED == 1) begin
@@ -215,8 +216,8 @@ module axi_adrv9001_tdd #(
 
   ad_tdd_control #(
     .TX_DATA_PATH_DELAY(),
-    .CONTROL_PATH_DELAY())
-  i_tdd_control(
+    .CONTROL_PATH_DELAY()
+  ) i_tdd_control(
     .clk(clk),
     .rst(rst),
     .tdd_enable(tdd_enable_s),
diff --git a/library/axi_adrv9001/axi_adrv9001_tx.v b/library/axi_adrv9001/axi_adrv9001_tx.v
index 0cc367f03..748edd721 100644
--- a/library/axi_adrv9001/axi_adrv9001_tx.v
+++ b/library/axi_adrv9001/axi_adrv9001_tx.v
@@ -55,6 +55,7 @@ module axi_adrv9001_tx #(
   parameter   DAC_DDS_CORDIC_DW = 20,
   parameter   DAC_DDS_CORDIC_PHASE_DW = 18
 ) (
+
   // dac interface
   output                  dac_rst,
   input                   dac_clk,
@@ -108,321 +109,319 @@ module axi_adrv9001_tx #(
   output  reg [ 31:0]     up_rdata,
   output  reg             up_rack
 );
-generate
-if (ENABLED == 0) begin : core_disabled
 
-  assign dac_rst = 1'b0;
-  assign dac_data_valid_A = 1'b0;
-  assign dac_data_i_A = 16'b0;
-  assign dac_data_q_A = 16'b0;
-  assign dac_data_valid_B = 1'b0;
-  assign dac_data_i_B = 16'b0;
-  assign dac_data_q_B = 16'b0;
-  assign dac_single_lane = 1'b0;
-  assign dac_sdr_ddr_n = 1'b0;
-  assign dac_symb_op = 1'b0;
-  assign dac_symb_8_16b = 1'b0;
-  assign up_dac_r1_mode = 1'b0;
-  assign dac_sync_out = 1'b0;
-  assign dac_valid = 1'b0;
-  assign dac_enable_i0 = 1'b0;
-  assign dac_enable_q0 = 1'b0;
-  assign dac_enable_i1 = 1'b0;
-  assign dac_enable_q1 = 1'b0;
+  generate
+  if (ENABLED == 0) begin : core_disabled
 
-  always @(*) begin
-    up_wack = 1'b0;
-    up_rdata = 32'b0;
-    up_rack = 1'b0;
-  end
+    assign dac_rst = 1'b0;
+    assign dac_data_valid_A = 1'b0;
+    assign dac_data_i_A = 16'b0;
+    assign dac_data_q_A = 16'b0;
+    assign dac_data_valid_B = 1'b0;
+    assign dac_data_i_B = 16'b0;
+    assign dac_data_q_B = 16'b0;
+    assign dac_single_lane = 1'b0;
+    assign dac_sdr_ddr_n = 1'b0;
+    assign dac_symb_op = 1'b0;
+    assign dac_symb_8_16b = 1'b0;
+    assign up_dac_r1_mode = 1'b0;
+    assign dac_sync_out = 1'b0;
+    assign dac_valid = 1'b0;
+    assign dac_enable_i0 = 1'b0;
+    assign dac_enable_q0 = 1'b0;
+    assign dac_enable_i1 = 1'b0;
+    assign dac_enable_q1 = 1'b0;
 
-end else begin : core_enabled
+    always @(*) begin
+      up_wack = 1'b0;
+      up_rdata = 32'b0;
+      up_rack = 1'b0;
+    end
 
-  // configuration settings
+  end else begin : core_enabled
 
-  localparam  CONFIG =  (USE_RX_CLK_FOR_TX * 1024) +
-                        (CMOS_LVDS_N * 128) +
-                        (MODE_R1 * 16) +
-                        (DDS_DISABLE * 64) +
-                        (IQCORRECTION_DISABLE * 1);
+    // configuration settings
 
-  // internal registers
+    localparam  CONFIG =  (USE_RX_CLK_FOR_TX * 1024) +
+                          (CMOS_LVDS_N * 128) +
+                          (MODE_R1 * 16) +
+                          (DDS_DISABLE * 64) +
+                          (IQCORRECTION_DISABLE * 1);
 
-  reg               dac_data_sync = 'd0;
-  reg     [15:0]    dac_rate_cnt = 'd0;
-  reg               dac_valid_int = 'd0;
+    // internal registers
 
-  // internal signals
+    reg               dac_data_sync = 'd0;
+    reg     [15:0]    dac_rate_cnt = 'd0;
+    reg               dac_valid_int = 'd0;
 
-  wire              dac_data_sync_s;
-  wire    [ 15:0]   dac_data_iq_i0_s;
-  wire    [ 15:0]   dac_data_iq_q0_s;
-  wire    [ 15:0]   dac_data_iq_i1_s;
-  wire    [ 15:0]   dac_data_iq_q1_s;
-  wire              dac_dds_format_s;
-  wire    [ 15:0]   dac_datarate_s;
-  wire      [4:0]   dac_num_lanes;
-  wire    [  4:0]   up_wack_s;
-  wire    [  4:0]   up_rack_s;
-  wire    [ 31:0]   up_rdata_s[0:4];
+    // internal signals
 
-  // master/slave
+    wire              dac_data_sync_s;
+    wire    [ 15:0]   dac_data_iq_i0_s;
+    wire    [ 15:0]   dac_data_iq_q0_s;
+    wire    [ 15:0]   dac_data_iq_i1_s;
+    wire    [ 15:0]   dac_data_iq_q1_s;
+    wire              dac_dds_format_s;
+    wire    [ 15:0]   dac_datarate_s;
+    wire      [4:0]   dac_num_lanes;
+    wire    [  4:0]   up_wack_s;
+    wire    [  4:0]   up_rack_s;
+    wire    [ 31:0]   up_rdata_s[0:4];
 
-  assign dac_data_sync_s = (EXT_SYNC == 0) ? dac_sync_out : dac_sync_in;
+    // master/slave
 
-  always @(posedge dac_clk) begin
-    dac_data_sync <= dac_data_sync_s;
-  end
+    assign dac_data_sync_s = (EXT_SYNC == 0) ? dac_sync_out : dac_sync_in;
 
-  // rate counters and data sync signals
+    always @(posedge dac_clk) begin
+      dac_data_sync <= dac_data_sync_s;
+    end
 
-  always @(posedge dac_clk) begin
-    if (dac_rst == 1'b1) begin
-      dac_rate_cnt <= 16'b0;
-    end else begin
-      if ((dac_data_sync == 1'b1) || (dac_rate_cnt == 16'd0)) begin
-        dac_rate_cnt <= dac_datarate_s;
+    // rate counters and data sync signals
+
+    always @(posedge dac_clk) begin
+      if (dac_rst == 1'b1) begin
+        dac_rate_cnt <= 16'b0;
       end else begin
-        dac_rate_cnt <= dac_rate_cnt - 1'b1;
+        if ((dac_data_sync == 1'b1) || (dac_rate_cnt == 16'd0)) begin
+          dac_rate_cnt <= dac_datarate_s;
+        end else begin
+          dac_rate_cnt <= dac_rate_cnt - 1'b1;
+        end
       end
     end
-  end
 
-  // dma interface
+    // dma interface
 
-  assign dac_data_valid_A = dac_valid_int;
-  assign dac_data_valid_B = dac_valid_int;
+    assign dac_data_valid_A = dac_valid_int;
+    assign dac_data_valid_B = dac_valid_int;
 
-  always @(posedge dac_clk) begin
-    if (dac_rst == 1'b1) begin
-      dac_valid_int <= 1'b0;
-    end else begin
-      dac_valid_int <= (dac_rate_cnt == 16'd0) ? tdd_tx_valid : 1'b0;
+    always @(posedge dac_clk) begin
+      if (dac_rst == 1'b1) begin
+        dac_valid_int <= 1'b0;
+      end else begin
+        dac_valid_int <= (dac_rate_cnt == 16'd0) ? tdd_tx_valid : 1'b0;
+      end
     end
-  end
 
-  // processor read interface
+    // processor read interface
 
-  always @(negedge up_rstn or posedge up_clk) begin
-    if (up_rstn == 0) begin
-      up_wack <= 'd0;
-      up_rack <= 'd0;
-      up_rdata <= 'd0;
-    end else begin
-      up_wack <= | up_wack_s;
-      up_rack <= | up_rack_s;
-      up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] |
-                  up_rdata_s[3] | up_rdata_s[4];
+    always @(negedge up_rstn or posedge up_clk) begin
+      if (up_rstn == 0) begin
+        up_wack <= 'd0;
+        up_rack <= 'd0;
+        up_rdata <= 'd0;
+      end else begin
+        up_wack <= | up_wack_s;
+        up_rack <= | up_rack_s;
+        up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] |
+                    up_rdata_s[3] | up_rdata_s[4];
+      end
     end
+
+    // dac channel 0
+
+    axi_adrv9001_tx_channel #(
+      .CHANNEL_ID (0),
+      .COMMON_ID (CHANNEL_BASE_ADDR),
+      .Q_OR_I_N (0),
+      .DISABLE (DISABLE),
+      .DDS_DISABLE (DDS_DISABLE),
+      .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
+      .DAC_DDS_TYPE (DAC_DDS_TYPE),
+      .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
+      .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW)
+    ) i_tx_channel_0 (
+      .dac_clk (dac_clk),
+      .dac_rst (dac_rst),
+      .dac_data_in_req (dac_valid),
+      .dac_data_in (dac_data_i0),
+      .dac_data_out_req (dac_data_valid_A),
+      .dac_data_out (dac_data_i_A[15:0]),
+      .dac_data_iq_in (dac_data_iq_q0_s),
+      .dac_data_iq_out (dac_data_iq_i0_s),
+      .dac_enable (dac_enable_i0),
+      .dac_data_sync (dac_data_sync),
+      .dac_dds_format (dac_dds_format_s),
+      .up_rstn (up_rstn),
+      .up_clk (up_clk),
+      .up_wreq (up_wreq),
+      .up_waddr (up_waddr),
+      .up_wdata (up_wdata),
+      .up_wack (up_wack_s[0]),
+      .up_rreq (up_rreq),
+      .up_raddr (up_raddr),
+      .up_rdata (up_rdata_s[0]),
+      .up_rack (up_rack_s[0]));
+
+    // dac channel 1
+
+    axi_adrv9001_tx_channel #(
+      .CHANNEL_ID (1),
+      .COMMON_ID (CHANNEL_BASE_ADDR),
+      .Q_OR_I_N (1),
+      .DISABLE (DISABLE),
+      .DDS_DISABLE (DDS_DISABLE),
+      .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
+      .DAC_DDS_TYPE (DAC_DDS_TYPE),
+      .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
+      .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW)
+    ) i_tx_channel_1 (
+      .dac_clk (dac_clk),
+      .dac_rst (dac_rst),
+      .dac_data_in_req (),
+      .dac_data_in (dac_data_q0),
+      .dac_data_out_req (dac_data_valid_A),
+      .dac_data_out (dac_data_q_A[15:0]),
+      .dac_data_iq_in (dac_data_iq_i0_s),
+      .dac_data_iq_out (dac_data_iq_q0_s),
+      .dac_enable (dac_enable_q0),
+      .dac_data_sync (dac_data_sync),
+      .dac_dds_format (dac_dds_format_s),
+      .up_rstn (up_rstn),
+      .up_clk (up_clk),
+      .up_wreq (up_wreq),
+      .up_waddr (up_waddr),
+      .up_wdata (up_wdata),
+      .up_wack (up_wack_s[1]),
+      .up_rreq (up_rreq),
+      .up_raddr (up_raddr),
+      .up_rdata (up_rdata_s[1]),
+      .up_rack (up_rack_s[1]));
+
+    // dac channel 2 - disabled in 1R1T mode
+
+    axi_adrv9001_tx_channel #(
+      .CHANNEL_ID (2),
+      .COMMON_ID (CHANNEL_BASE_ADDR),
+      .Q_OR_I_N (0),
+      .DISABLE (MODE_R1),
+      .DDS_DISABLE (DDS_DISABLE),
+      .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
+      .DAC_DDS_TYPE (DAC_DDS_TYPE),
+      .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
+      .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW)
+    ) i_tx_channel_2 (
+      .dac_clk (dac_clk),
+      .dac_rst (dac_rst),
+      .dac_data_in_req (),
+      .dac_data_in (dac_data_i1),
+      .dac_data_out_req (dac_data_valid_B),
+      .dac_data_out (dac_data_i_B[15:0]),
+      .dac_data_iq_in (dac_data_iq_q1_s),
+      .dac_data_iq_out (dac_data_iq_i1_s),
+      .dac_enable (dac_enable_i1),
+      .dac_data_sync (dac_data_sync),
+      .dac_dds_format (dac_dds_format_s),
+      .up_rstn (up_rstn),
+      .up_clk (up_clk),
+      .up_wreq (up_wreq),
+      .up_waddr (up_waddr),
+      .up_wdata (up_wdata),
+      .up_wack (up_wack_s[2]),
+      .up_rreq (up_rreq),
+      .up_raddr (up_raddr),
+      .up_rdata (up_rdata_s[2]),
+      .up_rack (up_rack_s[2]));
+
+    // dac channel 3 - disabled in 1R1T mode
+
+    axi_adrv9001_tx_channel #(
+      .CHANNEL_ID (3),
+      .COMMON_ID (CHANNEL_BASE_ADDR),
+      .Q_OR_I_N (1),
+      .DISABLE (MODE_R1),
+      .DDS_DISABLE (DDS_DISABLE),
+      .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
+      .DAC_DDS_TYPE (DAC_DDS_TYPE),
+      .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
+      .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW)
+    ) i_tx_channel_3 (
+      .dac_clk (dac_clk),
+      .dac_rst (dac_rst),
+      .dac_data_in_req (),
+      .dac_data_in (dac_data_q1),
+      .dac_data_out_req (dac_data_valid_B),
+      .dac_data_out (dac_data_q_B[15:0]),
+      .dac_data_iq_in (dac_data_iq_i1_s),
+      .dac_data_iq_out (dac_data_iq_q1_s),
+      .dac_enable (dac_enable_q1),
+      .dac_data_sync (dac_data_sync),
+      .dac_dds_format (dac_dds_format_s),
+      .up_rstn (up_rstn),
+      .up_clk (up_clk),
+      .up_wreq (up_wreq),
+      .up_waddr (up_waddr),
+      .up_wdata (up_wdata),
+      .up_wack (up_wack_s[3]),
+      .up_rreq (up_rreq),
+      .up_raddr (up_raddr),
+      .up_rdata (up_rdata_s[3]),
+      .up_rack (up_rack_s[3]));
+
+    // dac common processor interface
+
+    up_dac_common #(
+      .ID (ID),
+      .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
+      .FPGA_FAMILY (FPGA_FAMILY),
+      .SPEED_GRADE (SPEED_GRADE),
+      .DEV_PACKAGE (DEV_PACKAGE),
+      .CONFIG(CONFIG),
+      .CLK_EDGE_SEL(0),
+      .COMMON_ID(COMMON_BASE_ADDR),
+      .DRP_DISABLE(1),
+      .USERPORTS_DISABLE(1),
+      .GPIO_DISABLE(1)
+    ) i_up_dac_common (
+      .mmcm_rst (),
+      .dac_clk (dac_clk),
+      .dac_rst (dac_rst),
+      .dac_num_lanes (dac_num_lanes),
+      .dac_sdr_ddr_n (dac_sdr_ddr_n),
+      .dac_symb_op (dac_symb_op),
+      .dac_symb_8_16b (dac_symb_8_16b),
+      .dac_sync (dac_sync_out),
+      .dac_ext_sync_arm (dac_ext_sync_arm),
+      .dac_frame (),
+      .dac_clksel (),
+      .dac_par_type (),
+      .dac_par_enb (),
+      .dac_r1_mode (),
+      .up_dac_r1_mode (up_dac_r1_mode),
+      .dac_datafmt (dac_dds_format_s),
+      .dac_datarate (dac_datarate_s),
+      .dac_status (1'b1),
+      .dac_status_unf (dac_dunf),
+      .dac_clk_ratio (dac_clk_ratio),
+      .up_dac_ce (),
+      .up_pps_rcounter(32'h0),
+      .up_pps_status(1'b0),
+      .up_pps_irq_mask(),
+      .up_drp_sel (),
+      .up_drp_wr (),
+      .up_drp_addr (),
+      .up_drp_wdata (),
+      .up_drp_rdata (32'd0),
+      .up_drp_ready (1'd0),
+      .up_drp_locked (1'd1),
+      .up_usr_chanmax (),
+      .dac_usr_chanmax (8'd3),
+      .up_dac_gpio_in (32'd0),
+      .up_dac_gpio_out (),
+      .up_rstn (up_rstn),
+      .up_clk (up_clk),
+      .up_wreq (up_wreq),
+      .up_waddr (up_waddr),
+      .up_wdata (up_wdata),
+      .up_wack (up_wack_s[4]),
+      .up_rreq (up_rreq),
+      .up_raddr (up_raddr),
+      .up_rdata (up_rdata_s[4]),
+      .up_rack (up_rack_s[4]));
+
+    assign dac_single_lane = dac_num_lanes[0];
+
   end
-
-  // dac channel 0
-
-  axi_adrv9001_tx_channel #(
-    .CHANNEL_ID (0),
-    .COMMON_ID (CHANNEL_BASE_ADDR),
-    .Q_OR_I_N (0),
-    .DISABLE (DISABLE),
-    .DDS_DISABLE (DDS_DISABLE),
-    .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
-    .DAC_DDS_TYPE (DAC_DDS_TYPE),
-    .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
-    .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
-  i_tx_channel_0 (
-    .dac_clk (dac_clk),
-    .dac_rst (dac_rst),
-    .dac_data_in_req (dac_valid),
-    .dac_data_in (dac_data_i0),
-    .dac_data_out_req (dac_data_valid_A),
-    .dac_data_out (dac_data_i_A[15:0]),
-    .dac_data_iq_in (dac_data_iq_q0_s),
-    .dac_data_iq_out (dac_data_iq_i0_s),
-    .dac_enable (dac_enable_i0),
-    .dac_data_sync (dac_data_sync),
-    .dac_dds_format (dac_dds_format_s),
-    .up_rstn (up_rstn),
-    .up_clk (up_clk),
-    .up_wreq (up_wreq),
-    .up_waddr (up_waddr),
-    .up_wdata (up_wdata),
-    .up_wack (up_wack_s[0]),
-    .up_rreq (up_rreq),
-    .up_raddr (up_raddr),
-    .up_rdata (up_rdata_s[0]),
-    .up_rack (up_rack_s[0]));
-
-  // dac channel 1
-
-  axi_adrv9001_tx_channel #(
-    .CHANNEL_ID (1),
-    .COMMON_ID (CHANNEL_BASE_ADDR),
-    .Q_OR_I_N (1),
-    .DISABLE (DISABLE),
-    .DDS_DISABLE (DDS_DISABLE),
-    .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
-    .DAC_DDS_TYPE (DAC_DDS_TYPE),
-    .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
-    .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
-  i_tx_channel_1 (
-    .dac_clk (dac_clk),
-    .dac_rst (dac_rst),
-    .dac_data_in_req (),
-    .dac_data_in (dac_data_q0),
-    .dac_data_out_req (dac_data_valid_A),
-    .dac_data_out (dac_data_q_A[15:0]),
-    .dac_data_iq_in (dac_data_iq_i0_s),
-    .dac_data_iq_out (dac_data_iq_q0_s),
-    .dac_enable (dac_enable_q0),
-    .dac_data_sync (dac_data_sync),
-    .dac_dds_format (dac_dds_format_s),
-    .up_rstn (up_rstn),
-    .up_clk (up_clk),
-    .up_wreq (up_wreq),
-    .up_waddr (up_waddr),
-    .up_wdata (up_wdata),
-    .up_wack (up_wack_s[1]),
-    .up_rreq (up_rreq),
-    .up_raddr (up_raddr),
-    .up_rdata (up_rdata_s[1]),
-    .up_rack (up_rack_s[1]));
-
-  // dac channel 2 - disabled in 1R1T mode
-
-  axi_adrv9001_tx_channel #(
-    .CHANNEL_ID (2),
-    .COMMON_ID (CHANNEL_BASE_ADDR),
-    .Q_OR_I_N (0),
-    .DISABLE (MODE_R1),
-    .DDS_DISABLE (DDS_DISABLE),
-    .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
-    .DAC_DDS_TYPE (DAC_DDS_TYPE),
-    .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
-    .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
-  i_tx_channel_2 (
-    .dac_clk (dac_clk),
-    .dac_rst (dac_rst),
-    .dac_data_in_req (),
-    .dac_data_in (dac_data_i1),
-    .dac_data_out_req (dac_data_valid_B),
-    .dac_data_out (dac_data_i_B[15:0]),
-    .dac_data_iq_in (dac_data_iq_q1_s),
-    .dac_data_iq_out (dac_data_iq_i1_s),
-    .dac_enable (dac_enable_i1),
-    .dac_data_sync (dac_data_sync),
-    .dac_dds_format (dac_dds_format_s),
-    .up_rstn (up_rstn),
-    .up_clk (up_clk),
-    .up_wreq (up_wreq),
-    .up_waddr (up_waddr),
-    .up_wdata (up_wdata),
-    .up_wack (up_wack_s[2]),
-    .up_rreq (up_rreq),
-    .up_raddr (up_raddr),
-    .up_rdata (up_rdata_s[2]),
-    .up_rack (up_rack_s[2]));
-
-  // dac channel 3 - disabled in 1R1T mode
-
-  axi_adrv9001_tx_channel #(
-    .CHANNEL_ID (3),
-    .COMMON_ID (CHANNEL_BASE_ADDR),
-    .Q_OR_I_N (1),
-    .DISABLE (MODE_R1),
-    .DDS_DISABLE (DDS_DISABLE),
-    .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
-    .DAC_DDS_TYPE (DAC_DDS_TYPE),
-    .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
-    .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
-  i_tx_channel_3 (
-    .dac_clk (dac_clk),
-    .dac_rst (dac_rst),
-    .dac_data_in_req (),
-    .dac_data_in (dac_data_q1),
-    .dac_data_out_req (dac_data_valid_B),
-    .dac_data_out (dac_data_q_B[15:0]),
-    .dac_data_iq_in (dac_data_iq_i1_s),
-    .dac_data_iq_out (dac_data_iq_q1_s),
-    .dac_enable (dac_enable_q1),
-    .dac_data_sync (dac_data_sync),
-    .dac_dds_format (dac_dds_format_s),
-    .up_rstn (up_rstn),
-    .up_clk (up_clk),
-    .up_wreq (up_wreq),
-    .up_waddr (up_waddr),
-    .up_wdata (up_wdata),
-    .up_wack (up_wack_s[3]),
-    .up_rreq (up_rreq),
-    .up_raddr (up_raddr),
-    .up_rdata (up_rdata_s[3]),
-    .up_rack (up_rack_s[3]));
-
-  // dac common processor interface
-
-  up_dac_common #(
-    .ID (ID),
-    .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
-    .FPGA_FAMILY (FPGA_FAMILY),
-    .SPEED_GRADE (SPEED_GRADE),
-    .DEV_PACKAGE (DEV_PACKAGE),
-    .CONFIG(CONFIG),
-    .CLK_EDGE_SEL(0),
-    .COMMON_ID(COMMON_BASE_ADDR),
-    .DRP_DISABLE(1),
-    .USERPORTS_DISABLE(1),
-    .GPIO_DISABLE(1))
-  i_up_dac_common (
-    .mmcm_rst (),
-    .dac_clk (dac_clk),
-    .dac_rst (dac_rst),
-    .dac_num_lanes (dac_num_lanes),
-    .dac_sdr_ddr_n (dac_sdr_ddr_n),
-    .dac_symb_op (dac_symb_op),
-    .dac_symb_8_16b (dac_symb_8_16b),
-    .dac_sync (dac_sync_out),
-    .dac_ext_sync_arm (dac_ext_sync_arm),
-    .dac_frame (),
-    .dac_clksel (),
-    .dac_par_type (),
-    .dac_par_enb (),
-    .dac_r1_mode (),
-    .up_dac_r1_mode (up_dac_r1_mode),
-    .dac_datafmt (dac_dds_format_s),
-    .dac_datarate (dac_datarate_s),
-    .dac_status (1'b1),
-    .dac_status_unf (dac_dunf),
-    .dac_clk_ratio (dac_clk_ratio),
-    .up_dac_ce (),
-    .up_pps_rcounter(32'h0),
-    .up_pps_status(1'b0),
-    .up_pps_irq_mask(),
-    .up_drp_sel (),
-    .up_drp_wr (),
-    .up_drp_addr (),
-    .up_drp_wdata (),
-    .up_drp_rdata (32'd0),
-    .up_drp_ready (1'd0),
-    .up_drp_locked (1'd1),
-    .up_usr_chanmax (),
-    .dac_usr_chanmax (8'd3),
-    .up_dac_gpio_in (32'd0),
-    .up_dac_gpio_out (),
-    .up_rstn (up_rstn),
-    .up_clk (up_clk),
-    .up_wreq (up_wreq),
-    .up_waddr (up_waddr),
-    .up_wdata (up_wdata),
-    .up_wack (up_wack_s[4]),
-    .up_rreq (up_rreq),
-    .up_raddr (up_raddr),
-    .up_rdata (up_rdata_s[4]),
-    .up_rack (up_rack_s[4]));
-
-  assign dac_single_lane = dac_num_lanes[0];
-
-end
-endgenerate
+  endgenerate
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_adrv9001/axi_adrv9001_tx_channel.v b/library/axi_adrv9001/axi_adrv9001_tx_channel.v
index 141b16a3f..c5d838ace 100644
--- a/library/axi_adrv9001/axi_adrv9001_tx_channel.v
+++ b/library/axi_adrv9001/axi_adrv9001_tx_channel.v
@@ -46,6 +46,7 @@ module axi_adrv9001_tx_channel #(
   parameter   DAC_DDS_CORDIC_DW = 20,
   parameter   DAC_DDS_CORDIC_PHASE_DW = 18
 ) (
+
   // dac interface
   input                   dac_clk,
   input                   dac_rst,
@@ -105,7 +106,9 @@ module axi_adrv9001_tx_channel #(
   assign dac_data_in_req = dac_data_out_req;
 
   end else begin
-  ad_iqcor #(.Q_OR_I_N (Q_OR_I_N)) i_ad_iqcor_0 (
+  ad_iqcor #(
+    .Q_OR_I_N (Q_OR_I_N)
+  ) i_ad_iqcor_0 (
     .clk (dac_clk),
     .valid (dac_data_out_req),
     .data_in (dac_data_iq_out[15:0]),
@@ -128,26 +131,24 @@ module axi_adrv9001_tx_channel #(
     .POL_MASK ((1<<7) | (1<<6)),
     .POL_W (7),
     .DW (16)
-    ) PN7_gen (
+  ) PN7_gen (
     .clk (dac_clk),
     .reset (dac_rst),
     .clk_en (dac_data_in_req),
     .pn_init (1'b0),
-    .pn_data_out (pn7_data)
-  );
+    .pn_data_out (pn7_data));
 
   // PN15 x^15 + x^14 + 1
   ad_pngen  #(
     .POL_MASK ((1<<15) | (1<<14)),
     .POL_W (15),
     .DW (16)
-    ) PN15_gen (
+  ) PN15_gen (
     .clk (dac_clk),
     .reset (dac_rst),
     .clk_en (dac_data_in_req),
     .pn_init (1'b0),
-    .pn_data_out (pn15_data)
-  );
+    .pn_data_out (pn15_data));
 
   // full ramp generator
   always @(posedge dac_clk) begin
@@ -183,8 +184,8 @@ module axi_adrv9001_tx_channel #(
     .DDS_TYPE (DAC_DDS_TYPE),
     .CORDIC_DW (DAC_DDS_CORDIC_DW),
     .CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
-    .CLK_RATIO (1))
-  i_dds (
+    .CLK_RATIO (1)
+  ) i_dds (
     .clk (dac_clk),
     .dac_dds_format (dac_dds_format),
     .dac_data_sync (dac_data_sync),
@@ -204,8 +205,8 @@ module axi_adrv9001_tx_channel #(
     .CHANNEL_ID (CHANNEL_ID),
     .DDS_DISABLE(DDS_DISABLE),
     .USERPORTS_DISABLE(1),
-    .IQCORRECTION_DISABLE(IQCORRECTION_DISABLE))
-    i_up_dac_channel (
+    .IQCORRECTION_DISABLE(IQCORRECTION_DISABLE)
+  ) i_up_dac_channel (
     .dac_clk (dac_clk),
     .dac_rst (dac_rst),
     .dac_dds_scale_1 (dac_dds_scale_1_s),
diff --git a/library/axi_adrv9001/intel/adrv9001_rx.v b/library/axi_adrv9001/intel/adrv9001_rx.v
index 3491d8ea6..f744865f0 100644
--- a/library/axi_adrv9001/intel/adrv9001_rx.v
+++ b/library/axi_adrv9001/intel/adrv9001_rx.v
@@ -44,6 +44,7 @@ module adrv9001_rx #(
   parameter USE_BUFG = 0,
   parameter IO_DELAY_GROUP = "dev_if_delay_group"
 ) (
+
   // device interface
   input                   rx_dclk_in_n_NC,
   input                   rx_dclk_in_p_dclk_in,
diff --git a/library/axi_clkgen/axi_clkgen.v b/library/axi_clkgen/axi_clkgen.v
index 97d7c623c..f407e98d5 100644
--- a/library/axi_clkgen/axi_clkgen.v
+++ b/library/axi_clkgen/axi_clkgen.v
@@ -52,7 +52,8 @@ module axi_clkgen #(
   parameter real    CLK0_DIV = 6.000,
   parameter real    CLK0_PHASE = 0.000,
   parameter integer CLK1_DIV = 6,
-  parameter real    CLK1_PHASE = 0.000) (
+  parameter real    CLK1_PHASE = 0.000
+) (
 
   // clocks
 
@@ -83,8 +84,8 @@ module axi_clkgen #(
   output      [ 1:0]      s_axi_rresp,
   input                   s_axi_rready,
   input       [ 2:0]      s_axi_awprot,
-  input       [ 2:0]      s_axi_arprot);
-
+  input       [ 2:0]      s_axi_arprot
+);
 
   // reset and clocks
 
@@ -199,8 +200,8 @@ module axi_clkgen #(
     .MMCM_CLK0_DIV (CLK0_DIV),
     .MMCM_CLK0_PHASE (CLK0_PHASE),
     .MMCM_CLK1_DIV (CLK1_DIV),
-    .MMCM_CLK1_PHASE (CLK1_PHASE))
-  i_mmcm_drp (
+    .MMCM_CLK1_PHASE (CLK1_PHASE)
+  ) i_mmcm_drp (
     .clk (clk),
     .clk2 (clk2),
     .clk_sel(clk_sel_s),
@@ -219,6 +220,3 @@ module axi_clkgen #(
     .up_drp_locked (up_drp_locked_s));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_clock_monitor/axi_clock_monitor.v b/library/axi_clock_monitor/axi_clock_monitor.v
index a1d7a521c..94e7bff67 100755
--- a/library/axi_clock_monitor/axi_clock_monitor.v
+++ b/library/axi_clock_monitor/axi_clock_monitor.v
@@ -38,7 +38,8 @@
 module axi_clock_monitor #(
 
   parameter   ID = 0,
-  parameter   NUM_OF_CLOCKS = 1) (
+  parameter   NUM_OF_CLOCKS = 1
+) (
 
   // clocks
 
@@ -83,7 +84,8 @@ module axi_clock_monitor #(
   output          s_axi_rvalid,
   output  [31:0]  s_axi_rdata,
   output  [ 1:0]  s_axi_rresp,
-  input           s_axi_rready);
+  input           s_axi_rready
+);
 
   // local parameters
 
@@ -226,8 +228,7 @@ module axi_clock_monitor #(
         .up_clk(up_clk),
         .up_d_count(clk_mon_count[n]),
         .d_rst(1'b0),
-        .d_clk(clock[n])
-      );
+        .d_clk(clock[n]));
     end
     for (n = NUM_OF_CLOCKS; n < 16; n = n + 1) begin: clk_mon_z
       assign clk_mon_count[n] = 21'd0;
@@ -266,6 +267,3 @@ module axi_clock_monitor #(
     .up_rack (up_rack_o_s));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_dac_interpolate/axi_dac_interpolate.v b/library/axi_dac_interpolate/axi_dac_interpolate.v
index f72226c6b..92d8f807e 100644
--- a/library/axi_dac_interpolate/axi_dac_interpolate.v
+++ b/library/axi_dac_interpolate/axi_dac_interpolate.v
@@ -37,8 +37,8 @@
 
 module axi_dac_interpolate #(
 
-  parameter CORRECTION_DISABLE = 1) (
-
+  parameter CORRECTION_DISABLE = 1
+) (
   input                 dac_clk,
   input                 dac_rst,
 
@@ -87,8 +87,8 @@ module axi_dac_interpolate #(
   output                s_axi_rvalid,
   output      [31:0]    s_axi_rdata,
   output      [ 1:0]    s_axi_rresp,
-  input                 s_axi_rready);
-
+  input                 s_axi_rready
+);
 
   reg    [ 1:0]    trigger_i_m1;
   reg    [ 1:0]    trigger_i_m2;
@@ -187,23 +187,23 @@ module axi_dac_interpolate #(
 
   // sync
   always @(posedge dac_clk) begin
-   trigger_i_m1 <= trigger_i;
-   trigger_i_m2 <= trigger_i_m1;
-   trigger_i_m3 <= trigger_i_m2;
+    trigger_i_m1 <= trigger_i;
+    trigger_i_m2 <= trigger_i_m1;
+    trigger_i_m3 <= trigger_i_m2;
 
-   trigger_adc_m1 <= trigger_adc;
-   trigger_adc_m2 <= trigger_adc_m1;
+    trigger_adc_m1 <= trigger_adc;
+    trigger_adc_m2 <= trigger_adc_m1;
 
-   trigger_la_m1 <= trigger_la;
-   trigger_la_m2 <= trigger_la_m1;
+    trigger_la_m1 <= trigger_la;
+    trigger_la_m2 <= trigger_la_m1;
   end
 
   always @(posedge dac_clk) begin
-   any_edge_trigger <= (trigger_i_m3 ^ trigger_i_m2) & any_edge;
-   rise_edge_trigger <= (~trigger_i_m3 & trigger_i_m2) & rise_edge;
-   fall_edge_trigger <= (trigger_i_m3 & ~trigger_i_m2) & fall_edge;
-   high_level_trigger <= trigger_i_m3 & high_level;
-   low_level_trigger <= ~trigger_i_m3 & low_level;
+    any_edge_trigger <= (trigger_i_m3 ^ trigger_i_m2) & any_edge;
+    rise_edge_trigger <= (~trigger_i_m3 & trigger_i_m2) & rise_edge;
+    fall_edge_trigger <= (trigger_i_m3 & ~trigger_i_m2) & fall_edge;
+    high_level_trigger <= trigger_i_m3 & high_level;
+    low_level_trigger <= ~trigger_i_m3 & low_level;
   end
 
   assign hold_last_sample = lsample_hold_config[0];
@@ -212,8 +212,8 @@ module axi_dac_interpolate #(
   assign underflow = underflow_a | underflow_b;
 
   axi_dac_interpolate_filter #(
-    .CORRECTION_DISABLE(CORRECTION_DISABLE))
-    i_filter_a (
+    .CORRECTION_DISABLE (CORRECTION_DISABLE)
+  ) i_filter_a (
     .dac_clk (dac_clk),
     .dac_rst (dac_rst),
 
@@ -238,12 +238,11 @@ module axi_dac_interpolate #(
     .dma_valid (dma_valid_a),
     .dma_valid_adjacent (dma_valid_b),
     .dac_correction_enable(dac_correction_enable_a),
-    .dac_correction_coefficient(dac_correction_coefficient_a)
-  );
+    .dac_correction_coefficient(dac_correction_coefficient_a));
 
   axi_dac_interpolate_filter #(
-    .CORRECTION_DISABLE(CORRECTION_DISABLE))
-    i_filter_b (
+    .CORRECTION_DISABLE(CORRECTION_DISABLE)
+  ) i_filter_b (
     .dac_clk (dac_clk),
     .dac_rst (dac_rst),
 
@@ -268,8 +267,7 @@ module axi_dac_interpolate #(
     .dma_valid (dma_valid_b),
     .dma_valid_adjacent (dma_valid_a),
     .dac_correction_enable(dac_correction_enable_b),
-    .dac_correction_coefficient(dac_correction_coefficient_b)
-  );
+    .dac_correction_coefficient(dac_correction_coefficient_b));
 
   axi_dac_interpolate_reg axi_dac_interpolate_reg_inst (
 
@@ -332,6 +330,3 @@ module axi_dac_interpolate #(
     .up_rack (up_rack));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_dac_interpolate/axi_dac_interpolate_filter.v b/library/axi_dac_interpolate/axi_dac_interpolate_filter.v
index 4a8e6ab40..01914878d 100644
--- a/library/axi_dac_interpolate/axi_dac_interpolate_filter.v
+++ b/library/axi_dac_interpolate/axi_dac_interpolate_filter.v
@@ -35,11 +35,10 @@
 
 `timescale 1ns/100ps
 
-
 module axi_dac_interpolate_filter #(
 
-  parameter CORRECTION_DISABLE = 1) (
-
+  parameter CORRECTION_DISABLE = 1
+) (
   input                 dac_clk,
   input                 dac_rst,
 
@@ -96,10 +95,11 @@ module axi_dac_interpolate_filter #(
   wire              dma_valid_ch_sync;
   wire              dma_valid_ch;
 
-  ad_iqcor #(.Q_OR_I_N (0),
+  ad_iqcor #(
+    .Q_OR_I_N (0),
     .DISABLE(CORRECTION_DISABLE),
-    .SCALE_ONLY(1))
-  i_ad_iqcor (
+    .SCALE_ONLY(1)
+  ) i_ad_iqcor (
     .clk (dac_clk),
     .valid (dac_valid),
     .data_in (dac_data),
diff --git a/library/axi_dac_interpolate/axi_dac_interpolate_reg.v b/library/axi_dac_interpolate/axi_dac_interpolate_reg.v
index b5a8d00ff..015fd3f1b 100644
--- a/library/axi_dac_interpolate/axi_dac_interpolate_reg.v
+++ b/library/axi_dac_interpolate/axi_dac_interpolate_reg.v
@@ -62,7 +62,8 @@ module axi_dac_interpolate_reg(
   input               up_rreq,
   input       [ 4:0]  up_raddr,
   output reg  [31:0]  up_rdata,
-  output reg          up_rack);
+  output reg          up_rack
+);
 
   // internal registers
 
@@ -167,7 +168,9 @@ module axi_dac_interpolate_reg(
     end
   end
 
-   up_xfer_cntrl #(.DATA_WIDTH(128)) i_xfer_cntrl (
+  up_xfer_cntrl #(
+    .DATA_WIDTH(128)
+  ) i_xfer_cntrl (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_data_cntrl ({ up_config[1],               // 1
@@ -198,7 +201,3 @@ module axi_dac_interpolate_reg(
                       dac_filter_mask_a}));         // 3
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
-
diff --git a/library/axi_dac_interpolate/cic_interp.v b/library/axi_dac_interpolate/cic_interp.v
index 5b0d3e493..2328ed766 100644
--- a/library/axi_dac_interpolate/cic_interp.v
+++ b/library/axi_dac_interpolate/cic_interp.v
@@ -37,26 +37,16 @@
 
 `timescale 1 ns / 1 ns
 
-module cic_interp
-               (
-                clk,
-                clk_enable,
-                reset,
-                filter_in,
-                rate,
-                load_rate,
-                filter_out,
-                ce_out
-                );
-
-  input   clk;
-  input   clk_enable;
-  input   reset;
-  input   signed [30:0] filter_in; //sfix31_En30
-  input   [15:0] rate; //ufix16
-  input   load_rate;
-  output  signed [109:0] filter_out; //sfix110_En30
-  output  ce_out;
+module cic_interp (
+  input  clk,
+  input  clk_enable,
+  input  reset,
+  input  signed [30:0] filter_in, //sfix31_En30
+  input  [15:0] rate, //ufix16
+  input  load_rate,
+  output signed [109:0] filter_out, //sfix110_En30
+  output ce_out
+);
 
 ////////////////////////////////////////////////////////////////
 //Module Architecture: cic_interp
@@ -611,4 +601,4 @@ module cic_interp
   // Assignment Statements
   assign ce_out = phase_0;
   assign filter_out = output_register;
-endmodule  // cic_interp
+endmodule
diff --git a/library/axi_dac_interpolate/fir_interp.v b/library/axi_dac_interpolate/fir_interp.v
index 4d6fd69ba..8b2b43adf 100644
--- a/library/axi_dac_interpolate/fir_interp.v
+++ b/library/axi_dac_interpolate/fir_interp.v
@@ -40,22 +40,14 @@
 
 `timescale 1 ns / 1 ns
 
-module fir_interp
-               (
-                clk,
-                clk_enable,
-                reset,
-                filter_in,
-                filter_out,
-                ce_out
-                );
-
-  input   clk;
-  input   clk_enable;
-  input   reset;
-  input   signed [15:0] filter_in; //sfix16_En15
-  output  signed [35:0] filter_out; //sfix36_En30
-  output  ce_out;
+module fir_interp (
+  input  clk,
+  input  clk_enable,
+  input  reset,
+  input  signed [15:0] filter_in, //sfix16_En15
+  output signed [35:0] filter_out, //sfix36_En30
+  output ce_out
+);
 
 ////////////////////////////////////////////////////////////////
 //Module Architecture: fir_interp
@@ -214,7 +206,6 @@ module fir_interp
       end
     end // Delay_Pipeline_process
 
-
   assign product_mux = (cur_count == 2'b00) ? coeffphase1_12 :
                       coeffphase2_12;
   assign product = delay_pipeline[11] * product_mux;
@@ -387,4 +378,4 @@ module fir_interp
   // Assignment Statements
   assign ce_out = phase_1;
   assign filter_out = output_register;
-endmodule  // fir_interp
+endmodule
diff --git a/library/axi_dmac/address_generator.v b/library/axi_dmac/address_generator.v
index 6404fe921..8d22e4f00 100644
--- a/library/axi_dmac/address_generator.v
+++ b/library/axi_dmac/address_generator.v
@@ -43,8 +43,8 @@ module address_generator #(
   parameter BEATS_PER_BURST_WIDTH = 4,
   parameter BYTES_PER_BEAT_WIDTH = $clog2(DMA_DATA_WIDTH/8),
   parameter LENGTH_WIDTH = 8,
-  parameter CACHE_COHERENT = 0)(
-
+  parameter CACHE_COHERENT = 0
+) (
   input                        clk,
   input                        resetn,
 
@@ -74,114 +74,114 @@ module address_generator #(
   output     [ 3:0]               cache
 );
 
-localparam MAX_BEATS_PER_BURST = {1'b1,{BEATS_PER_BURST_WIDTH{1'b0}}};
-localparam MAX_LENGTH = {BEATS_PER_BURST_WIDTH{1'b1}};
+  localparam MAX_BEATS_PER_BURST = {1'b1,{BEATS_PER_BURST_WIDTH{1'b0}}};
+  localparam MAX_LENGTH = {BEATS_PER_BURST_WIDTH{1'b1}};
 
 `include "inc_id.vh"
 
-assign burst = 2'b01;
-assign prot = 3'b000;
-// If CACHE_COHERENT is set, signal downstream that this transaction must be
-// looked up in cache. Otherwise default to "normal non-cachable bufferable".
-assign cache = CACHE_COHERENT ? 4'b1110 : 4'b0011;
-assign size = DMA_DATA_WIDTH == 1024 ? 3'b111 :
-              DMA_DATA_WIDTH ==  512 ? 3'b110 :
-              DMA_DATA_WIDTH ==  256 ? 3'b101 :
-              DMA_DATA_WIDTH ==  128 ? 3'b100 :
-              DMA_DATA_WIDTH ==   64 ? 3'b011 :
-              DMA_DATA_WIDTH ==   32 ? 3'b010 :
-              DMA_DATA_WIDTH ==   16 ? 3'b001 : 3'b000;
+  assign burst = 2'b01;
+  assign prot = 3'b000;
+  // If CACHE_COHERENT is set, signal downstream that this transaction must be
+  // looked up in cache. Otherwise default to "normal non-cachable bufferable".
+  assign cache = CACHE_COHERENT ? 4'b1110 : 4'b0011;
+  assign size = DMA_DATA_WIDTH == 1024 ? 3'b111 :
+                DMA_DATA_WIDTH ==  512 ? 3'b110 :
+                DMA_DATA_WIDTH ==  256 ? 3'b101 :
+                DMA_DATA_WIDTH ==  128 ? 3'b100 :
+                DMA_DATA_WIDTH ==   64 ? 3'b011 :
+                DMA_DATA_WIDTH ==   32 ? 3'b010 :
+                DMA_DATA_WIDTH ==   16 ? 3'b001 : 3'b000;
 
-reg [LENGTH_WIDTH-1:0] length = 'h0;
-reg [DMA_ADDR_WIDTH-BYTES_PER_BEAT_WIDTH-1:0] address = 'h00;
-reg [BEATS_PER_BURST_WIDTH-1:0] last_burst_len = 'h00;
-assign addr = {address, {BYTES_PER_BEAT_WIDTH{1'b0}}};
-assign len = length;
+  reg [LENGTH_WIDTH-1:0] length = 'h0;
+  reg [DMA_ADDR_WIDTH-BYTES_PER_BEAT_WIDTH-1:0] address = 'h00;
+  reg [BEATS_PER_BURST_WIDTH-1:0] last_burst_len = 'h00;
+  assign addr = {address, {BYTES_PER_BEAT_WIDTH{1'b0}}};
+  assign len = length;
 
-reg addr_valid_d1;
-reg last = 1'b0;
+  reg addr_valid_d1;
+  reg last = 1'b0;
 
-// If we already asserted addr_valid we have to wait until it is accepted before
-// we can disable the address generator.
-always @(posedge clk) begin
-  if (resetn == 1'b0) begin
-    enabled <= 1'b0;
-  end else if (enable == 1'b1) begin
-    enabled <= 1'b1;
-  end else if (addr_valid == 1'b0) begin
-    enabled <= 1'b0;
-  end
-end
-
-always @(posedge clk) begin
-  if (bl_valid == 1'b1 && bl_ready == 1'b1) begin
-    last_burst_len <= measured_last_burst_length;
-  end
-end
-
-always @(posedge clk) begin
-  if (addr_valid == 1'b0) begin
-    last <= eot;
-    if (eot == 1'b1) begin
-      length <= last_burst_len;
-    end else begin
-      length <= MAX_LENGTH;
+  // If we already asserted addr_valid we have to wait until it is accepted before
+  // we can disable the address generator.
+  always @(posedge clk) begin
+    if (resetn == 1'b0) begin
+      enabled <= 1'b0;
+    end else if (enable == 1'b1) begin
+      enabled <= 1'b1;
+    end else if (addr_valid == 1'b0) begin
+      enabled <= 1'b0;
     end
   end
-end
 
-always @(posedge clk) begin
-  if (req_ready == 1'b1) begin
-    address <= req_address;
-  end else if (addr_valid == 1'b1 && addr_ready == 1'b1) begin
-    address <= address + MAX_BEATS_PER_BURST;
+  always @(posedge clk) begin
+    if (bl_valid == 1'b1 && bl_ready == 1'b1) begin
+      last_burst_len <= measured_last_burst_length;
+    end
   end
-end
 
-always @(posedge clk) begin
-  if (resetn == 1'b0) begin
-    bl_ready <= 1'b1;
-  end else begin
-    if (bl_ready == 1'b1) begin
-      bl_ready <= ~bl_valid;
-    end else if (addr_valid == 1'b0 && eot == 1'b1) begin
-      // assert bl_ready only when the addr_valid asserts in the next cycle
-      if (id != request_id && enable == 1'b1) begin
-        bl_ready <= 1'b1;
+  always @(posedge clk) begin
+    if (addr_valid == 1'b0) begin
+      last <= eot;
+      if (eot == 1'b1) begin
+        length <= last_burst_len;
+      end else begin
+        length <= MAX_LENGTH;
       end
     end
   end
-end
 
-always @(posedge clk) begin
-  if (resetn == 1'b0) begin
-    req_ready <= 1'b1;
-    addr_valid <= 1'b0;
-  end else begin
+  always @(posedge clk) begin
     if (req_ready == 1'b1) begin
-      req_ready <= ~req_valid;
+      address <= req_address;
     end else if (addr_valid == 1'b1 && addr_ready == 1'b1) begin
-      addr_valid <= 1'b0;
-      req_ready <= last;
-    end else if (id != request_id && enable == 1'b1) begin
-      // if eot wait until the last_burst_len gets synced over
-      if (eot == 1'b0 || (eot == 1'b1 && bl_ready == 1'b0)) begin
-        addr_valid <= 1'b1;
+      address <= address + MAX_BEATS_PER_BURST;
+    end
+  end
+
+  always @(posedge clk) begin
+    if (resetn == 1'b0) begin
+      bl_ready <= 1'b1;
+    end else begin
+      if (bl_ready == 1'b1) begin
+        bl_ready <= ~bl_valid;
+      end else if (addr_valid == 1'b0 && eot == 1'b1) begin
+        // assert bl_ready only when the addr_valid asserts in the next cycle
+        if (id != request_id && enable == 1'b1) begin
+          bl_ready <= 1'b1;
+        end
       end
     end
   end
-end
 
-always @(posedge clk) begin
-  addr_valid_d1 <= addr_valid;
-end
-
-always @(posedge clk) begin
-  if (resetn == 1'b0) begin
-    id <= 'h0;
-  end else if (addr_valid == 1'b1 && addr_valid_d1 == 1'b0) begin
-    id <= inc_id(id);
+  always @(posedge clk) begin
+    if (resetn == 1'b0) begin
+      req_ready <= 1'b1;
+      addr_valid <= 1'b0;
+    end else begin
+      if (req_ready == 1'b1) begin
+        req_ready <= ~req_valid;
+      end else if (addr_valid == 1'b1 && addr_ready == 1'b1) begin
+        addr_valid <= 1'b0;
+        req_ready <= last;
+      end else if (id != request_id && enable == 1'b1) begin
+        // if eot wait until the last_burst_len gets synced over
+        if (eot == 1'b0 || (eot == 1'b1 && bl_ready == 1'b0)) begin
+          addr_valid <= 1'b1;
+        end
+      end
+    end
+  end
+
+  always @(posedge clk) begin
+    addr_valid_d1 <= addr_valid;
+  end
+
+  always @(posedge clk) begin
+    if (resetn == 1'b0) begin
+      id <= 'h0;
+    end else if (addr_valid == 1'b1 && addr_valid_d1 == 1'b0) begin
+      id <= inc_id(id);
+    end
   end
-end
 
 endmodule
diff --git a/library/axi_dmac/axi_dmac.v b/library/axi_dmac/axi_dmac.v
index 4a93001d9..e27d1dabf 100644
--- a/library/axi_dmac/axi_dmac.v
+++ b/library/axi_dmac/axi_dmac.v
@@ -65,6 +65,7 @@ module axi_dmac #(
   parameter ALLOW_ASYM_MEM = 0,
   parameter CACHE_COHERENT_DEST = 0
 ) (
+
   // Slave AXI interface
   input s_axi_aclk,
   input s_axi_aresetn,
@@ -186,8 +187,6 @@ module axi_dmac #(
   output [AXI_ID_WIDTH_SRC-1:0]            m_src_axi_wid,
   input  [AXI_ID_WIDTH_SRC-1:0]            m_src_axi_bid,
 
-
-
   // Slave streaming AXI interface
   input                                    s_axis_aclk,
   output                                   s_axis_ready,
@@ -234,399 +233,396 @@ module axi_dmac #(
   output  [7:0] dest_diag_level_bursts
 );
 
+  localparam DMA_TYPE_AXI_MM = 0;
+  localparam DMA_TYPE_AXI_STREAM = 1;
+  localparam DMA_TYPE_FIFO = 2;
 
-localparam DMA_TYPE_AXI_MM = 0;
-localparam DMA_TYPE_AXI_STREAM = 1;
-localparam DMA_TYPE_FIFO = 2;
+  localparam HAS_DEST_ADDR = DMA_TYPE_DEST == DMA_TYPE_AXI_MM;
+  localparam HAS_SRC_ADDR = DMA_TYPE_SRC == DMA_TYPE_AXI_MM;
 
-localparam HAS_DEST_ADDR = DMA_TYPE_DEST == DMA_TYPE_AXI_MM;
-localparam HAS_SRC_ADDR = DMA_TYPE_SRC == DMA_TYPE_AXI_MM;
+  // Argh... "[Synth 8-2722] system function call clog2 is not allowed here"
+  localparam BYTES_PER_BEAT_WIDTH_DEST = DMA_DATA_WIDTH_DEST > 1024 ? 8 :
+    DMA_DATA_WIDTH_DEST > 512 ? 7 :
+    DMA_DATA_WIDTH_DEST > 256 ? 6 :
+    DMA_DATA_WIDTH_DEST > 128 ? 5 :
+    DMA_DATA_WIDTH_DEST > 64 ? 4 :
+    DMA_DATA_WIDTH_DEST > 32 ? 3 :
+    DMA_DATA_WIDTH_DEST > 16 ? 2 :
+    DMA_DATA_WIDTH_DEST > 8 ? 1 : 0;
+  localparam BYTES_PER_BEAT_WIDTH_SRC = DMA_DATA_WIDTH_SRC > 1024 ? 8 :
+    DMA_DATA_WIDTH_SRC > 512 ? 7 :
+    DMA_DATA_WIDTH_SRC > 256 ? 6 :
+    DMA_DATA_WIDTH_SRC > 128 ? 5 :
+    DMA_DATA_WIDTH_SRC > 64 ? 4 :
+    DMA_DATA_WIDTH_SRC > 32 ? 3 :
+    DMA_DATA_WIDTH_SRC > 16 ? 2 :
+    DMA_DATA_WIDTH_SRC > 8 ? 1 : 0;
+  localparam ID_WIDTH = (FIFO_SIZE) > 64 ? 8 :
+    (FIFO_SIZE) > 32 ? 7 :
+    (FIFO_SIZE) > 16 ? 6 :
+    (FIFO_SIZE) > 8 ? 5 :
+    (FIFO_SIZE) > 4 ? 4 :
+    (FIFO_SIZE) > 2 ? 3 :
+    (FIFO_SIZE) > 1 ? 2 : 1;
+  localparam DBG_ID_PADDING = ID_WIDTH > 8 ? 0 : 8 - ID_WIDTH;
 
-// Argh... "[Synth 8-2722] system function call clog2 is not allowed here"
-localparam BYTES_PER_BEAT_WIDTH_DEST = DMA_DATA_WIDTH_DEST > 1024 ? 8 :
-  DMA_DATA_WIDTH_DEST > 512 ? 7 :
-  DMA_DATA_WIDTH_DEST > 256 ? 6 :
-  DMA_DATA_WIDTH_DEST > 128 ? 5 :
-  DMA_DATA_WIDTH_DEST > 64 ? 4 :
-  DMA_DATA_WIDTH_DEST > 32 ? 3 :
-  DMA_DATA_WIDTH_DEST > 16 ? 2 :
-  DMA_DATA_WIDTH_DEST > 8 ? 1 : 0;
-localparam BYTES_PER_BEAT_WIDTH_SRC = DMA_DATA_WIDTH_SRC > 1024 ? 8 :
-  DMA_DATA_WIDTH_SRC > 512 ? 7 :
-  DMA_DATA_WIDTH_SRC > 256 ? 6 :
-  DMA_DATA_WIDTH_SRC > 128 ? 5 :
-  DMA_DATA_WIDTH_SRC > 64 ? 4 :
-  DMA_DATA_WIDTH_SRC > 32 ? 3 :
-  DMA_DATA_WIDTH_SRC > 16 ? 2 :
-  DMA_DATA_WIDTH_SRC > 8 ? 1 : 0;
-localparam ID_WIDTH = (FIFO_SIZE) > 64 ? 8 :
-  (FIFO_SIZE) > 32 ? 7 :
-  (FIFO_SIZE) > 16 ? 6 :
-  (FIFO_SIZE) > 8 ? 5 :
-  (FIFO_SIZE) > 4 ? 4 :
-  (FIFO_SIZE) > 2 ? 3 :
-  (FIFO_SIZE) > 1 ? 2 : 1;
-localparam DBG_ID_PADDING = ID_WIDTH > 8 ? 0 : 8 - ID_WIDTH;
+  /* AXI3 supports a maximum of 16 beats per burst. AXI4 supports a maximum of
+     256 beats per burst. If either bus is AXI3 set the maximum number of beats
+     per burst to 16. For non AXI interfaces the maximum beats per burst is in
+     theory unlimted. Set it to 1024 to provide a reasonable upper threshold */
+  localparam BEATS_PER_BURST_LIMIT_DEST =
+    (DMA_TYPE_DEST == DMA_TYPE_AXI_MM) ?
+      (DMA_AXI_PROTOCOL_DEST == 1 ? 16 : 256) :
+      1024;
+  localparam BYTES_PER_BURST_LIMIT_DEST =
+      BEATS_PER_BURST_LIMIT_DEST * DMA_DATA_WIDTH_DEST / 8;
+  localparam BEATS_PER_BURST_LIMIT_SRC =
+    (DMA_TYPE_SRC == DMA_TYPE_AXI_MM) ?
+      (DMA_AXI_PROTOCOL_SRC == 1 ? 16 : 256) :
+      1024;
+  localparam BYTES_PER_BURST_LIMIT_SRC =
+      BEATS_PER_BURST_LIMIT_SRC * DMA_DATA_WIDTH_SRC / 8;
 
-/* AXI3 supports a maximum of 16 beats per burst. AXI4 supports a maximum of
-   256 beats per burst. If either bus is AXI3 set the maximum number of beats
-   per burst to 16. For non AXI interfaces the maximum beats per burst is in
-   theory unlimted. Set it to 1024 to provide a reasonable upper threshold */
-localparam BEATS_PER_BURST_LIMIT_DEST =
-  (DMA_TYPE_DEST == DMA_TYPE_AXI_MM) ?
-    (DMA_AXI_PROTOCOL_DEST == 1 ? 16 : 256) :
-    1024;
-localparam BYTES_PER_BURST_LIMIT_DEST =
-    BEATS_PER_BURST_LIMIT_DEST * DMA_DATA_WIDTH_DEST / 8;
-localparam BEATS_PER_BURST_LIMIT_SRC =
-  (DMA_TYPE_SRC == DMA_TYPE_AXI_MM) ?
-    (DMA_AXI_PROTOCOL_SRC == 1 ? 16 : 256) :
-    1024;
-localparam BYTES_PER_BURST_LIMIT_SRC =
-    BEATS_PER_BURST_LIMIT_SRC * DMA_DATA_WIDTH_SRC / 8;
+  /* The smaller bus limits the maximum bytes per burst. */
+  localparam BYTES_PER_BURST_LIMIT =
+    (BYTES_PER_BURST_LIMIT_DEST < BYTES_PER_BURST_LIMIT_SRC) ?
+    BYTES_PER_BURST_LIMIT_DEST : BYTES_PER_BURST_LIMIT_SRC;
 
-/* The smaller bus limits the maximum bytes per burst. */
-localparam BYTES_PER_BURST_LIMIT =
-  (BYTES_PER_BURST_LIMIT_DEST < BYTES_PER_BURST_LIMIT_SRC) ?
-  BYTES_PER_BURST_LIMIT_DEST : BYTES_PER_BURST_LIMIT_SRC;
+  /* Make sure the requested MAX_BYTES_PER_BURST does not exceed what the
+     interfaces can support. Limit the value if necessary. */
+  localparam REAL_MAX_BYTES_PER_BURST =
+    BYTES_PER_BURST_LIMIT < MAX_BYTES_PER_BURST ?
+      BYTES_PER_BURST_LIMIT : MAX_BYTES_PER_BURST;
 
-/* Make sure the requested MAX_BYTES_PER_BURST does not exceed what the
-   interfaces can support. Limit the value if necessary. */
-localparam REAL_MAX_BYTES_PER_BURST =
-  BYTES_PER_BURST_LIMIT < MAX_BYTES_PER_BURST ?
-    BYTES_PER_BURST_LIMIT : MAX_BYTES_PER_BURST;
+  /* MM has no alignment requirements */
+  localparam DMA_LENGTH_ALIGN_SRC =
+    DMA_TYPE_SRC == DMA_TYPE_AXI_MM ? 0 : BYTES_PER_BEAT_WIDTH_SRC;
+  localparam DMA_LENGTH_ALIGN_DEST =
+    DMA_TYPE_DEST == DMA_TYPE_AXI_MM ? 0 : BYTES_PER_BEAT_WIDTH_DEST;
 
-/* MM has no alignment requirements */
-localparam DMA_LENGTH_ALIGN_SRC =
-  DMA_TYPE_SRC == DMA_TYPE_AXI_MM ? 0 : BYTES_PER_BEAT_WIDTH_SRC;
-localparam DMA_LENGTH_ALIGN_DEST =
-  DMA_TYPE_DEST == DMA_TYPE_AXI_MM ? 0 : BYTES_PER_BEAT_WIDTH_DEST;
+  /* Choose the larger of the two */
+   localparam DMA_LENGTH_ALIGN =
+     DMA_LENGTH_ALIGN_SRC < DMA_LENGTH_ALIGN_DEST ?
+       DMA_LENGTH_ALIGN_DEST : DMA_LENGTH_ALIGN_SRC;
 
-/* Choose the larger of the two */
- localparam DMA_LENGTH_ALIGN =
-   DMA_LENGTH_ALIGN_SRC < DMA_LENGTH_ALIGN_DEST ?
-     DMA_LENGTH_ALIGN_DEST : DMA_LENGTH_ALIGN_SRC;
+  localparam BYTES_PER_BURST_WIDTH =
+    REAL_MAX_BYTES_PER_BURST > 2048 ? 12 :
+    REAL_MAX_BYTES_PER_BURST > 1024 ? 11 :
+    REAL_MAX_BYTES_PER_BURST > 512 ? 10 :
+    REAL_MAX_BYTES_PER_BURST > 256 ? 9 :
+    REAL_MAX_BYTES_PER_BURST > 128 ? 8 :
+    REAL_MAX_BYTES_PER_BURST > 64 ? 7 :
+    REAL_MAX_BYTES_PER_BURST > 32 ? 6 :
+    REAL_MAX_BYTES_PER_BURST > 16 ? 5 :
+    REAL_MAX_BYTES_PER_BURST > 8 ? 4 :
+    REAL_MAX_BYTES_PER_BURST > 4 ? 3 :
+    REAL_MAX_BYTES_PER_BURST > 2 ? 2 : 1;
 
-localparam BYTES_PER_BURST_WIDTH =
-  REAL_MAX_BYTES_PER_BURST > 2048 ? 12 :
-  REAL_MAX_BYTES_PER_BURST > 1024 ? 11 :
-  REAL_MAX_BYTES_PER_BURST > 512 ? 10 :
-  REAL_MAX_BYTES_PER_BURST > 256 ? 9 :
-  REAL_MAX_BYTES_PER_BURST > 128 ? 8 :
-  REAL_MAX_BYTES_PER_BURST > 64 ? 7 :
-  REAL_MAX_BYTES_PER_BURST > 32 ? 6 :
-  REAL_MAX_BYTES_PER_BURST > 16 ? 5 :
-  REAL_MAX_BYTES_PER_BURST > 8 ? 4 :
-  REAL_MAX_BYTES_PER_BURST > 4 ? 3 :
-  REAL_MAX_BYTES_PER_BURST > 2 ? 2 : 1;
+  // ID signals from the DMAC, just for debugging
+  wire [ID_WIDTH-1:0] dest_request_id;
+  wire [ID_WIDTH-1:0] dest_data_id;
+  wire [ID_WIDTH-1:0] dest_address_id;
+  wire [ID_WIDTH-1:0] dest_response_id;
+  wire [ID_WIDTH-1:0] src_request_id;
+  wire [ID_WIDTH-1:0] src_data_id;
+  wire [ID_WIDTH-1:0] src_address_id;
+  wire [ID_WIDTH-1:0] src_response_id;
+  wire [11:0] dbg_status;
+  wire [31:0] dbg_ids0;
+  wire [31:0] dbg_ids1;
 
-// ID signals from the DMAC, just for debugging
-wire [ID_WIDTH-1:0] dest_request_id;
-wire [ID_WIDTH-1:0] dest_data_id;
-wire [ID_WIDTH-1:0] dest_address_id;
-wire [ID_WIDTH-1:0] dest_response_id;
-wire [ID_WIDTH-1:0] src_request_id;
-wire [ID_WIDTH-1:0] src_data_id;
-wire [ID_WIDTH-1:0] src_address_id;
-wire [ID_WIDTH-1:0] src_response_id;
-wire [11:0] dbg_status;
-wire [31:0] dbg_ids0;
-wire [31:0] dbg_ids1;
+  assign m_dest_axi_araddr = 'd0;
+  assign m_dest_axi_arlen = 'd0;
+  assign m_dest_axi_arsize = 'd0;
+  assign m_dest_axi_arburst = 'd0;
+  assign m_dest_axi_arcache = 'd0;
+  assign m_dest_axi_arprot = 'd0;
+  assign m_dest_axi_awid = 'h0;
+  assign m_dest_axi_awlock = 'h0;
+  assign m_dest_axi_wid = 'h0;
+  assign m_dest_axi_arid = 'h0;
+  assign m_dest_axi_arlock = 'h0;
+  assign m_src_axi_awaddr = 'd0;
+  assign m_src_axi_awlen = 'd0;
+  assign m_src_axi_awsize = 'd0;
+  assign m_src_axi_awburst = 'd0;
+  assign m_src_axi_awcache = 'd0;
+  assign m_src_axi_awprot = 'd0;
+  assign m_src_axi_wdata = 'd0;
+  assign m_src_axi_wstrb = 'd0;
+  assign m_src_axi_wlast = 'd0;
+  assign m_src_axi_awid = 'h0;
+  assign m_src_axi_awlock = 'h0;
+  assign m_src_axi_wid = 'h0;
+  assign m_src_axi_arid = 'h0;
+  assign m_src_axi_arlock = 'h0;
 
-assign m_dest_axi_araddr = 'd0;
-assign m_dest_axi_arlen = 'd0;
-assign m_dest_axi_arsize = 'd0;
-assign m_dest_axi_arburst = 'd0;
-assign m_dest_axi_arcache = 'd0;
-assign m_dest_axi_arprot = 'd0;
-assign m_dest_axi_awid = 'h0;
-assign m_dest_axi_awlock = 'h0;
-assign m_dest_axi_wid = 'h0;
-assign m_dest_axi_arid = 'h0;
-assign m_dest_axi_arlock = 'h0;
-assign m_src_axi_awaddr = 'd0;
-assign m_src_axi_awlen = 'd0;
-assign m_src_axi_awsize = 'd0;
-assign m_src_axi_awburst = 'd0;
-assign m_src_axi_awcache = 'd0;
-assign m_src_axi_awprot = 'd0;
-assign m_src_axi_wdata = 'd0;
-assign m_src_axi_wstrb = 'd0;
-assign m_src_axi_wlast = 'd0;
-assign m_src_axi_awid = 'h0;
-assign m_src_axi_awlock = 'h0;
-assign m_src_axi_wid = 'h0;
-assign m_src_axi_arid = 'h0;
-assign m_src_axi_arlock = 'h0;
+  wire up_req_eot;
+  wire [BYTES_PER_BURST_WIDTH-1:0] up_req_measured_burst_length;
+  wire up_response_partial;
+  wire up_response_valid;
+  wire up_response_ready;
 
-wire up_req_eot;
-wire [BYTES_PER_BURST_WIDTH-1:0] up_req_measured_burst_length;
-wire up_response_partial;
-wire up_response_valid;
-wire up_response_ready;
+  wire ctrl_enable;
+  wire ctrl_pause;
 
-wire ctrl_enable;
-wire ctrl_pause;
+  wire up_dma_req_valid;
+  wire up_dma_req_ready;
+  wire [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] up_dma_req_dest_address;
+  wire [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] up_dma_req_src_address;
+  wire [DMA_LENGTH_WIDTH-1:0] up_dma_req_x_length;
+  wire [DMA_LENGTH_WIDTH-1:0] up_dma_req_y_length;
+  wire [DMA_LENGTH_WIDTH-1:0] up_dma_req_dest_stride;
+  wire [DMA_LENGTH_WIDTH-1:0] up_dma_req_src_stride;
+  wire up_dma_req_sync_transfer_start;
+  wire up_dma_req_last;
 
-wire up_dma_req_valid;
-wire up_dma_req_ready;
-wire [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] up_dma_req_dest_address;
-wire [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] up_dma_req_src_address;
-wire [DMA_LENGTH_WIDTH-1:0] up_dma_req_x_length;
-wire [DMA_LENGTH_WIDTH-1:0] up_dma_req_y_length;
-wire [DMA_LENGTH_WIDTH-1:0] up_dma_req_dest_stride;
-wire [DMA_LENGTH_WIDTH-1:0] up_dma_req_src_stride;
-wire up_dma_req_sync_transfer_start;
-wire up_dma_req_last;
+  assign dbg_ids0 = {
+    {DBG_ID_PADDING{1'b0}}, dest_response_id,
+    {DBG_ID_PADDING{1'b0}}, dest_data_id,
+    {DBG_ID_PADDING{1'b0}}, dest_address_id,
+    {DBG_ID_PADDING{1'b0}}, dest_request_id
+  };
 
-assign dbg_ids0 = {
-  {DBG_ID_PADDING{1'b0}}, dest_response_id,
-  {DBG_ID_PADDING{1'b0}}, dest_data_id,
-  {DBG_ID_PADDING{1'b0}}, dest_address_id,
-  {DBG_ID_PADDING{1'b0}}, dest_request_id
-};
+  assign dbg_ids1 = {
+    {DBG_ID_PADDING{1'b0}}, src_response_id,
+    {DBG_ID_PADDING{1'b0}}, src_data_id,
+    {DBG_ID_PADDING{1'b0}}, src_address_id,
+    {DBG_ID_PADDING{1'b0}}, src_request_id
+  };
 
-assign dbg_ids1 = {
-  {DBG_ID_PADDING{1'b0}}, src_response_id,
-  {DBG_ID_PADDING{1'b0}}, src_data_id,
-  {DBG_ID_PADDING{1'b0}}, src_address_id,
-  {DBG_ID_PADDING{1'b0}}, src_request_id
-};
+  axi_dmac_regmap #(
+    .ID(ID),
+    .DISABLE_DEBUG_REGISTERS(DISABLE_DEBUG_REGISTERS),
+    .BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT_WIDTH_DEST),
+    .BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC),
+    .BYTES_PER_BURST_WIDTH(BYTES_PER_BURST_WIDTH),
+    .DMA_TYPE_DEST(DMA_TYPE_DEST),
+    .DMA_TYPE_SRC(DMA_TYPE_SRC),
+    .DMA_AXI_ADDR_WIDTH(DMA_AXI_ADDR_WIDTH),
+    .DMA_LENGTH_WIDTH(DMA_LENGTH_WIDTH),
+    .DMA_LENGTH_ALIGN(DMA_LENGTH_ALIGN),
+    .DMA_CYCLIC(CYCLIC),
+    .HAS_DEST_ADDR(HAS_DEST_ADDR),
+    .HAS_SRC_ADDR(HAS_SRC_ADDR),
+    .DMA_2D_TRANSFER(DMA_2D_TRANSFER),
+    .SYNC_TRANSFER_START(SYNC_TRANSFER_START),
+    .CACHE_COHERENT_DEST(CACHE_COHERENT_DEST)
+  ) i_regmap (
+    .s_axi_aclk(s_axi_aclk),
+    .s_axi_aresetn(s_axi_aresetn),
 
-axi_dmac_regmap #(
-  .ID(ID),
-  .DISABLE_DEBUG_REGISTERS(DISABLE_DEBUG_REGISTERS),
-  .BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT_WIDTH_DEST),
-  .BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC),
-  .BYTES_PER_BURST_WIDTH(BYTES_PER_BURST_WIDTH),
-  .DMA_TYPE_DEST(DMA_TYPE_DEST),
-  .DMA_TYPE_SRC(DMA_TYPE_SRC),
-  .DMA_AXI_ADDR_WIDTH(DMA_AXI_ADDR_WIDTH),
-  .DMA_LENGTH_WIDTH(DMA_LENGTH_WIDTH),
-  .DMA_LENGTH_ALIGN(DMA_LENGTH_ALIGN),
-  .DMA_CYCLIC(CYCLIC),
-  .HAS_DEST_ADDR(HAS_DEST_ADDR),
-  .HAS_SRC_ADDR(HAS_SRC_ADDR),
-  .DMA_2D_TRANSFER(DMA_2D_TRANSFER),
-  .SYNC_TRANSFER_START(SYNC_TRANSFER_START),
-  .CACHE_COHERENT_DEST(CACHE_COHERENT_DEST)
-) i_regmap (
-  .s_axi_aclk(s_axi_aclk),
-  .s_axi_aresetn(s_axi_aresetn),
+    .s_axi_awvalid(s_axi_awvalid),
+    .s_axi_awaddr(s_axi_awaddr),
+    .s_axi_awready(s_axi_awready),
+    .s_axi_awprot(s_axi_awprot),
+    .s_axi_wvalid(s_axi_wvalid),
+    .s_axi_wdata(s_axi_wdata),
+    .s_axi_wstrb(s_axi_wstrb),
+    .s_axi_wready(s_axi_wready),
+    .s_axi_bvalid(s_axi_bvalid),
+    .s_axi_bresp(s_axi_bresp),
+    .s_axi_bready(s_axi_bready),
+    .s_axi_arvalid(s_axi_arvalid),
+    .s_axi_araddr(s_axi_araddr),
+    .s_axi_arready(s_axi_arready),
+    .s_axi_arprot(s_axi_arprot),
+    .s_axi_rvalid(s_axi_rvalid),
+    .s_axi_rready(s_axi_rready),
+    .s_axi_rresp(s_axi_rresp),
+    .s_axi_rdata(s_axi_rdata),
 
-  .s_axi_awvalid(s_axi_awvalid),
-  .s_axi_awaddr(s_axi_awaddr),
-  .s_axi_awready(s_axi_awready),
-  .s_axi_awprot(s_axi_awprot),
-  .s_axi_wvalid(s_axi_wvalid),
-  .s_axi_wdata(s_axi_wdata),
-  .s_axi_wstrb(s_axi_wstrb),
-  .s_axi_wready(s_axi_wready),
-  .s_axi_bvalid(s_axi_bvalid),
-  .s_axi_bresp(s_axi_bresp),
-  .s_axi_bready(s_axi_bready),
-  .s_axi_arvalid(s_axi_arvalid),
-  .s_axi_araddr(s_axi_araddr),
-  .s_axi_arready(s_axi_arready),
-  .s_axi_arprot(s_axi_arprot),
-  .s_axi_rvalid(s_axi_rvalid),
-  .s_axi_rready(s_axi_rready),
-  .s_axi_rresp(s_axi_rresp),
-  .s_axi_rdata(s_axi_rdata),
+    // Interrupt
+    .irq(irq),
 
-  // Interrupt
-  .irq(irq),
+     // Control interface
+    .ctrl_enable(ctrl_enable),
+    .ctrl_pause(ctrl_pause),
 
-   // Control interface
-  .ctrl_enable(ctrl_enable),
-  .ctrl_pause(ctrl_pause),
+     // Request interface
+    .request_valid(up_dma_req_valid),
+    .request_ready(up_dma_req_ready),
+    .request_dest_address(up_dma_req_dest_address),
+    .request_src_address(up_dma_req_src_address),
+    .request_x_length(up_dma_req_x_length),
+    .request_y_length(up_dma_req_y_length),
+    .request_dest_stride(up_dma_req_dest_stride),
+    .request_src_stride(up_dma_req_src_stride),
+    .request_sync_transfer_start(up_dma_req_sync_transfer_start),
+    .request_last(up_dma_req_last),
 
-   // Request interface
-  .request_valid(up_dma_req_valid),
-  .request_ready(up_dma_req_ready),
-  .request_dest_address(up_dma_req_dest_address),
-  .request_src_address(up_dma_req_src_address),
-  .request_x_length(up_dma_req_x_length),
-  .request_y_length(up_dma_req_y_length),
-  .request_dest_stride(up_dma_req_dest_stride),
-  .request_src_stride(up_dma_req_src_stride),
-  .request_sync_transfer_start(up_dma_req_sync_transfer_start),
-  .request_last(up_dma_req_last),
+    // DMA response interface
+    .response_eot(up_req_eot),
+    .response_measured_burst_length(up_req_measured_burst_length),
+    .response_partial(up_response_partial),
+    .response_valid(up_response_valid),
+    .response_ready(up_response_ready),
 
-  // DMA response interface
-  .response_eot(up_req_eot),
-  .response_measured_burst_length(up_req_measured_burst_length),
-  .response_partial(up_response_partial),
-  .response_valid(up_response_valid),
-  .response_ready(up_response_ready),
+    // Debug interface
+    .dbg_dest_addr(m_dest_axi_awaddr),
+    .dbg_src_addr(m_src_axi_araddr),
+    .dbg_status(dbg_status),
+    .dbg_ids0(dbg_ids0),
+    .dbg_ids1(dbg_ids1));
 
-  // Debug interface
-  .dbg_dest_addr(m_dest_axi_awaddr),
-  .dbg_src_addr(m_src_axi_araddr),
-  .dbg_status(dbg_status),
-  .dbg_ids0(dbg_ids0),
-  .dbg_ids1(dbg_ids1)
-);
+  axi_dmac_transfer #(
+    .DMA_DATA_WIDTH_SRC(DMA_DATA_WIDTH_SRC),
+    .DMA_DATA_WIDTH_DEST(DMA_DATA_WIDTH_DEST),
+    .DMA_LENGTH_WIDTH(DMA_LENGTH_WIDTH),
+    .DMA_LENGTH_ALIGN(DMA_LENGTH_ALIGN),
+    .BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT_WIDTH_DEST),
+    .BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC),
+    .BYTES_PER_BURST_WIDTH(BYTES_PER_BURST_WIDTH),
+    .DMA_TYPE_DEST(DMA_TYPE_DEST),
+    .DMA_TYPE_SRC(DMA_TYPE_SRC),
+    .DMA_AXI_ADDR_WIDTH(DMA_AXI_ADDR_WIDTH),
+    .DMA_2D_TRANSFER(DMA_2D_TRANSFER),
+    .ASYNC_CLK_REQ_SRC(ASYNC_CLK_REQ_SRC),
+    .ASYNC_CLK_SRC_DEST(ASYNC_CLK_SRC_DEST),
+    .ASYNC_CLK_DEST_REQ(ASYNC_CLK_DEST_REQ),
+    .AXI_SLICE_DEST(AXI_SLICE_DEST),
+    .AXI_SLICE_SRC(AXI_SLICE_SRC),
+    .MAX_BYTES_PER_BURST(REAL_MAX_BYTES_PER_BURST),
+    .FIFO_SIZE(FIFO_SIZE),
+    .ID_WIDTH(ID_WIDTH),
+    .AXI_LENGTH_WIDTH_SRC(8-(4*DMA_AXI_PROTOCOL_SRC)),
+    .AXI_LENGTH_WIDTH_DEST(8-(4*DMA_AXI_PROTOCOL_DEST)),
+    .ENABLE_DIAGNOSTICS_IF(ENABLE_DIAGNOSTICS_IF),
+    .ALLOW_ASYM_MEM(ALLOW_ASYM_MEM),
+    .CACHE_COHERENT_DEST(CACHE_COHERENT_DEST)
+  ) i_transfer (
+    .ctrl_clk(s_axi_aclk),
+    .ctrl_resetn(s_axi_aresetn),
 
-axi_dmac_transfer #(
-  .DMA_DATA_WIDTH_SRC(DMA_DATA_WIDTH_SRC),
-  .DMA_DATA_WIDTH_DEST(DMA_DATA_WIDTH_DEST),
-  .DMA_LENGTH_WIDTH(DMA_LENGTH_WIDTH),
-  .DMA_LENGTH_ALIGN(DMA_LENGTH_ALIGN),
-  .BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT_WIDTH_DEST),
-  .BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC),
-  .BYTES_PER_BURST_WIDTH(BYTES_PER_BURST_WIDTH),
-  .DMA_TYPE_DEST(DMA_TYPE_DEST),
-  .DMA_TYPE_SRC(DMA_TYPE_SRC),
-  .DMA_AXI_ADDR_WIDTH(DMA_AXI_ADDR_WIDTH),
-  .DMA_2D_TRANSFER(DMA_2D_TRANSFER),
-  .ASYNC_CLK_REQ_SRC(ASYNC_CLK_REQ_SRC),
-  .ASYNC_CLK_SRC_DEST(ASYNC_CLK_SRC_DEST),
-  .ASYNC_CLK_DEST_REQ(ASYNC_CLK_DEST_REQ),
-  .AXI_SLICE_DEST(AXI_SLICE_DEST),
-  .AXI_SLICE_SRC(AXI_SLICE_SRC),
-  .MAX_BYTES_PER_BURST(REAL_MAX_BYTES_PER_BURST),
-  .FIFO_SIZE(FIFO_SIZE),
-  .ID_WIDTH(ID_WIDTH),
-  .AXI_LENGTH_WIDTH_SRC(8-(4*DMA_AXI_PROTOCOL_SRC)),
-  .AXI_LENGTH_WIDTH_DEST(8-(4*DMA_AXI_PROTOCOL_DEST)),
-  .ENABLE_DIAGNOSTICS_IF(ENABLE_DIAGNOSTICS_IF),
-  .ALLOW_ASYM_MEM(ALLOW_ASYM_MEM),
-  .CACHE_COHERENT_DEST(CACHE_COHERENT_DEST)
-) i_transfer (
-  .ctrl_clk(s_axi_aclk),
-  .ctrl_resetn(s_axi_aresetn),
+    .ctrl_enable(ctrl_enable),
+    .ctrl_pause(ctrl_pause),
 
-  .ctrl_enable(ctrl_enable),
-  .ctrl_pause(ctrl_pause),
+    .req_valid(up_dma_req_valid),
+    .req_ready(up_dma_req_ready),
+    .req_dest_address(up_dma_req_dest_address),
+    .req_src_address(up_dma_req_src_address),
+    .req_x_length(up_dma_req_x_length),
+    .req_y_length(up_dma_req_y_length),
+    .req_dest_stride(up_dma_req_dest_stride),
+    .req_src_stride(up_dma_req_src_stride),
+    .req_sync_transfer_start(up_dma_req_sync_transfer_start),
+    .req_last(up_dma_req_last),
 
-  .req_valid(up_dma_req_valid),
-  .req_ready(up_dma_req_ready),
-  .req_dest_address(up_dma_req_dest_address),
-  .req_src_address(up_dma_req_src_address),
-  .req_x_length(up_dma_req_x_length),
-  .req_y_length(up_dma_req_y_length),
-  .req_dest_stride(up_dma_req_dest_stride),
-  .req_src_stride(up_dma_req_src_stride),
-  .req_sync_transfer_start(up_dma_req_sync_transfer_start),
-  .req_last(up_dma_req_last),
+    .req_eot(up_req_eot),
+    .req_measured_burst_length(up_req_measured_burst_length),
+    .req_response_partial(up_response_partial),
+    .req_response_valid(up_response_valid),
+    .req_response_ready(up_response_ready),
 
-  .req_eot(up_req_eot),
-  .req_measured_burst_length(up_req_measured_burst_length),
-  .req_response_partial(up_response_partial),
-  .req_response_valid(up_response_valid),
-  .req_response_ready(up_response_ready),
+    .m_dest_axi_aclk(m_dest_axi_aclk),
+    .m_dest_axi_aresetn(m_dest_axi_aresetn),
+    .m_src_axi_aclk(m_src_axi_aclk),
+    .m_src_axi_aresetn(m_src_axi_aresetn),
 
-  .m_dest_axi_aclk(m_dest_axi_aclk),
-  .m_dest_axi_aresetn(m_dest_axi_aresetn),
-  .m_src_axi_aclk(m_src_axi_aclk),
-  .m_src_axi_aresetn(m_src_axi_aresetn),
+    .m_axi_awaddr(m_dest_axi_awaddr),
+    .m_axi_awlen(m_dest_axi_awlen),
+    .m_axi_awsize(m_dest_axi_awsize),
+    .m_axi_awburst(m_dest_axi_awburst),
+    .m_axi_awprot(m_dest_axi_awprot),
+    .m_axi_awcache(m_dest_axi_awcache),
+    .m_axi_awvalid(m_dest_axi_awvalid),
+    .m_axi_awready(m_dest_axi_awready),
 
-  .m_axi_awaddr(m_dest_axi_awaddr),
-  .m_axi_awlen(m_dest_axi_awlen),
-  .m_axi_awsize(m_dest_axi_awsize),
-  .m_axi_awburst(m_dest_axi_awburst),
-  .m_axi_awprot(m_dest_axi_awprot),
-  .m_axi_awcache(m_dest_axi_awcache),
-  .m_axi_awvalid(m_dest_axi_awvalid),
-  .m_axi_awready(m_dest_axi_awready),
+    .m_axi_wdata(m_dest_axi_wdata),
+    .m_axi_wstrb(m_dest_axi_wstrb),
+    .m_axi_wready(m_dest_axi_wready),
+    .m_axi_wvalid(m_dest_axi_wvalid),
+    .m_axi_wlast(m_dest_axi_wlast),
 
-  .m_axi_wdata(m_dest_axi_wdata),
-  .m_axi_wstrb(m_dest_axi_wstrb),
-  .m_axi_wready(m_dest_axi_wready),
-  .m_axi_wvalid(m_dest_axi_wvalid),
-  .m_axi_wlast(m_dest_axi_wlast),
+    .m_axi_bvalid(m_dest_axi_bvalid),
+    .m_axi_bresp(m_dest_axi_bresp),
+    .m_axi_bready(m_dest_axi_bready),
 
-  .m_axi_bvalid(m_dest_axi_bvalid),
-  .m_axi_bresp(m_dest_axi_bresp),
-  .m_axi_bready(m_dest_axi_bready),
+    .m_axi_arready(m_src_axi_arready),
+    .m_axi_arvalid(m_src_axi_arvalid),
+    .m_axi_araddr(m_src_axi_araddr),
+    .m_axi_arlen(m_src_axi_arlen),
+    .m_axi_arsize(m_src_axi_arsize),
+    .m_axi_arburst(m_src_axi_arburst),
+    .m_axi_arprot(m_src_axi_arprot),
+    .m_axi_arcache(m_src_axi_arcache),
 
-  .m_axi_arready(m_src_axi_arready),
-  .m_axi_arvalid(m_src_axi_arvalid),
-  .m_axi_araddr(m_src_axi_araddr),
-  .m_axi_arlen(m_src_axi_arlen),
-  .m_axi_arsize(m_src_axi_arsize),
-  .m_axi_arburst(m_src_axi_arburst),
-  .m_axi_arprot(m_src_axi_arprot),
-  .m_axi_arcache(m_src_axi_arcache),
+    .m_axi_rdata(m_src_axi_rdata),
+    .m_axi_rready(m_src_axi_rready),
+    .m_axi_rvalid(m_src_axi_rvalid),
+    .m_axi_rlast(m_src_axi_rlast),
+    .m_axi_rresp(m_src_axi_rresp),
 
-  .m_axi_rdata(m_src_axi_rdata),
-  .m_axi_rready(m_src_axi_rready),
-  .m_axi_rvalid(m_src_axi_rvalid),
-  .m_axi_rlast(m_src_axi_rlast),
-  .m_axi_rresp(m_src_axi_rresp),
+    .s_axis_aclk(s_axis_aclk),
+    .s_axis_ready(s_axis_ready),
+    .s_axis_valid(s_axis_valid),
+    .s_axis_data(s_axis_data),
+    .s_axis_user(s_axis_user),
+    .s_axis_last(s_axis_last),
+    .s_axis_xfer_req(s_axis_xfer_req),
 
-  .s_axis_aclk(s_axis_aclk),
-  .s_axis_ready(s_axis_ready),
-  .s_axis_valid(s_axis_valid),
-  .s_axis_data(s_axis_data),
-  .s_axis_user(s_axis_user),
-  .s_axis_last(s_axis_last),
-  .s_axis_xfer_req(s_axis_xfer_req),
+    .m_axis_aclk(m_axis_aclk),
+    .m_axis_ready(m_axis_ready),
+    .m_axis_valid(m_axis_valid),
+    .m_axis_data(m_axis_data),
+    .m_axis_last(m_axis_last),
+    .m_axis_xfer_req(m_axis_xfer_req),
 
-  .m_axis_aclk(m_axis_aclk),
-  .m_axis_ready(m_axis_ready),
-  .m_axis_valid(m_axis_valid),
-  .m_axis_data(m_axis_data),
-  .m_axis_last(m_axis_last),
-  .m_axis_xfer_req(m_axis_xfer_req),
+    .fifo_wr_clk(fifo_wr_clk),
+    .fifo_wr_en(fifo_wr_en),
+    .fifo_wr_din(fifo_wr_din),
+    .fifo_wr_overflow(fifo_wr_overflow),
+    .fifo_wr_sync(fifo_wr_sync),
+    .fifo_wr_xfer_req(fifo_wr_xfer_req),
 
-  .fifo_wr_clk(fifo_wr_clk),
-  .fifo_wr_en(fifo_wr_en),
-  .fifo_wr_din(fifo_wr_din),
-  .fifo_wr_overflow(fifo_wr_overflow),
-  .fifo_wr_sync(fifo_wr_sync),
-  .fifo_wr_xfer_req(fifo_wr_xfer_req),
+    .fifo_rd_clk(fifo_rd_clk),
+    .fifo_rd_en(fifo_rd_en),
+    .fifo_rd_valid(fifo_rd_valid),
+    .fifo_rd_dout(fifo_rd_dout),
+    .fifo_rd_underflow(fifo_rd_underflow),
+    .fifo_rd_xfer_req(fifo_rd_xfer_req),
 
-  .fifo_rd_clk(fifo_rd_clk),
-  .fifo_rd_en(fifo_rd_en),
-  .fifo_rd_valid(fifo_rd_valid),
-  .fifo_rd_dout(fifo_rd_dout),
-  .fifo_rd_underflow(fifo_rd_underflow),
-  .fifo_rd_xfer_req(fifo_rd_xfer_req),
+    // DBG
+    .dbg_dest_request_id(dest_request_id),
+    .dbg_dest_address_id(dest_address_id),
+    .dbg_dest_data_id(dest_data_id),
+    .dbg_dest_response_id(dest_response_id),
+    .dbg_src_request_id(src_request_id),
+    .dbg_src_address_id(src_address_id),
+    .dbg_src_data_id(src_data_id),
+    .dbg_src_response_id(src_response_id),
+    .dbg_status(dbg_status),
 
-  // DBG
-  .dbg_dest_request_id(dest_request_id),
-  .dbg_dest_address_id(dest_address_id),
-  .dbg_dest_data_id(dest_data_id),
-  .dbg_dest_response_id(dest_response_id),
-  .dbg_src_request_id(src_request_id),
-  .dbg_src_address_id(src_address_id),
-  .dbg_src_data_id(src_data_id),
-  .dbg_src_response_id(src_response_id),
-  .dbg_status(dbg_status),
+    .dest_diag_level_bursts(dest_diag_level_bursts));
 
-  .dest_diag_level_bursts(dest_diag_level_bursts)
-);
+  assign m_dest_axi_arvalid = 1'b0;
+  assign m_dest_axi_rready = 1'b0;
+  assign m_dest_axi_araddr = 'h0;
+  assign m_dest_axi_arlen = 'h0;
+  assign m_dest_axi_arsize = 'h0;
+  assign m_dest_axi_arburst = 'h0;
+  assign m_dest_axi_arcache = 'h0;
+  assign m_dest_axi_arprot = 'h0;
 
-assign m_dest_axi_arvalid = 1'b0;
-assign m_dest_axi_rready = 1'b0;
-assign m_dest_axi_araddr = 'h0;
-assign m_dest_axi_arlen = 'h0;
-assign m_dest_axi_arsize = 'h0;
-assign m_dest_axi_arburst = 'h0;
-assign m_dest_axi_arcache = 'h0;
-assign m_dest_axi_arprot = 'h0;
+  assign m_src_axi_awvalid = 1'b0;
+  assign m_src_axi_wvalid = 1'b0;
+  assign m_src_axi_bready = 1'b0;
+  assign m_src_axi_awvalid = 'h0;
+  assign m_src_axi_awaddr = 'h0;
+  assign m_src_axi_awlen = 'h0;
+  assign m_src_axi_awsize = 'h0;
+  assign m_src_axi_awburst = 'h0;
+  assign m_src_axi_awcache = 'h0;
+  assign m_src_axi_awprot = 'h0;
+  assign m_src_axi_wvalid = 'h0;
+  assign m_src_axi_wdata = 'h0;
+  assign m_src_axi_wstrb = 'h0;
+  assign m_src_axi_wlast = 'h0;
 
-assign m_src_axi_awvalid = 1'b0;
-assign m_src_axi_wvalid = 1'b0;
-assign m_src_axi_bready = 1'b0;
-assign m_src_axi_awvalid = 'h0;
-assign m_src_axi_awaddr = 'h0;
-assign m_src_axi_awlen = 'h0;
-assign m_src_axi_awsize = 'h0;
-assign m_src_axi_awburst = 'h0;
-assign m_src_axi_awcache = 'h0;
-assign m_src_axi_awprot = 'h0;
-assign m_src_axi_wvalid = 'h0;
-assign m_src_axi_wdata = 'h0;
-assign m_src_axi_wstrb = 'h0;
-assign m_src_axi_wlast = 'h0;
-
-assign m_axis_keep = {DMA_DATA_WIDTH_DEST/8{1'b1}};
-assign m_axis_strb = {DMA_DATA_WIDTH_DEST/8{1'b1}};
-assign m_axis_id = 'h0;
-assign m_axis_dest = 'h0;
-assign m_axis_user = 'h0;
+  assign m_axis_keep = {DMA_DATA_WIDTH_DEST/8{1'b1}};
+  assign m_axis_strb = {DMA_DATA_WIDTH_DEST/8{1'b1}};
+  assign m_axis_id = 'h0;
+  assign m_axis_dest = 'h0;
+  assign m_axis_user = 'h0;
 
 endmodule
diff --git a/library/axi_dmac/axi_dmac_burst_memory.v b/library/axi_dmac/axi_dmac_burst_memory.v
index bf80f1122..60ace8453 100644
--- a/library/axi_dmac/axi_dmac_burst_memory.v
+++ b/library/axi_dmac/axi_dmac_burst_memory.v
@@ -80,379 +80,374 @@ module axi_dmac_burst_memory #(
   output  [7:0] dest_diag_level_bursts
 );
 
-localparam DATA_WIDTH_MEM = DATA_WIDTH_SRC > DATA_WIDTH_DEST ?
-  DATA_WIDTH_SRC : DATA_WIDTH_DEST;
-localparam MEM_RATIO = DATA_WIDTH_SRC > DATA_WIDTH_DEST ?
-  DATA_WIDTH_SRC / DATA_WIDTH_DEST : DATA_WIDTH_DEST / DATA_WIDTH_SRC;
+  localparam DATA_WIDTH_MEM = DATA_WIDTH_SRC > DATA_WIDTH_DEST ?
+    DATA_WIDTH_SRC : DATA_WIDTH_DEST;
+  localparam MEM_RATIO = DATA_WIDTH_SRC > DATA_WIDTH_DEST ?
+    DATA_WIDTH_SRC / DATA_WIDTH_DEST : DATA_WIDTH_DEST / DATA_WIDTH_SRC;
 
-/* A burst can have up to 256 beats */
-localparam BURST_LEN = MAX_BYTES_PER_BURST / (DATA_WIDTH_MEM / 8);
-localparam BURST_LEN_WIDTH = BURST_LEN > 128 ? 8 :
-  BURST_LEN > 64 ? 7 :
-  BURST_LEN > 32 ? 6 :
-  BURST_LEN > 16 ? 5 :
-  BURST_LEN > 8 ? 4 :
-  BURST_LEN > 4 ? 3 :
-  BURST_LEN > 2 ? 2 : 1;
+  // A burst can have up to 256 beats
+  localparam BURST_LEN = MAX_BYTES_PER_BURST / (DATA_WIDTH_MEM / 8);
+  localparam BURST_LEN_WIDTH = BURST_LEN > 128 ? 8 :
+    BURST_LEN > 64 ? 7 :
+    BURST_LEN > 32 ? 6 :
+    BURST_LEN > 16 ? 5 :
+    BURST_LEN > 8 ? 4 :
+    BURST_LEN > 4 ? 3 :
+    BURST_LEN > 2 ? 2 : 1;
 
-localparam AUX_FIFO_SIZE = 2**(ID_WIDTH-1);
+  localparam AUX_FIFO_SIZE = 2**(ID_WIDTH-1);
 
-localparam MEM_RATIO_WIDTH =
-    (ALLOW_ASYM_MEM == 0 || MEM_RATIO == 1) ? 0 :
-    MEM_RATIO == 2 ? 1 :
-    MEM_RATIO == 4 ? 2 : 3;
+  localparam MEM_RATIO_WIDTH =
+      (ALLOW_ASYM_MEM == 0 || MEM_RATIO == 1) ? 0 :
+      MEM_RATIO == 2 ? 1 :
+      MEM_RATIO == 4 ? 2 : 3;
 
-localparam BURST_LEN_WIDTH_SRC = BURST_LEN_WIDTH +
-  (DATA_WIDTH_SRC < DATA_WIDTH_MEM ? MEM_RATIO_WIDTH : 0);
-localparam BURST_LEN_WIDTH_DEST = BURST_LEN_WIDTH +
-  (DATA_WIDTH_DEST < DATA_WIDTH_MEM ? MEM_RATIO_WIDTH : 0);
-localparam DATA_WIDTH_MEM_SRC = DATA_WIDTH_MEM >>
-  (DATA_WIDTH_SRC < DATA_WIDTH_MEM ? MEM_RATIO_WIDTH : 0);
-localparam DATA_WIDTH_MEM_DEST = DATA_WIDTH_MEM >>
-  (DATA_WIDTH_DEST < DATA_WIDTH_MEM ? MEM_RATIO_WIDTH : 0);
+  localparam BURST_LEN_WIDTH_SRC = BURST_LEN_WIDTH +
+    (DATA_WIDTH_SRC < DATA_WIDTH_MEM ? MEM_RATIO_WIDTH : 0);
+  localparam BURST_LEN_WIDTH_DEST = BURST_LEN_WIDTH +
+    (DATA_WIDTH_DEST < DATA_WIDTH_MEM ? MEM_RATIO_WIDTH : 0);
+  localparam DATA_WIDTH_MEM_SRC = DATA_WIDTH_MEM >>
+    (DATA_WIDTH_SRC < DATA_WIDTH_MEM ? MEM_RATIO_WIDTH : 0);
+  localparam DATA_WIDTH_MEM_DEST = DATA_WIDTH_MEM >>
+    (DATA_WIDTH_DEST < DATA_WIDTH_MEM ? MEM_RATIO_WIDTH : 0);
 
-localparam ADDRESS_WIDTH_SRC = BURST_LEN_WIDTH_SRC + ID_WIDTH - 1;
-localparam ADDRESS_WIDTH_DEST = BURST_LEN_WIDTH_DEST + ID_WIDTH - 1;
+  localparam ADDRESS_WIDTH_SRC = BURST_LEN_WIDTH_SRC + ID_WIDTH - 1;
+  localparam ADDRESS_WIDTH_DEST = BURST_LEN_WIDTH_DEST + ID_WIDTH - 1;
 
-localparam BYTES_PER_BEAT_WIDTH_MEM_SRC = BYTES_PER_BURST_WIDTH - BURST_LEN_WIDTH_SRC;
-localparam BYTES_PER_BEAT_WIDTH_DEST = BYTES_PER_BURST_WIDTH - BURST_LEN_WIDTH_DEST;
+  localparam BYTES_PER_BEAT_WIDTH_MEM_SRC = BYTES_PER_BURST_WIDTH - BURST_LEN_WIDTH_SRC;
+  localparam BYTES_PER_BEAT_WIDTH_DEST = BYTES_PER_BURST_WIDTH - BURST_LEN_WIDTH_DEST;
 
-/*
- * The burst memory is separated into 2**(ID_WIDTH-1) segments. Each segment can
- * hold up to BURST_LEN beats. The addresses that are used to access the memory
- * are split into two parts. The MSBs index the segment and the LSBs index a
- * beat in a specific segment.
- *
- * src_id and dest_id are used to index the segment of the burst memory on the
- * write and read side respectively. The IDs are 1 bit wider than the address of
- * the burst memory. So we can't use them directly as an index into the burst
- * memory.  Since the IDs are gray counted we also can't just leave out the MSB
- * like with a binary counter. But XOR-ing the two MSBs of a gray counter gives
- * us a gray counter of 1 bit less. Use this to generate the segment index.
- * These addresses are captured in the src_id_reduced and dest_id_reduced
- * signals.
- *
- * src_beat_counter and dest_beat_counter are used to index the beat on the
- * write and read side respectively. They will be incremented for each beat that
- * is written/read. Note that the beat counters are not reset to 0 on the last
- * beat of a burst. This means the first beat of a burst might not be stored at
- * offset 0 in the segment memory. But this is OK since the beat counter
- * increments modulo the segment size and both the write and read side agree on
- * the order.
- */
+  /*
+   * The burst memory is separated into 2**(ID_WIDTH-1) segments. Each segment can
+   * hold up to BURST_LEN beats. The addresses that are used to access the memory
+   * are split into two parts. The MSBs index the segment and the LSBs index a
+   * beat in a specific segment.
+   *
+   * src_id and dest_id are used to index the segment of the burst memory on the
+   * write and read side respectively. The IDs are 1 bit wider than the address of
+   * the burst memory. So we can't use them directly as an index into the burst
+   * memory.  Since the IDs are gray counted we also can't just leave out the MSB
+   * like with a binary counter. But XOR-ing the two MSBs of a gray counter gives
+   * us a gray counter of 1 bit less. Use this to generate the segment index.
+   * These addresses are captured in the src_id_reduced and dest_id_reduced
+   * signals.
+   *
+   * src_beat_counter and dest_beat_counter are used to index the beat on the
+   * write and read side respectively. They will be incremented for each beat that
+   * is written/read. Note that the beat counters are not reset to 0 on the last
+   * beat of a burst. This means the first beat of a burst might not be stored at
+   * offset 0 in the segment memory. But this is OK since the beat counter
+   * increments modulo the segment size and both the write and read side agree on
+   * the order.
+   */
 
-reg [ID_WIDTH-1:0] src_id_next;
-reg [ID_WIDTH-1:0] src_id = 'h0;
-reg src_id_reduced_msb = 1'b0;
-reg [BURST_LEN_WIDTH_SRC-1:0] src_beat_counter = 'h00;
+  reg [ID_WIDTH-1:0] src_id_next;
+  reg [ID_WIDTH-1:0] src_id = 'h0;
+  reg src_id_reduced_msb = 1'b0;
+  reg [BURST_LEN_WIDTH_SRC-1:0] src_beat_counter = 'h00;
 
-reg [ID_WIDTH-1:0] dest_id_next = 'h0;
-reg dest_id_reduced_msb_next = 1'b0;
-reg dest_id_reduced_msb = 1'b0;
-reg [ID_WIDTH-1:0] dest_id = 'h0;
-reg [BURST_LEN_WIDTH_DEST-1:0] dest_beat_counter = 'h00;
-wire [BURST_LEN_WIDTH_DEST-1:0] dest_burst_len;
-reg dest_valid = 1'b0;
-reg dest_mem_data_valid = 1'b0;
-reg dest_mem_data_last = 1'b0;
-reg [DATA_WIDTH_MEM_DEST/8-1:0] dest_mem_data_strb = {DATA_WIDTH_MEM_DEST/8{1'b1}};
+  reg [ID_WIDTH-1:0] dest_id_next = 'h0;
+  reg dest_id_reduced_msb_next = 1'b0;
+  reg dest_id_reduced_msb = 1'b0;
+  reg [ID_WIDTH-1:0] dest_id = 'h0;
+  reg [BURST_LEN_WIDTH_DEST-1:0] dest_beat_counter = 'h00;
+  wire [BURST_LEN_WIDTH_DEST-1:0] dest_burst_len;
+  reg dest_valid = 1'b0;
+  reg dest_mem_data_valid = 1'b0;
+  reg dest_mem_data_last = 1'b0;
+  reg [DATA_WIDTH_MEM_DEST/8-1:0] dest_mem_data_strb = {DATA_WIDTH_MEM_DEST/8{1'b1}};
 
-reg [BYTES_PER_BURST_WIDTH+1-1-DMA_LENGTH_ALIGN:0] burst_len_mem[0:AUX_FIFO_SIZE-1];
+  reg [BYTES_PER_BURST_WIDTH+1-1-DMA_LENGTH_ALIGN:0] burst_len_mem[0:AUX_FIFO_SIZE-1];
 
-wire [BYTES_PER_BURST_WIDTH+1-1:0] src_burst_len_data;
-reg [BYTES_PER_BURST_WIDTH+1-1:0] dest_burst_len_data = {DMA_LENGTH_ALIGN{1'b1}};
+  wire [BYTES_PER_BURST_WIDTH+1-1:0] src_burst_len_data;
+  reg [BYTES_PER_BURST_WIDTH+1-1:0] dest_burst_len_data = {DMA_LENGTH_ALIGN{1'b1}};
 
-wire src_beat;
-wire src_last_beat;
-wire [ID_WIDTH-1:0] src_dest_id;
-wire [ADDRESS_WIDTH_SRC-1:0] src_waddr;
-wire [ID_WIDTH-2:0] src_id_reduced;
-wire src_mem_data_valid;
-wire src_mem_data_last;
-wire [DATA_WIDTH_MEM_SRC-1:0] src_mem_data;
-wire [BYTES_PER_BEAT_WIDTH_MEM_SRC-1:0] src_mem_data_valid_bytes;
-wire src_mem_data_partial_burst;
+  wire src_beat;
+  wire src_last_beat;
+  wire [ID_WIDTH-1:0] src_dest_id;
+  wire [ADDRESS_WIDTH_SRC-1:0] src_waddr;
+  wire [ID_WIDTH-2:0] src_id_reduced;
+  wire src_mem_data_valid;
+  wire src_mem_data_last;
+  wire [DATA_WIDTH_MEM_SRC-1:0] src_mem_data;
+  wire [BYTES_PER_BEAT_WIDTH_MEM_SRC-1:0] src_mem_data_valid_bytes;
+  wire src_mem_data_partial_burst;
 
-wire dest_beat;
-wire dest_last_beat;
-wire dest_last;
-wire [ID_WIDTH-1:0] dest_src_id;
-wire [ADDRESS_WIDTH_DEST-1:0] dest_raddr;
-wire [ID_WIDTH-2:0] dest_id_reduced_next;
-wire [ID_WIDTH-1:0] dest_id_next_inc;
-wire [ID_WIDTH-2:0] dest_id_reduced;
-wire dest_burst_valid;
-wire dest_burst_ready;
-wire dest_ready;
-wire [DATA_WIDTH_MEM_DEST-1:0] dest_mem_data;
-wire dest_mem_data_ready;
+  wire dest_beat;
+  wire dest_last_beat;
+  wire dest_last;
+  wire [ID_WIDTH-1:0] dest_src_id;
+  wire [ADDRESS_WIDTH_DEST-1:0] dest_raddr;
+  wire [ID_WIDTH-2:0] dest_id_reduced_next;
+  wire [ID_WIDTH-1:0] dest_id_next_inc;
+  wire [ID_WIDTH-2:0] dest_id_reduced;
+  wire dest_burst_valid;
+  wire dest_burst_ready;
+  wire dest_ready;
+  wire [DATA_WIDTH_MEM_DEST-1:0] dest_mem_data;
+  wire dest_mem_data_ready;
 
-`include "inc_id.vh"
+  `include "inc_id.vh"
 
-generate if (ID_WIDTH >= 3) begin
-  assign src_id_reduced = {src_id_reduced_msb,src_id[ID_WIDTH-3:0]};
-  assign dest_id_reduced_next = {dest_id_reduced_msb_next,dest_id_next[ID_WIDTH-3:0]};
-  assign dest_id_reduced = {dest_id_reduced_msb,dest_id[ID_WIDTH-3:0]};
-end else begin
-  assign src_id_reduced = src_id_reduced_msb;
-  assign dest_id_reduced_next = dest_id_reduced_msb_next;
-  assign dest_id_reduced = dest_id_reduced_msb;
-end endgenerate
-
-assign src_beat = src_mem_data_valid;
-assign src_last_beat = src_beat & src_mem_data_last;
-assign src_waddr = {src_id_reduced,src_beat_counter};
-
-assign src_data_request_id = src_dest_id;
-
-always @(*) begin
-  if (src_last_beat == 1'b1) begin
-    src_id_next = inc_id(src_id);
+  generate if (ID_WIDTH >= 3) begin
+    assign src_id_reduced = {src_id_reduced_msb,src_id[ID_WIDTH-3:0]};
+    assign dest_id_reduced_next = {dest_id_reduced_msb_next,dest_id_next[ID_WIDTH-3:0]};
+    assign dest_id_reduced = {dest_id_reduced_msb,dest_id[ID_WIDTH-3:0]};
   end else begin
-    src_id_next = src_id;
-  end
-end
+    assign src_id_reduced = src_id_reduced_msb;
+    assign dest_id_reduced_next = dest_id_reduced_msb_next;
+    assign dest_id_reduced = dest_id_reduced_msb;
+  end endgenerate
 
-always @(posedge src_clk) begin
-  if (src_reset == 1'b1) begin
-    src_id <= 'h00;
-    src_id_reduced_msb <= 1'b0;
-  end else begin
-    src_id <= src_id_next;
-    src_id_reduced_msb <= ^src_id_next[ID_WIDTH-1-:2];
-  end
-end
+  assign src_beat = src_mem_data_valid;
+  assign src_last_beat = src_beat & src_mem_data_last;
+  assign src_waddr = {src_id_reduced,src_beat_counter};
 
-always @(posedge src_clk) begin
-  if (src_reset == 1'b1 || src_last_beat == 1'b1) begin
-    src_beat_counter <= 'h00;
-  end else if (src_beat == 1'b1) begin
-    src_beat_counter <= src_beat_counter + 1'b1;
-  end
-end
+  assign src_data_request_id = src_dest_id;
 
-always @(posedge src_clk) begin
-  if (src_last_beat == 1'b1) begin
-    burst_len_mem[src_id_reduced] <= src_burst_len_data[BYTES_PER_BURST_WIDTH:DMA_LENGTH_ALIGN];
-  end
-end
-
-assign dest_ready = ~dest_mem_data_valid | dest_mem_data_ready;
-assign dest_last = dest_beat_counter == dest_burst_len;
-
-assign dest_beat = dest_valid & dest_ready;
-assign dest_last_beat = dest_last & dest_beat;
-assign dest_raddr = {dest_id_reduced,dest_beat_counter};
-
-assign dest_burst_valid = dest_data_request_id != dest_id_next;
-assign dest_burst_ready = ~dest_valid | dest_last_beat;
-
-/*
- * The data valid signal for the destination side is asserted if there are one
- * or more pending bursts. It is de-asserted if there are no more pending burst
- * and it is the last beat of the current burst
- */
-always @(posedge dest_clk) begin
-  if (dest_reset == 1'b1) begin
-    dest_valid <= 1'b0;
-  end else if (dest_burst_valid == 1'b1) begin
-    dest_valid <= 1'b1;
-  end else if (dest_last_beat == 1'b1) begin
-    dest_valid <= 1'b0;
-  end
-end
-
-/*
- * The output register of the memory creates a extra clock cycle of latency on
- * the data path. We need to handle this more the handshaking signals. If data
- * is available in the memory it will be available one clock cycle later in the
- * output register.
- */
-always @(posedge dest_clk) begin
-  if (dest_reset == 1'b1) begin
-    dest_mem_data_valid <= 1'b0;
-  end else if (dest_valid == 1'b1) begin
-    dest_mem_data_valid <= 1'b1;
-  end else if (dest_mem_data_ready == 1'b1) begin
-    dest_mem_data_valid <= 1'b0;
-  end
-end
-
-/*
- * This clears dest_data_last after the last beat. Strictly speaking this is not
- * necessary if this followed AXI handshaking rules since dest_data_last would
- * be qualified by dest_data_valid and it is OK to retain the previous value of
- * dest_data_last when dest_data_valid is not asserted. But clearing the signal
- * here doesn't cost much and can simplify some of the more congested
- * combinatorical logic further up the pipeline since we can assume that
- * fifo_last == 1'b1 implies fifo_valid == 1'b1.
- */
-always @(posedge dest_clk) begin
-  if (dest_reset == 1'b1) begin
-    dest_mem_data_last <= 1'b0;
-  end else if (dest_beat == 1'b1) begin
-    dest_mem_data_last <= dest_last;
-  end else if (dest_mem_data_ready == 1'b1) begin
-    dest_mem_data_last <= 1'b0;
-  end
-end
-
-always @(posedge dest_clk) begin
-  if (dest_beat == 1'b1) begin
-    if (dest_last == 1'b1) begin
-      dest_mem_data_strb <= {DATA_WIDTH_MEM_DEST/8{1'b1}} >> ~dest_burst_len_data[BYTES_PER_BEAT_WIDTH_DEST-1:0];
+  always @(*) begin
+    if (src_last_beat == 1'b1) begin
+      src_id_next = inc_id(src_id);
     end else begin
-      dest_mem_data_strb <= {DATA_WIDTH_MEM_DEST/8{1'b1}};
+      src_id_next = src_id;
     end
   end
-end
 
-assign dest_id_next_inc = inc_id(dest_id_next);
-
-always @(posedge dest_clk) begin
-  if (dest_reset == 1'b1) begin
-    dest_id_next <= 'h00;
-    dest_id_reduced_msb_next <= 1'b0;
-  end else if (dest_burst_valid == 1'b1 && dest_burst_ready == 1'b1) begin
-    dest_id_next <= dest_id_next_inc;
-    dest_id_reduced_msb_next <= ^dest_id_next_inc[ID_WIDTH-1-:2];
+  always @(posedge src_clk) begin
+    if (src_reset == 1'b1) begin
+      src_id <= 'h00;
+      src_id_reduced_msb <= 1'b0;
+    end else begin
+      src_id <= src_id_next;
+      src_id_reduced_msb <= ^src_id_next[ID_WIDTH-1-:2];
+    end
   end
-end
 
-always @(posedge dest_clk) begin
-  if (dest_burst_valid == 1'b1 && dest_burst_ready == 1'b1) begin
-    dest_burst_len_data[BYTES_PER_BURST_WIDTH:DMA_LENGTH_ALIGN] <= burst_len_mem[dest_id_reduced_next];
+  always @(posedge src_clk) begin
+    if (src_reset == 1'b1 || src_last_beat == 1'b1) begin
+      src_beat_counter <= 'h00;
+    end else if (src_beat == 1'b1) begin
+      src_beat_counter <= src_beat_counter + 1'b1;
+    end
   end
-end
 
-always @(posedge dest_clk) begin
-  if (dest_burst_ready == 1'b1) begin
-    dest_id <= dest_id_next;
-    dest_id_reduced_msb <= dest_id_reduced_msb_next;
+  always @(posedge src_clk) begin
+    if (src_last_beat == 1'b1) begin
+      burst_len_mem[src_id_reduced] <= src_burst_len_data[BYTES_PER_BURST_WIDTH:DMA_LENGTH_ALIGN];
+    end
   end
-end
 
-always @(posedge dest_clk) begin
-  if (dest_reset == 1'b1 || dest_last_beat == 1'b1) begin
-    dest_beat_counter <= 'h00;
-  end else if (dest_beat == 1'b1) begin
-    dest_beat_counter <= dest_beat_counter + 1'b1;
-  end
-end
+  assign dest_ready = ~dest_mem_data_valid | dest_mem_data_ready;
+  assign dest_last = dest_beat_counter == dest_burst_len;
 
-assign dest_burst_info_length = dest_burst_len_data[BYTES_PER_BURST_WIDTH-1:0];
-assign dest_burst_info_partial = dest_burst_len_data[BYTES_PER_BURST_WIDTH];
-assign dest_burst_info_id = dest_id;
+  assign dest_beat = dest_valid & dest_ready;
+  assign dest_last_beat = dest_last & dest_beat;
+  assign dest_raddr = {dest_id_reduced,dest_beat_counter};
 
-always @(posedge dest_clk) begin
-  dest_burst_info_write <= (dest_burst_valid == 1'b1 && dest_burst_ready == 1'b1);
-end
+  assign dest_burst_valid = dest_data_request_id != dest_id_next;
+  assign dest_burst_ready = ~dest_valid | dest_last_beat;
 
-assign dest_burst_len = dest_burst_len_data[BYTES_PER_BURST_WIDTH-1 -: BURST_LEN_WIDTH_DEST];
-
-axi_dmac_resize_src #(
-  .DATA_WIDTH_SRC (DATA_WIDTH_SRC),
-  .BYTES_PER_BEAT_WIDTH_SRC (BYTES_PER_BEAT_WIDTH_SRC),
-  .DATA_WIDTH_MEM (DATA_WIDTH_MEM_SRC),
-  .BYTES_PER_BEAT_WIDTH_MEM (BYTES_PER_BEAT_WIDTH_MEM_SRC)
-) i_resize_src (
-  .clk (src_clk),
-  .reset (src_reset),
-
-  .src_data_valid (src_data_valid),
-  .src_data (src_data),
-  .src_data_last (src_data_last),
-  .src_data_valid_bytes (src_data_valid_bytes),
-  .src_data_partial_burst (src_data_partial_burst),
-
-  .mem_data_valid (src_mem_data_valid),
-  .mem_data (src_mem_data),
-  .mem_data_last (src_mem_data_last),
-  .mem_data_valid_bytes (src_mem_data_valid_bytes),
-  .mem_data_partial_burst (src_mem_data_partial_burst)
-);
-
-assign src_burst_len_data = {src_mem_data_partial_burst,
-                             src_beat_counter,
-                             src_mem_data_valid_bytes};
-
-ad_mem_asym #(
-  .A_ADDRESS_WIDTH (ADDRESS_WIDTH_SRC),
-  .A_DATA_WIDTH (DATA_WIDTH_MEM_SRC),
-  .B_ADDRESS_WIDTH (ADDRESS_WIDTH_DEST),
-  .B_DATA_WIDTH (DATA_WIDTH_MEM_DEST)
-) i_mem (
-  .clka (src_clk),
-  .wea (src_beat),
-  .addra (src_waddr),
-  .dina (src_mem_data),
-
-  .clkb (dest_clk),
-  .reb (dest_beat),
-  .addrb (dest_raddr),
-  .doutb (dest_mem_data)
-);
-
-axi_dmac_resize_dest #(
-  .DATA_WIDTH_DEST (DATA_WIDTH_DEST),
-  .DATA_WIDTH_MEM (DATA_WIDTH_MEM_DEST)
-) i_resize_dest (
-  .clk (dest_clk),
-  .reset (dest_reset),
-
-  .mem_data_valid (dest_mem_data_valid),
-  .mem_data_ready (dest_mem_data_ready),
-  .mem_data (dest_mem_data),
-  .mem_data_last (dest_mem_data_last),
-  .mem_data_strb (dest_mem_data_strb),
-
-  .dest_data_valid (dest_data_valid),
-  .dest_data_ready (dest_data_ready),
-  .dest_data (dest_data),
-  .dest_data_last (dest_data_last),
-  .dest_data_strb (dest_data_strb)
-);
-
-sync_bits #(
-  .NUM_OF_BITS (ID_WIDTH),
-  .ASYNC_CLK (ASYNC_CLK)
-) i_dest_sync_id (
-  .in_bits (src_id),
-  .out_clk (dest_clk),
-  .out_resetn (1'b1),
-  .out_bits (dest_src_id)
-);
-
-sync_bits #(
-  .NUM_OF_BITS (ID_WIDTH),
-  .ASYNC_CLK (ASYNC_CLK)
-) i_src_sync_id (
-  .in_bits (dest_id),
-  .out_clk (src_clk),
-  .out_resetn (1'b1),
-  .out_bits (src_dest_id)
-);
-
-assign dest_request_id = dest_src_id;
-assign dest_data_response_id = dest_id;
-
-generate if (ENABLE_DIAGNOSTICS_IF == 1) begin
-
-  reg [ID_WIDTH-1:0] _dest_diag_level_bursts = 'h0;
-
-  // calculate buffer fullness in bursts
+  /*
+   * The data valid signal for the destination side is asserted if there are one
+   * or more pending bursts. It is de-asserted if there are no more pending burst
+   * and it is the last beat of the current burst
+   */
   always @(posedge dest_clk) begin
     if (dest_reset == 1'b1) begin
-      _dest_diag_level_bursts <= 'h0;
-    end else begin
-      _dest_diag_level_bursts <= g2b(dest_src_id) - g2b(dest_id);
+      dest_valid <= 1'b0;
+    end else if (dest_burst_valid == 1'b1) begin
+      dest_valid <= 1'b1;
+    end else if (dest_last_beat == 1'b1) begin
+      dest_valid <= 1'b0;
     end
   end
-  assign dest_diag_level_bursts = {{{8-ID_WIDTH}{1'b0}},_dest_diag_level_bursts};
 
-end else begin
-  assign dest_diag_level_bursts = 'h0;
-end
-endgenerate
+  /*
+   * The output register of the memory creates a extra clock cycle of latency on
+   * the data path. We need to handle this more the handshaking signals. If data
+   * is available in the memory it will be available one clock cycle later in the
+   * output register.
+   */
+  always @(posedge dest_clk) begin
+    if (dest_reset == 1'b1) begin
+      dest_mem_data_valid <= 1'b0;
+    end else if (dest_valid == 1'b1) begin
+      dest_mem_data_valid <= 1'b1;
+    end else if (dest_mem_data_ready == 1'b1) begin
+      dest_mem_data_valid <= 1'b0;
+    end
+  end
+
+  /*
+   * This clears dest_data_last after the last beat. Strictly speaking this is not
+   * necessary if this followed AXI handshaking rules since dest_data_last would
+   * be qualified by dest_data_valid and it is OK to retain the previous value of
+   * dest_data_last when dest_data_valid is not asserted. But clearing the signal
+   * here doesn't cost much and can simplify some of the more congested
+   * combinatorical logic further up the pipeline since we can assume that
+   * fifo_last == 1'b1 implies fifo_valid == 1'b1.
+   */
+  always @(posedge dest_clk) begin
+    if (dest_reset == 1'b1) begin
+      dest_mem_data_last <= 1'b0;
+    end else if (dest_beat == 1'b1) begin
+      dest_mem_data_last <= dest_last;
+    end else if (dest_mem_data_ready == 1'b1) begin
+      dest_mem_data_last <= 1'b0;
+    end
+  end
+
+  always @(posedge dest_clk) begin
+    if (dest_beat == 1'b1) begin
+      if (dest_last == 1'b1) begin
+        dest_mem_data_strb <= {DATA_WIDTH_MEM_DEST/8{1'b1}} >> ~dest_burst_len_data[BYTES_PER_BEAT_WIDTH_DEST-1:0];
+      end else begin
+        dest_mem_data_strb <= {DATA_WIDTH_MEM_DEST/8{1'b1}};
+      end
+    end
+  end
+
+  assign dest_id_next_inc = inc_id(dest_id_next);
+
+  always @(posedge dest_clk) begin
+    if (dest_reset == 1'b1) begin
+      dest_id_next <= 'h00;
+      dest_id_reduced_msb_next <= 1'b0;
+    end else if (dest_burst_valid == 1'b1 && dest_burst_ready == 1'b1) begin
+      dest_id_next <= dest_id_next_inc;
+      dest_id_reduced_msb_next <= ^dest_id_next_inc[ID_WIDTH-1-:2];
+    end
+  end
+
+  always @(posedge dest_clk) begin
+    if (dest_burst_valid == 1'b1 && dest_burst_ready == 1'b1) begin
+      dest_burst_len_data[BYTES_PER_BURST_WIDTH:DMA_LENGTH_ALIGN] <= burst_len_mem[dest_id_reduced_next];
+    end
+  end
+
+  always @(posedge dest_clk) begin
+    if (dest_burst_ready == 1'b1) begin
+      dest_id <= dest_id_next;
+      dest_id_reduced_msb <= dest_id_reduced_msb_next;
+    end
+  end
+
+  always @(posedge dest_clk) begin
+    if (dest_reset == 1'b1 || dest_last_beat == 1'b1) begin
+      dest_beat_counter <= 'h00;
+    end else if (dest_beat == 1'b1) begin
+      dest_beat_counter <= dest_beat_counter + 1'b1;
+    end
+  end
+
+  assign dest_burst_info_length = dest_burst_len_data[BYTES_PER_BURST_WIDTH-1:0];
+  assign dest_burst_info_partial = dest_burst_len_data[BYTES_PER_BURST_WIDTH];
+  assign dest_burst_info_id = dest_id;
+
+  always @(posedge dest_clk) begin
+    dest_burst_info_write <= (dest_burst_valid == 1'b1 && dest_burst_ready == 1'b1);
+  end
+
+  assign dest_burst_len = dest_burst_len_data[BYTES_PER_BURST_WIDTH-1 -: BURST_LEN_WIDTH_DEST];
+
+  axi_dmac_resize_src #(
+    .DATA_WIDTH_SRC (DATA_WIDTH_SRC),
+    .BYTES_PER_BEAT_WIDTH_SRC (BYTES_PER_BEAT_WIDTH_SRC),
+    .DATA_WIDTH_MEM (DATA_WIDTH_MEM_SRC),
+    .BYTES_PER_BEAT_WIDTH_MEM (BYTES_PER_BEAT_WIDTH_MEM_SRC)
+  ) i_resize_src (
+    .clk (src_clk),
+    .reset (src_reset),
+
+    .src_data_valid (src_data_valid),
+    .src_data (src_data),
+    .src_data_last (src_data_last),
+    .src_data_valid_bytes (src_data_valid_bytes),
+    .src_data_partial_burst (src_data_partial_burst),
+
+    .mem_data_valid (src_mem_data_valid),
+    .mem_data (src_mem_data),
+    .mem_data_last (src_mem_data_last),
+    .mem_data_valid_bytes (src_mem_data_valid_bytes),
+    .mem_data_partial_burst (src_mem_data_partial_burst));
+
+  assign src_burst_len_data = {src_mem_data_partial_burst,
+                               src_beat_counter,
+                               src_mem_data_valid_bytes};
+
+  ad_mem_asym #(
+    .A_ADDRESS_WIDTH (ADDRESS_WIDTH_SRC),
+    .A_DATA_WIDTH (DATA_WIDTH_MEM_SRC),
+    .B_ADDRESS_WIDTH (ADDRESS_WIDTH_DEST),
+    .B_DATA_WIDTH (DATA_WIDTH_MEM_DEST)
+  ) i_mem (
+    .clka (src_clk),
+    .wea (src_beat),
+    .addra (src_waddr),
+    .dina (src_mem_data),
+
+    .clkb (dest_clk),
+    .reb (dest_beat),
+    .addrb (dest_raddr),
+    .doutb (dest_mem_data));
+
+  axi_dmac_resize_dest #(
+    .DATA_WIDTH_DEST (DATA_WIDTH_DEST),
+    .DATA_WIDTH_MEM (DATA_WIDTH_MEM_DEST)
+  ) i_resize_dest (
+    .clk (dest_clk),
+    .reset (dest_reset),
+
+    .mem_data_valid (dest_mem_data_valid),
+    .mem_data_ready (dest_mem_data_ready),
+    .mem_data (dest_mem_data),
+    .mem_data_last (dest_mem_data_last),
+    .mem_data_strb (dest_mem_data_strb),
+
+    .dest_data_valid (dest_data_valid),
+    .dest_data_ready (dest_data_ready),
+    .dest_data (dest_data),
+    .dest_data_last (dest_data_last),
+    .dest_data_strb (dest_data_strb));
+
+  sync_bits #(
+    .NUM_OF_BITS (ID_WIDTH),
+    .ASYNC_CLK (ASYNC_CLK)
+  ) i_dest_sync_id (
+    .in_bits (src_id),
+    .out_clk (dest_clk),
+    .out_resetn (1'b1),
+    .out_bits (dest_src_id));
+
+  sync_bits #(
+    .NUM_OF_BITS (ID_WIDTH),
+    .ASYNC_CLK (ASYNC_CLK)
+  ) i_src_sync_id (
+    .in_bits (dest_id),
+    .out_clk (src_clk),
+    .out_resetn (1'b1),
+    .out_bits (src_dest_id));
+
+  assign dest_request_id = dest_src_id;
+  assign dest_data_response_id = dest_id;
+
+  generate if (ENABLE_DIAGNOSTICS_IF == 1) begin
+
+    reg [ID_WIDTH-1:0] _dest_diag_level_bursts = 'h0;
+
+    // calculate buffer fullness in bursts
+    always @(posedge dest_clk) begin
+      if (dest_reset == 1'b1) begin
+        _dest_diag_level_bursts <= 'h0;
+      end else begin
+        _dest_diag_level_bursts <= g2b(dest_src_id) - g2b(dest_id);
+      end
+    end
+    assign dest_diag_level_bursts = {{{8-ID_WIDTH}{1'b0}},_dest_diag_level_bursts};
+
+  end else begin
+    assign dest_diag_level_bursts = 'h0;
+  end
+  endgenerate
 
 endmodule
diff --git a/library/axi_dmac/axi_dmac_regmap.v b/library/axi_dmac/axi_dmac_regmap.v
index 2905973ae..9b510163c 100644
--- a/library/axi_dmac/axi_dmac_regmap.v
+++ b/library/axi_dmac/axi_dmac_regmap.v
@@ -53,6 +53,7 @@ module axi_dmac_regmap #(
   parameter SYNC_TRANSFER_START = 0,
   parameter CACHE_COHERENT_DEST = 0
 ) (
+
   // Slave AXI interface
   input s_axi_aclk,
   input s_axi_aresetn,
@@ -115,189 +116,187 @@ module axi_dmac_regmap #(
   input [31:0] dbg_ids1
 );
 
-localparam PCORE_VERSION = 'h00040461;
+  localparam PCORE_VERSION = 'h00040461;
 
-// Register interface signals
-reg [31:0] up_rdata = 32'h00;
-reg up_wack = 1'b0;
-reg up_rack = 1'b0;
+  // Register interface signals
+  reg [31:0] up_rdata = 32'h00;
+  reg up_wack = 1'b0;
+  reg up_rack = 1'b0;
 
-wire up_wreq;
-wire up_rreq;
-wire [31:0] up_wdata;
-wire [8:0] up_waddr;
-wire [8:0] up_raddr;
-wire [31:0] up_rdata_request;
+  wire up_wreq;
+  wire up_rreq;
+  wire [31:0] up_wdata;
+  wire [8:0] up_waddr;
+  wire [8:0] up_raddr;
+  wire [31:0] up_rdata_request;
 
-// Scratch register
-reg [31:0] up_scratch = 32'h00;
+  // Scratch register
+  reg [31:0] up_scratch = 32'h00;
 
-// Start and end of transfer
-wire up_eot; // Asserted for one cycle when a transfer has been completed
-wire up_sot; // Asserted for one cycle when a transfer has been queued
+  // Start and end of transfer
+  wire up_eot; // Asserted for one cycle when a transfer has been completed
+  wire up_sot; // Asserted for one cycle when a transfer has been queued
 
-// Interupt handling
-reg [1:0] up_irq_mask = 2'h3;
-reg [1:0] up_irq_source = 2'h0;
+  // Interupt handling
+  reg [1:0] up_irq_mask = 2'h3;
+  reg [1:0] up_irq_source = 2'h0;
 
-wire [1:0] up_irq_pending;
-wire [1:0] up_irq_trigger;
-wire [1:0] up_irq_source_clear;
+  wire [1:0] up_irq_pending;
+  wire [1:0] up_irq_trigger;
+  wire [1:0] up_irq_source_clear;
 
-// IRQ handling
-assign up_irq_pending = ~up_irq_mask & up_irq_source;
-assign up_irq_trigger  = {up_eot, up_sot};
-assign up_irq_source_clear = (up_wreq == 1'b1 && up_waddr == 9'h021) ? up_wdata[1:0] : 2'b00;
+  // IRQ handling
+  assign up_irq_pending = ~up_irq_mask & up_irq_source;
+  assign up_irq_trigger  = {up_eot, up_sot};
+  assign up_irq_source_clear = (up_wreq == 1'b1 && up_waddr == 9'h021) ? up_wdata[1:0] : 2'b00;
 
-always @(posedge s_axi_aclk) begin
-  if (s_axi_aresetn == 1'b0) begin
-    irq <= 1'b0;
-  end else begin
-    irq <= |up_irq_pending;
+  always @(posedge s_axi_aclk) begin
+    if (s_axi_aresetn == 1'b0) begin
+      irq <= 1'b0;
+    end else begin
+      irq <= |up_irq_pending;
+    end
   end
-end
 
-always @(posedge s_axi_aclk) begin
-  if (s_axi_aresetn == 1'b0) begin
-    up_irq_source <= 2'b00;
-  end else begin
-    up_irq_source <= up_irq_trigger | (up_irq_source & ~up_irq_source_clear);
+  always @(posedge s_axi_aclk) begin
+    if (s_axi_aresetn == 1'b0) begin
+      up_irq_source <= 2'b00;
+    end else begin
+      up_irq_source <= up_irq_trigger | (up_irq_source & ~up_irq_source_clear);
+    end
   end
-end
 
-// Register Interface
+  // Register Interface
 
-always @(posedge s_axi_aclk) begin
-  if (s_axi_aresetn == 1'b0) begin
-    ctrl_enable <= 1'b0;
-    ctrl_pause <= 1'b0;
-    up_irq_mask <= 2'b11;
-    up_scratch <= 32'h00;
-    up_wack <= 1'b0;
-  end else begin
-    up_wack <= up_wreq;
+  always @(posedge s_axi_aclk) begin
+    if (s_axi_aresetn == 1'b0) begin
+      ctrl_enable <= 1'b0;
+      ctrl_pause <= 1'b0;
+      up_irq_mask <= 2'b11;
+      up_scratch <= 32'h00;
+      up_wack <= 1'b0;
+    end else begin
+      up_wack <= up_wreq;
 
-    if (up_wreq == 1'b1) begin
-      case (up_waddr)
-      9'h002: up_scratch <= up_wdata;
-      9'h020: up_irq_mask <= up_wdata[1:0];
-      9'h100: {ctrl_pause, ctrl_enable} <= up_wdata[1:0];
+      if (up_wreq == 1'b1) begin
+        case (up_waddr)
+        9'h002: up_scratch <= up_wdata;
+        9'h020: up_irq_mask <= up_wdata[1:0];
+        9'h100: {ctrl_pause, ctrl_enable} <= up_wdata[1:0];
+        endcase
+      end
+    end
+  end
+
+  always @(posedge s_axi_aclk) begin
+    if (s_axi_aresetn == 1'b0) begin
+      up_rack <= 'd0;
+    end else begin
+      up_rack <= up_rreq;
+    end
+  end
+
+  always @(posedge s_axi_aclk) begin
+    if (up_rreq == 1'b1) begin
+      case (up_raddr)
+      9'h000: up_rdata <= PCORE_VERSION;
+      9'h001: up_rdata <= ID;
+      9'h002: up_rdata <= up_scratch;
+      9'h003: up_rdata <= 32'h444d4143; // "DMAC"
+      9'h004: up_rdata <= {8'b0,
+                           4'b0,BYTES_PER_BURST_WIDTH[3:0],
+                           2'b0,DMA_TYPE_SRC[1:0],BYTES_PER_BEAT_WIDTH_SRC[3:0],
+                           2'b0,DMA_TYPE_DEST[1:0],BYTES_PER_BEAT_WIDTH_DEST[3:0]};
+      9'h005: up_rdata <= {31'd0, CACHE_COHERENT_DEST};
+      9'h020: up_rdata <= up_irq_mask;
+      9'h021: up_rdata <= up_irq_pending;
+      9'h022: up_rdata <= up_irq_source;
+      9'h100: up_rdata <= {ctrl_pause, ctrl_enable};
+      9'h10d: up_rdata <= DISABLE_DEBUG_REGISTERS ? 32'h00 : dbg_dest_addr;
+      9'h10e: up_rdata <= DISABLE_DEBUG_REGISTERS ? 32'h00 : dbg_src_addr;
+      9'h10f: up_rdata <= DISABLE_DEBUG_REGISTERS ? 32'h00 : dbg_status;
+      9'h110: up_rdata <= DISABLE_DEBUG_REGISTERS ? 32'h00 : dbg_ids0;
+      9'h111: up_rdata <= DISABLE_DEBUG_REGISTERS ? 32'h00 : dbg_ids1;
+      default: up_rdata <= up_rdata_request;
       endcase
     end
   end
-end
 
-always @(posedge s_axi_aclk) begin
-  if (s_axi_aresetn == 1'b0) begin
-    up_rack <= 'd0;
-  end else begin
-    up_rack <= up_rreq;
-  end
-end
+  axi_dmac_regmap_request #(
+    .DISABLE_DEBUG_REGISTERS(DISABLE_DEBUG_REGISTERS),
+    .BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT_WIDTH_DEST),
+    .BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC),
+    .BYTES_PER_BURST_WIDTH(BYTES_PER_BURST_WIDTH),
+    .DMA_AXI_ADDR_WIDTH(DMA_AXI_ADDR_WIDTH),
+    .DMA_LENGTH_WIDTH(DMA_LENGTH_WIDTH),
+    .DMA_LENGTH_ALIGN(DMA_LENGTH_ALIGN),
+    .DMA_CYCLIC(DMA_CYCLIC),
+    .HAS_DEST_ADDR(HAS_DEST_ADDR),
+    .HAS_SRC_ADDR(HAS_SRC_ADDR),
+    .DMA_2D_TRANSFER(DMA_2D_TRANSFER),
+    .SYNC_TRANSFER_START(SYNC_TRANSFER_START)
+  ) i_regmap_request (
+    .clk(s_axi_aclk),
+    .reset(~s_axi_aresetn),
 
-always @(posedge s_axi_aclk) begin
-  if (up_rreq == 1'b1) begin
-    case (up_raddr)
-    9'h000: up_rdata <= PCORE_VERSION;
-    9'h001: up_rdata <= ID;
-    9'h002: up_rdata <= up_scratch;
-    9'h003: up_rdata <= 32'h444d4143; // "DMAC"
-    9'h004: up_rdata <= {8'b0,
-                         4'b0,BYTES_PER_BURST_WIDTH[3:0],
-                         2'b0,DMA_TYPE_SRC[1:0],BYTES_PER_BEAT_WIDTH_SRC[3:0],
-                         2'b0,DMA_TYPE_DEST[1:0],BYTES_PER_BEAT_WIDTH_DEST[3:0]};
-    9'h005: up_rdata <= {31'd0, CACHE_COHERENT_DEST};
-    9'h020: up_rdata <= up_irq_mask;
-    9'h021: up_rdata <= up_irq_pending;
-    9'h022: up_rdata <= up_irq_source;
-    9'h100: up_rdata <= {ctrl_pause, ctrl_enable};
-    9'h10d: up_rdata <= DISABLE_DEBUG_REGISTERS ? 32'h00 : dbg_dest_addr;
-    9'h10e: up_rdata <= DISABLE_DEBUG_REGISTERS ? 32'h00 : dbg_src_addr;
-    9'h10f: up_rdata <= DISABLE_DEBUG_REGISTERS ? 32'h00 : dbg_status;
-    9'h110: up_rdata <= DISABLE_DEBUG_REGISTERS ? 32'h00 : dbg_ids0;
-    9'h111: up_rdata <= DISABLE_DEBUG_REGISTERS ? 32'h00 : dbg_ids1;
-    default: up_rdata <= up_rdata_request;
-    endcase
-  end
-end
+    .up_sot(up_sot),
+    .up_eot(up_eot),
 
-axi_dmac_regmap_request #(
-  .DISABLE_DEBUG_REGISTERS(DISABLE_DEBUG_REGISTERS),
-  .BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT_WIDTH_DEST),
-  .BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC),
-  .BYTES_PER_BURST_WIDTH(BYTES_PER_BURST_WIDTH),
-  .DMA_AXI_ADDR_WIDTH(DMA_AXI_ADDR_WIDTH),
-  .DMA_LENGTH_WIDTH(DMA_LENGTH_WIDTH),
-  .DMA_LENGTH_ALIGN(DMA_LENGTH_ALIGN),
-  .DMA_CYCLIC(DMA_CYCLIC),
-  .HAS_DEST_ADDR(HAS_DEST_ADDR),
-  .HAS_SRC_ADDR(HAS_SRC_ADDR),
-  .DMA_2D_TRANSFER(DMA_2D_TRANSFER),
-  .SYNC_TRANSFER_START(SYNC_TRANSFER_START)
-) i_regmap_request (
-  .clk(s_axi_aclk),
-  .reset(~s_axi_aresetn),
+    .up_wreq(up_wreq),
+    .up_rreq(up_rreq),
+    .up_waddr(up_waddr),
+    .up_wdata(up_wdata),
+    .up_raddr(up_raddr),
+    .up_rdata(up_rdata_request),
 
-  .up_sot(up_sot),
-  .up_eot(up_eot),
+    .ctrl_enable(ctrl_enable),
 
-  .up_wreq(up_wreq),
-  .up_rreq(up_rreq),
-  .up_waddr(up_waddr),
-  .up_wdata(up_wdata),
-  .up_raddr(up_raddr),
-  .up_rdata(up_rdata_request),
+    .request_valid(request_valid),
+    .request_ready(request_ready),
+    .request_dest_address(request_dest_address),
+    .request_src_address(request_src_address),
+    .request_x_length(request_x_length),
+    .request_y_length(request_y_length),
+    .request_dest_stride(request_dest_stride),
+    .request_src_stride(request_src_stride),
+    .request_sync_transfer_start(request_sync_transfer_start),
+    .request_last(request_last),
 
-  .ctrl_enable(ctrl_enable),
+    .response_eot(response_eot),
+    .response_measured_burst_length(response_measured_burst_length),
+    .response_partial(response_partial),
+    .response_valid(response_valid),
+    .response_ready(response_ready));
 
-  .request_valid(request_valid),
-  .request_ready(request_ready),
-  .request_dest_address(request_dest_address),
-  .request_src_address(request_src_address),
-  .request_x_length(request_x_length),
-  .request_y_length(request_y_length),
-  .request_dest_stride(request_dest_stride),
-  .request_src_stride(request_src_stride),
-  .request_sync_transfer_start(request_sync_transfer_start),
-  .request_last(request_last),
-
-  .response_eot(response_eot),
-  .response_measured_burst_length(response_measured_burst_length),
-  .response_partial(response_partial),
-  .response_valid(response_valid),
-  .response_ready(response_ready)
-);
-
-up_axi #(
-  .AXI_ADDRESS_WIDTH (11)
-) i_up_axi (
-  .up_rstn(s_axi_aresetn),
-  .up_clk(s_axi_aclk),
-  .up_axi_awvalid(s_axi_awvalid),
-  .up_axi_awaddr(s_axi_awaddr),
-  .up_axi_awready(s_axi_awready),
-  .up_axi_wvalid(s_axi_wvalid),
-  .up_axi_wdata(s_axi_wdata),
-  .up_axi_wstrb(s_axi_wstrb),
-  .up_axi_wready(s_axi_wready),
-  .up_axi_bvalid(s_axi_bvalid),
-  .up_axi_bresp(s_axi_bresp),
-  .up_axi_bready(s_axi_bready),
-  .up_axi_arvalid(s_axi_arvalid),
-  .up_axi_araddr(s_axi_araddr),
-  .up_axi_arready(s_axi_arready),
-  .up_axi_rvalid(s_axi_rvalid),
-  .up_axi_rresp(s_axi_rresp),
-  .up_axi_rdata(s_axi_rdata),
-  .up_axi_rready(s_axi_rready),
-  .up_wreq(up_wreq),
-  .up_waddr(up_waddr),
-  .up_wdata(up_wdata),
-  .up_wack(up_wack),
-  .up_rreq(up_rreq),
-  .up_raddr(up_raddr),
-  .up_rdata(up_rdata),
-  .up_rack(up_rack)
-);
+  up_axi #(
+    .AXI_ADDRESS_WIDTH (11)
+  ) i_up_axi (
+    .up_rstn(s_axi_aresetn),
+    .up_clk(s_axi_aclk),
+    .up_axi_awvalid(s_axi_awvalid),
+    .up_axi_awaddr(s_axi_awaddr),
+    .up_axi_awready(s_axi_awready),
+    .up_axi_wvalid(s_axi_wvalid),
+    .up_axi_wdata(s_axi_wdata),
+    .up_axi_wstrb(s_axi_wstrb),
+    .up_axi_wready(s_axi_wready),
+    .up_axi_bvalid(s_axi_bvalid),
+    .up_axi_bresp(s_axi_bresp),
+    .up_axi_bready(s_axi_bready),
+    .up_axi_arvalid(s_axi_arvalid),
+    .up_axi_araddr(s_axi_araddr),
+    .up_axi_arready(s_axi_arready),
+    .up_axi_rvalid(s_axi_rvalid),
+    .up_axi_rresp(s_axi_rresp),
+    .up_axi_rdata(s_axi_rdata),
+    .up_axi_rready(s_axi_rready),
+    .up_wreq(up_wreq),
+    .up_waddr(up_waddr),
+    .up_wdata(up_wdata),
+    .up_wack(up_wack),
+    .up_rreq(up_rreq),
+    .up_raddr(up_raddr),
+    .up_rdata(up_rdata),
+    .up_rack(up_rack));
 
 endmodule
diff --git a/library/axi_dmac/axi_dmac_regmap_request.v b/library/axi_dmac/axi_dmac_regmap_request.v
index c6b57b742..438d1e04c 100644
--- a/library/axi_dmac/axi_dmac_regmap_request.v
+++ b/library/axi_dmac/axi_dmac_regmap_request.v
@@ -85,230 +85,228 @@ module axi_dmac_regmap_request #(
   input response_partial,
   input response_valid,
   output reg response_ready = 1'b1
-
 );
 
-localparam MEASURED_LENGTH_WIDTH = (DMA_2D_TRANSFER == 1) ? 32 : DMA_LENGTH_WIDTH;
+  localparam MEASURED_LENGTH_WIDTH = (DMA_2D_TRANSFER == 1) ? 32 : DMA_LENGTH_WIDTH;
 
-// DMA transfer signals
-reg up_dma_req_valid = 1'b0;
-wire up_dma_req_ready;
+  // DMA transfer signals
+  reg up_dma_req_valid = 1'b0;
+  wire up_dma_req_ready;
 
-reg [1:0] up_transfer_id = 2'b0;
-reg [1:0] up_transfer_id_eot = 2'b0;
-reg [3:0] up_transfer_done_bitmap = 4'b0;
+  reg [1:0] up_transfer_id = 2'b0;
+  reg [1:0] up_transfer_id_eot = 2'b0;
+  reg [3:0] up_transfer_done_bitmap = 4'b0;
 
-reg [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] up_dma_dest_address = 'h00;
-reg [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC]  up_dma_src_address = 'h00;
-reg [DMA_LENGTH_WIDTH-1:0] up_dma_x_length = {DMA_LENGTH_ALIGN{1'b1}};
-reg up_dma_cyclic = DMA_CYCLIC ? 1'b1 : 1'b0;
-reg up_dma_last = 1'b1;
-reg up_dma_enable_tlen_reporting = 1'b0;
+  reg [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] up_dma_dest_address = 'h00;
+  reg [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC]  up_dma_src_address = 'h00;
+  reg [DMA_LENGTH_WIDTH-1:0] up_dma_x_length = {DMA_LENGTH_ALIGN{1'b1}};
+  reg up_dma_cyclic = DMA_CYCLIC ? 1'b1 : 1'b0;
+  reg up_dma_last = 1'b1;
+  reg up_dma_enable_tlen_reporting = 1'b0;
 
-wire up_tlf_s_ready;
-reg up_tlf_s_valid = 1'b0;
+  wire up_tlf_s_ready;
+  reg up_tlf_s_valid = 1'b0;
 
-wire [MEASURED_LENGTH_WIDTH+2-1:0] up_tlf_data;
-wire up_tlf_valid;
-wire up_tlf_rd;
-reg up_partial_length_valid = 1'b0;
+  wire [MEASURED_LENGTH_WIDTH+2-1:0] up_tlf_data;
+  wire up_tlf_valid;
+  wire up_tlf_rd;
+  reg up_partial_length_valid = 1'b0;
 
-reg [MEASURED_LENGTH_WIDTH-1:0] up_measured_transfer_length = 'h0;
-reg up_clear_tl = 1'b0;
-reg [1:0] up_transfer_id_eot_d = 'h0;
-wire up_bl_partial;
+  reg [MEASURED_LENGTH_WIDTH-1:0] up_measured_transfer_length = 'h0;
+  reg up_clear_tl = 1'b0;
+  reg [1:0] up_transfer_id_eot_d = 'h0;
+  wire up_bl_partial;
 
-assign request_dest_address = up_dma_dest_address;
-assign request_src_address = up_dma_src_address;
-assign request_x_length = up_dma_x_length;
-assign request_sync_transfer_start = SYNC_TRANSFER_START ? 1'b1 : 1'b0;
-assign request_last = up_dma_last;
-
-always @(posedge clk) begin
-  if (reset == 1'b1) begin
-    up_dma_src_address <= 'h00;
-    up_dma_dest_address <= 'h00;
-    up_dma_x_length[DMA_LENGTH_WIDTH-1:DMA_LENGTH_ALIGN] <= 'h00;
-    up_dma_req_valid <= 1'b0;
-    up_dma_cyclic <= DMA_CYCLIC ? 1'b1 : 1'b0;
-    up_dma_last <= 1'b1;
-    up_dma_enable_tlen_reporting <= 1'b0;
-  end else begin
-    if (ctrl_enable == 1'b1) begin
-      if (up_wreq == 1'b1 && up_waddr == 9'h102) begin
-        up_dma_req_valid <= up_dma_req_valid | up_wdata[0];
-      end else if (up_sot == 1'b1) begin
-        up_dma_req_valid <= 1'b0;
-      end
-    end else begin
-      up_dma_req_valid <= 1'b0;
-    end
-
-    if (up_wreq == 1'b1) begin
-      case (up_waddr)
-      9'h103: begin
-        if (DMA_CYCLIC) up_dma_cyclic <= up_wdata[0];
-        up_dma_last <= up_wdata[1];
-        up_dma_enable_tlen_reporting <= up_wdata[2];
-      end
-      9'h104: up_dma_dest_address <= up_wdata[DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST];
-      9'h105: up_dma_src_address <= up_wdata[DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC];
-      9'h106: up_dma_x_length[DMA_LENGTH_WIDTH-1:DMA_LENGTH_ALIGN] <= up_wdata[DMA_LENGTH_WIDTH-1:DMA_LENGTH_ALIGN];
-      endcase
-    end
-  end
-end
-
-always @(*) begin
-  case (up_raddr)
-  9'h101: up_rdata <= up_transfer_id;
-  9'h102: up_rdata <= up_dma_req_valid;
-  9'h103: up_rdata <= {29'h00, up_dma_enable_tlen_reporting, up_dma_last, up_dma_cyclic}; // Flags
-  9'h104: up_rdata <= HAS_DEST_ADDR ? {up_dma_dest_address,{BYTES_PER_BEAT_WIDTH_DEST{1'b0}}} : 'h00;
-  9'h105: up_rdata <= HAS_SRC_ADDR ? {up_dma_src_address,{BYTES_PER_BEAT_WIDTH_SRC{1'b0}}} : 'h00;
-  9'h106: up_rdata <= up_dma_x_length;
-  9'h107: up_rdata <= request_y_length;
-  9'h108: up_rdata <= request_dest_stride;
-  9'h109: up_rdata <= request_src_stride;
-  9'h10a: up_rdata <= {up_partial_length_valid,27'b0,up_transfer_done_bitmap};
-  9'h10b: up_rdata <= up_transfer_id_eot;
-  9'h10c: up_rdata <= 32'h0;
-  9'h112: up_rdata <= up_measured_transfer_length;
-  9'h113: up_rdata <= up_tlf_data[MEASURED_LENGTH_WIDTH-1 : 0];   // Length
-  9'h114: up_rdata <= up_tlf_data[MEASURED_LENGTH_WIDTH+: 2];  // ID
-  default: up_rdata <= 32'h00;
-  endcase
-end
-
-generate
-if (DMA_2D_TRANSFER == 1) begin
-  reg [DMA_LENGTH_WIDTH-1:0] up_dma_y_length = 'h00;
-  reg [DMA_LENGTH_WIDTH-1:0] up_dma_src_stride = 'h00;
-  reg [DMA_LENGTH_WIDTH-1:0] up_dma_dest_stride = 'h00;
+  assign request_dest_address = up_dma_dest_address;
+  assign request_src_address = up_dma_src_address;
+  assign request_x_length = up_dma_x_length;
+  assign request_sync_transfer_start = SYNC_TRANSFER_START ? 1'b1 : 1'b0;
+  assign request_last = up_dma_last;
 
   always @(posedge clk) begin
     if (reset == 1'b1) begin
-      up_dma_y_length <= 'h00;
-      up_dma_dest_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] <= 'h00;
-      up_dma_src_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] <= 'h00;
-    end else if (up_wreq == 1'b1) begin
-      case (up_waddr)
-      9'h107: up_dma_y_length <= up_wdata[DMA_LENGTH_WIDTH-1:0];
-      9'h108: up_dma_dest_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] <= up_wdata[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST];
-      9'h109: up_dma_src_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] <= up_wdata[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC];
-      endcase
+      up_dma_src_address <= 'h00;
+      up_dma_dest_address <= 'h00;
+      up_dma_x_length[DMA_LENGTH_WIDTH-1:DMA_LENGTH_ALIGN] <= 'h00;
+      up_dma_req_valid <= 1'b0;
+      up_dma_cyclic <= DMA_CYCLIC ? 1'b1 : 1'b0;
+      up_dma_last <= 1'b1;
+      up_dma_enable_tlen_reporting <= 1'b0;
+    end else begin
+      if (ctrl_enable == 1'b1) begin
+        if (up_wreq == 1'b1 && up_waddr == 9'h102) begin
+          up_dma_req_valid <= up_dma_req_valid | up_wdata[0];
+        end else if (up_sot == 1'b1) begin
+          up_dma_req_valid <= 1'b0;
+        end
+      end else begin
+        up_dma_req_valid <= 1'b0;
+      end
+
+      if (up_wreq == 1'b1) begin
+        case (up_waddr)
+        9'h103: begin
+          if (DMA_CYCLIC) up_dma_cyclic <= up_wdata[0];
+          up_dma_last <= up_wdata[1];
+          up_dma_enable_tlen_reporting <= up_wdata[2];
+        end
+        9'h104: up_dma_dest_address <= up_wdata[DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST];
+        9'h105: up_dma_src_address <= up_wdata[DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC];
+        9'h106: up_dma_x_length[DMA_LENGTH_WIDTH-1:DMA_LENGTH_ALIGN] <= up_wdata[DMA_LENGTH_WIDTH-1:DMA_LENGTH_ALIGN];
+        endcase
+      end
     end
   end
-  assign request_y_length = up_dma_y_length;
-  assign request_dest_stride = up_dma_dest_stride;
-  assign request_src_stride = up_dma_src_stride;
-end else begin
-  assign request_y_length = 'h0;
-  assign request_dest_stride = 'h0;
-  assign request_src_stride = 'h0;
-end
-endgenerate
 
-// In cyclic mode the same transfer is submitted over and over again
-assign up_sot = up_dma_cyclic ? 1'b0 : up_dma_req_valid & up_dma_req_ready;
-assign up_eot = up_dma_cyclic ? 1'b0 : response_eot & response_valid & response_ready;
+  always @(*) begin
+    case (up_raddr)
+    9'h101: up_rdata <= up_transfer_id;
+    9'h102: up_rdata <= up_dma_req_valid;
+    9'h103: up_rdata <= {29'h00, up_dma_enable_tlen_reporting, up_dma_last, up_dma_cyclic}; // Flags
+    9'h104: up_rdata <= HAS_DEST_ADDR ? {up_dma_dest_address,{BYTES_PER_BEAT_WIDTH_DEST{1'b0}}} : 'h00;
+    9'h105: up_rdata <= HAS_SRC_ADDR ? {up_dma_src_address,{BYTES_PER_BEAT_WIDTH_SRC{1'b0}}} : 'h00;
+    9'h106: up_rdata <= up_dma_x_length;
+    9'h107: up_rdata <= request_y_length;
+    9'h108: up_rdata <= request_dest_stride;
+    9'h109: up_rdata <= request_src_stride;
+    9'h10a: up_rdata <= {up_partial_length_valid,27'b0,up_transfer_done_bitmap};
+    9'h10b: up_rdata <= up_transfer_id_eot;
+    9'h10c: up_rdata <= 32'h0;
+    9'h112: up_rdata <= up_measured_transfer_length;
+    9'h113: up_rdata <= up_tlf_data[MEASURED_LENGTH_WIDTH-1 : 0];   // Length
+    9'h114: up_rdata <= up_tlf_data[MEASURED_LENGTH_WIDTH+: 2];  // ID
+    default: up_rdata <= 32'h00;
+    endcase
+  end
 
-assign request_valid = up_dma_req_valid;
-assign up_dma_req_ready = request_ready;
+  generate
+  if (DMA_2D_TRANSFER == 1) begin
+    reg [DMA_LENGTH_WIDTH-1:0] up_dma_y_length = 'h00;
+    reg [DMA_LENGTH_WIDTH-1:0] up_dma_src_stride = 'h00;
+    reg [DMA_LENGTH_WIDTH-1:0] up_dma_dest_stride = 'h00;
 
-// Request ID and Request done bitmap handling
-always @(posedge clk) begin
-  if (ctrl_enable == 1'b0) begin
-    up_transfer_id <= 2'h0;
-    up_transfer_id_eot <= 2'h0;
-    up_transfer_done_bitmap <= 4'h0;
-  end else begin
-    if (up_sot == 1'b1) begin
-      up_transfer_id <= up_transfer_id + 1'b1;
-      up_transfer_done_bitmap[up_transfer_id] <= 1'b0;
+    always @(posedge clk) begin
+      if (reset == 1'b1) begin
+        up_dma_y_length <= 'h00;
+        up_dma_dest_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] <= 'h00;
+        up_dma_src_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] <= 'h00;
+      end else if (up_wreq == 1'b1) begin
+        case (up_waddr)
+        9'h107: up_dma_y_length <= up_wdata[DMA_LENGTH_WIDTH-1:0];
+        9'h108: up_dma_dest_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] <= up_wdata[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST];
+        9'h109: up_dma_src_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] <= up_wdata[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC];
+        endcase
+      end
     end
+    assign request_y_length = up_dma_y_length;
+    assign request_dest_stride = up_dma_dest_stride;
+    assign request_src_stride = up_dma_src_stride;
+  end else begin
+    assign request_y_length = 'h0;
+    assign request_dest_stride = 'h0;
+    assign request_src_stride = 'h0;
+  end
+  endgenerate
 
-    if (up_eot == 1'b1) begin
-      up_transfer_id_eot <= up_transfer_id_eot + 1'b1;
-      up_transfer_done_bitmap[up_transfer_id_eot] <= 1'b1;
+  // In cyclic mode the same transfer is submitted over and over again
+  assign up_sot = up_dma_cyclic ? 1'b0 : up_dma_req_valid & up_dma_req_ready;
+  assign up_eot = up_dma_cyclic ? 1'b0 : response_eot & response_valid & response_ready;
+
+  assign request_valid = up_dma_req_valid;
+  assign up_dma_req_ready = request_ready;
+
+  // Request ID and Request done bitmap handling
+  always @(posedge clk) begin
+    if (ctrl_enable == 1'b0) begin
+      up_transfer_id <= 2'h0;
+      up_transfer_id_eot <= 2'h0;
+      up_transfer_done_bitmap <= 4'h0;
+    end else begin
+      if (up_sot == 1'b1) begin
+        up_transfer_id <= up_transfer_id + 1'b1;
+        up_transfer_done_bitmap[up_transfer_id] <= 1'b0;
+      end
+
+      if (up_eot == 1'b1) begin
+        up_transfer_id_eot <= up_transfer_id_eot + 1'b1;
+        up_transfer_done_bitmap[up_transfer_id_eot] <= 1'b1;
+      end
     end
   end
-end
 
-assign up_tlf_rd = up_rreq && up_raddr == 'h114;
-assign up_bl_partial = response_valid & response_ready & response_partial & up_dma_enable_tlen_reporting;
+  assign up_tlf_rd = up_rreq && up_raddr == 'h114;
+  assign up_bl_partial = response_valid & response_ready & response_partial & up_dma_enable_tlen_reporting;
 
-always @(posedge clk) begin
-  if (ctrl_enable == 1'b0) begin
-    up_partial_length_valid <= 1'b0;
-  end else begin
-    if (up_bl_partial == 1'b1) begin
-      up_partial_length_valid <= 1'b1;
-    end else if (up_tlf_rd == 1'b1) begin
+  always @(posedge clk) begin
+    if (ctrl_enable == 1'b0) begin
       up_partial_length_valid <= 1'b0;
-    end else if (up_tlf_valid == 1'b1) begin
-      up_partial_length_valid <= 1'b1;
+    end else begin
+      if (up_bl_partial == 1'b1) begin
+        up_partial_length_valid <= 1'b1;
+      end else if (up_tlf_rd == 1'b1) begin
+        up_partial_length_valid <= 1'b0;
+      end else if (up_tlf_valid == 1'b1) begin
+        up_partial_length_valid <= 1'b1;
+      end
     end
   end
-end
 
-always @(posedge clk) begin
-  if (ctrl_enable == 1'b0) begin
-    up_measured_transfer_length <= 'h0;
-  end else if (response_valid == 1'b1 && response_ready == 1'b1) begin
-    up_measured_transfer_length <= up_measured_transfer_length + response_measured_burst_length + 1'b1;
-  end else if (up_clear_tl == 1'b1) begin
-    up_measured_transfer_length <= 'h0;
+  always @(posedge clk) begin
+    if (ctrl_enable == 1'b0) begin
+      up_measured_transfer_length <= 'h0;
+    end else if (response_valid == 1'b1 && response_ready == 1'b1) begin
+      up_measured_transfer_length <= up_measured_transfer_length + response_measured_burst_length + 1'b1;
+    end else if (up_clear_tl == 1'b1) begin
+      up_measured_transfer_length <= 'h0;
+    end
   end
-end
 
-always @(posedge clk) begin
-  if (response_valid == 1'b1 && response_ready == 1'b1) begin
-    up_transfer_id_eot_d <= up_transfer_id_eot;
+  always @(posedge clk) begin
+    if (response_valid == 1'b1 && response_ready == 1'b1) begin
+      up_transfer_id_eot_d <= up_transfer_id_eot;
+    end
   end
-end
 
-always @(posedge clk) begin
-  if (ctrl_enable == 1'b0) begin
-    response_ready <= 1'b1;
-  end else if (response_ready == 1'b1) begin
-    response_ready <= ~response_valid;
-  end else if (up_tlf_s_ready == 1'b1) begin
-    response_ready <= 1'b1;
+  always @(posedge clk) begin
+    if (ctrl_enable == 1'b0) begin
+      response_ready <= 1'b1;
+    end else if (response_ready == 1'b1) begin
+      response_ready <= ~response_valid;
+    end else if (up_tlf_s_ready == 1'b1) begin
+      response_ready <= 1'b1;
+    end
   end
-end
 
-always @(posedge clk)
-begin
-  if (response_valid == 1'b1 && response_ready == 1'b1) begin
-    up_tlf_s_valid <= up_bl_partial;
-    up_clear_tl <= response_eot;
-  end else if (up_tlf_s_ready == 1'b1) begin
-    up_tlf_s_valid <= 1'b0;
+  always @(posedge clk)
+  begin
+    if (response_valid == 1'b1 && response_ready == 1'b1) begin
+      up_tlf_s_valid <= up_bl_partial;
+      up_clear_tl <= response_eot;
+    end else if (up_tlf_s_ready == 1'b1) begin
+      up_tlf_s_valid <= 1'b0;
+    end
   end
-end
 
-// Buffer the length and transfer ID of partial transfers
-util_axis_fifo #(
-  .DATA_WIDTH(MEASURED_LENGTH_WIDTH + 2),
-  .ADDRESS_WIDTH(2),
-  .ASYNC_CLK(0)
-) i_transfer_lenghts_fifo (
-  .s_axis_aclk(clk),
-  .s_axis_aresetn(ctrl_enable),
-  .s_axis_valid(up_tlf_s_valid),
-  .s_axis_ready(up_tlf_s_ready),
-  .s_axis_full(),
-  .s_axis_data({up_transfer_id_eot_d, up_measured_transfer_length}),
-  .s_axis_room(),
-  
-  .m_axis_aclk(clk),
-  .m_axis_aresetn(ctrl_enable),
-  .m_axis_valid(up_tlf_valid),
-  .m_axis_ready(up_tlf_rd & up_tlf_valid),
-  .m_axis_data(up_tlf_data),
-  .m_axis_level(),
-  .m_axis_empty ()
-  );
+  // Buffer the length and transfer ID of partial transfers
+  util_axis_fifo #(
+    .DATA_WIDTH(MEASURED_LENGTH_WIDTH + 2),
+    .ADDRESS_WIDTH(2),
+    .ASYNC_CLK(0)
+  ) i_transfer_lenghts_fifo (
+    .s_axis_aclk(clk),
+    .s_axis_aresetn(ctrl_enable),
+    .s_axis_valid(up_tlf_s_valid),
+    .s_axis_ready(up_tlf_s_ready),
+    .s_axis_full(),
+    .s_axis_data({up_transfer_id_eot_d, up_measured_transfer_length}),
+    .s_axis_room(),
+
+    .m_axis_aclk(clk),
+    .m_axis_aresetn(ctrl_enable),
+    .m_axis_valid(up_tlf_valid),
+    .m_axis_ready(up_tlf_rd & up_tlf_valid),
+    .m_axis_data(up_tlf_data),
+    .m_axis_level(),
+    .m_axis_empty ());
 
 endmodule
diff --git a/library/axi_dmac/axi_dmac_reset_manager.v b/library/axi_dmac/axi_dmac_reset_manager.v
index 7eebb9097..8f6193066 100644
--- a/library/axi_dmac/axi_dmac_reset_manager.v
+++ b/library/axi_dmac/axi_dmac_reset_manager.v
@@ -65,240 +65,236 @@ module axi_dmac_reset_manager #(
   output [11:0] dbg_status
 );
 
-/*
- * TODO:
- * If an external reset is asserted for a domain that domain will go into reset
- * immediately. If a transfer is currently active the transfer will be aborted
- * and other domains will be shutdown gracefully. The reset manager will stay in
- * the shutdown state until all external resets have been de-asserted.
- */
+  /*
+   * TODO:
+   * If an external reset is asserted for a domain that domain will go into reset
+   * immediately. If a transfer is currently active the transfer will be aborted
+   * and other domains will be shutdown gracefully. The reset manager will stay in
+   * the shutdown state until all external resets have been de-asserted.
+   */
 
-localparam STATE_DO_RESET = 3'h0;
-localparam STATE_RESET = 3'h1;
-localparam STATE_DISABLED = 3'h2;
-localparam STATE_STARTUP = 3'h3;
-localparam STATE_ENABLED = 3'h4;
-localparam STATE_SHUTDOWN = 3'h5;
+  localparam STATE_DO_RESET = 3'h0;
+  localparam STATE_RESET = 3'h1;
+  localparam STATE_DISABLED = 3'h2;
+  localparam STATE_STARTUP = 3'h3;
+  localparam STATE_ENABLED = 3'h4;
+  localparam STATE_SHUTDOWN = 3'h5;
 
-reg [2:0] state = 3'b000;
-reg needs_reset = 1'b0;
-reg do_reset = 1'b0;
-reg do_enable = 1'b0;
+  reg [2:0] state = 3'b000;
+  reg needs_reset = 1'b0;
+  reg do_reset = 1'b0;
+  reg do_enable = 1'b0;
 
-wire enabled_dest;
-wire enabled_src;
+  wire enabled_dest;
+  wire enabled_src;
 
-wire enabled_all;
-wire disabled_all;
+  wire enabled_all;
+  wire disabled_all;
 
-assign enabled_all = req_enabled & enabled_src & enabled_dest;
-assign disabled_all = ~(req_enabled | enabled_src | enabled_dest);
+  assign enabled_all = req_enabled & enabled_src & enabled_dest;
+  assign disabled_all = ~(req_enabled | enabled_src | enabled_dest);
 
-assign req_enable = do_enable;
+  assign req_enable = do_enable;
 
-assign dbg_status = {needs_reset,req_resetn,src_resetn,dest_resetn,1'b0,req_enabled,enabled_src,enabled_dest,1'b0,state};
+  assign dbg_status = {needs_reset,req_resetn,src_resetn,dest_resetn,1'b0,req_enabled,enabled_src,enabled_dest,1'b0,state};
 
-always @(posedge clk) begin
-  if (state == STATE_DO_RESET) begin
-    do_reset <= 1'b1;
-  end else begin
-    do_reset <= 1'b0;
+  always @(posedge clk) begin
+    if (state == STATE_DO_RESET) begin
+      do_reset <= 1'b1;
+    end else begin
+      do_reset <= 1'b0;
+    end
   end
-end
 
-always @(posedge clk) begin
-  if (state == STATE_STARTUP || state == STATE_ENABLED) begin
-    do_enable <= 1'b1;
-  end else begin
-    do_enable <= 1'b0;
+  always @(posedge clk) begin
+    if (state == STATE_STARTUP || state == STATE_ENABLED) begin
+      do_enable <= 1'b1;
+    end else begin
+      do_enable <= 1'b0;
+    end
   end
-end
 
-/*
- * If ctrl_enable goes from 1 to 0 a shutdown procedure is initiated. During the
- * shutdown procedure all domains are signaled that a shutdown should occur. The
- * domains will then complete any active transactions that are required to
- * complete according to the interface semantics. Once a domain has completed
- * its transactions it will indicate that it has been shutdown. Once all domains
- * indicate that they have been disabled a reset pulse will be generated to all
- * domains to clear all residual state. The reset pulse is long enough so that it
- * is active in all domains for at least 4 clock cycles.
- *
- * Once the reset signal is de-asserted the DMA is in an idle state and can be
- * enabled again. If the DMA receives a enable while it is performing a shutdown
- * sequence it will only be re-enabled once the shutdown sequence has
- * successfully completed.
- *
- * If ctrl_pause is asserted all domains will be disabled. But there will be no
- * reset, so when the ctrl_pause signal is de-asserted again the DMA will resume
- * with its previous state.
- *
- */
+  /*
+   * If ctrl_enable goes from 1 to 0 a shutdown procedure is initiated. During the
+   * shutdown procedure all domains are signaled that a shutdown should occur. The
+   * domains will then complete any active transactions that are required to
+   * complete according to the interface semantics. Once a domain has completed
+   * its transactions it will indicate that it has been shutdown. Once all domains
+   * indicate that they have been disabled a reset pulse will be generated to all
+   * domains to clear all residual state. The reset pulse is long enough so that it
+   * is active in all domains for at least 4 clock cycles.
+   *
+   * Once the reset signal is de-asserted the DMA is in an idle state and can be
+   * enabled again. If the DMA receives a enable while it is performing a shutdown
+   * sequence it will only be re-enabled once the shutdown sequence has
+   * successfully completed.
+   *
+   * If ctrl_pause is asserted all domains will be disabled. But there will be no
+   * reset, so when the ctrl_pause signal is de-asserted again the DMA will resume
+   * with its previous state.
+   *
+   */
 
-/*
- * If ctrl_enable goes low, even for a single clock cycle, we want to go through
- * a full reset sequence. This might happen when the state machine is busy, e.g.
- * going through a startup sequence. To avoid missing the event store it for
- * later.
- */
-always @(posedge clk) begin
-  if (state == STATE_RESET) begin
-    needs_reset <= 1'b0;
-  end else if (ctrl_enable == 1'b0) begin
-    needs_reset <= 1'b1;
+  /*
+   * If ctrl_enable goes low, even for a single clock cycle, we want to go through
+   * a full reset sequence. This might happen when the state machine is busy, e.g.
+   * going through a startup sequence. To avoid missing the event store it for
+   * later.
+   */
+  always @(posedge clk) begin
+    if (state == STATE_RESET) begin
+      needs_reset <= 1'b0;
+    end else if (ctrl_enable == 1'b0) begin
+      needs_reset <= 1'b1;
+    end
   end
-end
 
-always @(posedge clk) begin
-  if (resetn == 1'b0) begin
-    state <= STATE_DO_RESET;
-  end else begin
-    case (state)
-    STATE_DO_RESET: begin
-      state <= STATE_RESET;
-    end
-    STATE_RESET: begin
-      /*
-       * Wait for the reset sequence to complete. Stay in this state when
-       * ctrl_enable == 1'b0, otherwise we'd go through the reset sequence
-       * again and again.
-       */
-      if (ctrl_enable == 1'b1 && req_resetn == 1'b1) begin
-        state <= STATE_DISABLED;
+  always @(posedge clk) begin
+    if (resetn == 1'b0) begin
+      state <= STATE_DO_RESET;
+    end else begin
+      case (state)
+      STATE_DO_RESET: begin
+        state <= STATE_RESET;
       end
-    end
-    STATE_DISABLED: begin
-      if (needs_reset == 1'b1) begin
-        state <= STATE_DO_RESET;
-      end else if (ctrl_pause == 1'b0) begin
-        state <= STATE_STARTUP;
+      STATE_RESET: begin
+        /*
+         * Wait for the reset sequence to complete. Stay in this state when
+         * ctrl_enable == 1'b0, otherwise we'd go through the reset sequence
+         * again and again.
+         */
+        if (ctrl_enable == 1'b1 && req_resetn == 1'b1) begin
+          state <= STATE_DISABLED;
+        end
       end
-    end
-    STATE_STARTUP: begin
-      /* Wait for all domains to be ready */
-      if (enabled_all == 1'b1) begin
-        state <= STATE_ENABLED;
+      STATE_DISABLED: begin
+        if (needs_reset == 1'b1) begin
+          state <= STATE_DO_RESET;
+        end else if (ctrl_pause == 1'b0) begin
+          state <= STATE_STARTUP;
+        end
       end
-    end
-    STATE_ENABLED: begin
-      if (needs_reset == 1'b1 || ctrl_pause == 1'b1) begin
-        state <= STATE_SHUTDOWN;
+      STATE_STARTUP: begin
+        /* Wait for all domains to be ready */
+        if (enabled_all == 1'b1) begin
+          state <= STATE_ENABLED;
+        end
       end
-    end
-    STATE_SHUTDOWN: begin
-      /* Wait for all domains to complete outstanding transactions */
-      if (disabled_all == 1'b1) begin
-        state <= STATE_DISABLED;
+      STATE_ENABLED: begin
+        if (needs_reset == 1'b1 || ctrl_pause == 1'b1) begin
+          state <= STATE_SHUTDOWN;
+        end
       end
+      STATE_SHUTDOWN: begin
+        /* Wait for all domains to complete outstanding transactions */
+        if (disabled_all == 1'b1) begin
+          state <= STATE_DISABLED;
+        end
+      end
+      endcase
     end
-    endcase
   end
-end
 
-/*
- * Chain the reset through all clock domains. This makes sure that is asserted
- * for at least 4 clock cycles of the slowest domain, no matter what. If
- * successive domains have the same clock they'll share their reset signal.
- */
+  /*
+   * Chain the reset through all clock domains. This makes sure that is asserted
+   * for at least 4 clock cycles of the slowest domain, no matter what. If
+   * successive domains have the same clock they'll share their reset signal.
+   */
 
-wire [3:0] reset_async_chain;
-wire [3:0] reset_sync_chain;
-wire [2:0] reset_chain_clks = {clk, src_clk, dest_clk};
+  wire [3:0] reset_async_chain;
+  wire [3:0] reset_sync_chain;
+  wire [2:0] reset_chain_clks = {clk, src_clk, dest_clk};
 
-localparam GEN_ASYNC_RESET = {
-  ASYNC_CLK_REQ_SRC ? 1'b1 : 1'b0,
-  ASYNC_CLK_SRC_DEST ? 1'b1 : 1'b0,
-  1'b1
-};
+  localparam GEN_ASYNC_RESET = {
+    ASYNC_CLK_REQ_SRC ? 1'b1 : 1'b0,
+    ASYNC_CLK_SRC_DEST ? 1'b1 : 1'b0,
+    1'b1
+  };
 
-assign reset_async_chain[0] = 1'b0;
-assign reset_sync_chain[0] = reset_async_chain[3];
+  assign reset_async_chain[0] = 1'b0;
+  assign reset_sync_chain[0] = reset_async_chain[3];
 
-generate
-genvar i;
+  generate
+  genvar i;
 
-for (i = 0; i < 3; i = i + 1) begin: reset_gen
+  for (i = 0; i < 3; i = i + 1) begin: reset_gen
 
-  if (GEN_ASYNC_RESET[i] == 1'b1) begin
+    if (GEN_ASYNC_RESET[i] == 1'b1) begin
 
-    reg [3:0] reset_async = 4'b1111;
-    reg [1:0] reset_sync = 2'b11;
-    reg reset_sync_in = 1'b1;
+      reg [3:0] reset_async = 4'b1111;
+      reg [1:0] reset_sync = 2'b11;
+      reg reset_sync_in = 1'b1;
 
-    always @(posedge reset_chain_clks[i] or posedge reset_sync_chain[i]) begin
-      if (reset_sync_chain[i] == 1'b1) begin
-        reset_sync_in <= 1'b1;
-      end else begin
-        reset_sync_in <= reset_async[0];
+      always @(posedge reset_chain_clks[i] or posedge reset_sync_chain[i]) begin
+        if (reset_sync_chain[i] == 1'b1) begin
+          reset_sync_in <= 1'b1;
+        end else begin
+          reset_sync_in <= reset_async[0];
+        end
       end
-    end
 
-    always @(posedge reset_chain_clks[i] or posedge do_reset) begin
-      if (do_reset == 1'b1) begin
-        reset_async <= 4'b1111;
-      end else begin
-        reset_async <= {reset_async_chain[i], reset_async[3:1]};
+      always @(posedge reset_chain_clks[i] or posedge do_reset) begin
+        if (do_reset == 1'b1) begin
+          reset_async <= 4'b1111;
+        end else begin
+          reset_async <= {reset_async_chain[i], reset_async[3:1]};
+        end
       end
+
+      always @(posedge reset_chain_clks[i]) begin
+        reset_sync <= {reset_sync_in,reset_sync[1]};
+      end
+
+      assign reset_async_chain[i+1] = reset_async[0];
+      assign reset_sync_chain[i+1] = reset_sync[0];
+
+    end else begin
+      assign reset_async_chain[i+1] = reset_async_chain[i];
+      assign reset_sync_chain[i+1] = reset_sync_chain[i];
     end
-
-    always @(posedge reset_chain_clks[i]) begin
-      reset_sync <= {reset_sync_in,reset_sync[1]};
-    end
-
-    assign reset_async_chain[i+1] = reset_async[0];
-    assign reset_sync_chain[i+1] = reset_sync[0];
-
-  end else begin
-    assign reset_async_chain[i+1] = reset_async_chain[i];
-    assign reset_sync_chain[i+1] = reset_sync_chain[i];
   end
-end
 
-endgenerate
+  endgenerate
 
-/* De-assertions in the opposite direction of the data flow: dest, src, request */
-assign dest_resetn = ~reset_sync_chain[1];
-assign src_resetn = ~reset_sync_chain[2];
-assign req_resetn = ~reset_sync_chain[3];
+  /* De-assertions in the opposite direction of the data flow: dest, src, request */
+  assign dest_resetn = ~reset_sync_chain[1];
+  assign src_resetn = ~reset_sync_chain[2];
+  assign req_resetn = ~reset_sync_chain[3];
 
-sync_bits #(
-  .NUM_OF_BITS (1),
-  .ASYNC_CLK (ASYNC_CLK_DEST_REQ)
-) i_sync_control_dest (
-  .out_clk (dest_clk),
-  .out_resetn (1'b1),
-  .in_bits (do_enable),
-  .out_bits (dest_enable)
-);
+  sync_bits #(
+    .NUM_OF_BITS (1),
+    .ASYNC_CLK (ASYNC_CLK_DEST_REQ)
+  ) i_sync_control_dest (
+    .out_clk (dest_clk),
+    .out_resetn (1'b1),
+    .in_bits (do_enable),
+    .out_bits (dest_enable));
 
-sync_bits #(
-  .NUM_OF_BITS (1),
-  .ASYNC_CLK (ASYNC_CLK_DEST_REQ)
-) i_sync_status_dest (
-  .out_clk (clk),
-  .out_resetn (1'b1),
-  .in_bits (dest_enabled),
-  .out_bits (enabled_dest)
-);
+  sync_bits #(
+    .NUM_OF_BITS (1),
+    .ASYNC_CLK (ASYNC_CLK_DEST_REQ)
+  ) i_sync_status_dest (
+    .out_clk (clk),
+    .out_resetn (1'b1),
+    .in_bits (dest_enabled),
+    .out_bits (enabled_dest));
 
-sync_bits #(
-  .NUM_OF_BITS (1),
-  .ASYNC_CLK (ASYNC_CLK_REQ_SRC)
-) i_sync_control_src (
-  .out_clk (src_clk),
-  .out_resetn (1'b1),
-  .in_bits (do_enable),
-  .out_bits (src_enable)
-);
+  sync_bits #(
+    .NUM_OF_BITS (1),
+    .ASYNC_CLK (ASYNC_CLK_REQ_SRC)
+  ) i_sync_control_src (
+    .out_clk (src_clk),
+    .out_resetn (1'b1),
+    .in_bits (do_enable),
+    .out_bits (src_enable));
 
-sync_bits #(
-  .NUM_OF_BITS (1),
-  .ASYNC_CLK (ASYNC_CLK_REQ_SRC)
-) i_sync_status_src (
-  .out_clk (clk),
-  .out_resetn (1'b1),
-  .in_bits (src_enabled),
-  .out_bits (enabled_src)
-);
+  sync_bits #(
+    .NUM_OF_BITS (1),
+    .ASYNC_CLK (ASYNC_CLK_REQ_SRC)
+  ) i_sync_status_src (
+    .out_clk (clk),
+    .out_resetn (1'b1),
+    .in_bits (src_enabled),
+    .out_bits (enabled_src));
 
 endmodule
diff --git a/library/axi_dmac/axi_dmac_resize_dest.v b/library/axi_dmac/axi_dmac_resize_dest.v
index 8a7eeb237..b185386ed 100644
--- a/library/axi_dmac/axi_dmac_resize_dest.v
+++ b/library/axi_dmac/axi_dmac_resize_dest.v
@@ -55,84 +55,84 @@ module axi_dmac_resize_dest #(
   output [DATA_WIDTH_DEST/8-1:0] dest_data_strb
 );
 
-/*
- * Resize the data width between the burst memory and the destination interface
- * if necessary.
- */
+  /*
+   * Resize the data width between the burst memory and the destination interface
+   * if necessary.
+   */
 
-generate if (DATA_WIDTH_DEST == DATA_WIDTH_MEM)  begin
-  assign dest_data_valid = mem_data_valid;
-  assign dest_data = mem_data;
-  assign dest_data_last = mem_data_last;
-  assign dest_data_strb = mem_data_strb;
-  assign mem_data_ready = dest_data_ready;
-end else begin
+  generate if (DATA_WIDTH_DEST == DATA_WIDTH_MEM)  begin
+    assign dest_data_valid = mem_data_valid;
+    assign dest_data = mem_data;
+    assign dest_data_last = mem_data_last;
+    assign dest_data_strb = mem_data_strb;
+    assign mem_data_ready = dest_data_ready;
+  end else begin
 
-  localparam RATIO = DATA_WIDTH_MEM / DATA_WIDTH_DEST;
+    localparam RATIO = DATA_WIDTH_MEM / DATA_WIDTH_DEST;
 
-  reg [$clog2(RATIO)-1:0] count = 'h0;
-  reg valid = 1'b0;
-  reg [RATIO-1:0] last = 'h0;
-  reg [DATA_WIDTH_MEM-1:0] data = 'h0;
-  reg [DATA_WIDTH_MEM/8-1:0] strb = {DATA_WIDTH_MEM/8{1'b1}};
+    reg [$clog2(RATIO)-1:0] count = 'h0;
+    reg valid = 1'b0;
+    reg [RATIO-1:0] last = 'h0;
+    reg [DATA_WIDTH_MEM-1:0] data = 'h0;
+    reg [DATA_WIDTH_MEM/8-1:0] strb = {DATA_WIDTH_MEM/8{1'b1}};
 
-  wire last_beat;
+    wire last_beat;
 
-  assign last_beat = (count == RATIO - 1) | last[0];
+    assign last_beat = (count == RATIO - 1) | last[0];
 
-  always @(posedge clk) begin
-    if (reset == 1'b1) begin
-      valid <= 1'b0;
-    end else if (mem_data_valid == 1'b1) begin
-      valid <= 1'b1;
-    end else if (last_beat == 1'b1 && dest_data_ready == 1'b1) begin
-      valid <= 1'b0;
+    always @(posedge clk) begin
+      if (reset == 1'b1) begin
+        valid <= 1'b0;
+      end else if (mem_data_valid == 1'b1) begin
+        valid <= 1'b1;
+      end else if (last_beat == 1'b1 && dest_data_ready == 1'b1) begin
+        valid <= 1'b0;
+      end
     end
-  end
 
-  always @(posedge clk) begin
-    if (reset == 1'b1) begin
-      count <= 'h0;
-    end else if (dest_data_ready == 1'b1 && dest_data_valid == 1'b1) begin
-      if (last_beat == 1'b1) begin
+    always @(posedge clk) begin
+      if (reset == 1'b1) begin
         count <= 'h0;
-      end else begin
-        count <= count + 1;
+      end else if (dest_data_ready == 1'b1 && dest_data_valid == 1'b1) begin
+        if (last_beat == 1'b1) begin
+          count <= 'h0;
+        end else begin
+          count <= count + 1;
+        end
       end
     end
-  end
 
-  assign mem_data_ready = ~valid | (dest_data_ready & last_beat);
+    assign mem_data_ready = ~valid | (dest_data_ready & last_beat);
 
-  integer i;
-  always @(posedge clk) begin
-    if (mem_data_ready == 1'b1) begin
-      data <= mem_data;
+    integer i;
+    always @(posedge clk) begin
+      if (mem_data_ready == 1'b1) begin
+        data <= mem_data;
 
-      /*
-       * Skip those words where strb would be completely zero for the output
-       * word. We assume that strb is thermometer encoded (i.e. a certain number
-       * of LSBs are 1'b1 followed by all 1'b0 in the MSBs) and by extension
-       * that if the first strb bit for a word is zero that means that all strb
-       * bits for a word will be zero.
-       */
-      for (i = 0; i < RATIO-1; i = i + 1) begin
-        last[i] <= mem_data_last & ~mem_data_strb[(i+1)*(DATA_WIDTH_MEM/8/RATIO)];
+        /*
+         * Skip those words where strb would be completely zero for the output
+         * word. We assume that strb is thermometer encoded (i.e. a certain number
+         * of LSBs are 1'b1 followed by all 1'b0 in the MSBs) and by extension
+         * that if the first strb bit for a word is zero that means that all strb
+         * bits for a word will be zero.
+         */
+        for (i = 0; i < RATIO-1; i = i + 1) begin
+          last[i] <= mem_data_last & ~mem_data_strb[(i+1)*(DATA_WIDTH_MEM/8/RATIO)];
+        end
+        last[RATIO-1] <= mem_data_last;
+        strb <= mem_data_strb;
+      end else if (dest_data_ready == 1'b1) begin
+        data[DATA_WIDTH_MEM-DATA_WIDTH_DEST-1:0] <= data[DATA_WIDTH_MEM-1:DATA_WIDTH_DEST];
+        strb[(DATA_WIDTH_MEM-DATA_WIDTH_DEST)/8-1:0] <= strb[DATA_WIDTH_MEM/8-1:DATA_WIDTH_DEST/8];
+        last[RATIO-2:0] <= last[RATIO-1:1];
       end
-      last[RATIO-1] <= mem_data_last;
-      strb <= mem_data_strb;
-    end else if (dest_data_ready == 1'b1) begin
-      data[DATA_WIDTH_MEM-DATA_WIDTH_DEST-1:0] <= data[DATA_WIDTH_MEM-1:DATA_WIDTH_DEST];
-      strb[(DATA_WIDTH_MEM-DATA_WIDTH_DEST)/8-1:0] <= strb[DATA_WIDTH_MEM/8-1:DATA_WIDTH_DEST/8];
-      last[RATIO-2:0] <= last[RATIO-1:1];
     end
-  end
 
-  assign dest_data_valid = valid;
-  assign dest_data = data[DATA_WIDTH_DEST-1:0];
-  assign dest_data_strb = strb[DATA_WIDTH_DEST/8-1:0];
-  assign dest_data_last = last[0];
+    assign dest_data_valid = valid;
+    assign dest_data = data[DATA_WIDTH_DEST-1:0];
+    assign dest_data_strb = strb[DATA_WIDTH_DEST/8-1:0];
+    assign dest_data_last = last[0];
 
-end endgenerate
+  end endgenerate
 
 endmodule
diff --git a/library/axi_dmac/axi_dmac_resize_src.v b/library/axi_dmac/axi_dmac_resize_src.v
index 3c5131a7f..09ea81be9 100644
--- a/library/axi_dmac/axi_dmac_resize_src.v
+++ b/library/axi_dmac/axi_dmac_resize_src.v
@@ -62,85 +62,85 @@ module axi_dmac_resize_src #(
   output mem_data_partial_burst
 );
 
-generate if (DATA_WIDTH_SRC == DATA_WIDTH_MEM)  begin
-  assign mem_data_valid = src_data_valid;
-  assign mem_data = src_data;
-  assign mem_data_last = src_data_last;
-  assign mem_data_valid_bytes = src_data_valid_bytes;
-  assign mem_data_partial_burst = src_data_partial_burst;
-end else begin
+  generate if (DATA_WIDTH_SRC == DATA_WIDTH_MEM)  begin
+    assign mem_data_valid = src_data_valid;
+    assign mem_data = src_data;
+    assign mem_data_last = src_data_last;
+    assign mem_data_valid_bytes = src_data_valid_bytes;
+    assign mem_data_partial_burst = src_data_partial_burst;
+  end else begin
 
-  localparam RATIO = DATA_WIDTH_MEM / DATA_WIDTH_SRC;
-  localparam RATIO_WIDTH = RATIO > 64 ? 7 :
-                           RATIO > 32 ? 6 :
-                           RATIO > 16 ? 5 :
-                           RATIO > 8 ? 4 :
-                           RATIO > 4 ? 3 :
-                           RATIO > 2 ? 2 : 1;
+    localparam RATIO = DATA_WIDTH_MEM / DATA_WIDTH_SRC;
+    localparam RATIO_WIDTH = RATIO > 64 ? 7 :
+                             RATIO > 32 ? 6 :
+                             RATIO > 16 ? 5 :
+                             RATIO > 8 ? 4 :
+                             RATIO > 4 ? 3 :
+                             RATIO > 2 ? 2 : 1;
 
-  reg [RATIO-1:0] mask = 'h1;
-  reg valid = 1'b0;
-  reg last = 1'b0;
-  reg [DATA_WIDTH_MEM-1:0] data = 'h0;
-  reg [BYTES_PER_BEAT_WIDTH_SRC-1:0] valid_bytes = 'h00;
-  reg partial_burst = 1'b0;
-  reg [RATIO_WIDTH-1:0] num_beats = {RATIO_WIDTH{1'b1}};
+    reg [RATIO-1:0] mask = 'h1;
+    reg valid = 1'b0;
+    reg last = 1'b0;
+    reg [DATA_WIDTH_MEM-1:0] data = 'h0;
+    reg [BYTES_PER_BEAT_WIDTH_SRC-1:0] valid_bytes = 'h00;
+    reg partial_burst = 1'b0;
+    reg [RATIO_WIDTH-1:0] num_beats = {RATIO_WIDTH{1'b1}};
 
-  always @(posedge clk) begin
-    if (reset == 1'b1) begin
-      valid <= 1'b0;
-      mask <= 'h1;
-    end else if (src_data_valid == 1'b1) begin
-      valid <= mask[RATIO-1] || src_data_last;
-      if (src_data_last) begin
+    always @(posedge clk) begin
+      if (reset == 1'b1) begin
+        valid <= 1'b0;
         mask <= 'h1;
+      end else if (src_data_valid == 1'b1) begin
+        valid <= mask[RATIO-1] || src_data_last;
+        if (src_data_last) begin
+          mask <= 'h1;
+        end else begin
+          mask <= {mask[RATIO-2:0],mask[RATIO-1]};
+        end
       end else begin
-        mask <= {mask[RATIO-2:0],mask[RATIO-1]};
+        valid <= 1'b0;
       end
-    end else begin
-      valid <= 1'b0;
     end
-  end
 
-  // This counter will hold the number of source beat in a destination beat
-  // minus one
-  always @(posedge clk) begin
-    if (reset == 1'b1) begin
-      num_beats <= {RATIO_WIDTH{1'b1}};
-    end else if (valid == 1'b1 && last == 1'b1) begin
-      if (src_data_valid == 1'b1) begin
-        num_beats <= {RATIO_WIDTH{1'b0}};
-      end else begin
+    // This counter will hold the number of source beat in a destination beat
+    // minus one
+    always @(posedge clk) begin
+      if (reset == 1'b1) begin
         num_beats <= {RATIO_WIDTH{1'b1}};
-      end
-    end else if (src_data_valid == 1'b1) begin
-      num_beats <= num_beats + 1'b1;
-    end
-  end
-
-  integer i;
-
-  always @(posedge clk) begin
-    for (i = 0; i < RATIO; i = i+1) begin
-      if (mask[i] == 1'b1) begin
-        data[i*DATA_WIDTH_SRC+:DATA_WIDTH_SRC] <= src_data;
+      end else if (valid == 1'b1 && last == 1'b1) begin
+        if (src_data_valid == 1'b1) begin
+          num_beats <= {RATIO_WIDTH{1'b0}};
+        end else begin
+          num_beats <= {RATIO_WIDTH{1'b1}};
+        end
+      end else if (src_data_valid == 1'b1) begin
+        num_beats <= num_beats + 1'b1;
       end
     end
 
-    // Compensate for the one clock cycle pipeline delay of the data
-    last <= src_data_last;
-    if (src_data_valid == 1'b1) begin
-      valid_bytes <= src_data_valid_bytes;
-      partial_burst <= src_data_partial_burst;
+    integer i;
+
+    always @(posedge clk) begin
+      for (i = 0; i < RATIO; i = i+1) begin
+        if (mask[i] == 1'b1) begin
+          data[i*DATA_WIDTH_SRC+:DATA_WIDTH_SRC] <= src_data;
+        end
+      end
+
+      // Compensate for the one clock cycle pipeline delay of the data
+      last <= src_data_last;
+      if (src_data_valid == 1'b1) begin
+        valid_bytes <= src_data_valid_bytes;
+        partial_burst <= src_data_partial_burst;
+      end
     end
-  end
 
-  assign mem_data_valid = valid;
-  assign mem_data = data;
-  assign mem_data_last = last;
-  assign mem_data_valid_bytes = {num_beats,valid_bytes};
-  assign mem_data_partial_burst = partial_burst;
+    assign mem_data_valid = valid;
+    assign mem_data = data;
+    assign mem_data_last = last;
+    assign mem_data_valid_bytes = {num_beats,valid_bytes};
+    assign mem_data_partial_burst = partial_burst;
 
-end endgenerate
+  end endgenerate
 
 endmodule
diff --git a/library/axi_dmac/axi_dmac_response_manager.v b/library/axi_dmac/axi_dmac_response_manager.v
index 3f1aef429..e1f478a5f 100644
--- a/library/axi_dmac/axi_dmac_response_manager.v
+++ b/library/axi_dmac/axi_dmac_response_manager.v
@@ -42,7 +42,8 @@ module axi_dmac_response_manager #(
   parameter BYTES_PER_BURST_WIDTH = 7,
   parameter BYTES_PER_BEAT_WIDTH_SRC = $clog2(DMA_DATA_WIDTH_SRC/8),
   parameter ASYNC_CLK_DEST_REQ = 1
-)(
+) (
+
   // Interface to destination side
   input dest_clk,
   input dest_resetn,
@@ -71,212 +72,211 @@ module axi_dmac_response_manager #(
   input [1:0] completion_transfer_id
 );
 
-localparam STATE_IDLE         = 3'h0;
-localparam STATE_ACC          = 3'h1;
-localparam STATE_WRITE_RESPR  = 3'h2;
-localparam STATE_ZERO_COMPL   = 3'h3;
-localparam STATE_WRITE_ZRCMPL = 3'h4;
+  localparam STATE_IDLE         = 3'h0;
+  localparam STATE_ACC          = 3'h1;
+  localparam STATE_WRITE_RESPR  = 3'h2;
+  localparam STATE_ZERO_COMPL   = 3'h3;
+  localparam STATE_WRITE_ZRCMPL = 3'h4;
 
-reg [2:0] state = STATE_IDLE;
-reg [2:0] nx_state;
+  reg [2:0] state = STATE_IDLE;
+  reg [2:0] nx_state;
 
-localparam DEST_SRC_RATIO = DMA_DATA_WIDTH_DEST/DMA_DATA_WIDTH_SRC;
+  localparam DEST_SRC_RATIO = DMA_DATA_WIDTH_DEST/DMA_DATA_WIDTH_SRC;
 
-localparam DEST_SRC_RATIO_WIDTH = DEST_SRC_RATIO > 64 ? 7 :
-  DEST_SRC_RATIO > 32 ? 6 :
-  DEST_SRC_RATIO > 16 ? 5 :
-  DEST_SRC_RATIO > 8 ? 4 :
-  DEST_SRC_RATIO > 4 ? 3 :
-  DEST_SRC_RATIO > 2 ? 2 :
-  DEST_SRC_RATIO > 1 ? 1 : 0;
+  localparam DEST_SRC_RATIO_WIDTH = DEST_SRC_RATIO > 64 ? 7 :
+    DEST_SRC_RATIO > 32 ? 6 :
+    DEST_SRC_RATIO > 16 ? 5 :
+    DEST_SRC_RATIO > 8 ? 4 :
+    DEST_SRC_RATIO > 4 ? 3 :
+    DEST_SRC_RATIO > 2 ? 2 :
+    DEST_SRC_RATIO > 1 ? 1 : 0;
 
-localparam BYTES_PER_BEAT_WIDTH = DEST_SRC_RATIO_WIDTH + BYTES_PER_BEAT_WIDTH_SRC;
-localparam BURST_LEN_WIDTH = BYTES_PER_BURST_WIDTH - BYTES_PER_BEAT_WIDTH;
+  localparam BYTES_PER_BEAT_WIDTH = DEST_SRC_RATIO_WIDTH + BYTES_PER_BEAT_WIDTH_SRC;
+  localparam BURST_LEN_WIDTH = BYTES_PER_BURST_WIDTH - BYTES_PER_BEAT_WIDTH;
 
-wire do_acc_st;
-wire do_compl;
-reg req_eot = 1'b0;
-reg req_response_partial = 1'b0;
-reg [BYTES_PER_BURST_WIDTH-1:0] req_response_dest_data_burst_length = 'h0;
+  wire do_acc_st;
+  wire do_compl;
+  reg req_eot = 1'b0;
+  reg req_response_partial = 1'b0;
+  reg [BYTES_PER_BURST_WIDTH-1:0] req_response_dest_data_burst_length = 'h0;
 
-wire response_dest_valid;
-reg response_dest_ready = 1'b1;
-wire [1:0] response_dest_resp;
-wire response_dest_resp_eot;
-wire [BYTES_PER_BURST_WIDTH-1:0] response_dest_data_burst_length;
+  wire response_dest_valid;
+  reg response_dest_ready = 1'b1;
+  wire [1:0] response_dest_resp;
+  wire response_dest_resp_eot;
+  wire [BYTES_PER_BURST_WIDTH-1:0] response_dest_data_burst_length;
 
-wire completion_req;
+  wire completion_req;
 
-reg [1:0] to_complete_count = 'h0;
-reg [1:0] transfer_id = 'h0;
-reg completion_req_last_found = 1'b0;
+  reg [1:0] to_complete_count = 'h0;
+  reg [1:0] transfer_id = 'h0;
+  reg completion_req_last_found = 1'b0;
 
-util_axis_fifo #(
-  .DATA_WIDTH(BYTES_PER_BURST_WIDTH+1+1),
-  .ADDRESS_WIDTH(0),
-  .ASYNC_CLK(ASYNC_CLK_DEST_REQ)
-) i_dest_response_fifo (
-  .s_axis_aclk(dest_clk),
-  .s_axis_aresetn(dest_resetn),
-  .s_axis_valid(dest_response_valid),
-  .s_axis_ready(dest_response_ready),
-  .s_axis_full(),
-  .s_axis_data({dest_response_data_burst_length,
-                dest_response_partial,
-                dest_response_resp_eot}),
-  .s_axis_room(),
+  util_axis_fifo #(
+    .DATA_WIDTH(BYTES_PER_BURST_WIDTH+1+1),
+    .ADDRESS_WIDTH(0),
+    .ASYNC_CLK(ASYNC_CLK_DEST_REQ)
+  ) i_dest_response_fifo (
+    .s_axis_aclk(dest_clk),
+    .s_axis_aresetn(dest_resetn),
+    .s_axis_valid(dest_response_valid),
+    .s_axis_ready(dest_response_ready),
+    .s_axis_full(),
+    .s_axis_data({dest_response_data_burst_length,
+                  dest_response_partial,
+                  dest_response_resp_eot}),
+    .s_axis_room(),
 
-  .m_axis_aclk(req_clk),
-  .m_axis_aresetn(req_resetn),
-  .m_axis_valid(response_dest_valid),
-  .m_axis_ready(response_dest_ready),
-  .m_axis_data({response_dest_data_burst_length,
-                response_dest_partial,
-                response_dest_resp_eot}),
-  .m_axis_level(),
-  .m_axis_empty()
-);
+    .m_axis_aclk(req_clk),
+    .m_axis_aresetn(req_resetn),
+    .m_axis_valid(response_dest_valid),
+    .m_axis_ready(response_dest_ready),
+    .m_axis_data({response_dest_data_burst_length,
+                  response_dest_partial,
+                  response_dest_resp_eot}),
+    .m_axis_level(),
+    .m_axis_empty());
 
-always @(posedge req_clk)
-begin
-  if (response_dest_valid & response_dest_ready) begin
-    req_eot <= response_dest_resp_eot;
-    req_response_partial <= response_dest_partial;
-    req_response_dest_data_burst_length <= response_dest_data_burst_length;
+  always @(posedge req_clk)
+  begin
+    if (response_dest_valid & response_dest_ready) begin
+      req_eot <= response_dest_resp_eot;
+      req_response_partial <= response_dest_partial;
+      req_response_dest_data_burst_length <= response_dest_data_burst_length;
+    end
   end
-end
 
-always @(posedge req_clk)
-begin
-  if (req_resetn == 1'b0) begin
-    response_dest_ready <= 1'b1;
-  end else begin
-    response_dest_ready <= (nx_state == STATE_IDLE);
+  always @(posedge req_clk)
+  begin
+    if (req_resetn == 1'b0) begin
+      response_dest_ready <= 1'b1;
+    end else begin
+      response_dest_ready <= (nx_state == STATE_IDLE);
+    end
   end
-end
 
-assign response_eot = (state == STATE_WRITE_RESPR) ? req_eot : 1'b1;
-assign response_partial = (state == STATE_WRITE_RESPR) ? req_response_partial : 1'b0;
+  assign response_eot = (state == STATE_WRITE_RESPR) ? req_eot : 1'b1;
+  assign response_partial = (state == STATE_WRITE_RESPR) ? req_response_partial : 1'b0;
 
-always @(posedge req_clk)
-begin
-  if (req_resetn == 1'b0) begin
-    response_valid <= 1'b0;
-  end else begin
-    if (nx_state == STATE_WRITE_RESPR || nx_state == STATE_WRITE_ZRCMPL) begin
-      response_valid <= 1'b1;
-    end else if (response_ready == 1'b1) begin
+  always @(posedge req_clk)
+  begin
+    if (req_resetn == 1'b0) begin
       response_valid <= 1'b0;
-    end
-  end
-end
-
-always @(posedge req_clk)
-begin
-  if (state == STATE_ZERO_COMPL) begin
-    measured_burst_length <= {BYTES_PER_BURST_WIDTH{1'b1}};
-  end else if (state == STATE_ACC) begin
-    measured_burst_length <= req_response_dest_data_burst_length;
-  end
-end
-
-always @(*) begin
-  nx_state = state;
-  case (state)
-    STATE_IDLE: begin
-      if (response_dest_valid == 1'b1) begin
-        nx_state = STATE_ACC;
-      end else if (|to_complete_count) begin
-        if (transfer_id == completion_transfer_id)
-          nx_state = STATE_ZERO_COMPL;
+    end else begin
+      if (nx_state == STATE_WRITE_RESPR || nx_state == STATE_WRITE_ZRCMPL) begin
+        response_valid <= 1'b1;
+      end else if (response_ready == 1'b1) begin
+        response_valid <= 1'b0;
       end
     end
-    STATE_ACC: begin
-      nx_state = STATE_WRITE_RESPR;
+  end
+
+  always @(posedge req_clk)
+  begin
+    if (state == STATE_ZERO_COMPL) begin
+      measured_burst_length <= {BYTES_PER_BURST_WIDTH{1'b1}};
+    end else if (state == STATE_ACC) begin
+      measured_burst_length <= req_response_dest_data_burst_length;
     end
-    STATE_WRITE_RESPR: begin
-      if (response_ready == 1'b1) begin
-        if (|to_complete_count && transfer_id == completion_transfer_id) begin
-          nx_state = STATE_ZERO_COMPL;
+  end
+
+  always @(*) begin
+    nx_state = state;
+    case (state)
+      STATE_IDLE: begin
+        if (response_dest_valid == 1'b1) begin
+          nx_state = STATE_ACC;
+        end else if (|to_complete_count) begin
+          if (transfer_id == completion_transfer_id)
+            nx_state = STATE_ZERO_COMPL;
+        end
+      end
+      STATE_ACC: begin
+        nx_state = STATE_WRITE_RESPR;
+      end
+      STATE_WRITE_RESPR: begin
+        if (response_ready == 1'b1) begin
+          if (|to_complete_count && transfer_id == completion_transfer_id) begin
+            nx_state = STATE_ZERO_COMPL;
+          end else begin
+            nx_state = STATE_IDLE;
+          end
+        end
+      end
+      STATE_ZERO_COMPL: begin
+        if (|to_complete_count) begin
+          nx_state = STATE_WRITE_ZRCMPL;
         end else begin
-          nx_state = STATE_IDLE;
+          if (completion_req_last_found == 1'b1) begin
+            nx_state = STATE_IDLE;
+          end
         end
       end
-    end
-    STATE_ZERO_COMPL: begin
-      if (|to_complete_count) begin
-        nx_state = STATE_WRITE_ZRCMPL;
-      end else begin
-        if (completion_req_last_found == 1'b1) begin
-          nx_state = STATE_IDLE;
+      STATE_WRITE_ZRCMPL:begin
+        if (response_ready == 1'b1) begin
+          nx_state = STATE_ZERO_COMPL;
         end
       end
-    end
-    STATE_WRITE_ZRCMPL:begin
-      if (response_ready == 1'b1) begin
-        nx_state = STATE_ZERO_COMPL;
+      default: begin
+        nx_state = STATE_IDLE;
       end
+    endcase
+  end
+
+  always @(posedge req_clk) begin
+    if (req_resetn == 1'b0) begin
+      state <= STATE_IDLE;
+    end else begin
+      state <= nx_state;
     end
-    default: begin
-      nx_state = STATE_IDLE;
+  end
+
+  assign do_compl = (state == STATE_WRITE_ZRCMPL) && response_ready;
+
+  // Once the last completion request from request generator is received
+  // we can wait for completions from the destination side
+  always @(posedge req_clk) begin
+    if (req_resetn == 1'b0) begin
+      completion_req_last_found <= 1'b0;
+    end else if (completion_req) begin
+      completion_req_last_found <= completion_req_last;
+    end else if (state ==STATE_ZERO_COMPL && ~(|to_complete_count)) begin
+      completion_req_last_found <= 1'b0;
     end
-  endcase
-end
-
-always @(posedge req_clk) begin
-  if (req_resetn == 1'b0) begin
-    state <= STATE_IDLE;
-  end else begin
-    state <= nx_state;
   end
-end
 
-assign do_compl = (state == STATE_WRITE_ZRCMPL) && response_ready;
-
-// Once the last completion request from request generator is received
-// we can wait for completions from the destination side
-always @(posedge req_clk) begin
-  if (req_resetn == 1'b0) begin
-    completion_req_last_found <= 1'b0;
-  end else if (completion_req) begin
-    completion_req_last_found <= completion_req_last;
-  end else if (state ==STATE_ZERO_COMPL && ~(|to_complete_count)) begin
-    completion_req_last_found <= 1'b0;
+  // Once the last completion is received wit until all completions are done
+  always @(posedge req_clk) begin
+    if (req_resetn == 1'b0) begin
+      completion_req_ready <= 1'b1;
+    end else if (completion_req_valid && completion_req_last) begin
+      completion_req_ready <= 1'b0;
+    end else if (to_complete_count == 0) begin
+      completion_req_ready <= 1'b1;
+    end
   end
-end
 
-// Once the last completion is received wit until all completions are done
-always @(posedge req_clk) begin
-  if (req_resetn == 1'b0) begin
-    completion_req_ready <= 1'b1;
-  end else if (completion_req_valid && completion_req_last) begin
-    completion_req_ready <= 1'b0;
-  end else if (to_complete_count == 0) begin
-    completion_req_ready <= 1'b1;
+  assign completion_req = completion_req_ready && completion_req_valid;
+
+  // Track transfers so we can tell when did the destination completed all its
+  // transfers
+  always @(posedge req_clk) begin
+    if (req_resetn == 1'b0) begin
+      transfer_id <= 'h0;
+    end else if ((state == STATE_ACC && req_eot) || do_compl) begin
+      transfer_id <= transfer_id + 1;
+    end
   end
-end
 
-assign completion_req = completion_req_ready && completion_req_valid;
-
-// Track transfers so we can tell when did the destination completed all its
-// transfers
-always @(posedge req_clk) begin
-  if (req_resetn == 1'b0) begin
-    transfer_id <= 'h0;
-  end else if ((state == STATE_ACC && req_eot) || do_compl) begin
-    transfer_id <= transfer_id + 1;
+  // Count how many transfers we need to complete
+  always @(posedge req_clk) begin
+    if (req_resetn == 1'b0) begin
+      to_complete_count <= 'h0;
+    end else if (completion_req & ~do_compl) begin
+      to_complete_count <= to_complete_count + 1;
+    end else if (~completion_req & do_compl) begin
+      to_complete_count <= to_complete_count - 1;
+    end
   end
-end
-
-// Count how many transfers we need to complete
-always @(posedge req_clk) begin
-  if (req_resetn == 1'b0) begin
-    to_complete_count <= 'h0;
-  end else if (completion_req & ~do_compl) begin
-    to_complete_count <= to_complete_count + 1;
-  end else if (~completion_req & do_compl) begin
-    to_complete_count <= to_complete_count - 1;
-  end
-end
 
 endmodule
diff --git a/library/axi_dmac/axi_dmac_transfer.v b/library/axi_dmac/axi_dmac_transfer.v
index 0597b6021..4f82ea29e 100644
--- a/library/axi_dmac/axi_dmac_transfer.v
+++ b/library/axi_dmac/axi_dmac_transfer.v
@@ -177,281 +177,278 @@ module axi_dmac_transfer #(
   output [7:0] dest_diag_level_bursts
 );
 
-wire dma_req_valid;
-wire dma_req_ready;
-wire [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] dma_req_dest_address;
-wire [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] dma_req_src_address;
-wire [DMA_LENGTH_WIDTH-1:0] dma_req_length;
-wire [BYTES_PER_BURST_WIDTH-1:0] dma_req_measured_burst_length;
-wire dma_req_eot;
-wire dma_response_valid;
-wire dma_response_ready;
-wire dma_response_partial;
-wire dma_req_sync_transfer_start;
-wire dma_req_last;
+  wire dma_req_valid;
+  wire dma_req_ready;
+  wire [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] dma_req_dest_address;
+  wire [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] dma_req_src_address;
+  wire [DMA_LENGTH_WIDTH-1:0] dma_req_length;
+  wire [BYTES_PER_BURST_WIDTH-1:0] dma_req_measured_burst_length;
+  wire dma_req_eot;
+  wire dma_response_valid;
+  wire dma_response_ready;
+  wire dma_response_partial;
+  wire dma_req_sync_transfer_start;
+  wire dma_req_last;
 
-wire req_clk = ctrl_clk;
-wire req_resetn;
+  wire req_clk = ctrl_clk;
+  wire req_resetn;
 
-wire req_enable;
+  wire req_enable;
 
-wire dest_clk;
-wire dest_ext_resetn;
-wire dest_resetn;
-wire dest_enable;
-wire dest_enabled;
+  wire dest_clk;
+  wire dest_ext_resetn;
+  wire dest_resetn;
+  wire dest_enable;
+  wire dest_enabled;
 
-wire src_clk;
-wire src_ext_resetn;
-wire src_resetn;
-wire src_enable;
-wire src_enabled;
+  wire src_clk;
+  wire src_ext_resetn;
+  wire src_resetn;
+  wire src_enable;
+  wire src_enabled;
 
-wire req_valid_gated;
-wire req_ready_gated;
+  wire req_valid_gated;
+  wire req_ready_gated;
 
-wire abort_req;
+  wire abort_req;
 
-axi_dmac_reset_manager #(
-  .ASYNC_CLK_REQ_SRC (ASYNC_CLK_REQ_SRC),
-  .ASYNC_CLK_SRC_DEST (ASYNC_CLK_SRC_DEST),
-  .ASYNC_CLK_DEST_REQ (ASYNC_CLK_DEST_REQ)
-) i_reset_manager (
-  .clk (ctrl_clk),
-  .resetn (ctrl_resetn),
+  axi_dmac_reset_manager #(
+    .ASYNC_CLK_REQ_SRC (ASYNC_CLK_REQ_SRC),
+    .ASYNC_CLK_SRC_DEST (ASYNC_CLK_SRC_DEST),
+    .ASYNC_CLK_DEST_REQ (ASYNC_CLK_DEST_REQ)
+  ) i_reset_manager (
+    .clk (ctrl_clk),
+    .resetn (ctrl_resetn),
 
-  .ctrl_enable (ctrl_enable),
-  .ctrl_pause (ctrl_pause),
+    .ctrl_enable (ctrl_enable),
+    .ctrl_pause (ctrl_pause),
 
-  .req_resetn (req_resetn),
-  .req_enable (req_enable),
-  .req_enabled (req_enable),
+    .req_resetn (req_resetn),
+    .req_enable (req_enable),
+    .req_enabled (req_enable),
 
-  .dest_clk (dest_clk),
-  .dest_ext_resetn (dest_ext_resetn),
-  .dest_resetn (dest_resetn),
-  .dest_enable (dest_enable),
-  .dest_enabled (dest_enabled),
+    .dest_clk (dest_clk),
+    .dest_ext_resetn (dest_ext_resetn),
+    .dest_resetn (dest_resetn),
+    .dest_enable (dest_enable),
+    .dest_enabled (dest_enabled),
 
-  .src_clk (src_clk),
-  .src_ext_resetn (src_ext_resetn),
-  .src_resetn (src_resetn),
-  .src_enable (src_enable),
-  .src_enabled (src_enabled),
+    .src_clk (src_clk),
+    .src_ext_resetn (src_ext_resetn),
+    .src_resetn (src_resetn),
+    .src_enable (src_enable),
+    .src_enabled (src_enabled),
 
-  .dbg_status (dbg_status)
-);
+    .dbg_status (dbg_status));
 
-/*
- * Things become a lot easier if we gate incoming requests in a central place
- * before they are propagated downstream. Otherwise we'd need to take special
- * care to not accidentally accept requests while the DMA is going through a
- * shutdown and reset phase.
- */
-assign req_valid_gated = req_enable & req_valid;
-assign req_ready = req_enable & req_ready_gated;
+  /*
+   * Things become a lot easier if we gate incoming requests in a central place
+   * before they are propagated downstream. Otherwise we'd need to take special
+   * care to not accidentally accept requests while the DMA is going through a
+   * shutdown and reset phase.
+   */
+  assign req_valid_gated = req_enable & req_valid;
+  assign req_ready = req_enable & req_ready_gated;
 
-generate if (DMA_2D_TRANSFER == 1) begin
+  generate if (DMA_2D_TRANSFER == 1) begin
 
-dmac_2d_transfer #(
-  .DMA_AXI_ADDR_WIDTH(DMA_AXI_ADDR_WIDTH),
-  .DMA_LENGTH_WIDTH (DMA_LENGTH_WIDTH),
-  .BYTES_PER_BURST_WIDTH (BYTES_PER_BURST_WIDTH),
-  .BYTES_PER_BEAT_WIDTH_DEST (BYTES_PER_BEAT_WIDTH_DEST),
-  .BYTES_PER_BEAT_WIDTH_SRC (BYTES_PER_BEAT_WIDTH_SRC)
-) i_2d_transfer (
-  .req_aclk (req_clk),
-  .req_aresetn (req_resetn),
+  dmac_2d_transfer #(
+    .DMA_AXI_ADDR_WIDTH(DMA_AXI_ADDR_WIDTH),
+    .DMA_LENGTH_WIDTH (DMA_LENGTH_WIDTH),
+    .BYTES_PER_BURST_WIDTH (BYTES_PER_BURST_WIDTH),
+    .BYTES_PER_BEAT_WIDTH_DEST (BYTES_PER_BEAT_WIDTH_DEST),
+    .BYTES_PER_BEAT_WIDTH_SRC (BYTES_PER_BEAT_WIDTH_SRC)
+  ) i_2d_transfer (
+    .req_aclk (req_clk),
+    .req_aresetn (req_resetn),
 
-  .req_eot (req_eot),
-  .req_measured_burst_length (req_measured_burst_length),
-  .req_response_partial (req_response_partial),
-  .req_response_valid (req_response_valid),
-  .req_response_ready (req_response_ready),
+    .req_eot (req_eot),
+    .req_measured_burst_length (req_measured_burst_length),
+    .req_response_partial (req_response_partial),
+    .req_response_valid (req_response_valid),
+    .req_response_ready (req_response_ready),
 
-  .req_valid (req_valid_gated),
-  .req_ready (req_ready_gated),
-  .req_dest_address (req_dest_address),
-  .req_src_address (req_src_address),
-  .req_x_length (req_x_length),
-  .req_y_length (req_y_length),
-  .req_dest_stride (req_dest_stride),
-  .req_src_stride (req_src_stride),
-  .req_sync_transfer_start (req_sync_transfer_start),
-  .req_last (req_last),
+    .req_valid (req_valid_gated),
+    .req_ready (req_ready_gated),
+    .req_dest_address (req_dest_address),
+    .req_src_address (req_src_address),
+    .req_x_length (req_x_length),
+    .req_y_length (req_y_length),
+    .req_dest_stride (req_dest_stride),
+    .req_src_stride (req_src_stride),
+    .req_sync_transfer_start (req_sync_transfer_start),
+    .req_last (req_last),
 
-  .out_abort_req (abort_req),
-  .out_req_valid (dma_req_valid),
-  .out_req_ready (dma_req_ready),
-  .out_req_dest_address (dma_req_dest_address),
-  .out_req_src_address (dma_req_src_address),
-  .out_req_length (dma_req_length),
-  .out_req_sync_transfer_start (dma_req_sync_transfer_start),
-  .out_req_last (dma_req_last),
-  .out_eot (dma_req_eot),
-  .out_measured_burst_length (dma_req_measured_burst_length),
-  .out_response_partial (dma_response_partial),
-  .out_response_valid (dma_response_valid),
-  .out_response_ready (dma_response_ready)
-  );
+    .out_abort_req (abort_req),
+    .out_req_valid (dma_req_valid),
+    .out_req_ready (dma_req_ready),
+    .out_req_dest_address (dma_req_dest_address),
+    .out_req_src_address (dma_req_src_address),
+    .out_req_length (dma_req_length),
+    .out_req_sync_transfer_start (dma_req_sync_transfer_start),
+    .out_req_last (dma_req_last),
+    .out_eot (dma_req_eot),
+    .out_measured_burst_length (dma_req_measured_burst_length),
+    .out_response_partial (dma_response_partial),
+    .out_response_valid (dma_response_valid),
+    .out_response_ready (dma_response_ready));
 
-end else begin
+  end else begin
 
-/* Request */
-assign dma_req_valid = req_valid_gated;
-assign req_ready_gated = dma_req_ready;
+  /* Request */
+  assign dma_req_valid = req_valid_gated;
+  assign req_ready_gated = dma_req_ready;
 
-assign dma_req_dest_address = req_dest_address;
-assign dma_req_src_address = req_src_address;
-assign dma_req_length = req_x_length;
-assign dma_req_sync_transfer_start = req_sync_transfer_start;
-assign dma_req_last = req_last;
+  assign dma_req_dest_address = req_dest_address;
+  assign dma_req_src_address = req_src_address;
+  assign dma_req_length = req_x_length;
+  assign dma_req_sync_transfer_start = req_sync_transfer_start;
+  assign dma_req_last = req_last;
 
-/* Response */
-assign req_eot = dma_req_eot;
-assign req_measured_burst_length = dma_req_measured_burst_length;
-assign req_response_partial = dma_response_partial;
-assign req_response_valid = dma_response_valid;
-assign dma_response_ready = req_response_ready;
+  /* Response */
+  assign req_eot = dma_req_eot;
+  assign req_measured_burst_length = dma_req_measured_burst_length;
+  assign req_response_partial = dma_response_partial;
+  assign req_response_valid = dma_response_valid;
+  assign dma_response_ready = req_response_ready;
 
-end endgenerate
+  end endgenerate
 
-request_arb #(
-  .DMA_DATA_WIDTH_SRC (DMA_DATA_WIDTH_SRC),
-  .DMA_DATA_WIDTH_DEST (DMA_DATA_WIDTH_DEST),
-  .DMA_LENGTH_WIDTH (DMA_LENGTH_WIDTH),
-  .DMA_LENGTH_ALIGN (DMA_LENGTH_ALIGN),
-  .BYTES_PER_BEAT_WIDTH_DEST (BYTES_PER_BEAT_WIDTH_DEST),
-  .BYTES_PER_BEAT_WIDTH_SRC (BYTES_PER_BEAT_WIDTH_SRC),
-  .DMA_TYPE_DEST (DMA_TYPE_DEST),
-  .DMA_TYPE_SRC (DMA_TYPE_SRC),
-  .DMA_AXI_ADDR_WIDTH (DMA_AXI_ADDR_WIDTH),
-  .ASYNC_CLK_REQ_SRC (ASYNC_CLK_REQ_SRC),
-  .ASYNC_CLK_SRC_DEST (ASYNC_CLK_SRC_DEST),
-  .ASYNC_CLK_DEST_REQ (ASYNC_CLK_DEST_REQ),
-  .AXI_SLICE_DEST (AXI_SLICE_DEST),
-  .AXI_SLICE_SRC (AXI_SLICE_SRC),
-  .MAX_BYTES_PER_BURST (MAX_BYTES_PER_BURST),
-  .BYTES_PER_BURST_WIDTH (BYTES_PER_BURST_WIDTH),
-  .FIFO_SIZE (FIFO_SIZE),
-  .ID_WIDTH (ID_WIDTH),
-  .AXI_LENGTH_WIDTH_DEST (AXI_LENGTH_WIDTH_DEST),
-  .AXI_LENGTH_WIDTH_SRC (AXI_LENGTH_WIDTH_SRC),
-  .ENABLE_DIAGNOSTICS_IF(ENABLE_DIAGNOSTICS_IF),
-  .ALLOW_ASYM_MEM (ALLOW_ASYM_MEM),
-  .CACHE_COHERENT_DEST(CACHE_COHERENT_DEST)
-) i_request_arb (
-  .req_clk (req_clk),
-  .req_resetn (req_resetn),
+  request_arb #(
+    .DMA_DATA_WIDTH_SRC (DMA_DATA_WIDTH_SRC),
+    .DMA_DATA_WIDTH_DEST (DMA_DATA_WIDTH_DEST),
+    .DMA_LENGTH_WIDTH (DMA_LENGTH_WIDTH),
+    .DMA_LENGTH_ALIGN (DMA_LENGTH_ALIGN),
+    .BYTES_PER_BEAT_WIDTH_DEST (BYTES_PER_BEAT_WIDTH_DEST),
+    .BYTES_PER_BEAT_WIDTH_SRC (BYTES_PER_BEAT_WIDTH_SRC),
+    .DMA_TYPE_DEST (DMA_TYPE_DEST),
+    .DMA_TYPE_SRC (DMA_TYPE_SRC),
+    .DMA_AXI_ADDR_WIDTH (DMA_AXI_ADDR_WIDTH),
+    .ASYNC_CLK_REQ_SRC (ASYNC_CLK_REQ_SRC),
+    .ASYNC_CLK_SRC_DEST (ASYNC_CLK_SRC_DEST),
+    .ASYNC_CLK_DEST_REQ (ASYNC_CLK_DEST_REQ),
+    .AXI_SLICE_DEST (AXI_SLICE_DEST),
+    .AXI_SLICE_SRC (AXI_SLICE_SRC),
+    .MAX_BYTES_PER_BURST (MAX_BYTES_PER_BURST),
+    .BYTES_PER_BURST_WIDTH (BYTES_PER_BURST_WIDTH),
+    .FIFO_SIZE (FIFO_SIZE),
+    .ID_WIDTH (ID_WIDTH),
+    .AXI_LENGTH_WIDTH_DEST (AXI_LENGTH_WIDTH_DEST),
+    .AXI_LENGTH_WIDTH_SRC (AXI_LENGTH_WIDTH_SRC),
+    .ENABLE_DIAGNOSTICS_IF(ENABLE_DIAGNOSTICS_IF),
+    .ALLOW_ASYM_MEM (ALLOW_ASYM_MEM),
+    .CACHE_COHERENT_DEST(CACHE_COHERENT_DEST)
+  ) i_request_arb (
+    .req_clk (req_clk),
+    .req_resetn (req_resetn),
 
-  .req_valid (dma_req_valid),
-  .req_ready (dma_req_ready),
-  .req_dest_address (dma_req_dest_address),
-  .req_src_address (dma_req_src_address),
-  .req_length (dma_req_length),
-  .req_xlast (dma_req_last),
-  .req_sync_transfer_start (dma_req_sync_transfer_start),
+    .req_valid (dma_req_valid),
+    .req_ready (dma_req_ready),
+    .req_dest_address (dma_req_dest_address),
+    .req_src_address (dma_req_src_address),
+    .req_length (dma_req_length),
+    .req_xlast (dma_req_last),
+    .req_sync_transfer_start (dma_req_sync_transfer_start),
 
-  .eot (dma_req_eot),
-  .measured_burst_length(dma_req_measured_burst_length),
-  .response_partial (dma_response_partial),
-  .response_valid (dma_response_valid),
-  .response_ready (dma_response_ready),
+    .eot (dma_req_eot),
+    .measured_burst_length(dma_req_measured_burst_length),
+    .response_partial (dma_response_partial),
+    .response_valid (dma_response_valid),
+    .response_ready (dma_response_ready),
 
-  .abort_req (abort_req),
+    .abort_req (abort_req),
 
-  .req_enable (req_enable),
+    .req_enable (req_enable),
 
-  .dest_clk (dest_clk),
-  .dest_ext_resetn (dest_ext_resetn),
-  .dest_resetn (dest_resetn),
-  .dest_enable (dest_enable),
-  .dest_enabled (dest_enabled),
+    .dest_clk (dest_clk),
+    .dest_ext_resetn (dest_ext_resetn),
+    .dest_resetn (dest_resetn),
+    .dest_enable (dest_enable),
+    .dest_enabled (dest_enabled),
 
-  .src_clk (src_clk),
-  .src_ext_resetn (src_ext_resetn),
-  .src_resetn (src_resetn),
-  .src_enable (src_enable),
-  .src_enabled (src_enabled),
+    .src_clk (src_clk),
+    .src_ext_resetn (src_ext_resetn),
+    .src_resetn (src_resetn),
+    .src_enable (src_enable),
+    .src_enabled (src_enabled),
 
-  .m_dest_axi_aclk (m_dest_axi_aclk),
-  .m_dest_axi_aresetn (m_dest_axi_aresetn),
-  .m_src_axi_aclk (m_src_axi_aclk),
-  .m_src_axi_aresetn (m_src_axi_aresetn),
+    .m_dest_axi_aclk (m_dest_axi_aclk),
+    .m_dest_axi_aresetn (m_dest_axi_aresetn),
+    .m_src_axi_aclk (m_src_axi_aclk),
+    .m_src_axi_aresetn (m_src_axi_aresetn),
 
-  .m_axi_awvalid (m_axi_awvalid),
-  .m_axi_awready (m_axi_awready),
-  .m_axi_awaddr (m_axi_awaddr),
-  .m_axi_awlen (m_axi_awlen),
-  .m_axi_awsize (m_axi_awsize),
-  .m_axi_awburst (m_axi_awburst),
-  .m_axi_awprot (m_axi_awprot),
-  .m_axi_awcache (m_axi_awcache),
+    .m_axi_awvalid (m_axi_awvalid),
+    .m_axi_awready (m_axi_awready),
+    .m_axi_awaddr (m_axi_awaddr),
+    .m_axi_awlen (m_axi_awlen),
+    .m_axi_awsize (m_axi_awsize),
+    .m_axi_awburst (m_axi_awburst),
+    .m_axi_awprot (m_axi_awprot),
+    .m_axi_awcache (m_axi_awcache),
 
-  .m_axi_wvalid (m_axi_wvalid),
-  .m_axi_wready (m_axi_wready),
-  .m_axi_wdata (m_axi_wdata),
-  .m_axi_wstrb (m_axi_wstrb),
-  .m_axi_wlast (m_axi_wlast),
+    .m_axi_wvalid (m_axi_wvalid),
+    .m_axi_wready (m_axi_wready),
+    .m_axi_wdata (m_axi_wdata),
+    .m_axi_wstrb (m_axi_wstrb),
+    .m_axi_wlast (m_axi_wlast),
 
-  .m_axi_bvalid (m_axi_bvalid),
-  .m_axi_bready (m_axi_bready),
-  .m_axi_bresp (m_axi_bresp),
+    .m_axi_bvalid (m_axi_bvalid),
+    .m_axi_bready (m_axi_bready),
+    .m_axi_bresp (m_axi_bresp),
 
-  .m_axi_arvalid (m_axi_arvalid),
-  .m_axi_arready (m_axi_arready),
-  .m_axi_araddr (m_axi_araddr),
-  .m_axi_arlen (m_axi_arlen),
-  .m_axi_arsize (m_axi_arsize),
-  .m_axi_arburst (m_axi_arburst),
-  .m_axi_arprot (m_axi_arprot),
-  .m_axi_arcache (m_axi_arcache),
+    .m_axi_arvalid (m_axi_arvalid),
+    .m_axi_arready (m_axi_arready),
+    .m_axi_araddr (m_axi_araddr),
+    .m_axi_arlen (m_axi_arlen),
+    .m_axi_arsize (m_axi_arsize),
+    .m_axi_arburst (m_axi_arburst),
+    .m_axi_arprot (m_axi_arprot),
+    .m_axi_arcache (m_axi_arcache),
 
-  .m_axi_rready (m_axi_rready),
-  .m_axi_rvalid (m_axi_rvalid),
-  .m_axi_rdata (m_axi_rdata),
-  .m_axi_rlast (m_axi_rlast),
-  .m_axi_rresp (m_axi_rresp),
+    .m_axi_rready (m_axi_rready),
+    .m_axi_rvalid (m_axi_rvalid),
+    .m_axi_rdata (m_axi_rdata),
+    .m_axi_rlast (m_axi_rlast),
+    .m_axi_rresp (m_axi_rresp),
 
-  .s_axis_aclk (s_axis_aclk),
-  .s_axis_ready (s_axis_ready),
-  .s_axis_valid (s_axis_valid),
-  .s_axis_data (s_axis_data),
-  .s_axis_user (s_axis_user),
-  .s_axis_last (s_axis_last),
-  .s_axis_xfer_req (s_axis_xfer_req),
+    .s_axis_aclk (s_axis_aclk),
+    .s_axis_ready (s_axis_ready),
+    .s_axis_valid (s_axis_valid),
+    .s_axis_data (s_axis_data),
+    .s_axis_user (s_axis_user),
+    .s_axis_last (s_axis_last),
+    .s_axis_xfer_req (s_axis_xfer_req),
 
-  .m_axis_aclk (m_axis_aclk),
-  .m_axis_ready (m_axis_ready),
-  .m_axis_valid (m_axis_valid),
-  .m_axis_data (m_axis_data),
-  .m_axis_last (m_axis_last),
-  .m_axis_xfer_req (m_axis_xfer_req),
+    .m_axis_aclk (m_axis_aclk),
+    .m_axis_ready (m_axis_ready),
+    .m_axis_valid (m_axis_valid),
+    .m_axis_data (m_axis_data),
+    .m_axis_last (m_axis_last),
+    .m_axis_xfer_req (m_axis_xfer_req),
 
-  .fifo_wr_clk (fifo_wr_clk),
-  .fifo_wr_en (fifo_wr_en),
-  .fifo_wr_din (fifo_wr_din),
-  .fifo_wr_overflow (fifo_wr_overflow),
-  .fifo_wr_sync (fifo_wr_sync),
-  .fifo_wr_xfer_req (fifo_wr_xfer_req),
+    .fifo_wr_clk (fifo_wr_clk),
+    .fifo_wr_en (fifo_wr_en),
+    .fifo_wr_din (fifo_wr_din),
+    .fifo_wr_overflow (fifo_wr_overflow),
+    .fifo_wr_sync (fifo_wr_sync),
+    .fifo_wr_xfer_req (fifo_wr_xfer_req),
 
-  .fifo_rd_clk (fifo_rd_clk),
-  .fifo_rd_en (fifo_rd_en),
-  .fifo_rd_valid (fifo_rd_valid),
-  .fifo_rd_dout (fifo_rd_dout),
-  .fifo_rd_underflow (fifo_rd_underflow),
-  .fifo_rd_xfer_req (fifo_rd_xfer_req),
+    .fifo_rd_clk (fifo_rd_clk),
+    .fifo_rd_en (fifo_rd_en),
+    .fifo_rd_valid (fifo_rd_valid),
+    .fifo_rd_dout (fifo_rd_dout),
+    .fifo_rd_underflow (fifo_rd_underflow),
+    .fifo_rd_xfer_req (fifo_rd_xfer_req),
 
-  .dbg_dest_request_id (dbg_dest_request_id),
-  .dbg_dest_address_id (dbg_dest_address_id),
-  .dbg_dest_data_id (dbg_dest_data_id),
-  .dbg_dest_response_id (dbg_dest_response_id),
-  .dbg_src_request_id (dbg_src_request_id),
-  .dbg_src_address_id (dbg_src_address_id),
-  .dbg_src_data_id (dbg_src_data_id),
-  .dbg_src_response_id (dbg_src_response_id),
+    .dbg_dest_request_id (dbg_dest_request_id),
+    .dbg_dest_address_id (dbg_dest_address_id),
+    .dbg_dest_data_id (dbg_dest_data_id),
+    .dbg_dest_response_id (dbg_dest_response_id),
+    .dbg_src_request_id (dbg_src_request_id),
+    .dbg_src_address_id (dbg_src_address_id),
+    .dbg_src_data_id (dbg_src_data_id),
+    .dbg_src_response_id (dbg_src_response_id),
 
-  .dest_diag_level_bursts(dest_diag_level_bursts)
-);
+    .dest_diag_level_bursts(dest_diag_level_bursts));
 
 endmodule
diff --git a/library/axi_dmac/axi_register_slice.v b/library/axi_dmac/axi_register_slice.v
index e2eea5007..d3de9a1c8 100644
--- a/library/axi_dmac/axi_register_slice.v
+++ b/library/axi_dmac/axi_register_slice.v
@@ -39,8 +39,8 @@ module axi_register_slice #(
 
   parameter DATA_WIDTH = 32,
   parameter FORWARD_REGISTERED = 0,
-  parameter BACKWARD_REGISTERED = 0)(
-
+  parameter BACKWARD_REGISTERED = 0
+) (
   input clk,
   input resetn,
 
@@ -53,87 +53,83 @@ module axi_register_slice #(
   output [DATA_WIDTH-1:0] m_axi_data
 );
 
-/*
- s_axi_data  -> bwd_data     -> fwd_data(1)  -> m_axi_data
- s_axi_valid -> bwd_valid    -> fwd_valid(1) -> m_axi_valid
- s_axi_ready <- bwd_ready(2) <- fwd_ready <- m_axi_ready
+  /*
+   s_axi_data  -> bwd_data     -> fwd_data(1)  -> m_axi_data
+   s_axi_valid -> bwd_valid    -> fwd_valid(1) -> m_axi_valid
+   s_axi_ready <- bwd_ready(2) <- fwd_ready <- m_axi_ready
 
- (1) FORWARD_REGISTERED inserts a set of FF before m_axi_data and m_axi_valid
- (2) BACKWARD_REGISTERED insters a FF before s_axi_ready
-*/
+   (1) FORWARD_REGISTERED inserts a set of FF before m_axi_data and m_axi_valid
+   (2) BACKWARD_REGISTERED insters a FF before s_axi_ready
+  */
 
-wire [DATA_WIDTH-1:0] bwd_data_s;
-wire bwd_valid_s;
-wire bwd_ready_s;
-wire [DATA_WIDTH-1:0] fwd_data_s;
-wire fwd_valid_s;
-wire fwd_ready_s;
+  wire [DATA_WIDTH-1:0] bwd_data_s;
+  wire bwd_valid_s;
+  wire bwd_ready_s;
+  wire [DATA_WIDTH-1:0] fwd_data_s;
+  wire fwd_valid_s;
+  wire fwd_ready_s;
 
-generate if (FORWARD_REGISTERED == 1) begin
+  generate if (FORWARD_REGISTERED == 1) begin
+    reg fwd_valid = 1'b0;
+    reg [DATA_WIDTH-1:0] fwd_data = 'h00;
 
-reg fwd_valid = 1'b0;
-reg [DATA_WIDTH-1:0] fwd_data = 'h00;
+    assign fwd_ready_s = ~fwd_valid | m_axi_ready;
+    assign fwd_valid_s = fwd_valid;
+    assign fwd_data_s = fwd_data;
 
-assign fwd_ready_s = ~fwd_valid | m_axi_ready;
-assign fwd_valid_s = fwd_valid;
-assign fwd_data_s = fwd_data;
+    always @(posedge clk) begin
+      if (~fwd_valid | m_axi_ready)
+        fwd_data <= bwd_data_s;
+    end
 
-always @(posedge clk) begin
-  if (~fwd_valid | m_axi_ready)
-    fwd_data <= bwd_data_s;
-end
-
-always @(posedge clk) begin
-  if (resetn == 1'b0) begin
-    fwd_valid <= 1'b0;
+    always @(posedge clk) begin
+      if (resetn == 1'b0) begin
+        fwd_valid <= 1'b0;
+      end else begin
+        if (bwd_valid_s)
+          fwd_valid <= 1'b1;
+        else if (m_axi_ready)
+          fwd_valid <= 1'b0;
+      end
+    end
   end else begin
-    if (bwd_valid_s)
-      fwd_valid <= 1'b1;
-    else if (m_axi_ready)
-      fwd_valid <= 1'b0;
+    assign fwd_data_s = bwd_data_s;
+    assign fwd_valid_s = bwd_valid_s;
+    assign fwd_ready_s = m_axi_ready;
   end
-end
+  endgenerate
 
-end else begin
-assign fwd_data_s = bwd_data_s;
-assign fwd_valid_s = bwd_valid_s;
-assign fwd_ready_s = m_axi_ready;
-end
-endgenerate
+  generate if (BACKWARD_REGISTERED == 1) begin
+    reg bwd_ready = 1'b1;
+    reg [DATA_WIDTH-1:0] bwd_data = 'h00;
 
-generate if (BACKWARD_REGISTERED == 1) begin
+    assign bwd_valid_s = ~bwd_ready | s_axi_valid;
+    assign bwd_data_s = bwd_ready ? s_axi_data : bwd_data;
+    assign bwd_ready_s = bwd_ready;
 
-reg bwd_ready = 1'b1;
-reg [DATA_WIDTH-1:0] bwd_data = 'h00;
+    always @(posedge clk) begin
+      if (bwd_ready)
+        bwd_data <= s_axi_data;
+    end
 
-assign bwd_valid_s = ~bwd_ready | s_axi_valid;
-assign bwd_data_s = bwd_ready ? s_axi_data : bwd_data;
-assign bwd_ready_s = bwd_ready;
-
-always @(posedge clk) begin
-  if (bwd_ready)
-    bwd_data <= s_axi_data;
-end
-
-always @(posedge clk) begin
-  if (resetn == 1'b0) begin
-    bwd_ready <= 1'b1;
+    always @(posedge clk) begin
+      if (resetn == 1'b0) begin
+        bwd_ready <= 1'b1;
+      end else begin
+        if (fwd_ready_s)
+          bwd_ready <= 1'b1;
+        else if (s_axi_valid)
+          bwd_ready <= 1'b0;
+      end
+    end
   end else begin
-    if (fwd_ready_s)
-      bwd_ready <= 1'b1;
-    else if (s_axi_valid)
-      bwd_ready <= 1'b0;
-  end
-end
+    assign bwd_valid_s = s_axi_valid;
+    assign bwd_data_s = s_axi_data;
+    assign bwd_ready_s = fwd_ready_s;
+  end endgenerate
 
-end else begin
-assign bwd_valid_s = s_axi_valid;
-assign bwd_data_s = s_axi_data;
-assign bwd_ready_s = fwd_ready_s;
-end endgenerate
-
-assign m_axi_data = fwd_data_s;
-assign m_axi_valid = fwd_valid_s;
-assign s_axi_ready = bwd_ready_s;
+  assign m_axi_data = fwd_data_s;
+  assign m_axi_valid = fwd_valid_s;
+  assign s_axi_ready = bwd_ready_s;
 
 endmodule
diff --git a/library/axi_dmac/data_mover.v b/library/axi_dmac/data_mover.v
index 1756e3d03..a23f16e9a 100644
--- a/library/axi_dmac/data_mover.v
+++ b/library/axi_dmac/data_mover.v
@@ -40,8 +40,8 @@ module data_mover #(
   parameter ID_WIDTH = 3,
   parameter DATA_WIDTH = 64,
   parameter BEATS_PER_BURST_WIDTH = 4,
-  parameter ALLOW_ABORT = 0) (
-
+  parameter ALLOW_ABORT = 0
+) (
   input clk,
   input resetn,
 
@@ -82,191 +82,191 @@ module data_mover #(
   input req_xlast
 );
 
-localparam BEAT_COUNTER_MAX = {BEATS_PER_BURST_WIDTH{1'b1}};
+  localparam BEAT_COUNTER_MAX = {BEATS_PER_BURST_WIDTH{1'b1}};
 
 `include "inc_id.vh"
 
-reg [BEATS_PER_BURST_WIDTH-1:0] last_burst_length = 'h00;
-reg [BEATS_PER_BURST_WIDTH-1:0] beat_counter = 'h00;
-reg [BEATS_PER_BURST_WIDTH-1:0] beat_counter_minus_one = 'h0;
-reg [ID_WIDTH-1:0] id = 'h00;
-reg [ID_WIDTH-1:0] id_next = 'h00;
+  reg [BEATS_PER_BURST_WIDTH-1:0] last_burst_length = 'h00;
+  reg [BEATS_PER_BURST_WIDTH-1:0] beat_counter = 'h00;
+  reg [BEATS_PER_BURST_WIDTH-1:0] beat_counter_minus_one = 'h0;
+  reg [ID_WIDTH-1:0] id = 'h00;
+  reg [ID_WIDTH-1:0] id_next = 'h00;
 
-reg pending_burst = 1'b0;
-reg active = 1'b0;
-reg last_eot = 1'b0;
-reg last_non_eot = 1'b0;
+  reg pending_burst = 1'b0;
+  reg active = 1'b0;
+  reg last_eot = 1'b0;
+  reg last_non_eot = 1'b0;
 
-reg needs_sync = 1'b0;
-wire has_sync = ~needs_sync | s_axi_sync;
+  reg needs_sync = 1'b0;
+  wire has_sync = ~needs_sync | s_axi_sync;
 
-wire s_axi_sync_valid = has_sync & s_axi_valid;
-wire transfer_abort_s;
+  wire s_axi_sync_valid = has_sync & s_axi_valid;
+  wire transfer_abort_s;
 
-wire last_load;
-wire last;
-wire early_tlast;
+  wire last_load;
+  wire last;
+  wire early_tlast;
 
-assign xfer_req = active;
+  assign xfer_req = active;
 
-assign response_id = id;
+  assign response_id = id;
 
-assign source_id = id;
-assign source_eot = eot || early_tlast;
+  assign source_id = id;
+  assign source_eot = eot || early_tlast;
 
-assign last = eot ? last_eot : last_non_eot;
+  assign last = eot ? last_eot : last_non_eot;
 
-assign s_axi_ready = (pending_burst & active) & ~transfer_abort_s;
-assign m_axi_valid = s_axi_sync_valid & s_axi_ready;
-assign m_axi_data = s_axi_data;
-assign m_axi_last = last || early_tlast;
-assign m_axi_partial_burst = early_tlast;
+  assign s_axi_ready = (pending_burst & active) & ~transfer_abort_s;
+  assign m_axi_valid = s_axi_sync_valid & s_axi_ready;
+  assign m_axi_data = s_axi_data;
+  assign m_axi_last = last || early_tlast;
+  assign m_axi_partial_burst = early_tlast;
 
-assign block_descr_to_dst = transfer_abort_s;
+  assign block_descr_to_dst = transfer_abort_s;
 
-generate if (ALLOW_ABORT == 1) begin
-  wire programmed_last;
+  generate if (ALLOW_ABORT == 1) begin
+    wire programmed_last;
 
-  reg transfer_abort = 1'b0;
-  reg req_xlast_d = 1'b0;
-  reg [1:0] transfer_id = 2'b0;
+    reg transfer_abort = 1'b0;
+    reg req_xlast_d = 1'b0;
+    reg [1:0] transfer_id = 2'b0;
 
-  assign programmed_last = (last == 1'b1 && eot == 1'b1 && req_xlast_d == 1'b1);
-  /*
-   * A 'last' on the external interface indicates the end of an packet. If such a
-   * 'last' indicator is observed before the end of the current transfer stop
-   * accepting data on the external interface until a new descriptor is
-   * received that is the first segment of a transfer.
-   */
-  always @(posedge clk) begin
-    if (resetn == 1'b0) begin
-      transfer_abort <= 1'b0;
-    end else if (req_valid == 1'b1 && req_ready == 1'b1 && req_xlast_d == 1'b1) begin
-      transfer_abort <= 1'b0;
-    end else if (m_axi_valid == 1'b1) begin
-      if (programmed_last == 1'b1) begin
+    assign programmed_last = (last == 1'b1 && eot == 1'b1 && req_xlast_d == 1'b1);
+    /*
+     * A 'last' on the external interface indicates the end of an packet. If such a
+     * 'last' indicator is observed before the end of the current transfer stop
+     * accepting data on the external interface until a new descriptor is
+     * received that is the first segment of a transfer.
+     */
+    always @(posedge clk) begin
+      if (resetn == 1'b0) begin
         transfer_abort <= 1'b0;
-      end else if (s_axi_last == 1'b1) begin
-        transfer_abort <= 1'b1;
+      end else if (req_valid == 1'b1 && req_ready == 1'b1 && req_xlast_d == 1'b1) begin
+        transfer_abort <= 1'b0;
+      end else if (m_axi_valid == 1'b1) begin
+        if (programmed_last == 1'b1) begin
+          transfer_abort <= 1'b0;
+        end else if (s_axi_last == 1'b1) begin
+          transfer_abort <= 1'b1;
+        end
       end
     end
-  end
 
+    always @(posedge clk) begin
+      if (req_ready == 1'b1 && req_valid == 1'b1) begin
+        req_xlast_d <= req_xlast;
+      end
+    end
+
+    assign transfer_abort_s = transfer_abort;
+    assign early_tlast = (s_axi_ready == 1'b1) && (m_axi_valid == 1'b1) &&
+                         (s_axi_last == 1'b1) && (programmed_last == 1'b0);
+
+    assign rewind_req_valid = early_tlast;
+    assign rewind_req_data = {transfer_id,req_xlast_d,id_next};
+
+    // The width of the id must fit the number of transfers that can be in flight
+    // in the burst memory
+    always @(posedge clk) begin
+      if (resetn == 1'b0) begin
+        transfer_id <= 2'b0;
+      end else if (req_valid == 1'b1 && req_ready == 1'b1) begin
+        transfer_id <= transfer_id + 1'b1;
+      end
+    end
+
+  end else begin
+    assign transfer_abort_s = 1'b0;
+    assign early_tlast = 1'b0;
+    assign rewind_req_valid = 1'b0;
+    assign rewind_req_data = 'h0;
+  end endgenerate
+
+  /*
+   * If req_sync_transfer_start is set all incoming beats will be skipped until
+   * one has s_axi_sync set. This will be the first beat that is passsed through.
+   */
   always @(posedge clk) begin
-    if (req_ready == 1'b1 && req_valid == 1'b1) begin
-      req_xlast_d <= req_xlast;
+    if (req_ready == 1'b1) begin
+      needs_sync <= req_sync_transfer_start;
+    end else if (m_axi_valid == 1'b1) begin
+      needs_sync <= 1'b0;
     end
   end
 
-  assign transfer_abort_s = transfer_abort;
-  assign early_tlast = (s_axi_ready == 1'b1) && (m_axi_valid == 1'b1) &&
-                       (s_axi_last == 1'b1) && (programmed_last == 1'b0);
+  // If we want to support zero delay between transfers we have to assert
+  // req_ready on the same cycle on which the last load happens.
+  // In case early tlast happens accept the new descriptor only when the rewind
+  // request got accepted.
+  // In case the data mover is not active accept a new descriptor only when the
+  // upstream logic incremented its id (pending_burst is set).
+  assign last_load = m_axi_valid && last_eot && eot;
+  assign req_ready = (last_load && ~early_tlast) ||
+                     ((~active && ~transfer_abort_s) && pending_burst) ||
+                     (transfer_abort_s && rewind_req_ready);
 
-  assign rewind_req_valid = early_tlast;
-  assign rewind_req_data = {transfer_id,req_xlast_d,id_next};
+  always @(posedge clk) begin
+    if (req_ready) begin
+      last_eot <= req_last_burst_length == 'h0;
+      last_non_eot <= 1'b0;
+      beat_counter <= 'h1;
+    end else if (m_axi_valid == 1'b1) begin
+      last_eot <= beat_counter == last_burst_length;
+      last_non_eot <= beat_counter == BEAT_COUNTER_MAX;
+      beat_counter <= beat_counter + 1'b1;
+    end
+  end
+
+  always @(posedge clk) begin
+    if (req_ready)
+      last_burst_length <= req_last_burst_length;
+  end
+
+  always @(posedge clk) begin
+    if (req_ready) begin
+      beat_counter_minus_one <= 'h0;
+    end else if (m_axi_valid == 1'b1) begin
+      beat_counter_minus_one <= beat_counter;
+    end
+  end
+
+  always @(posedge clk) begin
+    if (last_load || early_tlast) begin
+      bl_valid <= 1'b1;
+      measured_last_burst_length <= beat_counter_minus_one;
+    end else if (bl_ready) begin
+      bl_valid <= 1'b0;
+    end
+  end
 
-  // The width of the id must fit the number of transfers that can be in flight
-  // in the burst memory
   always @(posedge clk) begin
     if (resetn == 1'b0) begin
-      transfer_id <= 2'b0;
+      active <= 1'b0;
     end else if (req_valid == 1'b1 && req_ready == 1'b1) begin
-      transfer_id <= transfer_id + 1'b1;
+      active <= 1'b1;
+    end else if (last_load == 1'b1) begin
+      active <= 1'b0;
     end
   end
 
-end else begin
-  assign transfer_abort_s = 1'b0;
-  assign early_tlast = 1'b0;
-  assign rewind_req_valid = 1'b0;
-  assign rewind_req_data = 'h0;
-end endgenerate
-
-/*
- * If req_sync_transfer_start is set all incoming beats will be skipped until
- * one has s_axi_sync set. This will be the first beat that is passsed through.
- */
-always @(posedge clk) begin
-  if (req_ready == 1'b1) begin
-    needs_sync <= req_sync_transfer_start;
-  end else if (m_axi_valid == 1'b1) begin
-    needs_sync <= 1'b0;
+  always @(*)
+  begin
+    if (m_axi_valid == 1'b1 && (last == 1'b1 || early_tlast == 1'b1))
+      id_next <= inc_id(id);
+    else
+      id_next <= id;
   end
-end
 
-// If we want to support zero delay between transfers we have to assert
-// req_ready on the same cycle on which the last load happens.
-// In case early tlast happens accept the new descriptor only when the rewind
-// request got accepted.
-// In case the data mover is not active accept a new descriptor only when the
-// upstream logic incremented its id (pending_burst is set).
-assign last_load = m_axi_valid && last_eot && eot;
-assign req_ready = (last_load && ~early_tlast) ||
-                   ((~active && ~transfer_abort_s) && pending_burst) ||
-                   (transfer_abort_s && rewind_req_ready);
-
-always @(posedge clk) begin
-  if (req_ready) begin
-    last_eot <= req_last_burst_length == 'h0;
-    last_non_eot <= 1'b0;
-    beat_counter <= 'h1;
-  end else if (m_axi_valid == 1'b1) begin
-    last_eot <= beat_counter == last_burst_length;
-    last_non_eot <= beat_counter == BEAT_COUNTER_MAX;
-    beat_counter <= beat_counter + 1'b1;
+  always @(posedge clk) begin
+    if (resetn == 1'b0) begin
+      id <= 'h0;
+    end else begin
+      id <= id_next;
+    end
   end
-end
 
-always @(posedge clk) begin
-  if (req_ready)
-    last_burst_length <= req_last_burst_length;
-end
-
-always @(posedge clk) begin
-  if (req_ready) begin
-    beat_counter_minus_one <= 'h0;
-  end else if (m_axi_valid == 1'b1) begin
-    beat_counter_minus_one <= beat_counter;
+  always @(posedge clk) begin
+    pending_burst <= id_next != request_id;
   end
-end
-
-always @(posedge clk) begin
-  if (last_load || early_tlast) begin
-    bl_valid <= 1'b1;
-    measured_last_burst_length <= beat_counter_minus_one;
-  end else if (bl_ready) begin
-    bl_valid <= 1'b0;
-  end
-end
-
-always @(posedge clk) begin
-  if (resetn == 1'b0) begin
-    active <= 1'b0;
-  end else if (req_valid == 1'b1 && req_ready == 1'b1) begin
-    active <= 1'b1;
-  end else if (last_load == 1'b1) begin
-    active <= 1'b0;
-  end
-end
-
-always @(*)
-begin
-  if (m_axi_valid == 1'b1 && (last == 1'b1 || early_tlast == 1'b1))
-    id_next <= inc_id(id);
-  else
-    id_next <= id;
-end
-
-always @(posedge clk) begin
-  if (resetn == 1'b0) begin
-    id <= 'h0;
-  end else begin
-    id <= id_next;
-  end
-end
-
-always @(posedge clk) begin
-  pending_burst <= id_next != request_id;
-end
 
 endmodule
diff --git a/library/axi_dmac/dest_axi_mm.v b/library/axi_dmac/dest_axi_mm.v
index c52ad9852..f162d48ad 100644
--- a/library/axi_dmac/dest_axi_mm.v
+++ b/library/axi_dmac/dest_axi_mm.v
@@ -45,8 +45,8 @@ module dest_axi_mm #(
   parameter MAX_BYTES_PER_BURST = 128,
   parameter BYTES_PER_BURST_WIDTH = $clog2(MAX_BYTES_PER_BURST),
   parameter AXI_LENGTH_WIDTH = 8,
-  parameter CACHE_COHERENT = 0)(
-
+  parameter CACHE_COHERENT = 0
+) (
   input                               m_axi_aclk,
   input                               m_axi_aresetn,
 
@@ -108,86 +108,83 @@ module dest_axi_mm #(
   output                              m_axi_bready
 );
 
-wire address_enabled;
+  wire address_enabled;
 
-address_generator #(
-  .ID_WIDTH(ID_WIDTH),
-  .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH),
-  .BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH),
-  .DMA_DATA_WIDTH(DMA_DATA_WIDTH),
-  .LENGTH_WIDTH(AXI_LENGTH_WIDTH),
-  .DMA_ADDR_WIDTH(DMA_ADDR_WIDTH),
-  .CACHE_COHERENT(CACHE_COHERENT)
-) i_addr_gen (
-  .clk(m_axi_aclk),
-  .resetn(m_axi_aresetn),
+  address_generator #(
+    .ID_WIDTH(ID_WIDTH),
+    .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH),
+    .BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH),
+    .DMA_DATA_WIDTH(DMA_DATA_WIDTH),
+    .LENGTH_WIDTH(AXI_LENGTH_WIDTH),
+    .DMA_ADDR_WIDTH(DMA_ADDR_WIDTH),
+    .CACHE_COHERENT(CACHE_COHERENT)
+  ) i_addr_gen (
+    .clk(m_axi_aclk),
+    .resetn(m_axi_aresetn),
 
-  .enable(enable),
-  .enabled(address_enabled),
+    .enable(enable),
+    .enabled(address_enabled),
 
-  .id(address_id),
-  .request_id(request_id),
+    .id(address_id),
+    .request_id(request_id),
 
-  .req_valid(req_valid),
-  .req_ready(req_ready),
-  .req_address(req_address),
+    .req_valid(req_valid),
+    .req_ready(req_ready),
+    .req_address(req_address),
 
-  .bl_valid(bl_valid),
-  .bl_ready(bl_ready),
-  .measured_last_burst_length(measured_last_burst_length),
+    .bl_valid(bl_valid),
+    .bl_ready(bl_ready),
+    .measured_last_burst_length(measured_last_burst_length),
 
-  .eot(address_eot),
+    .eot(address_eot),
 
-  .addr_ready(m_axi_awready),
-  .addr_valid(m_axi_awvalid),
-  .addr(m_axi_awaddr),
-  .len(m_axi_awlen),
-  .size(m_axi_awsize),
-  .burst(m_axi_awburst),
-  .prot(m_axi_awprot),
-  .cache(m_axi_awcache)
-);
+    .addr_ready(m_axi_awready),
+    .addr_valid(m_axi_awvalid),
+    .addr(m_axi_awaddr),
+    .len(m_axi_awlen),
+    .size(m_axi_awsize),
+    .burst(m_axi_awburst),
+    .prot(m_axi_awprot),
+    .cache(m_axi_awcache));
 
-assign m_axi_wvalid = fifo_valid;
-assign fifo_ready = m_axi_wready;
-assign m_axi_wlast = fifo_last;
-assign m_axi_wdata = fifo_data;
-assign m_axi_wstrb = fifo_strb;
+  assign m_axi_wvalid = fifo_valid;
+  assign fifo_ready = m_axi_wready;
+  assign m_axi_wlast = fifo_last;
+  assign m_axi_wdata = fifo_data;
+  assign m_axi_wstrb = fifo_strb;
 
-response_handler #(
-  .ID_WIDTH(ID_WIDTH)
-) i_response_handler (
-  .clk(m_axi_aclk),
-  .resetn(m_axi_aresetn),
-  .bvalid(m_axi_bvalid),
-  .bready(m_axi_bready),
-  .bresp(m_axi_bresp),
+  response_handler #(
+    .ID_WIDTH(ID_WIDTH)
+  ) i_response_handler (
+    .clk(m_axi_aclk),
+    .resetn(m_axi_aresetn),
+    .bvalid(m_axi_bvalid),
+    .bready(m_axi_bready),
+    .bresp(m_axi_bresp),
 
-  .enable(address_enabled),
-  .enabled(enabled),
+    .enable(address_enabled),
+    .enabled(enabled),
 
-  .id(response_id),
-  .request_id(address_id),
+    .id(response_id),
+    .request_id(address_id),
 
-  .eot(response_eot),
+    .eot(response_eot),
 
-  .resp_valid(response_valid),
-  .resp_ready(response_ready),
-  .resp_resp(response_resp),
-  .resp_eot(response_resp_eot)
-);
+    .resp_valid(response_valid),
+    .resp_ready(response_ready),
+    .resp_resp(response_resp),
+    .resp_eot(response_resp_eot));
 
-reg [BYTES_PER_BURST_WIDTH+1-1:0] bl_mem [0:2**(ID_WIDTH)-1];
+  reg [BYTES_PER_BURST_WIDTH+1-1:0] bl_mem [0:2**(ID_WIDTH)-1];
 
-assign {response_resp_partial,
-        response_data_burst_length} = bl_mem[response_id];
+  assign {response_resp_partial,
+          response_data_burst_length} = bl_mem[response_id];
 
-always @(posedge m_axi_aclk) begin
-  if (dest_burst_info_write) begin
-    bl_mem[dest_burst_info_id] <= {dest_burst_info_partial,
-                                   dest_burst_info_length};
+  always @(posedge m_axi_aclk) begin
+    if (dest_burst_info_write) begin
+      bl_mem[dest_burst_info_id] <= {dest_burst_info_partial,
+                                     dest_burst_info_length};
+    end
   end
-end
-
 
 endmodule
diff --git a/library/axi_dmac/dest_axi_stream.v b/library/axi_dmac/dest_axi_stream.v
index f65cbd311..508e9ad1c 100644
--- a/library/axi_dmac/dest_axi_stream.v
+++ b/library/axi_dmac/dest_axi_stream.v
@@ -39,8 +39,8 @@ module dest_axi_stream #(
 
   parameter ID_WIDTH = 3,
   parameter S_AXIS_DATA_WIDTH = 64,
-  parameter BEATS_PER_BURST_WIDTH = 4)(
-
+  parameter BEATS_PER_BURST_WIDTH = 4
+) (
   input s_axis_aclk,
   input s_axis_aresetn,
 
@@ -75,82 +75,81 @@ module dest_axi_stream #(
 
 `include "inc_id.vh"
 
-reg data_enabled = 1'b0;
-reg req_xlast_d = 1'b0;
-reg active = 1'b0;
+  reg data_enabled = 1'b0;
+  reg req_xlast_d = 1'b0;
+  reg active = 1'b0;
 
-reg [ID_WIDTH-1:0] id = 'h0;
+  reg [ID_WIDTH-1:0] id = 'h0;
 
-/* Last beat of the burst */
-wire fifo_last_beat;
-/* Last beat of the segment */
-wire fifo_eot_beat;
+  // Last beat of the burst
+  wire fifo_last_beat;
+  // Last beat of the segment
+  wire fifo_eot_beat;
 
-/* fifo_last == 1'b1 implies fifo_valid == 1'b1 */
-assign fifo_last_beat = fifo_ready & fifo_last;
-assign fifo_eot_beat = fifo_last_beat & data_eot;
+  // fifo_last == 1'b1 implies fifo_valid == 1'b1
+  assign fifo_last_beat = fifo_ready & fifo_last;
+  assign fifo_eot_beat = fifo_last_beat & data_eot;
 
-assign req_ready = fifo_eot_beat | ~active;
-assign data_id = id;
-assign xfer_req = active;
+  assign req_ready = fifo_eot_beat | ~active;
+  assign data_id = id;
+  assign xfer_req = active;
 
-assign m_axis_valid = fifo_valid & active;
-assign fifo_ready = m_axis_ready & active;
-assign m_axis_last = req_xlast_d & fifo_last & data_eot;
-assign m_axis_data = fifo_data;
+  assign m_axis_valid = fifo_valid & active;
+  assign fifo_ready = m_axis_ready & active;
+  assign m_axis_last = req_xlast_d & fifo_last & data_eot;
+  assign m_axis_data = fifo_data;
 
-always @(posedge s_axis_aclk) begin
-  if (s_axis_aresetn == 1'b0) begin
-    data_enabled <= 1'b0;
-  end else if (enable == 1'b1) begin
-    data_enabled <= 1'b1;
-  end else if (m_axis_valid == 1'b0 || m_axis_ready == 1'b1) begin
-    data_enabled <= 1'b0;
+  always @(posedge s_axis_aclk) begin
+    if (s_axis_aresetn == 1'b0) begin
+      data_enabled <= 1'b0;
+    end else if (enable == 1'b1) begin
+      data_enabled <= 1'b1;
+    end else if (m_axis_valid == 1'b0 || m_axis_ready == 1'b1) begin
+      data_enabled <= 1'b0;
+    end
   end
-end
 
-always @(posedge s_axis_aclk) begin
-  if (req_ready == 1'b1) begin
-    req_xlast_d <= req_xlast;
+  always @(posedge s_axis_aclk) begin
+    if (req_ready == 1'b1) begin
+      req_xlast_d <= req_xlast;
+    end
   end
-end
 
-always @(posedge s_axis_aclk) begin
-  if (s_axis_aresetn == 1'b0) begin
-    active <= 1'b0;
-  end else if (req_valid == 1'b1) begin
-    active <= 1'b1;
-  end else if (fifo_eot_beat == 1'b1) begin
-    active <= 1'b0;
+  always @(posedge s_axis_aclk) begin
+    if (s_axis_aresetn == 1'b0) begin
+      active <= 1'b0;
+    end else if (req_valid == 1'b1) begin
+      active <= 1'b1;
+    end else if (fifo_eot_beat == 1'b1) begin
+      active <= 1'b0;
+    end
   end
-end
 
-always @(posedge s_axis_aclk) begin
-  if (s_axis_aresetn == 1'b0) begin
-    id <= 'h00;
-  end else if (fifo_last_beat == 1'b1) begin
-    id <= inc_id(id);
+  always @(posedge s_axis_aclk) begin
+    if (s_axis_aresetn == 1'b0) begin
+      id <= 'h00;
+    end else if (fifo_last_beat == 1'b1) begin
+      id <= inc_id(id);
+    end
   end
-end
 
-response_generator # (
-  .ID_WIDTH(ID_WIDTH)
-) i_response_generator (
-  .clk(s_axis_aclk),
-  .resetn(s_axis_aresetn),
+  response_generator #(
+    .ID_WIDTH(ID_WIDTH)
+  ) i_response_generator (
+    .clk(s_axis_aclk),
+    .resetn(s_axis_aresetn),
 
-  .enable(data_enabled),
-  .enabled(enabled),
+    .enable(data_enabled),
+    .enabled(enabled),
 
-  .request_id(id),
-  .response_id(response_id),
+    .request_id(id),
+    .response_id(response_id),
 
-  .eot(response_eot),
+    .eot(response_eot),
 
-  .resp_valid(response_valid),
-  .resp_ready(response_ready),
-  .resp_eot(response_resp_eot),
-  .resp_resp(response_resp)
-);
+    .resp_valid(response_valid),
+    .resp_ready(response_ready),
+    .resp_eot(response_resp_eot),
+    .resp_resp(response_resp));
 
 endmodule
diff --git a/library/axi_dmac/dest_fifo_inf.v b/library/axi_dmac/dest_fifo_inf.v
index 2986aa93a..fe2a74758 100644
--- a/library/axi_dmac/dest_fifo_inf.v
+++ b/library/axi_dmac/dest_fifo_inf.v
@@ -39,8 +39,8 @@ module dest_fifo_inf #(
 
   parameter ID_WIDTH = 3,
   parameter DATA_WIDTH = 64,
-  parameter BEATS_PER_BURST_WIDTH = 4)(
-
+  parameter BEATS_PER_BURST_WIDTH = 4
+) (
   input clk,
   input resetn,
 
@@ -75,70 +75,69 @@ module dest_fifo_inf #(
 
 `include "inc_id.vh"
 
-reg active = 1'b0;
+  reg active = 1'b0;
 
-/* Last beat of the burst */
-wire fifo_last_beat;
-/* Last beat of the segment */
-wire fifo_eot_beat;
+  // Last beat of the burst
+  wire fifo_last_beat;
+  // Last beat of the segment
+  wire fifo_eot_beat;
 
-assign enabled = enable;
-assign fifo_ready = en & (fifo_valid | ~enable);
+  assign enabled = enable;
+  assign fifo_ready = en & (fifo_valid | ~enable);
 
-/* fifo_last == 1'b1 implies fifo_valid == 1'b1 */
-assign fifo_last_beat = fifo_ready & fifo_last;
-assign fifo_eot_beat = fifo_last_beat & data_eot;
+  // fifo_last == 1'b1 implies fifo_valid == 1'b1
+  assign fifo_last_beat = fifo_ready & fifo_last;
+  assign fifo_eot_beat = fifo_last_beat & data_eot;
 
-assign req_ready = fifo_eot_beat | ~active;
-assign xfer_req = active;
+  assign req_ready = fifo_eot_beat | ~active;
+  assign xfer_req = active;
 
-always @(posedge clk) begin
-  if (en) begin
-    dout <= fifo_valid ? fifo_data : {DATA_WIDTH{1'b0}};
-    valid <= fifo_valid & enable;
-    underflow <= ~(fifo_valid & enable);
-  end else begin
-    valid <= 1'b0;
-    underflow <= 1'b0;
+  always @(posedge clk) begin
+    if (en) begin
+      dout <= fifo_valid ? fifo_data : {DATA_WIDTH{1'b0}};
+      valid <= fifo_valid & enable;
+      underflow <= ~(fifo_valid & enable);
+    end else begin
+      valid <= 1'b0;
+      underflow <= 1'b0;
+    end
   end
-end
 
-always @(posedge clk) begin
-  if (resetn == 1'b0) begin
-    data_id <= 'h00;
-  end else if (fifo_last_beat == 1'b1) begin
-    data_id <= inc_id(data_id);
+  always @(posedge clk) begin
+    if (resetn == 1'b0) begin
+      data_id <= 'h00;
+    end else if (fifo_last_beat == 1'b1) begin
+      data_id <= inc_id(data_id);
+    end
   end
-end
 
-always @(posedge clk) begin
-  if (resetn == 1'b0) begin
-    active <= 1'b0;
-  end else if (req_valid == 1'b1) begin
-    active <= 1'b1;
-  end else if (fifo_eot_beat == 1'b1) begin
-    active <= 1'b0;
+  always @(posedge clk) begin
+    if (resetn == 1'b0) begin
+      active <= 1'b0;
+    end else if (req_valid == 1'b1) begin
+      active <= 1'b1;
+    end else if (fifo_eot_beat == 1'b1) begin
+      active <= 1'b0;
+    end
   end
-end
 
-response_generator # (
-  .ID_WIDTH(ID_WIDTH)
-) i_response_generator (
-  .clk(clk),
-  .resetn(resetn),
+  response_generator #(
+    .ID_WIDTH(ID_WIDTH)
+  ) i_response_generator (
+    .clk(clk),
+    .resetn(resetn),
 
-  .enable(enable),
-  .enabled(),
+    .enable(enable),
+    .enabled(),
 
-  .request_id(data_id),
-  .response_id(response_id),
+    .request_id(data_id),
+    .response_id(response_id),
 
-  .eot(response_eot),
+    .eot(response_eot),
 
-  .resp_valid(response_valid),
-  .resp_ready(response_ready),
-  .resp_eot(response_resp_eot),
-  .resp_resp(response_resp)
-);
+    .resp_valid(response_valid),
+    .resp_ready(response_ready),
+    .resp_eot(response_resp_eot),
+    .resp_resp(response_resp));
 
 endmodule
diff --git a/library/axi_dmac/dmac_2d_transfer.v b/library/axi_dmac/dmac_2d_transfer.v
index e81b8199e..d3bf81638 100644
--- a/library/axi_dmac/dmac_2d_transfer.v
+++ b/library/axi_dmac/dmac_2d_transfer.v
@@ -41,8 +41,8 @@ module dmac_2d_transfer #(
   parameter DMA_LENGTH_WIDTH = 24,
   parameter BYTES_PER_BURST_WIDTH = 7,
   parameter BYTES_PER_BEAT_WIDTH_SRC = 3,
-  parameter BYTES_PER_BEAT_WIDTH_DEST = 3) (
-
+  parameter BYTES_PER_BEAT_WIDTH_DEST = 3
+) (
   input req_aclk,
   input req_aresetn,
 
@@ -78,7 +78,8 @@ module dmac_2d_transfer #(
   input [BYTES_PER_BURST_WIDTH-1:0] out_measured_burst_length,
   input out_response_partial,
   input out_response_valid,
-  output reg out_response_ready = 1'b1);
+  output reg out_response_ready = 1'b1
+);
 
   // internal registers
 
diff --git a/library/axi_dmac/request_arb.v b/library/axi_dmac/request_arb.v
index 1c26619f0..c0eb6d40c 100644
--- a/library/axi_dmac/request_arb.v
+++ b/library/axi_dmac/request_arb.v
@@ -59,7 +59,7 @@ module request_arb #(
   parameter ENABLE_DIAGNOSTICS_IF = 0,
   parameter ALLOW_ASYM_MEM = 0,
   parameter CACHE_COHERENT_DEST = 0
-)(
+) (
   input req_clk,
   input req_resetn,
 
@@ -184,1019 +184,989 @@ module request_arb #(
   output  [7:0] dest_diag_level_bursts
 );
 
-localparam DMA_TYPE_MM_AXI = 0;
-localparam DMA_TYPE_STREAM_AXI = 1;
-localparam DMA_TYPE_FIFO = 2;
-
-localparam DMA_ADDRESS_WIDTH_DEST = DMA_AXI_ADDR_WIDTH - BYTES_PER_BEAT_WIDTH_DEST;
-localparam DMA_ADDRESS_WIDTH_SRC = DMA_AXI_ADDR_WIDTH - BYTES_PER_BEAT_WIDTH_SRC;
-
-// Bytes per burst is the same for both dest and src, but bytes per beat may
-// differ, so beats per burst may also differ
-
-localparam BEATS_PER_BURST_WIDTH_SRC = BYTES_PER_BURST_WIDTH - BYTES_PER_BEAT_WIDTH_SRC;
-localparam BEATS_PER_BURST_WIDTH_DEST = BYTES_PER_BURST_WIDTH - BYTES_PER_BEAT_WIDTH_DEST;
-
-localparam BURSTS_PER_TRANSFER_WIDTH = DMA_LENGTH_WIDTH - BYTES_PER_BURST_WIDTH;
-
-
-reg eot_mem_src[0:2**ID_WIDTH-1];
-reg eot_mem_dest[0:2**ID_WIDTH-1];
-wire request_eot;
-wire source_eot;
-
-wire [ID_WIDTH-1:0] request_id;
-wire [ID_WIDTH-1:0] source_id;
-wire [ID_WIDTH-1:0] response_id;
-
-wire enabled_src;
-wire enabled_dest;
-
-wire req_gen_valid;
-wire req_gen_ready;
-wire src_dest_valid;
-wire src_dest_ready;
-wire req_src_valid;
-wire req_src_ready;
-
-wire dest_req_valid;
-wire dest_req_ready;
-wire [DMA_ADDRESS_WIDTH_DEST-1:0] dest_req_dest_address;
-wire dest_req_xlast;
-
-wire dest_response_valid;
-wire dest_response_ready;
-wire [1:0] dest_response_resp;
-wire dest_response_resp_eot;
-wire [BYTES_PER_BURST_WIDTH-1:0] dest_response_data_burst_length;
-wire dest_response_partial;
-
-wire [ID_WIDTH-1:0] dest_request_id;
-wire [ID_WIDTH-1:0] dest_data_request_id;
-wire [ID_WIDTH-1:0] dest_data_response_id;
-wire [ID_WIDTH-1:0] dest_response_id;
-
-wire dest_valid;
-wire dest_ready;
-wire [DMA_DATA_WIDTH_DEST-1:0] dest_data;
-wire [DMA_DATA_WIDTH_DEST/8-1:0] dest_strb;
-wire dest_last;
-wire dest_fifo_valid;
-wire dest_fifo_ready;
-wire [DMA_DATA_WIDTH_DEST-1:0] dest_fifo_data;
-wire [DMA_DATA_WIDTH_DEST/8-1:0] dest_fifo_strb;
-wire dest_fifo_last;
-
-wire src_req_valid;
-wire src_req_ready;
-wire [DMA_ADDRESS_WIDTH_DEST-1:0] src_req_dest_address;
-wire [DMA_ADDRESS_WIDTH_SRC-1:0] src_req_src_address;
-wire [BEATS_PER_BURST_WIDTH_SRC-1:0] src_req_last_burst_length;
-wire [BYTES_PER_BEAT_WIDTH_SRC-1:0] src_req_last_beat_bytes;
-wire src_req_sync_transfer_start;
-wire src_req_xlast;
-
-reg [DMA_ADDRESS_WIDTH_DEST-1:0] src_req_dest_address_cur = 'h0;
-reg src_req_xlast_cur = 1'b0;
-
-/* TODO
-wire src_response_valid;
-wire src_response_ready;
-wire src_response_empty;
-wire [1:0] src_response_resp;
-*/
-
-wire [ID_WIDTH-1:0] src_request_id;
-reg [ID_WIDTH-1:0] src_throttled_request_id;
-wire [ID_WIDTH-1:0] src_data_request_id;
-wire [ID_WIDTH-1:0] src_response_id;
-
-wire src_valid;
-wire [DMA_DATA_WIDTH_SRC-1:0] src_data;
-wire [BYTES_PER_BEAT_WIDTH_SRC-1:0] src_valid_bytes;
-wire src_last;
-wire src_partial_burst;
-wire block_descr_to_dst;
-wire src_fifo_valid;
-wire [DMA_DATA_WIDTH_SRC-1:0] src_fifo_data;
-wire [BYTES_PER_BEAT_WIDTH_SRC-1:0] src_fifo_valid_bytes;
-wire src_fifo_last;
-wire src_fifo_partial_burst;
-
-wire                                 src_bl_valid;
-wire                                 src_bl_ready;
-wire [BEATS_PER_BURST_WIDTH_SRC-1:0] src_burst_length;
-
-wire [BYTES_PER_BURST_WIDTH-1:0] dest_burst_info_length;
-wire                             dest_burst_info_partial;
-wire [ID_WIDTH-1:0] dest_burst_info_id;
-wire                dest_burst_info_write;
-
-reg src_dest_valid_hs = 1'b0;
-wire src_dest_valid_hs_masked;
-wire src_dest_ready_hs;
-
-wire req_rewind_req_valid;
-wire req_rewind_req_ready;
-wire [ID_WIDTH+3-1:0] req_rewind_req_data;
-
-wire completion_req_valid;
-wire completion_req_ready;
-wire completion_req_last;
-wire [1:0] completion_transfer_id;
-
-wire rewind_req_valid;
-wire rewind_req_ready;
-wire [ID_WIDTH+3-1:0] rewind_req_data;
-
-reg src_throttler_enabled = 1'b1;
-wire src_throttler_enable;
-wire rewind_state;
-
-/* Unused for now
-wire response_src_valid;
-wire response_src_ready = 1'b1;
-wire [1:0] response_src_resp;
-*/
-
-assign dbg_dest_request_id = dest_request_id;
-assign dbg_dest_response_id = dest_response_id;
-assign dbg_src_request_id = src_request_id;
-assign dbg_src_response_id = src_response_id;
-
-always @(posedge req_clk)
-begin
-  eot_mem_src[request_id] <= request_eot;
-end
-
-always @(posedge src_clk)
-begin
-  eot_mem_dest[source_id] <= source_eot;
-end
-
-
-generate if (DMA_TYPE_DEST == DMA_TYPE_MM_AXI) begin
-
-wire                                  dest_bl_valid;
-wire                                  dest_bl_ready;
-wire [BEATS_PER_BURST_WIDTH_DEST-1:0] dest_burst_length;
-wire [BEATS_PER_BURST_WIDTH_SRC-1:0] dest_src_burst_length;
-
-assign dest_clk = m_dest_axi_aclk;
-assign dest_ext_resetn = m_dest_axi_aresetn;
-
-wire [ID_WIDTH-1:0] dest_address_id;
-wire dest_address_eot = eot_mem_dest[dest_address_id];
-wire dest_response_eot = eot_mem_dest[dest_response_id];
-
-assign dbg_dest_address_id = dest_address_id;
-assign dbg_dest_data_id = dest_data_response_id;
-
-assign dest_data_request_id = dest_address_id;
-
-dest_axi_mm #(
-  .ID_WIDTH(ID_WIDTH),
-  .DMA_DATA_WIDTH(DMA_DATA_WIDTH_DEST),
-  .DMA_ADDR_WIDTH(DMA_AXI_ADDR_WIDTH),
-  .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_DEST),
-  .BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH_DEST),
-  .MAX_BYTES_PER_BURST(MAX_BYTES_PER_BURST),
-  .BYTES_PER_BURST_WIDTH(BYTES_PER_BURST_WIDTH),
-  .AXI_LENGTH_WIDTH(AXI_LENGTH_WIDTH_DEST),
-  .CACHE_COHERENT(CACHE_COHERENT_DEST)
-) i_dest_dma_mm (
-  .m_axi_aclk(m_dest_axi_aclk),
-  .m_axi_aresetn(dest_resetn),
-
-  .enable(dest_enable),
-  .enabled(dest_enabled),
-
-  .req_valid(dest_req_valid),
-  .req_ready(dest_req_ready),
-  .req_address(dest_req_dest_address),
-
-  .bl_valid(dest_bl_valid),
-  .bl_ready(dest_bl_ready),
-  .measured_last_burst_length(dest_burst_length),
-
-  .response_valid(dest_response_valid),
-  .response_ready(dest_response_ready),
-  .response_resp(dest_response_resp),
-  .response_resp_eot(dest_response_resp_eot),
-  .response_resp_partial(dest_response_partial),
-  .response_data_burst_length(dest_response_data_burst_length),
-
-  .request_id(dest_request_id),
-  .response_id(dest_response_id),
-
-  .address_id(dest_address_id),
-
-  .address_eot(dest_address_eot),
-  .response_eot(dest_response_eot),
-
-  .fifo_valid(dest_valid),
-  .fifo_ready(dest_ready),
-  .fifo_data(dest_data),
-  .fifo_strb(dest_strb),
-  .fifo_last(dest_last),
-
-  .dest_burst_info_length(dest_burst_info_length),
-  .dest_burst_info_partial(dest_burst_info_partial),
-  .dest_burst_info_id(dest_burst_info_id),
-  .dest_burst_info_write(dest_burst_info_write),
-
-  .m_axi_awready(m_axi_awready),
-  .m_axi_awvalid(m_axi_awvalid),
-  .m_axi_awaddr(m_axi_awaddr),
-  .m_axi_awlen(m_axi_awlen),
-  .m_axi_awsize(m_axi_awsize),
-  .m_axi_awburst(m_axi_awburst),
-  .m_axi_awprot(m_axi_awprot),
-  .m_axi_awcache(m_axi_awcache),
-  .m_axi_wready(m_axi_wready),
-  .m_axi_wvalid(m_axi_wvalid),
-  .m_axi_wdata(m_axi_wdata),
-  .m_axi_wstrb(m_axi_wstrb),
-  .m_axi_wlast(m_axi_wlast),
-
-  .m_axi_bvalid(m_axi_bvalid),
-  .m_axi_bresp(m_axi_bresp),
-  .m_axi_bready(m_axi_bready)
-);
-
-util_axis_fifo #(
-  .DATA_WIDTH(BEATS_PER_BURST_WIDTH_SRC),
-  .ADDRESS_WIDTH(0),
-  .ASYNC_CLK(ASYNC_CLK_SRC_DEST)
-) i_src_dest_bl_fifo (
-  .s_axis_aclk(src_clk),
-  .s_axis_aresetn(src_resetn),
-  .s_axis_valid(src_bl_valid),
-  .s_axis_ready(src_bl_ready),
-  .s_axis_full(),
-  .s_axis_data(src_burst_length),
-  .s_axis_room(),
-
-  .m_axis_aclk(dest_clk),
-  .m_axis_aresetn(dest_resetn),
-  .m_axis_valid(dest_bl_valid),
-  .m_axis_ready(dest_bl_ready),
-  .m_axis_data(dest_src_burst_length),
-  .m_axis_level(),
-  .m_axis_empty()
-);
-
-// Adapt burst length from source width to destination width by either
-// truncation or completion with ones.
-if (BEATS_PER_BURST_WIDTH_SRC == BEATS_PER_BURST_WIDTH_DEST) begin
-assign dest_burst_length = dest_src_burst_length;
-end
-
-if (BEATS_PER_BURST_WIDTH_SRC < BEATS_PER_BURST_WIDTH_DEST) begin
-assign dest_burst_length = {dest_src_burst_length,
-                           {BEATS_PER_BURST_WIDTH_DEST - BEATS_PER_BURST_WIDTH_SRC{1'b1}}};
-end
-
-if (BEATS_PER_BURST_WIDTH_SRC > BEATS_PER_BURST_WIDTH_DEST) begin
-assign dest_burst_length = dest_src_burst_length[BEATS_PER_BURST_WIDTH_SRC-1 -: BEATS_PER_BURST_WIDTH_DEST];
-end
-
-end else begin
-
-assign m_axi_awvalid = 1'b0;
-assign m_axi_awaddr = 'h00;
-assign m_axi_awlen = 'h00;
-assign m_axi_awsize = 'h00;
-assign m_axi_awburst = 'h00;
-assign m_axi_awprot = 'h00;
-assign m_axi_awcache = 'h00;
-
-assign m_axi_wvalid = 1'b0;
-assign m_axi_wdata = 'h00;
-assign m_axi_wstrb = 'h00;
-assign m_axi_wlast = 1'b0;
-
-assign m_axi_bready = 1'b0;
-
-assign src_bl_ready = 1'b1;
-
-assign dest_response_partial = 1'b0;
-assign dest_response_data_burst_length = 'h0;
-
-end
-
-if (DMA_TYPE_DEST == DMA_TYPE_STREAM_AXI) begin
-
-assign dest_clk = m_axis_aclk;
-assign dest_ext_resetn = 1'b1;
-
-wire [ID_WIDTH-1:0] data_id;
-
-wire data_eot = eot_mem_dest[data_id];
-wire response_eot = eot_mem_dest[dest_response_id];
-
-assign dest_data_request_id = dest_request_id;
-
-assign dbg_dest_address_id = 'h00;
-assign dbg_dest_data_id = data_id;
-
-
-dest_axi_stream #(
-  .ID_WIDTH(ID_WIDTH),
-  .S_AXIS_DATA_WIDTH(DMA_DATA_WIDTH_DEST),
-  .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_DEST)
-) i_dest_dma_stream (
-  .s_axis_aclk(m_axis_aclk),
-  .s_axis_aresetn(dest_resetn),
-
-  .enable(dest_enable),
-  .enabled(dest_enabled),
-
-  .req_valid(dest_req_valid),
-  .req_ready(dest_req_ready),
-  .req_xlast(dest_req_xlast),
-
-  .response_valid(dest_response_valid),
-  .response_ready(dest_response_ready),
-  .response_resp(dest_response_resp),
-  .response_resp_eot(dest_response_resp_eot),
-
-  .response_id(dest_response_id),
-  .data_id(data_id),
-  .xfer_req(m_axis_xfer_req),
-
-  .data_eot(data_eot),
-  .response_eot(response_eot),
-
-  .fifo_valid(dest_valid),
-  .fifo_ready(dest_ready),
-  .fifo_data(dest_data),
-  .fifo_last(dest_last),
-
-  .m_axis_valid(m_axis_valid),
-  .m_axis_ready(m_axis_ready),
-  .m_axis_data(m_axis_data),
-  .m_axis_last(m_axis_last)
-);
-
-end else begin
-
-assign m_axis_valid = 1'b0;
-assign m_axis_last = 1'b0;
-assign m_axis_xfer_req = 1'b0;
-assign m_axis_data = 'h00;
-
-end
-
-if (DMA_TYPE_DEST == DMA_TYPE_FIFO) begin
-
-assign dest_clk = fifo_rd_clk;
-assign dest_ext_resetn = 1'b1;
-
-wire [ID_WIDTH-1:0] data_id;
-
-wire data_eot = eot_mem_dest[data_id];
-wire response_eot = eot_mem_dest[dest_response_id];
-
-assign dest_data_request_id = dest_request_id;
-
-assign dbg_dest_address_id = 'h00;
-assign dbg_dest_data_id = data_id;
-
-dest_fifo_inf #(
-  .ID_WIDTH(ID_WIDTH),
-  .DATA_WIDTH(DMA_DATA_WIDTH_DEST),
-  .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_DEST)
-) i_dest_dma_fifo (
-  .clk(fifo_rd_clk),
-  .resetn(dest_resetn),
-
-  .enable(dest_enable),
-  .enabled(dest_enabled),
-
-  .req_valid(dest_req_valid),
-  .req_ready(dest_req_ready),
-
-  .response_valid(dest_response_valid),
-  .response_ready(dest_response_ready),
-  .response_resp(dest_response_resp),
-  .response_resp_eot(dest_response_resp_eot),
-
-  .response_id(dest_response_id),
-  .data_id(data_id),
-
-  .data_eot(data_eot),
-  .response_eot(response_eot),
-
-  .fifo_valid(dest_valid),
-  .fifo_ready(dest_ready),
-  .fifo_data(dest_data),
-  .fifo_last(dest_last),
-
-  .en(fifo_rd_en),
-  .valid(fifo_rd_valid),
-  .dout(fifo_rd_dout),
-  .underflow(fifo_rd_underflow),
-  .xfer_req(fifo_rd_xfer_req)
-);
-
-end else begin
-
-assign fifo_rd_valid = 1'b0;
-assign fifo_rd_dout = 'h0;
-assign fifo_rd_underflow = 1'b0;
-assign fifo_rd_xfer_req = 1'b0;
-
-end endgenerate
-
-generate if (DMA_TYPE_SRC == DMA_TYPE_MM_AXI) begin
-
-wire [ID_WIDTH-1:0] src_data_id;
-wire [ID_WIDTH-1:0] src_address_id;
-wire src_address_eot = eot_mem_src[src_address_id];
-
-assign source_id = src_address_id;
-assign source_eot = src_address_eot;
-
-assign src_clk = m_src_axi_aclk;
-assign src_ext_resetn = m_src_axi_aresetn;
-
-assign dbg_src_address_id = src_address_id;
-assign dbg_src_data_id = src_data_id;
-
-src_axi_mm #(
-  .ID_WIDTH(ID_WIDTH),
-  .DMA_DATA_WIDTH(DMA_DATA_WIDTH_SRC),
-  .DMA_ADDR_WIDTH(DMA_AXI_ADDR_WIDTH),
-  .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_SRC),
-  .BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH_SRC),
-  .AXI_LENGTH_WIDTH(AXI_LENGTH_WIDTH_SRC)
-) i_src_dma_mm (
-  .m_axi_aclk(m_src_axi_aclk),
-  .m_axi_aresetn(src_resetn),
-
-  .enable(src_enable),
-  .enabled(src_enabled),
-
-  .req_valid(src_req_valid),
-  .req_ready(src_req_ready),
-  .req_address(src_req_src_address),
-  .req_last_burst_length(src_req_last_burst_length),
-  .req_last_beat_bytes(src_req_last_beat_bytes),
-
-  .bl_valid(src_bl_valid),
-  .bl_ready(src_bl_ready),
-  .measured_last_burst_length(src_burst_length),
-
-/* TODO
-  .response_valid(src_response_valid),
-  .response_ready(src_response_ready),
-  .response_resp(src_response_resp),
-*/
-
-  .request_id(src_throttled_request_id),
-  .response_id(src_response_id),
-  .address_id(src_address_id),
-  .data_id(src_data_id),
-
-  .address_eot(src_address_eot),
-
-  .fifo_valid(src_valid),
-  .fifo_data(src_data),
-  .fifo_valid_bytes(src_valid_bytes),
-  .fifo_last(src_last),
-
-  .m_axi_arready(m_axi_arready),
-  .m_axi_arvalid(m_axi_arvalid),
-  .m_axi_araddr(m_axi_araddr),
-  .m_axi_arlen(m_axi_arlen),
-  .m_axi_arsize(m_axi_arsize),
-  .m_axi_arburst(m_axi_arburst),
-  .m_axi_arprot(m_axi_arprot),
-  .m_axi_arcache(m_axi_arcache),
-
-  .m_axi_rready(m_axi_rready),
-  .m_axi_rvalid(m_axi_rvalid),
-  .m_axi_rdata(m_axi_rdata),
-  .m_axi_rlast(m_axi_rlast),
-  .m_axi_rresp(m_axi_rresp)
-);
-
-end else begin
-
-assign m_axi_arvalid = 1'b0;
-assign m_axi_araddr = 'h00;
-assign m_axi_arlen = 'h00;
-assign m_axi_arsize = 'h00;
-assign m_axi_arburst = 'h00;
-assign m_axi_arcache = 'h00;
-assign m_axi_arprot = 'h00;
-assign m_axi_rready = 1'b0;
-
-end
-
-if (DMA_TYPE_SRC == DMA_TYPE_STREAM_AXI) begin
-
-assign src_clk = s_axis_aclk;
-assign src_ext_resetn = 1'b1;
-
-wire src_eot = eot_mem_src[src_response_id];
-
-assign dbg_src_address_id = 'h00;
-assign dbg_src_data_id = 'h00;
-
-/* TODO
-assign src_response_valid = 1'b0;
-assign src_response_resp = 2'b0;
-*/
-
-
-src_axi_stream #(
-  .ID_WIDTH(ID_WIDTH),
-  .S_AXIS_DATA_WIDTH(DMA_DATA_WIDTH_SRC),
-  .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_SRC)
-) i_src_dma_stream (
-  .s_axis_aclk(s_axis_aclk),
-  .s_axis_aresetn(src_resetn),
-
-  .enable(src_enable),
-  .enabled(src_enabled),
-
-  .req_valid(src_req_valid),
-  .req_ready(src_req_ready),
-  .req_last_burst_length(src_req_last_burst_length),
-  .req_sync_transfer_start(src_req_sync_transfer_start),
-  .req_xlast(src_req_xlast),
-
-  .request_id(src_throttled_request_id),
-  .response_id(src_response_id),
-
-  .eot(src_eot),
-
-  .rewind_req_valid(rewind_req_valid),
-  .rewind_req_ready(rewind_req_ready),
-  .rewind_req_data(rewind_req_data),
-
-  .bl_valid(src_bl_valid),
-  .bl_ready(src_bl_ready),
-  .measured_last_burst_length(src_burst_length),
-
-  .block_descr_to_dst(block_descr_to_dst),
-
-  .source_id(source_id),
-  .source_eot(source_eot),
-
-  .fifo_valid(src_valid),
-  .fifo_data(src_data),
-  .fifo_last(src_last),
-  .fifo_partial_burst(src_partial_burst),
-
-  .s_axis_valid(s_axis_valid),
-  .s_axis_ready(s_axis_ready),
-  .s_axis_data(s_axis_data),
-  .s_axis_last(s_axis_last),
-  .s_axis_user(s_axis_user),
-  .s_axis_xfer_req(s_axis_xfer_req)
-);
-
-assign src_valid_bytes = {BYTES_PER_BEAT_WIDTH_SRC{1'b1}};
-
-util_axis_fifo #(
-  .DATA_WIDTH(ID_WIDTH + 3),
-  .ADDRESS_WIDTH(0),
-  .ASYNC_CLK(ASYNC_CLK_REQ_SRC)
-) i_rewind_req_fifo (
-  .s_axis_aclk(src_clk),
-  .s_axis_aresetn(src_resetn),
-  .s_axis_valid(rewind_req_valid),
-  .s_axis_ready(rewind_req_ready),
-  .s_axis_full(),
-  .s_axis_data(rewind_req_data),
-  .s_axis_room(),
-
-  .m_axis_aclk(req_clk),
-  .m_axis_aresetn(req_resetn),
-  .m_axis_valid(req_rewind_req_valid),
-  .m_axis_ready(req_rewind_req_ready),
-  .m_axis_data(req_rewind_req_data),
-  .m_axis_level(),
-  .m_axis_empty()
-);
-
-end else begin
-
-assign s_axis_ready = 1'b0;
-assign s_axis_xfer_req = 1'b0;
-assign rewind_req_valid = 1'b0;
-assign rewind_req_data = 'h0;
-
-assign req_rewind_req_valid = 'b0;
-assign req_rewind_req_data = 'h0;
-
-assign src_partial_burst = 1'b0;
-assign block_descr_to_dst = 1'b0;
-
-end
-
-if (DMA_TYPE_SRC == DMA_TYPE_FIFO) begin
-
-wire src_eot = eot_mem_src[src_response_id];
-
-assign source_id = src_response_id;
-assign source_eot = src_eot;
-
-assign src_clk = fifo_wr_clk;
-assign src_ext_resetn = 1'b1;
-
-assign dbg_src_address_id = 'h00;
-assign dbg_src_data_id = 'h00;
-
-/* TODO
-assign src_response_valid = 1'b0;
-assign src_response_resp = 2'b0;
-*/
-
-src_fifo_inf #(
-  .ID_WIDTH(ID_WIDTH),
-  .DATA_WIDTH(DMA_DATA_WIDTH_SRC),
-  .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_SRC)
-) i_src_dma_fifo (
-  .clk(fifo_wr_clk),
-  .resetn(src_resetn),
-
-  .enable(src_enable),
-  .enabled(src_enabled),
-
-  .req_valid(src_req_valid),
-  .req_ready(src_req_ready),
-  .req_last_burst_length(src_req_last_burst_length),
-  .req_sync_transfer_start(src_req_sync_transfer_start),
-
-  .request_id(src_throttled_request_id),
-  .response_id(src_response_id),
-
-  .eot(src_eot),
-
-  .bl_valid(src_bl_valid),
-  .bl_ready(src_bl_ready),
-  .measured_last_burst_length(src_burst_length),
-
-  .fifo_valid(src_valid),
-  .fifo_data(src_data),
-  .fifo_last(src_last),
-
-  .en(fifo_wr_en),
-  .din(fifo_wr_din),
-  .overflow(fifo_wr_overflow),
-  .sync(fifo_wr_sync),
-  .xfer_req(fifo_wr_xfer_req)
-);
-
-assign src_valid_bytes = {BYTES_PER_BEAT_WIDTH_SRC{1'b1}};
-
-end else begin
-
-assign fifo_wr_overflow = 1'b0;
-assign fifo_wr_xfer_req = 1'b0;
-
-end endgenerate
-
-sync_bits #(
-  .NUM_OF_BITS(ID_WIDTH),
-  .ASYNC_CLK(ASYNC_CLK_REQ_SRC)
-) i_sync_src_request_id (
-  .out_clk(src_clk),
-  .out_resetn(1'b1),
-  .in_bits(request_id),
-  .out_bits(src_request_id)
-);
-
-`include "inc_id.vh"
-
-function compare_id;
-  input [ID_WIDTH-1:0] a;
-  input [ID_WIDTH-1:0] b;
+  localparam DMA_TYPE_MM_AXI = 0;
+  localparam DMA_TYPE_STREAM_AXI = 1;
+  localparam DMA_TYPE_FIFO = 2;
+
+  localparam DMA_ADDRESS_WIDTH_DEST = DMA_AXI_ADDR_WIDTH - BYTES_PER_BEAT_WIDTH_DEST;
+  localparam DMA_ADDRESS_WIDTH_SRC = DMA_AXI_ADDR_WIDTH - BYTES_PER_BEAT_WIDTH_SRC;
+
+  // Bytes per burst is the same for both dest and src, but bytes per beat may
+  // differ, so beats per burst may also differ
+
+  localparam BEATS_PER_BURST_WIDTH_SRC = BYTES_PER_BURST_WIDTH - BYTES_PER_BEAT_WIDTH_SRC;
+  localparam BEATS_PER_BURST_WIDTH_DEST = BYTES_PER_BURST_WIDTH - BYTES_PER_BEAT_WIDTH_DEST;
+
+  localparam BURSTS_PER_TRANSFER_WIDTH = DMA_LENGTH_WIDTH - BYTES_PER_BURST_WIDTH;
+
+  reg eot_mem_src[0:2**ID_WIDTH-1];
+  reg eot_mem_dest[0:2**ID_WIDTH-1];
+  wire request_eot;
+  wire source_eot;
+
+  wire [ID_WIDTH-1:0] request_id;
+  wire [ID_WIDTH-1:0] source_id;
+  wire [ID_WIDTH-1:0] response_id;
+
+  wire enabled_src;
+  wire enabled_dest;
+
+  wire req_gen_valid;
+  wire req_gen_ready;
+  wire src_dest_valid;
+  wire src_dest_ready;
+  wire req_src_valid;
+  wire req_src_ready;
+
+  wire dest_req_valid;
+  wire dest_req_ready;
+  wire [DMA_ADDRESS_WIDTH_DEST-1:0] dest_req_dest_address;
+  wire dest_req_xlast;
+
+  wire dest_response_valid;
+  wire dest_response_ready;
+  wire [1:0] dest_response_resp;
+  wire dest_response_resp_eot;
+  wire [BYTES_PER_BURST_WIDTH-1:0] dest_response_data_burst_length;
+  wire dest_response_partial;
+
+  wire [ID_WIDTH-1:0] dest_request_id;
+  wire [ID_WIDTH-1:0] dest_data_request_id;
+  wire [ID_WIDTH-1:0] dest_data_response_id;
+  wire [ID_WIDTH-1:0] dest_response_id;
+
+  wire dest_valid;
+  wire dest_ready;
+  wire [DMA_DATA_WIDTH_DEST-1:0] dest_data;
+  wire [DMA_DATA_WIDTH_DEST/8-1:0] dest_strb;
+  wire dest_last;
+  wire dest_fifo_valid;
+  wire dest_fifo_ready;
+  wire [DMA_DATA_WIDTH_DEST-1:0] dest_fifo_data;
+  wire [DMA_DATA_WIDTH_DEST/8-1:0] dest_fifo_strb;
+  wire dest_fifo_last;
+
+  wire src_req_valid;
+  wire src_req_ready;
+  wire [DMA_ADDRESS_WIDTH_DEST-1:0] src_req_dest_address;
+  wire [DMA_ADDRESS_WIDTH_SRC-1:0] src_req_src_address;
+  wire [BEATS_PER_BURST_WIDTH_SRC-1:0] src_req_last_burst_length;
+  wire [BYTES_PER_BEAT_WIDTH_SRC-1:0] src_req_last_beat_bytes;
+  wire src_req_sync_transfer_start;
+  wire src_req_xlast;
+
+  reg [DMA_ADDRESS_WIDTH_DEST-1:0] src_req_dest_address_cur = 'h0;
+  reg src_req_xlast_cur = 1'b0;
+
+  /* TODO
+  wire src_response_valid;
+  wire src_response_ready;
+  wire src_response_empty;
+  wire [1:0] src_response_resp;
+  */
+
+  wire [ID_WIDTH-1:0] src_request_id;
+  reg [ID_WIDTH-1:0] src_throttled_request_id;
+  wire [ID_WIDTH-1:0] src_data_request_id;
+  wire [ID_WIDTH-1:0] src_response_id;
+
+  wire src_valid;
+  wire [DMA_DATA_WIDTH_SRC-1:0] src_data;
+  wire [BYTES_PER_BEAT_WIDTH_SRC-1:0] src_valid_bytes;
+  wire src_last;
+  wire src_partial_burst;
+  wire block_descr_to_dst;
+  wire src_fifo_valid;
+  wire [DMA_DATA_WIDTH_SRC-1:0] src_fifo_data;
+  wire [BYTES_PER_BEAT_WIDTH_SRC-1:0] src_fifo_valid_bytes;
+  wire src_fifo_last;
+  wire src_fifo_partial_burst;
+
+  wire                                 src_bl_valid;
+  wire                                 src_bl_ready;
+  wire [BEATS_PER_BURST_WIDTH_SRC-1:0] src_burst_length;
+
+  wire [BYTES_PER_BURST_WIDTH-1:0] dest_burst_info_length;
+  wire                             dest_burst_info_partial;
+  wire [ID_WIDTH-1:0] dest_burst_info_id;
+  wire                dest_burst_info_write;
+
+  reg src_dest_valid_hs = 1'b0;
+  wire src_dest_valid_hs_masked;
+  wire src_dest_ready_hs;
+
+  wire req_rewind_req_valid;
+  wire req_rewind_req_ready;
+  wire [ID_WIDTH+3-1:0] req_rewind_req_data;
+
+  wire completion_req_valid;
+  wire completion_req_ready;
+  wire completion_req_last;
+  wire [1:0] completion_transfer_id;
+
+  wire rewind_req_valid;
+  wire rewind_req_ready;
+  wire [ID_WIDTH+3-1:0] rewind_req_data;
+
+  reg src_throttler_enabled = 1'b1;
+  wire src_throttler_enable;
+  wire rewind_state;
+
+  /* Unused for now
+  wire response_src_valid;
+  wire response_src_ready = 1'b1;
+  wire [1:0] response_src_resp;
+  */
+
+  assign dbg_dest_request_id = dest_request_id;
+  assign dbg_dest_response_id = dest_response_id;
+  assign dbg_src_request_id = src_request_id;
+  assign dbg_src_response_id = src_response_id;
+
+  always @(posedge req_clk)
   begin
-    compare_id = a[ID_WIDTH-1] == b[ID_WIDTH-1];
-    if (ID_WIDTH >= 2) begin
-      if (a[ID_WIDTH-2] == b[ID_WIDTH-2]) begin
-        compare_id = 1'b1;
+    eot_mem_src[request_id] <= request_eot;
+  end
+
+  always @(posedge src_clk)
+  begin
+    eot_mem_dest[source_id] <= source_eot;
+  end
+
+  generate if (DMA_TYPE_DEST == DMA_TYPE_MM_AXI) begin
+
+  wire                                  dest_bl_valid;
+  wire                                  dest_bl_ready;
+  wire [BEATS_PER_BURST_WIDTH_DEST-1:0] dest_burst_length;
+  wire [BEATS_PER_BURST_WIDTH_SRC-1:0] dest_src_burst_length;
+
+  assign dest_clk = m_dest_axi_aclk;
+  assign dest_ext_resetn = m_dest_axi_aresetn;
+
+  wire [ID_WIDTH-1:0] dest_address_id;
+  wire dest_address_eot = eot_mem_dest[dest_address_id];
+  wire dest_response_eot = eot_mem_dest[dest_response_id];
+
+  assign dbg_dest_address_id = dest_address_id;
+  assign dbg_dest_data_id = dest_data_response_id;
+
+  assign dest_data_request_id = dest_address_id;
+
+  dest_axi_mm #(
+    .ID_WIDTH(ID_WIDTH),
+    .DMA_DATA_WIDTH(DMA_DATA_WIDTH_DEST),
+    .DMA_ADDR_WIDTH(DMA_AXI_ADDR_WIDTH),
+    .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_DEST),
+    .BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH_DEST),
+    .MAX_BYTES_PER_BURST(MAX_BYTES_PER_BURST),
+    .BYTES_PER_BURST_WIDTH(BYTES_PER_BURST_WIDTH),
+    .AXI_LENGTH_WIDTH(AXI_LENGTH_WIDTH_DEST),
+    .CACHE_COHERENT(CACHE_COHERENT_DEST)
+  ) i_dest_dma_mm (
+    .m_axi_aclk(m_dest_axi_aclk),
+    .m_axi_aresetn(dest_resetn),
+
+    .enable(dest_enable),
+    .enabled(dest_enabled),
+
+    .req_valid(dest_req_valid),
+    .req_ready(dest_req_ready),
+    .req_address(dest_req_dest_address),
+
+    .bl_valid(dest_bl_valid),
+    .bl_ready(dest_bl_ready),
+    .measured_last_burst_length(dest_burst_length),
+
+    .response_valid(dest_response_valid),
+    .response_ready(dest_response_ready),
+    .response_resp(dest_response_resp),
+    .response_resp_eot(dest_response_resp_eot),
+    .response_resp_partial(dest_response_partial),
+    .response_data_burst_length(dest_response_data_burst_length),
+
+    .request_id(dest_request_id),
+    .response_id(dest_response_id),
+
+    .address_id(dest_address_id),
+
+    .address_eot(dest_address_eot),
+    .response_eot(dest_response_eot),
+
+    .fifo_valid(dest_valid),
+    .fifo_ready(dest_ready),
+    .fifo_data(dest_data),
+    .fifo_strb(dest_strb),
+    .fifo_last(dest_last),
+
+    .dest_burst_info_length(dest_burst_info_length),
+    .dest_burst_info_partial(dest_burst_info_partial),
+    .dest_burst_info_id(dest_burst_info_id),
+    .dest_burst_info_write(dest_burst_info_write),
+
+    .m_axi_awready(m_axi_awready),
+    .m_axi_awvalid(m_axi_awvalid),
+    .m_axi_awaddr(m_axi_awaddr),
+    .m_axi_awlen(m_axi_awlen),
+    .m_axi_awsize(m_axi_awsize),
+    .m_axi_awburst(m_axi_awburst),
+    .m_axi_awprot(m_axi_awprot),
+    .m_axi_awcache(m_axi_awcache),
+    .m_axi_wready(m_axi_wready),
+    .m_axi_wvalid(m_axi_wvalid),
+    .m_axi_wdata(m_axi_wdata),
+    .m_axi_wstrb(m_axi_wstrb),
+    .m_axi_wlast(m_axi_wlast),
+
+    .m_axi_bvalid(m_axi_bvalid),
+    .m_axi_bresp(m_axi_bresp),
+    .m_axi_bready(m_axi_bready));
+
+  util_axis_fifo #(
+    .DATA_WIDTH(BEATS_PER_BURST_WIDTH_SRC),
+    .ADDRESS_WIDTH(0),
+    .ASYNC_CLK(ASYNC_CLK_SRC_DEST)
+  ) i_src_dest_bl_fifo (
+    .s_axis_aclk(src_clk),
+    .s_axis_aresetn(src_resetn),
+    .s_axis_valid(src_bl_valid),
+    .s_axis_ready(src_bl_ready),
+    .s_axis_full(),
+    .s_axis_data(src_burst_length),
+    .s_axis_room(),
+
+    .m_axis_aclk(dest_clk),
+    .m_axis_aresetn(dest_resetn),
+    .m_axis_valid(dest_bl_valid),
+    .m_axis_ready(dest_bl_ready),
+    .m_axis_data(dest_src_burst_length),
+    .m_axis_level(),
+    .m_axis_empty());
+
+  // Adapt burst length from source width to destination width by either
+  // truncation or completion with ones.
+  if (BEATS_PER_BURST_WIDTH_SRC == BEATS_PER_BURST_WIDTH_DEST) begin
+  assign dest_burst_length = dest_src_burst_length;
+  end
+
+  if (BEATS_PER_BURST_WIDTH_SRC < BEATS_PER_BURST_WIDTH_DEST) begin
+  assign dest_burst_length = {dest_src_burst_length,
+                             {BEATS_PER_BURST_WIDTH_DEST - BEATS_PER_BURST_WIDTH_SRC{1'b1}}};
+  end
+
+  if (BEATS_PER_BURST_WIDTH_SRC > BEATS_PER_BURST_WIDTH_DEST) begin
+  assign dest_burst_length = dest_src_burst_length[BEATS_PER_BURST_WIDTH_SRC-1 -: BEATS_PER_BURST_WIDTH_DEST];
+  end
+
+  end else begin
+
+  assign m_axi_awvalid = 1'b0;
+  assign m_axi_awaddr = 'h00;
+  assign m_axi_awlen = 'h00;
+  assign m_axi_awsize = 'h00;
+  assign m_axi_awburst = 'h00;
+  assign m_axi_awprot = 'h00;
+  assign m_axi_awcache = 'h00;
+
+  assign m_axi_wvalid = 1'b0;
+  assign m_axi_wdata = 'h00;
+  assign m_axi_wstrb = 'h00;
+  assign m_axi_wlast = 1'b0;
+
+  assign m_axi_bready = 1'b0;
+
+  assign src_bl_ready = 1'b1;
+
+  assign dest_response_partial = 1'b0;
+  assign dest_response_data_burst_length = 'h0;
+
+  end
+
+  if (DMA_TYPE_DEST == DMA_TYPE_STREAM_AXI) begin
+
+  assign dest_clk = m_axis_aclk;
+  assign dest_ext_resetn = 1'b1;
+
+  wire [ID_WIDTH-1:0] data_id;
+
+  wire data_eot = eot_mem_dest[data_id];
+  wire response_eot = eot_mem_dest[dest_response_id];
+
+  assign dest_data_request_id = dest_request_id;
+
+  assign dbg_dest_address_id = 'h00;
+  assign dbg_dest_data_id = data_id;
+
+  dest_axi_stream #(
+    .ID_WIDTH(ID_WIDTH),
+    .S_AXIS_DATA_WIDTH(DMA_DATA_WIDTH_DEST),
+    .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_DEST)
+  ) i_dest_dma_stream (
+    .s_axis_aclk(m_axis_aclk),
+    .s_axis_aresetn(dest_resetn),
+
+    .enable(dest_enable),
+    .enabled(dest_enabled),
+
+    .req_valid(dest_req_valid),
+    .req_ready(dest_req_ready),
+    .req_xlast(dest_req_xlast),
+
+    .response_valid(dest_response_valid),
+    .response_ready(dest_response_ready),
+    .response_resp(dest_response_resp),
+    .response_resp_eot(dest_response_resp_eot),
+
+    .response_id(dest_response_id),
+    .data_id(data_id),
+    .xfer_req(m_axis_xfer_req),
+
+    .data_eot(data_eot),
+    .response_eot(response_eot),
+
+    .fifo_valid(dest_valid),
+    .fifo_ready(dest_ready),
+    .fifo_data(dest_data),
+    .fifo_last(dest_last),
+
+    .m_axis_valid(m_axis_valid),
+    .m_axis_ready(m_axis_ready),
+    .m_axis_data(m_axis_data),
+    .m_axis_last(m_axis_last));
+
+  end else begin
+
+  assign m_axis_valid = 1'b0;
+  assign m_axis_last = 1'b0;
+  assign m_axis_xfer_req = 1'b0;
+  assign m_axis_data = 'h00;
+
+  end
+
+  if (DMA_TYPE_DEST == DMA_TYPE_FIFO) begin
+
+  assign dest_clk = fifo_rd_clk;
+  assign dest_ext_resetn = 1'b1;
+
+  wire [ID_WIDTH-1:0] data_id;
+
+  wire data_eot = eot_mem_dest[data_id];
+  wire response_eot = eot_mem_dest[dest_response_id];
+
+  assign dest_data_request_id = dest_request_id;
+
+  assign dbg_dest_address_id = 'h00;
+  assign dbg_dest_data_id = data_id;
+
+  dest_fifo_inf #(
+    .ID_WIDTH(ID_WIDTH),
+    .DATA_WIDTH(DMA_DATA_WIDTH_DEST),
+    .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_DEST)
+  ) i_dest_dma_fifo (
+    .clk(fifo_rd_clk),
+    .resetn(dest_resetn),
+
+    .enable(dest_enable),
+    .enabled(dest_enabled),
+
+    .req_valid(dest_req_valid),
+    .req_ready(dest_req_ready),
+
+    .response_valid(dest_response_valid),
+    .response_ready(dest_response_ready),
+    .response_resp(dest_response_resp),
+    .response_resp_eot(dest_response_resp_eot),
+
+    .response_id(dest_response_id),
+    .data_id(data_id),
+
+    .data_eot(data_eot),
+    .response_eot(response_eot),
+
+    .fifo_valid(dest_valid),
+    .fifo_ready(dest_ready),
+    .fifo_data(dest_data),
+    .fifo_last(dest_last),
+
+    .en(fifo_rd_en),
+    .valid(fifo_rd_valid),
+    .dout(fifo_rd_dout),
+    .underflow(fifo_rd_underflow),
+    .xfer_req(fifo_rd_xfer_req));
+
+  end else begin
+
+  assign fifo_rd_valid = 1'b0;
+  assign fifo_rd_dout = 'h0;
+  assign fifo_rd_underflow = 1'b0;
+  assign fifo_rd_xfer_req = 1'b0;
+
+  end endgenerate
+
+  generate if (DMA_TYPE_SRC == DMA_TYPE_MM_AXI) begin
+
+  wire [ID_WIDTH-1:0] src_data_id;
+  wire [ID_WIDTH-1:0] src_address_id;
+  wire src_address_eot = eot_mem_src[src_address_id];
+
+  assign source_id = src_address_id;
+  assign source_eot = src_address_eot;
+
+  assign src_clk = m_src_axi_aclk;
+  assign src_ext_resetn = m_src_axi_aresetn;
+
+  assign dbg_src_address_id = src_address_id;
+  assign dbg_src_data_id = src_data_id;
+
+  src_axi_mm #(
+    .ID_WIDTH(ID_WIDTH),
+    .DMA_DATA_WIDTH(DMA_DATA_WIDTH_SRC),
+    .DMA_ADDR_WIDTH(DMA_AXI_ADDR_WIDTH),
+    .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_SRC),
+    .BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH_SRC),
+    .AXI_LENGTH_WIDTH(AXI_LENGTH_WIDTH_SRC)
+  ) i_src_dma_mm (
+    .m_axi_aclk(m_src_axi_aclk),
+    .m_axi_aresetn(src_resetn),
+
+    .enable(src_enable),
+    .enabled(src_enabled),
+
+    .req_valid(src_req_valid),
+    .req_ready(src_req_ready),
+    .req_address(src_req_src_address),
+    .req_last_burst_length(src_req_last_burst_length),
+    .req_last_beat_bytes(src_req_last_beat_bytes),
+
+    .bl_valid(src_bl_valid),
+    .bl_ready(src_bl_ready),
+    .measured_last_burst_length(src_burst_length),
+
+  /* TODO
+    .response_valid(src_response_valid),
+    .response_ready(src_response_ready),
+    .response_resp(src_response_resp),
+  */
+
+    .request_id(src_throttled_request_id),
+    .response_id(src_response_id),
+    .address_id(src_address_id),
+    .data_id(src_data_id),
+
+    .address_eot(src_address_eot),
+
+    .fifo_valid(src_valid),
+    .fifo_data(src_data),
+    .fifo_valid_bytes(src_valid_bytes),
+    .fifo_last(src_last),
+
+    .m_axi_arready(m_axi_arready),
+    .m_axi_arvalid(m_axi_arvalid),
+    .m_axi_araddr(m_axi_araddr),
+    .m_axi_arlen(m_axi_arlen),
+    .m_axi_arsize(m_axi_arsize),
+    .m_axi_arburst(m_axi_arburst),
+    .m_axi_arprot(m_axi_arprot),
+    .m_axi_arcache(m_axi_arcache),
+
+    .m_axi_rready(m_axi_rready),
+    .m_axi_rvalid(m_axi_rvalid),
+    .m_axi_rdata(m_axi_rdata),
+    .m_axi_rlast(m_axi_rlast),
+    .m_axi_rresp(m_axi_rresp));
+
+  end else begin
+
+  assign m_axi_arvalid = 1'b0;
+  assign m_axi_araddr = 'h00;
+  assign m_axi_arlen = 'h00;
+  assign m_axi_arsize = 'h00;
+  assign m_axi_arburst = 'h00;
+  assign m_axi_arcache = 'h00;
+  assign m_axi_arprot = 'h00;
+  assign m_axi_rready = 1'b0;
+
+  end
+
+  if (DMA_TYPE_SRC == DMA_TYPE_STREAM_AXI) begin
+
+  assign src_clk = s_axis_aclk;
+  assign src_ext_resetn = 1'b1;
+
+  wire src_eot = eot_mem_src[src_response_id];
+
+  assign dbg_src_address_id = 'h00;
+  assign dbg_src_data_id = 'h00;
+
+  /* TODO
+  assign src_response_valid = 1'b0;
+  assign src_response_resp = 2'b0;
+  */
+
+  src_axi_stream #(
+    .ID_WIDTH(ID_WIDTH),
+    .S_AXIS_DATA_WIDTH(DMA_DATA_WIDTH_SRC),
+    .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_SRC)
+  ) i_src_dma_stream (
+    .s_axis_aclk(s_axis_aclk),
+    .s_axis_aresetn(src_resetn),
+
+    .enable(src_enable),
+    .enabled(src_enabled),
+
+    .req_valid(src_req_valid),
+    .req_ready(src_req_ready),
+    .req_last_burst_length(src_req_last_burst_length),
+    .req_sync_transfer_start(src_req_sync_transfer_start),
+    .req_xlast(src_req_xlast),
+
+    .request_id(src_throttled_request_id),
+    .response_id(src_response_id),
+
+    .eot(src_eot),
+
+    .rewind_req_valid(rewind_req_valid),
+    .rewind_req_ready(rewind_req_ready),
+    .rewind_req_data(rewind_req_data),
+
+    .bl_valid(src_bl_valid),
+    .bl_ready(src_bl_ready),
+    .measured_last_burst_length(src_burst_length),
+
+    .block_descr_to_dst(block_descr_to_dst),
+
+    .source_id(source_id),
+    .source_eot(source_eot),
+
+    .fifo_valid(src_valid),
+    .fifo_data(src_data),
+    .fifo_last(src_last),
+    .fifo_partial_burst(src_partial_burst),
+
+    .s_axis_valid(s_axis_valid),
+    .s_axis_ready(s_axis_ready),
+    .s_axis_data(s_axis_data),
+    .s_axis_last(s_axis_last),
+    .s_axis_user(s_axis_user),
+    .s_axis_xfer_req(s_axis_xfer_req));
+
+  assign src_valid_bytes = {BYTES_PER_BEAT_WIDTH_SRC{1'b1}};
+
+  util_axis_fifo #(
+    .DATA_WIDTH(ID_WIDTH + 3),
+    .ADDRESS_WIDTH(0),
+    .ASYNC_CLK(ASYNC_CLK_REQ_SRC)
+  ) i_rewind_req_fifo (
+    .s_axis_aclk(src_clk),
+    .s_axis_aresetn(src_resetn),
+    .s_axis_valid(rewind_req_valid),
+    .s_axis_ready(rewind_req_ready),
+    .s_axis_full(),
+    .s_axis_data(rewind_req_data),
+    .s_axis_room(),
+
+    .m_axis_aclk(req_clk),
+    .m_axis_aresetn(req_resetn),
+    .m_axis_valid(req_rewind_req_valid),
+    .m_axis_ready(req_rewind_req_ready),
+    .m_axis_data(req_rewind_req_data),
+    .m_axis_level(),
+    .m_axis_empty());
+
+  end else begin
+
+  assign s_axis_ready = 1'b0;
+  assign s_axis_xfer_req = 1'b0;
+  assign rewind_req_valid = 1'b0;
+  assign rewind_req_data = 'h0;
+
+  assign req_rewind_req_valid = 'b0;
+  assign req_rewind_req_data = 'h0;
+
+  assign src_partial_burst = 1'b0;
+  assign block_descr_to_dst = 1'b0;
+
+  end
+
+  if (DMA_TYPE_SRC == DMA_TYPE_FIFO) begin
+
+  wire src_eot = eot_mem_src[src_response_id];
+
+  assign source_id = src_response_id;
+  assign source_eot = src_eot;
+
+  assign src_clk = fifo_wr_clk;
+  assign src_ext_resetn = 1'b1;
+
+  assign dbg_src_address_id = 'h00;
+  assign dbg_src_data_id = 'h00;
+
+  /* TODO
+  assign src_response_valid = 1'b0;
+  assign src_response_resp = 2'b0;
+  */
+
+  src_fifo_inf #(
+    .ID_WIDTH(ID_WIDTH),
+    .DATA_WIDTH(DMA_DATA_WIDTH_SRC),
+    .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_SRC)
+  ) i_src_dma_fifo (
+    .clk(fifo_wr_clk),
+    .resetn(src_resetn),
+
+    .enable(src_enable),
+    .enabled(src_enabled),
+
+    .req_valid(src_req_valid),
+    .req_ready(src_req_ready),
+    .req_last_burst_length(src_req_last_burst_length),
+    .req_sync_transfer_start(src_req_sync_transfer_start),
+
+    .request_id(src_throttled_request_id),
+    .response_id(src_response_id),
+
+    .eot(src_eot),
+
+    .bl_valid(src_bl_valid),
+    .bl_ready(src_bl_ready),
+    .measured_last_burst_length(src_burst_length),
+
+    .fifo_valid(src_valid),
+    .fifo_data(src_data),
+    .fifo_last(src_last),
+
+    .en(fifo_wr_en),
+    .din(fifo_wr_din),
+    .overflow(fifo_wr_overflow),
+    .sync(fifo_wr_sync),
+    .xfer_req(fifo_wr_xfer_req));
+
+  assign src_valid_bytes = {BYTES_PER_BEAT_WIDTH_SRC{1'b1}};
+
+  end else begin
+
+  assign fifo_wr_overflow = 1'b0;
+  assign fifo_wr_xfer_req = 1'b0;
+
+  end endgenerate
+
+  sync_bits #(
+    .NUM_OF_BITS(ID_WIDTH),
+    .ASYNC_CLK(ASYNC_CLK_REQ_SRC)
+  ) i_sync_src_request_id (
+    .out_clk(src_clk),
+    .out_resetn(1'b1),
+    .in_bits(request_id),
+    .out_bits(src_request_id));
+
+  `include "inc_id.vh"
+
+  function compare_id;
+    input [ID_WIDTH-1:0] a;
+    input [ID_WIDTH-1:0] b;
+    begin
+      compare_id = a[ID_WIDTH-1] == b[ID_WIDTH-1];
+      if (ID_WIDTH >= 2) begin
+        if (a[ID_WIDTH-2] == b[ID_WIDTH-2]) begin
+          compare_id = 1'b1;
+        end
+      end
+      if (ID_WIDTH >= 3) begin
+        if (a[ID_WIDTH-3:0] != b[ID_WIDTH-3:0]) begin
+          compare_id = 1'b1;
+        end
       end
     end
-    if (ID_WIDTH >= 3) begin
-      if (a[ID_WIDTH-3:0] != b[ID_WIDTH-3:0]) begin
-        compare_id = 1'b1;
-      end
+  endfunction
+
+  sync_event #(
+    .ASYNC_CLK(ASYNC_CLK_REQ_SRC)
+  ) sync_rewind (
+    .in_clk(req_clk),
+    .in_event(rewind_state),
+    .out_clk(src_clk),
+    .out_event(src_throttler_enable));
+
+  always @(posedge src_clk) begin
+    if (src_resetn == 1'b0) begin
+      src_throttler_enabled <= 'b1;
+    end else if (rewind_req_valid) begin
+      src_throttler_enabled <= 'b0;
+    end else if (src_throttler_enable) begin
+      src_throttler_enabled <= 'b1;
     end
   end
-endfunction
 
-sync_event #(.ASYNC_CLK(ASYNC_CLK_REQ_SRC)) sync_rewind (
-  .in_clk(req_clk),
-  .in_event(rewind_state),
-  .out_clk(src_clk),
-  .out_event(src_throttler_enable)
-);
-
-always @(posedge src_clk) begin
-  if (src_resetn == 1'b0) begin
-    src_throttler_enabled <= 'b1;
-  end else if (rewind_req_valid) begin
-    src_throttler_enabled <= 'b0;
-  end else if (src_throttler_enable) begin
-    src_throttler_enabled <= 'b1;
+  /*
+   * Make sure that we do not request more data than what fits into the
+   * store-and-forward burst memory.
+   * Throttler must be blocked during rewind since it does not tolerate
+   * a decrement of the request ID.
+   */
+  always @(posedge src_clk) begin
+    if (src_resetn == 1'b0) begin
+      src_throttled_request_id <= 'h00;
+    end else if (rewind_req_valid) begin
+      src_throttled_request_id <= rewind_req_data[ID_WIDTH-1:0];
+    end else if (src_throttled_request_id != src_request_id &&
+                 compare_id(src_throttled_request_id, src_data_request_id) &&
+                 src_throttler_enabled) begin
+      src_throttled_request_id <= inc_id(src_throttled_request_id);
+    end
   end
-end
 
-/*
- * Make sure that we do not request more data than what fits into the
- * store-and-forward burst memory.
- * Throttler must be blocked during rewind since it does not tolerate
- * a decrement of the request ID.
- */
-always @(posedge src_clk) begin
-  if (src_resetn == 1'b0) begin
-    src_throttled_request_id <= 'h00;
-  end else if (rewind_req_valid) begin
-    src_throttled_request_id <= rewind_req_data[ID_WIDTH-1:0];
-  end else if (src_throttled_request_id != src_request_id &&
-               compare_id(src_throttled_request_id, src_data_request_id) &&
-               src_throttler_enabled) begin
-    src_throttled_request_id <= inc_id(src_throttled_request_id);
+  sync_bits #(
+    .NUM_OF_BITS(ID_WIDTH),
+    .ASYNC_CLK(ASYNC_CLK_DEST_REQ)
+  ) i_sync_req_response_id (
+    .out_clk(req_clk),
+    .out_resetn(1'b1),
+    .in_bits(dest_response_id),
+    .out_bits(response_id));
+
+  axi_register_slice #(
+    .DATA_WIDTH(DMA_DATA_WIDTH_SRC + BYTES_PER_BEAT_WIDTH_SRC + 2),
+    .FORWARD_REGISTERED(AXI_SLICE_SRC),
+    .BACKWARD_REGISTERED(0)
+  ) i_src_slice (
+    .clk(src_clk),
+    .resetn(src_resetn),
+    .s_axi_valid(src_valid),
+    .s_axi_ready(),
+    .s_axi_data({src_data,src_valid_bytes,src_last,src_partial_burst}),
+    .m_axi_valid(src_fifo_valid),
+    .m_axi_ready(1'b1), /* No backpressure */
+    .m_axi_data({src_fifo_data,src_fifo_valid_bytes,src_fifo_last,src_fifo_partial_burst}));
+
+  axi_dmac_burst_memory #(
+    .DATA_WIDTH_SRC(DMA_DATA_WIDTH_SRC),
+    .DATA_WIDTH_DEST(DMA_DATA_WIDTH_DEST),
+    .ID_WIDTH(ID_WIDTH),
+    .MAX_BYTES_PER_BURST(MAX_BYTES_PER_BURST),
+    .ASYNC_CLK(ASYNC_CLK_SRC_DEST),
+    .BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC),
+    .BYTES_PER_BURST_WIDTH(BYTES_PER_BURST_WIDTH),
+    .DMA_LENGTH_ALIGN(DMA_LENGTH_ALIGN),
+    .ENABLE_DIAGNOSTICS_IF(ENABLE_DIAGNOSTICS_IF),
+    .ALLOW_ASYM_MEM(ALLOW_ASYM_MEM)
+  ) i_store_and_forward (
+    .src_clk(src_clk),
+    .src_reset(~src_resetn),
+    .src_data_valid(src_fifo_valid),
+    .src_data(src_fifo_data),
+    .src_data_last(src_fifo_last),
+    .src_data_valid_bytes(src_fifo_valid_bytes),
+    .src_data_partial_burst(src_fifo_partial_burst),
+
+    .src_data_request_id(src_data_request_id),
+
+    .dest_clk(dest_clk),
+    .dest_reset(~dest_resetn),
+    .dest_data_valid(dest_fifo_valid),
+    .dest_data_ready(dest_fifo_ready),
+    .dest_data(dest_fifo_data),
+    .dest_data_last(dest_fifo_last),
+    .dest_data_strb(dest_fifo_strb),
+
+    .dest_burst_info_length(dest_burst_info_length),
+    .dest_burst_info_partial(dest_burst_info_partial),
+    .dest_burst_info_id(dest_burst_info_id),
+    .dest_burst_info_write(dest_burst_info_write),
+
+    .dest_request_id(dest_request_id),
+    .dest_data_request_id(dest_data_request_id),
+    .dest_data_response_id(dest_data_response_id),
+
+    .dest_diag_level_bursts(dest_diag_level_bursts));
+
+  axi_register_slice #(
+    .DATA_WIDTH(DMA_DATA_WIDTH_DEST + DMA_DATA_WIDTH_DEST / 8 + 1),
+    .FORWARD_REGISTERED(AXI_SLICE_DEST),
+    .BACKWARD_REGISTERED(AXI_SLICE_DEST)
+  ) i_dest_slice (
+    .clk(dest_clk),
+    .resetn(dest_resetn),
+    .s_axi_valid(dest_fifo_valid),
+    .s_axi_ready(dest_fifo_ready),
+    .s_axi_data({
+      dest_fifo_last,
+      dest_fifo_strb,
+      dest_fifo_data}),
+    .m_axi_valid(dest_valid),
+    .m_axi_ready(dest_ready),
+    .m_axi_data({
+      dest_last,
+      dest_strb,
+      dest_data}));
+
+  // Don't let the request generator run in advance more than one descriptor
+  // The descriptor FIFO should not block the start of the request generator
+  // since it becomes ready earlier.
+  assign req_gen_valid = req_valid & req_ready;
+  assign req_src_valid = req_valid & req_ready;
+  assign req_ready = req_gen_ready & req_src_ready;
+
+  util_axis_fifo #(
+    .DATA_WIDTH(DMA_ADDRESS_WIDTH_DEST + 1),
+    .ADDRESS_WIDTH(0),
+    .ASYNC_CLK(ASYNC_CLK_SRC_DEST)
+  ) i_dest_req_fifo (
+    .s_axis_aclk(src_clk),
+    .s_axis_aresetn(src_resetn),
+    .s_axis_valid(src_dest_valid_hs_masked),
+    .s_axis_ready(src_dest_ready_hs),
+    .s_axis_full(),
+    .s_axis_data({
+      src_req_dest_address_cur,
+      src_req_xlast_cur}),
+    .s_axis_room(),
+
+    .m_axis_aclk(dest_clk),
+    .m_axis_aresetn(dest_resetn),
+    .m_axis_valid(dest_req_valid),
+    .m_axis_ready(dest_req_ready),
+    .m_axis_data({
+      dest_req_dest_address,
+      dest_req_xlast}),
+    .m_axis_level(),
+    .m_axis_empty());
+
+  util_axis_fifo #(
+    .DATA_WIDTH(DMA_ADDRESS_WIDTH_DEST + DMA_ADDRESS_WIDTH_SRC + BYTES_PER_BURST_WIDTH + 2),
+    .ADDRESS_WIDTH(0),
+    .ASYNC_CLK(ASYNC_CLK_REQ_SRC)
+  ) i_src_req_fifo (
+    .s_axis_aclk(req_clk),
+    .s_axis_aresetn(req_resetn),
+    .s_axis_valid(req_src_valid),
+    .s_axis_ready(req_src_ready),
+    .s_axis_full(),
+    .s_axis_data({
+      req_dest_address,
+      req_src_address,
+      req_length[BYTES_PER_BURST_WIDTH-1:0],
+      req_sync_transfer_start,
+      req_xlast}),
+    .s_axis_room(),
+
+    .m_axis_aclk(src_clk),
+    .m_axis_aresetn(src_resetn),
+    .m_axis_valid(src_req_spltr_valid),
+    .m_axis_ready(src_req_spltr_ready),
+    .m_axis_data({
+      src_req_dest_address,
+      src_req_src_address,
+      src_req_last_burst_length,
+      src_req_last_beat_bytes,
+      src_req_sync_transfer_start,
+      src_req_xlast}),
+    .m_axis_level(),
+    .m_axis_empty());
+
+  // Save the descriptor in the source clock domain since the submission to
+  // destination is delayed.
+  always @(posedge src_clk) begin
+    if (src_req_valid == 1'b1 && src_req_ready == 1'b1) begin
+      src_req_dest_address_cur <= src_req_dest_address;
+      src_req_xlast_cur <= src_req_xlast;
+    end
   end
-end
 
-sync_bits #(
-  .NUM_OF_BITS(ID_WIDTH),
-  .ASYNC_CLK(ASYNC_CLK_DEST_REQ)
-) i_sync_req_response_id (
-  .out_clk(req_clk),
-  .out_resetn(1'b1),
-  .in_bits(dest_response_id),
-  .out_bits(response_id)
-);
-
-axi_register_slice #(
-  .DATA_WIDTH(DMA_DATA_WIDTH_SRC + BYTES_PER_BEAT_WIDTH_SRC + 2),
-  .FORWARD_REGISTERED(AXI_SLICE_SRC),
-  .BACKWARD_REGISTERED(0)
-) i_src_slice (
-  .clk(src_clk),
-  .resetn(src_resetn),
-  .s_axi_valid(src_valid),
-  .s_axi_ready(),
-  .s_axi_data({src_data,src_valid_bytes,src_last,src_partial_burst}),
-  .m_axi_valid(src_fifo_valid),
-  .m_axi_ready(1'b1), /* No backpressure */
-  .m_axi_data({src_fifo_data,src_fifo_valid_bytes,src_fifo_last,src_fifo_partial_burst})
-);
-
-axi_dmac_burst_memory #(
-  .DATA_WIDTH_SRC(DMA_DATA_WIDTH_SRC),
-  .DATA_WIDTH_DEST(DMA_DATA_WIDTH_DEST),
-  .ID_WIDTH(ID_WIDTH),
-  .MAX_BYTES_PER_BURST(MAX_BYTES_PER_BURST),
-  .ASYNC_CLK(ASYNC_CLK_SRC_DEST),
-  .BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC),
-  .BYTES_PER_BURST_WIDTH(BYTES_PER_BURST_WIDTH),
-  .DMA_LENGTH_ALIGN(DMA_LENGTH_ALIGN),
-  .ENABLE_DIAGNOSTICS_IF(ENABLE_DIAGNOSTICS_IF),
-  .ALLOW_ASYM_MEM(ALLOW_ASYM_MEM)
-) i_store_and_forward (
-  .src_clk(src_clk),
-  .src_reset(~src_resetn),
-  .src_data_valid(src_fifo_valid),
-  .src_data(src_fifo_data),
-  .src_data_last(src_fifo_last),
-  .src_data_valid_bytes(src_fifo_valid_bytes),
-  .src_data_partial_burst(src_fifo_partial_burst),
-
-  .src_data_request_id(src_data_request_id),
-
-  .dest_clk(dest_clk),
-  .dest_reset(~dest_resetn),
-  .dest_data_valid(dest_fifo_valid),
-  .dest_data_ready(dest_fifo_ready),
-  .dest_data(dest_fifo_data),
-  .dest_data_last(dest_fifo_last),
-  .dest_data_strb(dest_fifo_strb),
-
-  .dest_burst_info_length(dest_burst_info_length),
-  .dest_burst_info_partial(dest_burst_info_partial),
-  .dest_burst_info_id(dest_burst_info_id),
-  .dest_burst_info_write(dest_burst_info_write),
-
-  .dest_request_id(dest_request_id),
-  .dest_data_request_id(dest_data_request_id),
-  .dest_data_response_id(dest_data_response_id),
-
-  .dest_diag_level_bursts(dest_diag_level_bursts)
-);
-
-axi_register_slice #(
-  .DATA_WIDTH(DMA_DATA_WIDTH_DEST + DMA_DATA_WIDTH_DEST / 8 + 1),
-  .FORWARD_REGISTERED(AXI_SLICE_DEST),
-  .BACKWARD_REGISTERED(AXI_SLICE_DEST)
-) i_dest_slice (
-  .clk(dest_clk),
-  .resetn(dest_resetn),
-  .s_axi_valid(dest_fifo_valid),
-  .s_axi_ready(dest_fifo_ready),
-  .s_axi_data({
-    dest_fifo_last,
-    dest_fifo_strb,
-    dest_fifo_data
-  }),
-  .m_axi_valid(dest_valid),
-  .m_axi_ready(dest_ready),
-  .m_axi_data({
-    dest_last,
-    dest_strb,
-    dest_data
-  })
-);
-
-// Don't let the request generator run in advance more than one descriptor
-// The descriptor FIFO should not block the start of the request generator
-// since it becomes ready earlier.
-assign req_gen_valid = req_valid & req_ready;
-assign req_src_valid = req_valid & req_ready;
-assign req_ready = req_gen_ready & req_src_ready;
-
-util_axis_fifo #(
-  .DATA_WIDTH(DMA_ADDRESS_WIDTH_DEST + 1),
-  .ADDRESS_WIDTH(0),
-  .ASYNC_CLK(ASYNC_CLK_SRC_DEST)
-) i_dest_req_fifo (
-  .s_axis_aclk(src_clk),
-  .s_axis_aresetn(src_resetn),
-  .s_axis_valid(src_dest_valid_hs_masked),
-  .s_axis_ready(src_dest_ready_hs),
-  .s_axis_full(),
-  .s_axis_data({
-    src_req_dest_address_cur,
-    src_req_xlast_cur
-  }),
-  .s_axis_room(),
-
-  .m_axis_aclk(dest_clk),
-  .m_axis_aresetn(dest_resetn),
-  .m_axis_valid(dest_req_valid),
-  .m_axis_ready(dest_req_ready),
-  .m_axis_data({
-    dest_req_dest_address,
-    dest_req_xlast
-  }),
-  .m_axis_level(),
-  .m_axis_empty()
-);
-
-util_axis_fifo #(
-  .DATA_WIDTH(DMA_ADDRESS_WIDTH_DEST + DMA_ADDRESS_WIDTH_SRC + BYTES_PER_BURST_WIDTH + 2),
-  .ADDRESS_WIDTH(0),
-  .ASYNC_CLK(ASYNC_CLK_REQ_SRC)
-) i_src_req_fifo (
-  .s_axis_aclk(req_clk),
-  .s_axis_aresetn(req_resetn),
-  .s_axis_valid(req_src_valid),
-  .s_axis_ready(req_src_ready),
-  .s_axis_full(),
-  .s_axis_data({
-    req_dest_address,
-    req_src_address,
-    req_length[BYTES_PER_BURST_WIDTH-1:0],
-    req_sync_transfer_start,
-    req_xlast
-  }),
-  .s_axis_room(),
-
-  .m_axis_aclk(src_clk),
-  .m_axis_aresetn(src_resetn),
-  .m_axis_valid(src_req_spltr_valid),
-  .m_axis_ready(src_req_spltr_ready),
-  .m_axis_data({
-    src_req_dest_address,
-    src_req_src_address,
-    src_req_last_burst_length,
-    src_req_last_beat_bytes,
-    src_req_sync_transfer_start,
-    src_req_xlast
-  }),
-  .m_axis_level(),
-  .m_axis_empty()
-);
-
-// Save the descriptor in the source clock domain since the submission to
-// destination is delayed.
-always @(posedge src_clk) begin
-  if (src_req_valid == 1'b1 && src_req_ready == 1'b1) begin
-    src_req_dest_address_cur <= src_req_dest_address;
-    src_req_xlast_cur <= src_req_xlast;
+  always @(posedge src_clk) begin
+    if (src_resetn == 1'b0) begin
+      src_dest_valid_hs <= 1'b0;
+    end else if (src_req_valid == 1'b1 && src_req_ready == 1'b1) begin
+      src_dest_valid_hs <= 1'b1;
+    end else if (src_dest_ready_hs == 1'b1) begin
+      src_dest_valid_hs <= 1'b0;
+    end
   end
-end
 
-always @(posedge src_clk) begin
-  if (src_resetn == 1'b0) begin
-    src_dest_valid_hs <= 1'b0;
-  end else if (src_req_valid == 1'b1 && src_req_ready == 1'b1) begin
-    src_dest_valid_hs <= 1'b1;
-  end else if (src_dest_ready_hs == 1'b1) begin
-    src_dest_valid_hs <= 1'b0;
-  end
-end
+  // Forward the descriptor to the destination only after the source decided to
+  // do so
+  assign src_dest_valid_hs_masked = src_dest_valid_hs == 1'b1 && block_descr_to_dst == 1'b0;
+  assign src_req_spltr_ready = src_req_ready && src_dest_ready_hs;
+  assign src_req_valid = src_req_spltr_valid && src_req_spltr_ready;
 
-// Forward the descriptor to the destination only after the source decided to
-// do so
-assign src_dest_valid_hs_masked = src_dest_valid_hs == 1'b1 && block_descr_to_dst == 1'b0;
-assign src_req_spltr_ready = src_req_ready && src_dest_ready_hs;
-assign src_req_valid = src_req_spltr_valid && src_req_spltr_ready;
+  /* Unused for now
+  util_axis_fifo #(
+    .DATA_WIDTH(2),
+    .ADDRESS_WIDTH(0),
+    .ASYNC_CLK(ASYNC_CLK_REQ_SRC)
+  ) i_src_response_fifo (
+    .s_axis_aclk(src_clk),
+    .s_axis_aresetn(src_resetn),
+    .s_axis_valid(src_response_valid),
+    .s_axis_ready(src_response_ready),
+    .s_axis_empty(src_response_empty),
+    .s_axis_data(src_response_resp),
+    .m_axis_aclk(req_clk),
+    .m_axis_aresetn(req_resetn),
+    .m_axis_valid(response_src_valid),
+    .m_axis_ready(response_src_ready),
+    .m_axis_data(response_src_resp));
+  assign src_response_empty = 1'b1;
+  assign src_response_ready = 1'b1;
+  */
 
+  request_generator #(
+    .ID_WIDTH(ID_WIDTH),
+    .BURSTS_PER_TRANSFER_WIDTH(BURSTS_PER_TRANSFER_WIDTH)
+  ) i_req_gen (
+    .clk(req_clk),
+    .resetn(req_resetn),
 
-/* Unused for now
-util_axis_fifo #(
-  .DATA_WIDTH(2),
-  .ADDRESS_WIDTH(0),
-  .ASYNC_CLK(ASYNC_CLK_REQ_SRC)
-) i_src_response_fifo (
-  .s_axis_aclk(src_clk),
-  .s_axis_aresetn(src_resetn),
-  .s_axis_valid(src_response_valid),
-  .s_axis_ready(src_response_ready),
-  .s_axis_empty(src_response_empty),
-  .s_axis_data(src_response_resp),
-  .m_axis_aclk(req_clk),
-  .m_axis_aresetn(req_resetn),
-  .m_axis_valid(response_src_valid),
-  .m_axis_ready(response_src_ready),
-  .m_axis_data(response_src_resp)
-);
-assign src_response_empty = 1'b1;
-assign src_response_ready = 1'b1;
-*/
+    .request_id(request_id),
+    .response_id(response_id),
 
-request_generator #(
-  .ID_WIDTH(ID_WIDTH),
-  .BURSTS_PER_TRANSFER_WIDTH(BURSTS_PER_TRANSFER_WIDTH)
-) i_req_gen (
-  .clk(req_clk),
-  .resetn(req_resetn),
+    .rewind_req_valid(req_rewind_req_valid),
+    .rewind_req_ready(req_rewind_req_ready),
+    .rewind_req_data(req_rewind_req_data),
+    .rewind_state(rewind_state),
 
-  .request_id(request_id),
-  .response_id(response_id),
+    .abort_req(abort_req),
 
-  .rewind_req_valid(req_rewind_req_valid),
-  .rewind_req_ready(req_rewind_req_ready),
-  .rewind_req_data(req_rewind_req_data),
-  .rewind_state(rewind_state),
+    .completion_req_valid(completion_req_valid),
+    .completion_req_ready(completion_req_ready),
+    .completion_req_last(completion_req_last),
+    .completion_transfer_id(completion_transfer_id),
 
-  .abort_req(abort_req),
+    .req_valid(req_gen_valid),
+    .req_ready(req_gen_ready),
+    .req_burst_count(req_length[DMA_LENGTH_WIDTH-1:BYTES_PER_BURST_WIDTH]),
+    .req_xlast(req_xlast),
 
-  .completion_req_valid(completion_req_valid),
-  .completion_req_ready(completion_req_ready),
-  .completion_req_last(completion_req_last),
-  .completion_transfer_id(completion_transfer_id),
+    .enable(req_enable),
 
-  .req_valid(req_gen_valid),
-  .req_ready(req_gen_ready),
-  .req_burst_count(req_length[DMA_LENGTH_WIDTH-1:BYTES_PER_BURST_WIDTH]),
-  .req_xlast(req_xlast),
+    .eot(request_eot));
 
-  .enable(req_enable),
+  axi_dmac_response_manager #(
+    .DMA_DATA_WIDTH_SRC(DMA_DATA_WIDTH_SRC),
+    .DMA_DATA_WIDTH_DEST(DMA_DATA_WIDTH_DEST),
+    .DMA_LENGTH_WIDTH(DMA_LENGTH_WIDTH),
+    .BYTES_PER_BURST_WIDTH(BYTES_PER_BURST_WIDTH),
+    .BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC),
+    .ASYNC_CLK_DEST_REQ(ASYNC_CLK_DEST_REQ)
+  ) i_response_manager(
+    .dest_clk(dest_clk),
+    .dest_resetn(dest_resetn),
+    .dest_response_valid(dest_response_valid),
+    .dest_response_ready(dest_response_ready),
+    .dest_response_resp(dest_response_resp),
+    .dest_response_partial(dest_response_partial),
+    .dest_response_resp_eot(dest_response_resp_eot),
+    .dest_response_data_burst_length(dest_response_data_burst_length),
 
-  .eot(request_eot)
-);
-
-axi_dmac_response_manager #(
-  .DMA_DATA_WIDTH_SRC(DMA_DATA_WIDTH_SRC),
-  .DMA_DATA_WIDTH_DEST(DMA_DATA_WIDTH_DEST),
-  .DMA_LENGTH_WIDTH(DMA_LENGTH_WIDTH),
-  .BYTES_PER_BURST_WIDTH(BYTES_PER_BURST_WIDTH),
-  .BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC),
-  .ASYNC_CLK_DEST_REQ(ASYNC_CLK_DEST_REQ)
-) i_response_manager(
-  .dest_clk(dest_clk),
-  .dest_resetn(dest_resetn),
-  .dest_response_valid(dest_response_valid),
-  .dest_response_ready(dest_response_ready),
-  .dest_response_resp(dest_response_resp),
-  .dest_response_partial(dest_response_partial),
-  .dest_response_resp_eot(dest_response_resp_eot),
-  .dest_response_data_burst_length(dest_response_data_burst_length),
-
-  .req_clk(req_clk),
-  .req_resetn(req_resetn),
-  .response_eot(eot),
-  .measured_burst_length(measured_burst_length),
-  .response_partial(response_partial),
-  .response_valid(response_valid),
-  .response_ready(response_ready),
-
-  .completion_req_valid(completion_req_valid),
-  .completion_req_ready(completion_req_ready),
-  .completion_req_last(completion_req_last),
-  .completion_transfer_id(completion_transfer_id)
-
-);
+    .req_clk(req_clk),
+    .req_resetn(req_resetn),
+    .response_eot(eot),
+    .measured_burst_length(measured_burst_length),
+    .response_partial(response_partial),
+    .response_valid(response_valid),
+    .response_ready(response_ready),
 
+    .completion_req_valid(completion_req_valid),
+    .completion_req_ready(completion_req_ready),
+    .completion_req_last(completion_req_last),
+    .completion_transfer_id(completion_transfer_id));
 
 endmodule
diff --git a/library/axi_dmac/request_generator.v b/library/axi_dmac/request_generator.v
index 2a33f0a3b..0296fca88 100644
--- a/library/axi_dmac/request_generator.v
+++ b/library/axi_dmac/request_generator.v
@@ -38,8 +38,8 @@
 module request_generator #(
 
   parameter ID_WIDTH = 3,
-  parameter BURSTS_PER_TRANSFER_WIDTH = 17)(
-
+  parameter BURSTS_PER_TRANSFER_WIDTH = 17
+) (
   input clk,
   input resetn,
 
@@ -68,191 +68,191 @@ module request_generator #(
   output eot
 );
 
-`include "inc_id.vh"
+  `include "inc_id.vh"
 
-localparam STATE_IDLE      = 3'h0;
-localparam STATE_GEN_ID    = 3'h1;
-localparam STATE_REWIND_ID = 3'h2;
-localparam STATE_CONSUME   = 3'h3;
-localparam STATE_WAIT_LAST = 3'h4;
+  localparam STATE_IDLE      = 3'h0;
+  localparam STATE_GEN_ID    = 3'h1;
+  localparam STATE_REWIND_ID = 3'h2;
+  localparam STATE_CONSUME   = 3'h3;
+  localparam STATE_WAIT_LAST = 3'h4;
 
-reg [2:0] state = STATE_IDLE;
-reg [2:0] nx_state;
+  reg [2:0] state = STATE_IDLE;
+  reg [2:0] nx_state;
 
-reg [1:0] rew_transfer_id = 1'b0;
-reg rew_req_xlast;
-reg [ID_WIDTH-1:0] rew_id = 'h0;
+  reg [1:0] rew_transfer_id = 1'b0;
+  reg rew_req_xlast;
+  reg [ID_WIDTH-1:0] rew_id = 'h0;
 
-reg cur_transfer_id = 1'b0;
-reg cur_req_xlast;
+  reg cur_transfer_id = 1'b0;
+  reg cur_req_xlast;
 
-wire transfer_id_match;
-reg nx_completion_req_valid;
+  wire transfer_id_match;
+  reg nx_completion_req_valid;
 
-/*
- * Here we only need to count the number of bursts, which means we can ignore
- * the lower bits of the byte count. The last last burst may not contain the
- * maximum number of bytes, but the address_generator and data_mover will take
- * care that only the requested ammount of bytes is transfered.
- */
+  /*
+   * Here we only need to count the number of bursts, which means we can ignore
+   * the lower bits of the byte count. The last last burst may not contain the
+   * maximum number of bytes, but the address_generator and data_mover will take
+   * care that only the requested ammount of bytes is transfered.
+   */
 
-reg [BURSTS_PER_TRANSFER_WIDTH-1:0] burst_count = 'h00;
-reg [BURSTS_PER_TRANSFER_WIDTH-1:0] cur_burst_length = 'h00;
-reg [ID_WIDTH-1:0] id;
-wire [ID_WIDTH-1:0] id_next = inc_id(id);
-wire incr_en;
-wire incr_id;
+  reg [BURSTS_PER_TRANSFER_WIDTH-1:0] burst_count = 'h00;
+  reg [BURSTS_PER_TRANSFER_WIDTH-1:0] cur_burst_length = 'h00;
+  reg [ID_WIDTH-1:0] id;
+  wire [ID_WIDTH-1:0] id_next = inc_id(id);
+  wire incr_en;
+  wire incr_id;
 
-assign eot = burst_count == 'h00;
-assign request_id = id;
+  assign eot = burst_count == 'h00;
+  assign request_id = id;
 
-assign incr_en = (response_id != id_next) && (enable == 1'b1);
-assign incr_id = (state == STATE_GEN_ID) && (incr_en == 1'b1);
+  assign incr_en = (response_id != id_next) && (enable == 1'b1);
+  assign incr_id = (state == STATE_GEN_ID) && (incr_en == 1'b1);
 
-always @(posedge clk) begin
-  if (state == STATE_IDLE) begin
-    burst_count <= req_burst_count;
-  end else if (state == STATE_REWIND_ID) begin
-    burst_count <= cur_burst_length;
-  end else if (incr_id == 1'b1) begin
-    burst_count <= burst_count - 1'b1;
-  end
-end
-always @(posedge clk) begin
-  if (req_ready == 1'b1 & req_valid == 1'b1) begin
-    cur_req_xlast <= req_xlast;
-    cur_burst_length <= req_burst_count;
-  end
-end
-
-always @(posedge clk) begin
-  if (resetn == 1'b0) begin
-    id <= 'h0;
-  end else if (state == STATE_REWIND_ID) begin
-    id <= rew_id;
-  end else if (incr_id == 1'b1) begin
-    id <= id_next;
-  end
-end
-
-always @(posedge clk) begin
-  if (resetn == 1'b0) begin
-    req_ready <= 1'b0;
-  end else begin
-    req_ready <= (nx_state == STATE_IDLE || nx_state == STATE_CONSUME);
-  end
-end
-
-assign transfer_id_match = cur_transfer_id == rew_transfer_id[0];
-
-always @(posedge clk) begin
-  if (resetn == 1'b0) begin
-    cur_transfer_id <= 1'b0;
-  end else if (req_valid == 1'b1 && req_ready == 1'b1) begin
-    cur_transfer_id <= ~cur_transfer_id;
-  end
-end
-
-/*
- * Once rewind request is received we need to stop incrementing the burst ID.
- *
- * If the current segment matches the segment that was interrupted and
- * if it was a last segment we ignore consecutive segments until the last
- * segment is received, in other case we can jump to the next segment.
- *
- * If the current segment is newer than the one got interrupted and the
- * interrupted one was a last segment we need to replay the current
- * segment with the adjusted burst ID. If the interrupted segment was not last
- * we need to consume/ignore all segments until a last segment is received.
- *
- * Completion requests are generated for every segment that is
- * consumed/ignored. These are handled by the response_manager once the
- * interrupted segment got transferred to the destination.
- */
-always @(*) begin
-  nx_state = state;
-  nx_completion_req_valid = 0;
-  case (state)
-    STATE_IDLE: begin
-      if (rewind_req_valid == 1'b1 && rewind_req_ready == 1'b1) begin
-        nx_state = STATE_REWIND_ID;
-      end else if (req_valid == 1'b1) begin
-        nx_state = STATE_GEN_ID;
-      end
+  always @(posedge clk) begin
+    if (state == STATE_IDLE) begin
+      burst_count <= req_burst_count;
+    end else if (state == STATE_REWIND_ID) begin
+      burst_count <= cur_burst_length;
+    end else if (incr_id == 1'b1) begin
+      burst_count <= burst_count - 1'b1;
     end
-    STATE_GEN_ID: begin
-      if (rewind_req_valid == 1'b1 && rewind_req_ready == 1'b1) begin
-        nx_state = STATE_REWIND_ID;
-      end else if (eot == 1'b1 && incr_en == 1'b1) begin
-        nx_state = STATE_IDLE;
-      end
+  end
+  always @(posedge clk) begin
+    if (req_ready == 1'b1 & req_valid == 1'b1) begin
+      cur_req_xlast <= req_xlast;
+      cur_burst_length <= req_burst_count;
     end
-    STATE_REWIND_ID: begin
-      if (transfer_id_match) begin
-        if (rew_req_xlast) begin
-          nx_state = STATE_IDLE;
-        end else begin
-          nx_state = STATE_CONSUME;
-        end
-      end else begin
-        if (rew_req_xlast) begin
+  end
+
+  always @(posedge clk) begin
+    if (resetn == 1'b0) begin
+      id <= 'h0;
+    end else if (state == STATE_REWIND_ID) begin
+      id <= rew_id;
+    end else if (incr_id == 1'b1) begin
+      id <= id_next;
+    end
+  end
+
+  always @(posedge clk) begin
+    if (resetn == 1'b0) begin
+      req_ready <= 1'b0;
+    end else begin
+      req_ready <= (nx_state == STATE_IDLE || nx_state == STATE_CONSUME);
+    end
+  end
+
+  assign transfer_id_match = cur_transfer_id == rew_transfer_id[0];
+
+  always @(posedge clk) begin
+    if (resetn == 1'b0) begin
+      cur_transfer_id <= 1'b0;
+    end else if (req_valid == 1'b1 && req_ready == 1'b1) begin
+      cur_transfer_id <= ~cur_transfer_id;
+    end
+  end
+
+  /*
+   * Once rewind request is received we need to stop incrementing the burst ID.
+   *
+   * If the current segment matches the segment that was interrupted and
+   * if it was a last segment we ignore consecutive segments until the last
+   * segment is received, in other case we can jump to the next segment.
+   *
+   * If the current segment is newer than the one got interrupted and the
+   * interrupted one was a last segment we need to replay the current
+   * segment with the adjusted burst ID. If the interrupted segment was not last
+   * we need to consume/ignore all segments until a last segment is received.
+   *
+   * Completion requests are generated for every segment that is
+   * consumed/ignored. These are handled by the response_manager once the
+   * interrupted segment got transferred to the destination.
+   */
+  always @(*) begin
+    nx_state = state;
+    nx_completion_req_valid = 0;
+    case (state)
+      STATE_IDLE: begin
+        if (rewind_req_valid == 1'b1 && rewind_req_ready == 1'b1) begin
+          nx_state = STATE_REWIND_ID;
+        end else if (req_valid == 1'b1) begin
           nx_state = STATE_GEN_ID;
-        end else if (cur_req_xlast) begin
-          nx_state = STATE_IDLE;
-          nx_completion_req_valid = 1;
-        end else begin
-          nx_state = STATE_CONSUME;
-          nx_completion_req_valid = 1;
         end
       end
-    end
-    STATE_CONSUME: begin
-      if (req_valid) begin
-        nx_completion_req_valid = 1;
-        nx_state = STATE_WAIT_LAST;
+      STATE_GEN_ID: begin
+        if (rewind_req_valid == 1'b1 && rewind_req_ready == 1'b1) begin
+          nx_state = STATE_REWIND_ID;
+        end else if (eot == 1'b1 && incr_en == 1'b1) begin
+          nx_state = STATE_IDLE;
+        end
       end
-    end
-    STATE_WAIT_LAST:begin
-      if (cur_req_xlast) begin
+      STATE_REWIND_ID: begin
+        if (transfer_id_match) begin
+          if (rew_req_xlast) begin
+            nx_state = STATE_IDLE;
+          end else begin
+            nx_state = STATE_CONSUME;
+          end
+        end else begin
+          if (rew_req_xlast) begin
+            nx_state = STATE_GEN_ID;
+          end else if (cur_req_xlast) begin
+            nx_state = STATE_IDLE;
+            nx_completion_req_valid = 1;
+          end else begin
+            nx_state = STATE_CONSUME;
+            nx_completion_req_valid = 1;
+          end
+        end
+      end
+      STATE_CONSUME: begin
+        if (req_valid) begin
+          nx_completion_req_valid = 1;
+          nx_state = STATE_WAIT_LAST;
+        end
+      end
+      STATE_WAIT_LAST:begin
+        if (cur_req_xlast) begin
+          nx_state = STATE_IDLE;
+        end else begin
+          nx_state = STATE_CONSUME;
+        end
+      end
+
+      default: begin
         nx_state = STATE_IDLE;
-      end else begin
-        nx_state = STATE_CONSUME;
       end
+    endcase
+  end
+
+  always @(posedge clk) begin
+    if (resetn == 1'b0) begin
+      state <= STATE_IDLE;
+    end else begin
+      state <= nx_state;
     end
+  end
 
-    default: begin
-      nx_state = STATE_IDLE;
+  always @(posedge clk) begin
+    if (rewind_req_valid == 1'b1 && rewind_req_ready == 1'b1) begin
+      {rew_transfer_id, rew_req_xlast, rew_id} <= rewind_req_data;
     end
-  endcase
-end
-
-always @(posedge clk) begin
-  if (resetn == 1'b0) begin
-    state <= STATE_IDLE;
-  end else begin
-    state <= nx_state;
   end
-end
 
-always @(posedge clk) begin
-  if (rewind_req_valid == 1'b1 && rewind_req_ready == 1'b1) begin
-    {rew_transfer_id, rew_req_xlast, rew_id} <= rewind_req_data;
+  always @(posedge clk) begin
+    if (resetn == 1'b0) begin
+      completion_req_valid <= 1'b0;
+    end else begin
+      completion_req_valid <= nx_completion_req_valid;
+    end
   end
-end
+  assign completion_req_last = cur_req_xlast;
+  assign completion_transfer_id = rew_transfer_id;
 
-always @(posedge clk) begin
-  if (resetn == 1'b0) begin
-    completion_req_valid <= 1'b0;
-  end else begin
-    completion_req_valid <= nx_completion_req_valid;
-  end
-end
-assign completion_req_last = cur_req_xlast;
-assign completion_transfer_id = rew_transfer_id;
+  assign rewind_state = (state == STATE_REWIND_ID);
+  assign rewind_req_ready = completion_req_ready;
 
-assign rewind_state = (state == STATE_REWIND_ID);
-assign rewind_req_ready = completion_req_ready;
-
-assign abort_req = (state == STATE_REWIND_ID) && !rew_req_xlast && !cur_req_xlast;
+  assign abort_req = (state == STATE_REWIND_ID) && !rew_req_xlast && !cur_req_xlast;
 
 endmodule
diff --git a/library/axi_dmac/response_generator.v b/library/axi_dmac/response_generator.v
index 2d0493dea..d17f6a7a3 100644
--- a/library/axi_dmac/response_generator.v
+++ b/library/axi_dmac/response_generator.v
@@ -37,8 +37,8 @@
 
 module response_generator #(
 
-  parameter ID_WIDTH = 3)(
-
+  parameter ID_WIDTH = 3
+) (
   input clk,
   input resetn,
 
@@ -59,28 +59,28 @@ module response_generator #(
 `include "inc_id.vh"
 `include "resp.vh"
 
-assign resp_resp = RESP_OKAY;
-assign resp_eot = eot;
+  assign resp_resp = RESP_OKAY;
+  assign resp_eot = eot;
 
-assign resp_valid = request_id != response_id && enabled;
+  assign resp_valid = request_id != response_id && enabled;
 
-// We have to wait for all responses before we can disable the response handler
-always @(posedge clk) begin
-  if (resetn == 1'b0) begin
-    enabled <= 1'b0;
-  end else if (enable == 1'b1) begin
-    enabled <= 1'b1;
-  end else if (request_id == response_id) begin
-    enabled <= 1'b0;
+  // We have to wait for all responses before we can disable the response handler
+  always @(posedge clk) begin
+    if (resetn == 1'b0) begin
+      enabled <= 1'b0;
+    end else if (enable == 1'b1) begin
+      enabled <= 1'b1;
+    end else if (request_id == response_id) begin
+      enabled <= 1'b0;
+    end
   end
-end
 
-always @(posedge clk) begin
-  if (resetn == 1'b0) begin
-    response_id <= 'h0;
-  end else if (resp_valid == 1'b1 && resp_ready == 1'b1) begin
-    response_id <= inc_id(response_id);
+  always @(posedge clk) begin
+    if (resetn == 1'b0) begin
+      response_id <= 'h0;
+    end else if (resp_valid == 1'b1 && resp_ready == 1'b1) begin
+      response_id <= inc_id(response_id);
+    end
   end
-end
 
 endmodule
diff --git a/library/axi_dmac/response_handler.v b/library/axi_dmac/response_handler.v
index a42099299..a45f29edf 100644
--- a/library/axi_dmac/response_handler.v
+++ b/library/axi_dmac/response_handler.v
@@ -37,8 +37,8 @@
 
 module response_handler #(
 
-  parameter ID_WIDTH = 3)(
-
+  parameter ID_WIDTH = 3
+) (
   input clk,
   input resetn,
 
@@ -60,34 +60,34 @@ module response_handler #(
   output [1:0] resp_resp
 );
 
-`include "resp.vh"
-`include "inc_id.vh"
+  `include "resp.vh"
+  `include "inc_id.vh"
 
-assign resp_resp = bresp;
-assign resp_eot = eot;
+  assign resp_resp = bresp;
+  assign resp_eot = eot;
 
-wire active = id != request_id;
+  wire active = id != request_id;
 
-assign bready = active && resp_ready;
-assign resp_valid = active && bvalid;
+  assign bready = active && resp_ready;
+  assign resp_valid = active && bvalid;
 
-// We have to wait for all responses before we can disable the response handler
-always @(posedge clk) begin
-  if (resetn == 1'b0) begin
-    enabled <= 1'b0;
-  end else if (enable == 1'b1) begin
-      enabled <= 1'b1;
-  end else if (request_id == id) begin
+  // We have to wait for all responses before we can disable the response handler
+  always @(posedge clk) begin
+    if (resetn == 1'b0) begin
       enabled <= 1'b0;
+    end else if (enable == 1'b1) begin
+        enabled <= 1'b1;
+    end else if (request_id == id) begin
+        enabled <= 1'b0;
+    end
   end
-end
 
-always @(posedge clk) begin
-  if (resetn == 1'b0) begin
-    id <= 'h0;
-  end else if (bready == 1'b1 && bvalid == 1'b1) begin
-    id <= inc_id(id);
+  always @(posedge clk) begin
+    if (resetn == 1'b0) begin
+      id <= 'h0;
+    end else if (bready == 1'b1 && bvalid == 1'b1) begin
+      id <= inc_id(id);
+    end
   end
-end
 
 endmodule
diff --git a/library/axi_dmac/splitter.v b/library/axi_dmac/splitter.v
index 04f1287d3..7f10dcc72 100644
--- a/library/axi_dmac/splitter.v
+++ b/library/axi_dmac/splitter.v
@@ -37,8 +37,8 @@
 
 module splitter #(
 
-  parameter NUM_M = 2)(
-
+  parameter NUM_M = 2
+) (
   input clk,
   input resetn,
 
@@ -49,21 +49,20 @@ module splitter #(
   input [NUM_M-1:0] m_ready
 );
 
-reg [NUM_M-1:0] acked;
+  reg [NUM_M-1:0] acked;
 
-assign s_ready = &(m_ready | acked);
-assign m_valid = s_valid ? ~acked : {NUM_M{1'b0}};
+  assign s_ready = &(m_ready | acked);
+  assign m_valid = s_valid ? ~acked : {NUM_M{1'b0}};
 
-always @(posedge clk)
-begin
-  if (resetn == 1'b0) begin
-    acked <= {NUM_M{1'b0}};
-  end else begin
-    if (s_valid & s_ready)
+  always @(posedge clk) begin
+    if (resetn == 1'b0) begin
       acked <= {NUM_M{1'b0}};
-    else
-      acked <= acked | (m_ready & m_valid);
+    end else begin
+      if (s_valid & s_ready)
+        acked <= {NUM_M{1'b0}};
+      else
+        acked <= acked | (m_ready & m_valid);
+    end
   end
-end
 
 endmodule
diff --git a/library/axi_dmac/src_axi_mm.v b/library/axi_dmac/src_axi_mm.v
index e50007642..abdb275b8 100644
--- a/library/axi_dmac/src_axi_mm.v
+++ b/library/axi_dmac/src_axi_mm.v
@@ -42,8 +42,8 @@ module src_axi_mm #(
   parameter DMA_ADDR_WIDTH = 32,
   parameter BYTES_PER_BEAT_WIDTH = 3,
   parameter BEATS_PER_BURST_WIDTH = 4,
-  parameter AXI_LENGTH_WIDTH = 8)(
-
+  parameter AXI_LENGTH_WIDTH = 8
+) (
   input                           m_axi_aclk,
   input                           m_axi_aresetn,
 
@@ -53,11 +53,11 @@ module src_axi_mm #(
   input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
   input [BYTES_PER_BEAT_WIDTH-1:0]  req_last_beat_bytes,
 
-  input                           enable,
-  output reg                      enabled = 1'b0,
+  input                            enable,
+  output reg                       enabled = 1'b0,
 
-  output                             bl_valid,
-  input                              bl_ready,
+  output                           bl_valid,
+  input                            bl_ready,
   output [BEATS_PER_BURST_WIDTH-1:0] measured_last_burst_length,
 /*
   output                          response_valid,
@@ -65,17 +65,17 @@ module src_axi_mm #(
   output [1:0]                    response_resp,
 */
 
-  input  [ID_WIDTH-1:0]         request_id,
-  output [ID_WIDTH-1:0]         response_id,
+  input  [ID_WIDTH-1:0]            request_id,
+  output [ID_WIDTH-1:0]            response_id,
 
-  output [ID_WIDTH-1:0]         data_id,
-  output [ID_WIDTH-1:0]         address_id,
-  input                           address_eot,
+  output [ID_WIDTH-1:0]            data_id,
+  output [ID_WIDTH-1:0]            address_id,
+  input                            address_eot,
 
-  output                          fifo_valid,
-  output [DMA_DATA_WIDTH-1:0]   fifo_data,
+  output                           fifo_valid,
+  output [DMA_DATA_WIDTH-1:0]      fifo_data,
   output [BYTES_PER_BEAT_WIDTH-1:0] fifo_valid_bytes,
-  output                          fifo_last,
+  output                           fifo_last,
 
   // Read address
   input                            m_axi_arready,
@@ -88,154 +88,149 @@ module src_axi_mm #(
   output [ 3:0]                    m_axi_arcache,
 
   // Read data and response
-  input  [DMA_DATA_WIDTH-1:0]    m_axi_rdata,
+  input  [DMA_DATA_WIDTH-1:0]      m_axi_rdata,
   output                           m_axi_rready,
   input                            m_axi_rvalid,
   input                            m_axi_rlast,
   input  [ 1:0]                    m_axi_rresp
 );
 
-`include "inc_id.vh"
+  `include "inc_id.vh"
 
-reg [ID_WIDTH-1:0] id = 'h00;
+  reg [ID_WIDTH-1:0] id = 'h00;
 
-wire address_enabled;
-wire req_ready_ag;
-wire req_valid_ag;
-wire bl_ready_ag;
-wire bl_valid_ag;
+  wire address_enabled;
+  wire req_ready_ag;
+  wire req_valid_ag;
+  wire bl_ready_ag;
+  wire bl_valid_ag;
 
-assign data_id = id;
-assign response_id = id;
+  assign data_id = id;
+  assign response_id = id;
 
-assign measured_last_burst_length = req_last_burst_length;
+  assign measured_last_burst_length = req_last_burst_length;
 
-reg [BYTES_PER_BEAT_WIDTH-1:0] last_beat_bytes;
-reg [BYTES_PER_BEAT_WIDTH-1:0] last_beat_bytes_mem[0:2**ID_WIDTH-1];
+  reg [BYTES_PER_BEAT_WIDTH-1:0] last_beat_bytes;
+  reg [BYTES_PER_BEAT_WIDTH-1:0] last_beat_bytes_mem[0:2**ID_WIDTH-1];
 
-assign fifo_valid_bytes = last_beat_bytes_mem[data_id];
+  assign fifo_valid_bytes = last_beat_bytes_mem[data_id];
 
-always @(posedge m_axi_aclk) begin
-  if (bl_ready_ag == 1'b1 && bl_valid_ag == 1'b1) begin
-    last_beat_bytes <= req_last_beat_bytes;
+  always @(posedge m_axi_aclk) begin
+    if (bl_ready_ag == 1'b1 && bl_valid_ag == 1'b1) begin
+      last_beat_bytes <= req_last_beat_bytes;
+    end
   end
-end
 
-
-always @(posedge m_axi_aclk) begin
-  last_beat_bytes_mem[address_id] <= address_eot ? last_beat_bytes :
-                                                   {BYTES_PER_BEAT_WIDTH{1'b1}};
-end
-
-splitter #(
-  .NUM_M(3)
-) i_req_splitter (
-  .clk(m_axi_aclk),
-  .resetn(m_axi_aresetn),
-  .s_valid(req_valid),
-  .s_ready(req_ready),
-  .m_valid({
-    bl_valid,
-    bl_valid_ag,
-    req_valid_ag
-  }),
-  .m_ready({
-    bl_ready,
-    bl_ready_ag,
-    req_ready_ag
-  })
-);
-
-address_generator #(
-  .ID_WIDTH(ID_WIDTH),
-  .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH),
-  .BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH),
-  .DMA_DATA_WIDTH(DMA_DATA_WIDTH),
-  .LENGTH_WIDTH(AXI_LENGTH_WIDTH),
-  .DMA_ADDR_WIDTH(DMA_ADDR_WIDTH)
-) i_addr_gen (
-  .clk(m_axi_aclk),
-  .resetn(m_axi_aresetn),
-
-  .enable(enable),
-  .enabled(address_enabled),
-
-  .request_id(request_id),
-  .id(address_id),
-
-  .req_valid(req_valid_ag),
-  .req_ready(req_ready_ag),
-  .req_address(req_address),
-
-  .bl_valid(bl_valid_ag),
-  .bl_ready(bl_ready_ag),
-  .measured_last_burst_length(req_last_burst_length),
-
-  .eot(address_eot),
-
-  .addr_ready(m_axi_arready),
-  .addr_valid(m_axi_arvalid),
-  .addr(m_axi_araddr),
-  .len(m_axi_arlen),
-  .size(m_axi_arsize),
-  .burst(m_axi_arburst),
-  .prot(m_axi_arprot),
-  .cache(m_axi_arcache)
-);
-
-assign fifo_valid = m_axi_rvalid;
-assign fifo_data = m_axi_rdata;
-assign fifo_last = m_axi_rlast;
-
-/*
- * There is a requirement that data_id <= address_id (modulo 2**ID_WIDTH).  We
- * know that we will never receive data before we have requested it so there is
- * an implicit dependency between data_id and address_id and no need to
- * explicitly track it.
- */
-always @(posedge m_axi_aclk) begin
-  if (m_axi_aresetn == 1'b0) begin
-    id <= 'h00;
-  end else if (m_axi_rvalid == 1'b1 && m_axi_rlast == 1'b1) begin
-    id <= inc_id(id);
+  always @(posedge m_axi_aclk) begin
+    last_beat_bytes_mem[address_id] <= address_eot ? last_beat_bytes :
+                                                     {BYTES_PER_BEAT_WIDTH{1'b1}};
   end
-end
 
-/*
- * We won't be receiving data before we've requested it and we won't request
- * data unless there is room in the store-and-forward memory.
- */
-assign m_axi_rready = 1'b1;
+  splitter #(
+    .NUM_M(3)
+  ) i_req_splitter (
+    .clk(m_axi_aclk),
+    .resetn(m_axi_aresetn),
+    .s_valid(req_valid),
+    .s_ready(req_ready),
+    .m_valid({
+      bl_valid,
+      bl_valid_ag,
+      req_valid_ag}),
+    .m_ready({
+      bl_ready,
+      bl_ready_ag,
+      req_ready_ag}));
 
-/*
- * We need to complete all bursts for which an address has been put onto the
- * AXI-MM interface.
- */
-always @(posedge m_axi_aclk) begin
-  if (m_axi_aresetn == 1'b0) begin
-    enabled <= 1'b0;
-  end else if (address_enabled == 1'b1) begin
-    enabled <= 1'b1;
-  end else if (id == address_id) begin
-    enabled <= 1'b0;
+  address_generator #(
+    .ID_WIDTH(ID_WIDTH),
+    .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH),
+    .BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH),
+    .DMA_DATA_WIDTH(DMA_DATA_WIDTH),
+    .LENGTH_WIDTH(AXI_LENGTH_WIDTH),
+    .DMA_ADDR_WIDTH(DMA_ADDR_WIDTH)
+  ) i_addr_gen (
+    .clk(m_axi_aclk),
+    .resetn(m_axi_aresetn),
+
+    .enable(enable),
+    .enabled(address_enabled),
+
+    .request_id(request_id),
+    .id(address_id),
+
+    .req_valid(req_valid_ag),
+    .req_ready(req_ready_ag),
+    .req_address(req_address),
+
+    .bl_valid(bl_valid_ag),
+    .bl_ready(bl_ready_ag),
+    .measured_last_burst_length(req_last_burst_length),
+
+    .eot(address_eot),
+
+    .addr_ready(m_axi_arready),
+    .addr_valid(m_axi_arvalid),
+    .addr(m_axi_araddr),
+    .len(m_axi_arlen),
+    .size(m_axi_arsize),
+    .burst(m_axi_arburst),
+    .prot(m_axi_arprot),
+    .cache(m_axi_arcache));
+
+  assign fifo_valid = m_axi_rvalid;
+  assign fifo_data = m_axi_rdata;
+  assign fifo_last = m_axi_rlast;
+
+  /*
+   * There is a requirement that data_id <= address_id (modulo 2**ID_WIDTH).  We
+   * know that we will never receive data before we have requested it so there is
+   * an implicit dependency between data_id and address_id and no need to
+   * explicitly track it.
+   */
+  always @(posedge m_axi_aclk) begin
+    if (m_axi_aresetn == 1'b0) begin
+      id <= 'h00;
+    end else if (m_axi_rvalid == 1'b1 && m_axi_rlast == 1'b1) begin
+      id <= inc_id(id);
+    end
   end
-end
 
-/* TODO
-`include "resp.vh"
+  /*
+   * We won't be receiving data before we've requested it and we won't request
+   * data unless there is room in the store-and-forward memory.
+   */
+  assign m_axi_rready = 1'b1;
 
-assign response_valid = 1'b0;
-assign response_resp = RESP_OKAY;
-
-reg [1:0] rresp;
-
-always @(posedge m_axi_aclk)
-begin
-  if (m_axi_rvalid && m_axi_rready) begin
-    if (m_axi_rresp != 2'b0)
-      rresp <= m_axi_rresp;
+  /*
+   * We need to complete all bursts for which an address has been put onto the
+   * AXI-MM interface.
+   */
+  always @(posedge m_axi_aclk) begin
+    if (m_axi_aresetn == 1'b0) begin
+      enabled <= 1'b0;
+    end else if (address_enabled == 1'b1) begin
+      enabled <= 1'b1;
+    end else if (id == address_id) begin
+      enabled <= 1'b0;
+    end
   end
-end
-*/
+
+  /* TODO
+  `include "resp.vh"
+
+  assign response_valid = 1'b0;
+  assign response_resp = RESP_OKAY;
+
+  reg [1:0] rresp;
+
+  always @(posedge m_axi_aclk)
+  begin
+    if (m_axi_rvalid && m_axi_rready) begin
+      if (m_axi_rresp != 2'b0)
+        rresp <= m_axi_rresp;
+    end
+  end
+  */
 
 endmodule
diff --git a/library/axi_dmac/src_axi_stream.v b/library/axi_dmac/src_axi_stream.v
index 7901bce26..fe64609e9 100644
--- a/library/axi_dmac/src_axi_stream.v
+++ b/library/axi_dmac/src_axi_stream.v
@@ -40,8 +40,8 @@ module src_axi_stream #(
   parameter ID_WIDTH = 3,
   parameter S_AXIS_DATA_WIDTH = 64,
   parameter LENGTH_WIDTH = 24,
-  parameter BEATS_PER_BURST_WIDTH = 4)(
-
+  parameter BEATS_PER_BURST_WIDTH = 4
+) (
   input s_axis_aclk,
   input s_axis_aresetn,
 
@@ -84,52 +84,51 @@ module src_axi_stream #(
   input req_xlast
 );
 
-assign enabled = enable;
+  assign enabled = enable;
 
-data_mover # (
-  .ID_WIDTH(ID_WIDTH),
-  .DATA_WIDTH(S_AXIS_DATA_WIDTH),
-  .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH),
-  .ALLOW_ABORT(1)
-) i_data_mover (
-  .clk(s_axis_aclk),
-  .resetn(s_axis_aresetn),
+  data_mover #(
+    .ID_WIDTH(ID_WIDTH),
+    .DATA_WIDTH(S_AXIS_DATA_WIDTH),
+    .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH),
+    .ALLOW_ABORT(1)
+  ) i_data_mover (
+    .clk(s_axis_aclk),
+    .resetn(s_axis_aresetn),
 
-  .xfer_req(s_axis_xfer_req),
+    .xfer_req(s_axis_xfer_req),
 
-  .request_id(request_id),
-  .response_id(response_id),
-  .eot(eot),
+    .request_id(request_id),
+    .response_id(response_id),
+    .eot(eot),
 
-  .rewind_req_valid(rewind_req_valid),
-  .rewind_req_ready(rewind_req_ready),
-  .rewind_req_data(rewind_req_data),
+    .rewind_req_valid(rewind_req_valid),
+    .rewind_req_ready(rewind_req_ready),
+    .rewind_req_data(rewind_req_data),
 
-  .bl_valid(bl_valid),
-  .bl_ready(bl_ready),
-  .measured_last_burst_length(measured_last_burst_length),
+    .bl_valid(bl_valid),
+    .bl_ready(bl_ready),
+    .measured_last_burst_length(measured_last_burst_length),
 
-  .block_descr_to_dst(block_descr_to_dst),
+    .block_descr_to_dst(block_descr_to_dst),
 
-  .source_id(source_id),
-  .source_eot(source_eot),
+    .source_id(source_id),
+    .source_eot(source_eot),
 
-  .req_valid(req_valid),
-  .req_ready(req_ready),
-  .req_last_burst_length(req_last_burst_length),
-  .req_sync_transfer_start(req_sync_transfer_start),
-  .req_xlast(req_xlast),
+    .req_valid(req_valid),
+    .req_ready(req_ready),
+    .req_last_burst_length(req_last_burst_length),
+    .req_sync_transfer_start(req_sync_transfer_start),
+    .req_xlast(req_xlast),
 
-  .s_axi_valid(s_axis_valid),
-  .s_axi_ready(s_axis_ready),
-  .s_axi_data(s_axis_data),
-  .s_axi_last(s_axis_last),
-  .s_axi_sync(s_axis_user[0]),
+    .s_axi_valid(s_axis_valid),
+    .s_axi_ready(s_axis_ready),
+    .s_axi_data(s_axis_data),
+    .s_axi_last(s_axis_last),
+    .s_axi_sync(s_axis_user[0]),
 
-  .m_axi_valid(fifo_valid),
-  .m_axi_data(fifo_data),
-  .m_axi_last(fifo_last),
-  .m_axi_partial_burst(fifo_partial_burst)
-);
+    .m_axi_valid(fifo_valid),
+    .m_axi_data(fifo_data),
+    .m_axi_last(fifo_last),
+    .m_axi_partial_burst(fifo_partial_burst));
 
 endmodule
diff --git a/library/axi_dmac/src_fifo_inf.v b/library/axi_dmac/src_fifo_inf.v
index 79409b35f..6a04bbd04 100644
--- a/library/axi_dmac/src_fifo_inf.v
+++ b/library/axi_dmac/src_fifo_inf.v
@@ -39,8 +39,8 @@ module src_fifo_inf #(
 
   parameter ID_WIDTH = 3,
   parameter DATA_WIDTH = 64,
-  parameter BEATS_PER_BURST_WIDTH = 4)(
-
+  parameter BEATS_PER_BURST_WIDTH = 4
+) (
   input clk,
   input resetn,
 
@@ -71,55 +71,54 @@ module src_fifo_inf #(
   input req_sync_transfer_start
 );
 
-wire ready;
-wire valid;
+  wire ready;
+  wire valid;
 
-assign enabled = enable;
+  assign enabled = enable;
 
-assign valid = en & ready;
+  assign valid = en & ready;
 
-always @(posedge clk)
-begin
-  if (enable) begin
-    overflow <= en & ~ready;
-  end else begin
-    overflow <= en;
+  always @(posedge clk)
+  begin
+    if (enable) begin
+      overflow <= en & ~ready;
+    end else begin
+      overflow <= en;
+    end
   end
-end
 
-data_mover # (
-  .ID_WIDTH(ID_WIDTH),
-  .DATA_WIDTH(DATA_WIDTH),
-  .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH)
-) i_data_mover (
-  .clk(clk),
-  .resetn(resetn),
+  data_mover #(
+    .ID_WIDTH(ID_WIDTH),
+    .DATA_WIDTH(DATA_WIDTH),
+    .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH)
+  ) i_data_mover (
+    .clk(clk),
+    .resetn(resetn),
 
-  .xfer_req(xfer_req),
+    .xfer_req(xfer_req),
 
-  .request_id(request_id),
-  .response_id(response_id),
-  .eot(eot),
+    .request_id(request_id),
+    .response_id(response_id),
+    .eot(eot),
 
-  .bl_valid(bl_valid),
-  .bl_ready(bl_ready),
-  .measured_last_burst_length(measured_last_burst_length),
+    .bl_valid(bl_valid),
+    .bl_ready(bl_ready),
+    .measured_last_burst_length(measured_last_burst_length),
 
-  .req_valid(req_valid),
-  .req_ready(req_ready),
-  .req_last_burst_length(req_last_burst_length),
-  .req_sync_transfer_start(req_sync_transfer_start),
-  .req_xlast(1'b0),
+    .req_valid(req_valid),
+    .req_ready(req_ready),
+    .req_last_burst_length(req_last_burst_length),
+    .req_sync_transfer_start(req_sync_transfer_start),
+    .req_xlast(1'b0),
 
-  .s_axi_ready(ready),
-  .s_axi_valid(valid),
-  .s_axi_data(din),
-  .s_axi_sync(sync),
-  .s_axi_last(1'b0),
+    .s_axi_ready(ready),
+    .s_axi_valid(valid),
+    .s_axi_data(din),
+    .s_axi_sync(sync),
+    .s_axi_last(1'b0),
 
-  .m_axi_valid(fifo_valid),
-  .m_axi_data(fifo_data),
-  .m_axi_last(fifo_last)
-);
+    .m_axi_valid(fifo_valid),
+    .m_axi_data(fifo_data),
+    .m_axi_last(fifo_last));
 
 endmodule
diff --git a/library/axi_dmac/tb/axi_read_slave.v b/library/axi_dmac/tb/axi_read_slave.v
index 9d5ed0383..8c8d6d39f 100644
--- a/library/axi_dmac/tb/axi_read_slave.v
+++ b/library/axi_dmac/tb/axi_read_slave.v
@@ -60,42 +60,41 @@ module axi_read_slave #(
   output rlast
 );
 
-reg [DATA_WIDTH-1:0] data = 'h00;
+  reg [DATA_WIDTH-1:0] data = 'h00;
 
-wire [31:0] beat_addr;
+  wire [31:0] beat_addr;
 
-assign rresp = 2'b00;
-assign rdata = data;
+  assign rresp = 2'b00;
+  assign rdata = data;
 
-always @(*) begin: gen_data
-  integer i;
-  for (i = 0; i < DATA_WIDTH; i = i + 8) begin
-    data[i+:8] <= beat_addr[7:0] + i / 8;
+  always @(*) begin: gen_data
+    integer i;
+    for (i = 0; i < DATA_WIDTH; i = i + 8) begin
+      data[i+:8] <= beat_addr[7:0] + i / 8;
+    end
   end
-end
 
-axi_slave #(
-  .DATA_WIDTH(DATA_WIDTH),
-  .ACCEPTANCE(READ_ACCEPTANCE),
-  .MIN_LATENCY(MIN_LATENCY),
-  .MAX_LATENCY(MAX_LATENCY)
-) i_axi_slave (
-  .clk(clk),
-  .reset(reset),
+  axi_slave #(
+    .DATA_WIDTH(DATA_WIDTH),
+    .ACCEPTANCE(READ_ACCEPTANCE),
+    .MIN_LATENCY(MIN_LATENCY),
+    .MAX_LATENCY(MAX_LATENCY)
+  ) i_axi_slave (
+    .clk(clk),
+    .reset(reset),
 
-  .valid(arvalid),
-  .ready(arready),
-  .addr(araddr),
-  .len(arlen),
-  .size(arsize),
-  .burst(arburst),
-  .prot(arprot),
-  .cache(arcache),
+    .valid(arvalid),
+    .ready(arready),
+    .addr(araddr),
+    .len(arlen),
+    .size(arsize),
+    .burst(arburst),
+    .prot(arprot),
+    .cache(arcache),
 
-  .beat_stb(rvalid),
-  .beat_ack(rvalid & rready),
-  .beat_last(rlast),
-  .beat_addr(beat_addr)
-);
+    .beat_stb(rvalid),
+    .beat_ack(rvalid & rready),
+    .beat_last(rlast),
+    .beat_addr(beat_addr));
 
 endmodule
diff --git a/library/axi_dmac/tb/axi_slave.v b/library/axi_dmac/tb/axi_slave.v
index 4d1003285..aa2191a47 100644
--- a/library/axi_dmac/tb/axi_slave.v
+++ b/library/axi_dmac/tb/axi_slave.v
@@ -59,55 +59,55 @@ module axi_slave #(
   output beat_last
 );
 
-reg [31:0] timestamp = 'h00;
+  reg [31:0] timestamp = 'h00;
 
-always @(posedge clk) begin
-  if (reset == 1'b1) begin
-    timestamp <= 'h00;
-  end else begin
-    timestamp <= timestamp + 1'b1;
-  end
-end
-
-reg [32+32+8-1:0] req_fifo[0:15];
-reg [3:0] req_fifo_rd = 'h00;
-reg [3:0] req_fifo_wr = 'h00;
-wire [3:0] req_fifo_level = req_fifo_wr - req_fifo_rd;
-
-assign ready = req_fifo_level < ACCEPTANCE;
-
-always @(posedge clk) begin
-  if (reset == 1'b1) begin
-    req_fifo_wr <= 'h00;
-  end else begin
-    if (valid == 1'b1 && ready == 1'b1) begin
-      req_fifo[req_fifo_wr][71:40] <= timestamp + {$random} % (MAX_LATENCY - MIN_LATENCY + 1) + MIN_LATENCY;
-      req_fifo[req_fifo_wr][39:0] <= {addr,len};
-      req_fifo_wr <= req_fifo_wr + 1'b1;
+  always @(posedge clk) begin
+    if (reset == 1'b1) begin
+      timestamp <= 'h00;
+    end else begin
+      timestamp <= timestamp + 1'b1;
     end
   end
-end
 
-reg [7:0] beat_counter = 'h00;
+  reg [32+32+8-1:0] req_fifo[0:15];
+  reg [3:0] req_fifo_rd = 'h00;
+  reg [3:0] req_fifo_wr = 'h00;
+  wire [3:0] req_fifo_level = req_fifo_wr - req_fifo_rd;
 
-assign beat_stb = req_fifo_level != 0 && timestamp > req_fifo[req_fifo_rd][71:40];
-assign beat_last = beat_stb ? beat_counter == req_fifo[req_fifo_rd][0+:8] : 1'b0;
-assign beat_addr = req_fifo[req_fifo_rd][8+:32] + beat_counter * DATA_WIDTH / 8;
+  assign ready = req_fifo_level < ACCEPTANCE;
 
-always @(posedge clk) begin
-  if (reset == 1'b1) begin
-    beat_counter <= 'h00;
-    req_fifo_rd <= 'h00;
-  end else begin
-    if (beat_ack == 1'b1) begin
-      if (beat_last == 1'b1) begin
-        beat_counter <= 'h00;
-        req_fifo_rd <= req_fifo_rd + 1'b1;
-      end else begin
-        beat_counter <= beat_counter + 1'b1;
+  always @(posedge clk) begin
+    if (reset == 1'b1) begin
+      req_fifo_wr <= 'h00;
+    end else begin
+      if (valid == 1'b1 && ready == 1'b1) begin
+        req_fifo[req_fifo_wr][71:40] <= timestamp + {$random} % (MAX_LATENCY - MIN_LATENCY + 1) + MIN_LATENCY;
+        req_fifo[req_fifo_wr][39:0] <= {addr,len};
+        req_fifo_wr <= req_fifo_wr + 1'b1;
+      end
+    end
+  end
+
+  reg [7:0] beat_counter = 'h00;
+
+  assign beat_stb = req_fifo_level != 0 && timestamp > req_fifo[req_fifo_rd][71:40];
+  assign beat_last = beat_stb ? beat_counter == req_fifo[req_fifo_rd][0+:8] : 1'b0;
+  assign beat_addr = req_fifo[req_fifo_rd][8+:32] + beat_counter * DATA_WIDTH / 8;
+
+  always @(posedge clk) begin
+    if (reset == 1'b1) begin
+      beat_counter <= 'h00;
+      req_fifo_rd <= 'h00;
+    end else begin
+      if (beat_ack == 1'b1) begin
+        if (beat_last == 1'b1) begin
+          beat_counter <= 'h00;
+          req_fifo_rd <= req_fifo_rd + 1'b1;
+        end else begin
+          beat_counter <= beat_counter + 1'b1;
+        end
       end
     end
   end
-end
 
 endmodule
diff --git a/library/axi_dmac/tb/axi_write_slave.v b/library/axi_dmac/tb/axi_write_slave.v
index e8595edec..646bafdbd 100644
--- a/library/axi_dmac/tb/axi_write_slave.v
+++ b/library/axi_dmac/tb/axi_write_slave.v
@@ -62,84 +62,83 @@ module axi_write_slave #(
   output [1:0] bresp
 );
 
-wire beat_last;
+  wire beat_last;
 
-axi_slave #(
-  .ACCEPTANCE(WRITE_ACCEPTANCE)
-) i_axi_slave (
-  .clk(clk),
-  .reset(reset),
+  axi_slave #(
+    .ACCEPTANCE(WRITE_ACCEPTANCE)
+  ) i_axi_slave (
+    .clk(clk),
+    .reset(reset),
 
-  .valid(awvalid),
-  .ready(awready),
-  .addr(awaddr),
-  .len(awlen),
-  .size(awsize),
-  .burst(awburst),
-  .prot(awprot),
-  .cache(awcache),
+    .valid(awvalid),
+    .ready(awready),
+    .addr(awaddr),
+    .len(awlen),
+    .size(awsize),
+    .burst(awburst),
+    .prot(awprot),
+    .cache(awcache),
 
-  .beat_stb(wready),
-  .beat_ack(wvalid & wready),
-  .beat_last(beat_last)
-);
+    .beat_stb(wready),
+    .beat_ack(wvalid & wready),
+    .beat_last(beat_last));
 
-reg [4:0] resp_count = 'h00;
-wire [4:0] resp_count_next;
-reg [DATA_WIDTH-1:0] data_cmp = 'h00;
-reg failed = 'b0;
+  reg [4:0] resp_count = 'h00;
+  wire [4:0] resp_count_next;
+  reg [DATA_WIDTH-1:0] data_cmp = 'h00;
+  reg failed = 'b0;
 
-assign bresp = 2'b00;
+  assign bresp = 2'b00;
 
-wire resp_count_dec = bvalid & bready;
-wire resp_count_inc = wvalid & wready & beat_last;
-assign resp_count_next = resp_count - resp_count_dec + resp_count_inc;
+  wire resp_count_dec = bvalid & bready;
+  wire resp_count_inc = wvalid & wready & beat_last;
+  assign resp_count_next = resp_count - resp_count_dec + resp_count_inc;
 
-always @(posedge clk) begin
-  if (reset == 1'b1) begin
-    resp_count <= 'h00;
-  end else begin
-    resp_count <= resp_count - resp_count_dec + resp_count_inc;
-  end
-end
-
-always @(posedge clk) begin
-  if (reset == 1'b1) begin
-    bvalid <= 1'b0;
-  end else if (bvalid == 1'b0 || bready == 1'b1) begin
-    if (resp_count_next != 'h00) begin
-      bvalid <= {$random} % 4 == 0;
+  always @(posedge clk) begin
+    if (reset == 1'b1) begin
+      resp_count <= 'h00;
     end else begin
+      resp_count <= resp_count - resp_count_dec + resp_count_inc;
+    end
+  end
+
+  always @(posedge clk) begin
+    if (reset == 1'b1) begin
       bvalid <= 1'b0;
-    end
-  end
-end
-
-integer byte_count;
-
-always @(*) begin: count
-  integer i;
-  byte_count = 0;
-  for (i = 0; i < DATA_WIDTH / 8; i = i + 1) begin
-    byte_count = byte_count + wstrb[i];
-  end
-end
-
-always @(posedge clk) begin: gen_data_cmp
-  integer i;
-  if (reset) begin
-    for (i = 0; i < DATA_WIDTH; i = i + 8) begin
-      data_cmp[i+:8] <= i/8;
-    end
-    failed <= 'b0;
-  end else if (wvalid & wready) begin
-    for (i = 0; i < DATA_WIDTH; i = i + 8) begin
-      if (data_cmp[i+:8] !== wdata[i+:8] && wstrb[i/8] == 1'b1) begin
-        failed <= 1'b1;
+    end else if (bvalid == 1'b0 || bready == 1'b1) begin
+      if (resp_count_next != 'h00) begin
+        bvalid <= {$random} % 4 == 0;
+      end else begin
+        bvalid <= 1'b0;
+      end
+    end
+  end
+
+  integer byte_count;
+
+  always @(*) begin: count
+    integer i;
+    byte_count = 0;
+    for (i = 0; i < DATA_WIDTH / 8; i = i + 1) begin
+      byte_count = byte_count + wstrb[i];
+    end
+  end
+
+  always @(posedge clk) begin: gen_data_cmp
+    integer i;
+    if (reset) begin
+      for (i = 0; i < DATA_WIDTH; i = i + 8) begin
+        data_cmp[i+:8] <= i/8;
+      end
+      failed <= 'b0;
+    end else if (wvalid & wready) begin
+      for (i = 0; i < DATA_WIDTH; i = i + 8) begin
+        if (data_cmp[i+:8] !== wdata[i+:8] && wstrb[i/8] == 1'b1) begin
+          failed <= 1'b1;
+        end
+        data_cmp[i+:8] <= data_cmp[i+:8] + byte_count;
       end
-      data_cmp[i+:8] <= data_cmp[i+:8] + byte_count;
     end
   end
-end
 
 endmodule
diff --git a/library/axi_dmac/tb/dma_read_shutdown_tb.v b/library/axi_dmac/tb/dma_read_shutdown_tb.v
index 618a68a8e..4dce05dc2 100644
--- a/library/axi_dmac/tb/dma_read_shutdown_tb.v
+++ b/library/axi_dmac/tb/dma_read_shutdown_tb.v
@@ -82,8 +82,7 @@ module dma_read_shutdown_tb;
     .rvalid(rvalid),
     .rdata(rdata),
     .rresp(rresp),
-    .rlast(rlast)
-  );
+    .rlast(rlast));
 
   wire [11:0] dbg_status;
 
@@ -157,7 +156,6 @@ module dma_read_shutdown_tb;
     .fifo_rd_underflow(),
     .fifo_rd_dout(),
 
-    .dbg_status(dbg_status)
-  );
+    .dbg_status(dbg_status));
 
 endmodule
diff --git a/library/axi_dmac/tb/dma_read_tb.v b/library/axi_dmac/tb/dma_read_tb.v
index 2ed302e3a..0cbc81562 100644
--- a/library/axi_dmac/tb/dma_read_tb.v
+++ b/library/axi_dmac/tb/dma_read_tb.v
@@ -91,8 +91,7 @@ module dma_read_tb;
     .rvalid(rvalid),
     .rdata(rdata),
     .rresp(rresp),
-    .rlast(rlast)
-  );
+    .rlast(rlast));
 
   wire fifo_rd_en = 1'b1;
   wire fifo_rd_valid;
@@ -151,8 +150,7 @@ module dma_read_tb;
     .fifo_rd_en(fifo_rd_en),
     .fifo_rd_valid(fifo_rd_valid),
     .fifo_rd_underflow(fifo_rd_underflow),
-    .fifo_rd_dout(fifo_rd_dout)
-  );
+    .fifo_rd_dout(fifo_rd_dout));
 
   always @(posedge clk) begin: dout
     integer i;
diff --git a/library/axi_dmac/tb/dma_write_shutdown_tb.v b/library/axi_dmac/tb/dma_write_shutdown_tb.v
index a3ac2494d..76dff6e89 100644
--- a/library/axi_dmac/tb/dma_write_shutdown_tb.v
+++ b/library/axi_dmac/tb/dma_write_shutdown_tb.v
@@ -92,8 +92,7 @@ module dma_write_shutdown_tb;
 
     .bvalid(bvalid),
     .bready(bready),
-    .bresp(bresp)
-  );
+    .bresp(bresp));
 
   reg ctrl_enable = 1'b0;
 
@@ -164,7 +163,6 @@ module dma_write_shutdown_tb;
     .fifo_wr_sync(1'b1),
     .fifo_wr_xfer_req(),
 
-    .dbg_status(dbg_status)
-  );
+    .dbg_status(dbg_status));
 
 endmodule
diff --git a/library/axi_dmac/tb/dma_write_tb.v b/library/axi_dmac/tb/dma_write_tb.v
index 34e8af185..b228b5e22 100644
--- a/library/axi_dmac/tb/dma_write_tb.v
+++ b/library/axi_dmac/tb/dma_write_tb.v
@@ -102,8 +102,7 @@ module dma_write_tb;
 
     .bvalid(bvalid),
     .bready(bready),
-    .bresp(bresp)
-  );
+    .bresp(bresp));
 
   axi_dmac_transfer #(
     .DMA_DATA_WIDTH_SRC(WIDTH_SRC),
@@ -156,8 +155,7 @@ module dma_write_tb;
     .fifo_wr_din(fifo_wr_din),
     .fifo_wr_overflow(fifo_wr_overflow),
     .fifo_wr_sync(1'b1),
-    .fifo_wr_xfer_req(fifo_wr_xfer_req)
-  );
+    .fifo_wr_xfer_req(fifo_wr_xfer_req));
 
   always @(posedge clk) begin: fifo_wr
     integer i;
diff --git a/library/axi_dmac/tb/regmap_tb.v b/library/axi_dmac/tb/regmap_tb.v
index c0fb2f26b..9dc4e38a3 100644
--- a/library/axi_dmac/tb/regmap_tb.v
+++ b/library/axi_dmac/tb/regmap_tb.v
@@ -155,7 +155,6 @@ module regmap_tb;
     end
   end
 
-
   task set_reset_reg_value;
   input [31:0] addr;
   input [31:0] value;
@@ -331,7 +330,6 @@ module regmap_tb;
     set_reset_reg_value('h450, 'h0);
     set_reset_reg_value('h448, 24'h000080);
 
-
     check_all_registers("Transfer completed");
 
     /* Clear interrupts */
@@ -423,7 +421,6 @@ module regmap_tb;
     .dbg_dest_addr(VAL_DBG_DEST_ADDR),
     .dbg_status(VAL_DBG_STATUS),
     .dbg_ids0(VAL_DBG_IDS0),
-    .dbg_ids1(VAL_DBG_IDS1)
-  );
+    .dbg_ids1(VAL_DBG_IDS1));
 
 endmodule
diff --git a/library/axi_dmac/tb/reset_manager_tb.v b/library/axi_dmac/tb/reset_manager_tb.v
index fa7fc8c4c..85b426c44 100644
--- a/library/axi_dmac/tb/reset_manager_tb.v
+++ b/library/axi_dmac/tb/reset_manager_tb.v
@@ -41,7 +41,6 @@ module reset_manager_tb;
   `define TIMEOUT 1000000
   `include "tb_base.v"
 
-
   reg clk_a = 1'b0;
   reg clk_b = 1'b0;
   reg clk_c = 1'b0;
@@ -84,7 +83,6 @@ module reset_manager_tb;
   wire src_enable;
   wire src_enabled = src_enabled_shift[15];
 
-
   always @(posedge clk_a) begin
     req_enabled_shift <= {req_enabled_shift[14:0],req_enable};
   end
@@ -115,7 +113,6 @@ module reset_manager_tb;
     .src_clk(clk_c),
     .src_ext_resetn(1'b0),
     .src_enable(src_enable),
-    .src_enabled(src_enabled)
-  );
+    .src_enabled(src_enabled));
 
 endmodule
diff --git a/library/axi_fan_control/axi_fan_control.v b/library/axi_fan_control/axi_fan_control.v
index 45040a3b8..72a955443 100644
--- a/library/axi_fan_control/axi_fan_control.v
+++ b/library/axi_fan_control/axi_fan_control.v
@@ -53,8 +53,8 @@ module axi_fan_control #(
   parameter     TEMP_50_H         = 70,
   parameter     TEMP_75_L         = 80,
   parameter     TEMP_75_H         = 90,
-  parameter     TEMP_00_L         = 95)(
-
+  parameter     TEMP_00_L         = 95
+) (
   input       [ 9:0]      temp_in,
   input                   tacho,
   output    reg           irq,
@@ -81,689 +81,688 @@ module axi_fan_control #(
   output                  s_axi_rvalid,
   output      [ 1:0]      s_axi_rresp,
   output      [31:0]      s_axi_rdata,
-  input                   s_axi_rready);
-
-//local parameters
-localparam [31:0] CORE_VERSION            = {16'h0001,     /* MAJOR */
-                                              8'h00,       /* MINOR */
-                                              8'h61};      /* PATCH */ // 0.0.0
-localparam [31:0] CORE_MAGIC              = 32'h46414E43;    // FANC
-
-localparam        CLK_FREQUENCY           = 100000000;
-localparam        PWM_PERIOD              = CLK_FREQUENCY / PWM_FREQUENCY_HZ;
-localparam        OVERFLOW_LIM            = CLK_FREQUENCY * 5;
-localparam        AVERAGE_DIV             = 2**AVG_POW;
-
-localparam        THRESH_PWM_000          = (INTERNAL_SYSMONE == 1) ? (((TEMP_00_H + 280.2308787) * 65535) / 509.3140064) : ((TEMP_00_H * 41 + 11195) / 20);
-localparam        THRESH_PWM_025_L        = (INTERNAL_SYSMONE == 1) ? (((TEMP_25_L + 280.2308787) * 65535) / 509.3140064) : ((TEMP_25_L * 41 + 11195) / 20);
-localparam        THRESH_PWM_025_H        = (INTERNAL_SYSMONE == 1) ? (((TEMP_25_H + 280.2308787) * 65535) / 509.3140064) : ((TEMP_25_H * 41 + 11195) / 20);
-localparam        THRESH_PWM_050_L        = (INTERNAL_SYSMONE == 1) ? (((TEMP_50_L + 280.2308787) * 65535) / 509.3140064) : ((TEMP_50_L * 41 + 11195) / 20);
-localparam        THRESH_PWM_050_H        = (INTERNAL_SYSMONE == 1) ? (((TEMP_50_H + 280.2308787) * 65535) / 509.3140064) : ((TEMP_50_H * 41 + 11195) / 20);
-localparam        THRESH_PWM_075_L        = (INTERNAL_SYSMONE == 1) ? (((TEMP_75_L + 280.2308787) * 65535) / 509.3140064) : ((TEMP_75_L * 41 + 11195) / 20);
-localparam        THRESH_PWM_075_H        = (INTERNAL_SYSMONE == 1) ? (((TEMP_75_H + 280.2308787) * 65535) / 509.3140064) : ((TEMP_75_H * 41 + 11195) / 20);
-localparam        THRESH_PWM_100          = (INTERNAL_SYSMONE == 1) ? (((TEMP_00_L + 280.2308787) * 65535) / 509.3140064) : ((TEMP_00_L * 41 + 11195) / 20);
-
-//pwm params
-localparam        PWM_ONTIME_25           = PWM_PERIOD / 4;
-localparam        PWM_ONTIME_50           = PWM_PERIOD / 2;
-localparam        PWM_ONTIME_75           = PWM_PERIOD * 3 / 4;
-
-//tacho params
-localparam        TACHO_T25_TOL           = TACHO_T25 * TACHO_TOL_PERCENT / 100;
-localparam        TACHO_T50_TOL           = TACHO_T50 * TACHO_TOL_PERCENT / 100;
-localparam        TACHO_T75_TOL           = TACHO_T75 * TACHO_TOL_PERCENT / 100;
-localparam        TACHO_T100_TOL          = TACHO_T100 * TACHO_TOL_PERCENT / 100;
-
-//state machine states
-localparam        INIT                    = 8'h00;
-localparam        DRP_WAIT_EOC            = 8'h01;
-localparam        DRP_WAIT_DRDY           = 8'h02;
-localparam        DRP_WAIT_FSM_EN         = 8'h03;
-localparam        DRP_READ_TEMP           = 8'h04;
-localparam        DRP_READ_TEMP_WAIT_DRDY = 8'h05;
-localparam        GET_TACHO               = 8'h06;
-localparam        EVAL_TEMP               = 8'h07;
-localparam        SET_PWM                 = 8'h08;
-localparam        EVAL_TACHO              = 8'h09;
-
-reg   [31:0]  up_scratch = 'd0;
-reg   [7:0]   state = INIT;
-reg   [7:0]   drp_daddr = 'h0;
-reg   [15:0]  drp_di = 'h0;
-reg   [1:0]   drp_den_reg = 'h0;
-reg   [1:0]   drp_dwe_reg = 'h0;
-reg   [15:0]  sysmone_temp = 'h0;
-reg           temp_increase_alarm = 'h0;
-reg           tacho_alarm = 'h0;
-
-reg   [31:0]  up_tacho_val = 'h0;
-reg   [31:0]  up_tacho_tol = 'h0;
-reg           up_tacho_en = 'h0;
-reg   [7:0]   tacho_avg_cnt = 'h0;
-reg   [31:0]  tacho_avg_sum = 'h0;
-reg   [31:0]  tacho_meas = 'h0;
-reg           tacho_delayed = 'h0;
-reg           tacho_meas_new = 'h0;
-reg           tacho_meas_ack = 'h0;
-reg           tacho_edge_det = 'h0;
-reg   [31:0]  up_tacho_avg_sum = 'h0;
-
-reg   [31:0]  counter_reg = 'h0;
-reg   [31:0]  pwm_width = 'h0;
-reg   [31:0]  pwm_width_req = 'h0;
-reg           counter_overflow = 'h0;
-reg           pwm_change_done = 1'b1;
-reg           pulse_gen_load_config = 'h0;
-reg           tacho_meas_int = 'h0;
-
-reg   [15:0]  presc_reg = 'h0;
-reg   [31:0]  up_pwm_width = 'd0;
-
-reg   [31:0]  up_temp_00_h  = THRESH_PWM_000  ;
-reg   [31:0]  up_temp_25_l  = THRESH_PWM_025_L;
-reg   [31:0]  up_temp_25_h  = THRESH_PWM_025_H;
-reg   [31:0]  up_temp_50_l  = THRESH_PWM_050_L;
-reg   [31:0]  up_temp_50_h  = THRESH_PWM_050_H;
-reg   [31:0]  up_temp_75_l  = THRESH_PWM_075_L;
-reg   [31:0]  up_temp_75_h  = THRESH_PWM_075_H;
-reg   [31:0]  up_temp_100_l = THRESH_PWM_100  ;
-
-reg   [31:0]  up_tacho_25 = TACHO_T25;
-reg   [31:0]  up_tacho_50 = TACHO_T50;
-reg   [31:0]  up_tacho_75 = TACHO_T75;
-reg   [31:0]  up_tacho_100 = TACHO_T100;
-reg   [31:0]  up_tacho_25_tol = TACHO_T25 * TACHO_TOL_PERCENT / 100;
-reg   [31:0]  up_tacho_50_tol = TACHO_T50 * TACHO_TOL_PERCENT / 100;
-reg   [31:0]  up_tacho_75_tol = TACHO_T75 * TACHO_TOL_PERCENT / 100;
-reg   [31:0]  up_tacho_100_tol = TACHO_T100 * TACHO_TOL_PERCENT / 100;
-
-reg           up_wack = 'd0;
-reg   [31:0]  up_rdata = 'd0;
-reg           up_rack = 'd0;
-reg           up_resetn = 1'b0;
-reg   [3:0]   up_irq_mask = 4'b1111;
-reg   [3:0]   up_irq_source = 4'h0;
-
-wire          counter_resetn;
-wire  [15:0]  drp_do;
-wire          drp_drdy;
-wire          drp_eoc;
-wire          drp_eos;
-
-wire          pwm_change_done_int;
-wire          pulse_gen_out;
-wire          up_clk;
-wire          up_rreq_s;
-wire  [7:0]   up_raddr_s;
-wire          up_wreq_s;
-wire  [7:0]   up_waddr_s;
-wire  [31:0]  up_wdata_s;
-wire  [3:0]   up_irq_pending;
-wire  [3:0]   up_irq_trigger;
-wire  [3:0]   up_irq_source_clear;
-
-assign up_clk = s_axi_aclk;
-assign pwm = ~pulse_gen_out & up_resetn; //reverse polarity because the board is also reversing it
-assign pwm_change_done_int = counter_overflow & !pwm_change_done;
-
-//IRQ handling
-assign up_irq_pending = ~up_irq_mask & up_irq_source;
-assign up_irq_trigger  = {tacho_meas_int, temp_increase_alarm, tacho_alarm, pwm_change_done_int};
-assign up_irq_source_clear = (up_wreq_s == 1'b1 && up_waddr_s == 8'h11) ? up_wdata_s[3:0] : 4'b0000;
-
-//switching the reset signal for the counter
-//counter is used to measure tacho and to provide delay between pwm_ontime changes
-assign counter_resetn = (pwm_change_done ) ? (!tacho_edge_det) : ((!pwm_change_done) & (!counter_overflow));
-
-up_axi #(
-  .AXI_ADDRESS_WIDTH(10))
-i_up_axi (
-  .up_rstn (s_axi_aresetn),
-  .up_clk (up_clk),
-  .up_axi_awvalid (s_axi_awvalid),
-  .up_axi_awaddr (s_axi_awaddr),
-  .up_axi_awready (s_axi_awready),
-  .up_axi_wvalid (s_axi_wvalid),
-  .up_axi_wdata (s_axi_wdata),
-  .up_axi_wstrb (s_axi_wstrb),
-  .up_axi_wready (s_axi_wready),
-  .up_axi_bvalid (s_axi_bvalid),
-  .up_axi_bresp (s_axi_bresp),
-  .up_axi_bready (s_axi_bready),
-  .up_axi_arvalid (s_axi_arvalid),
-  .up_axi_araddr (s_axi_araddr),
-  .up_axi_arready (s_axi_arready),
-  .up_axi_rvalid (s_axi_rvalid),
-  .up_axi_rresp (s_axi_rresp),
-  .up_axi_rdata (s_axi_rdata),
-  .up_axi_rready (s_axi_rready),
-  .up_wreq (up_wreq_s),
-  .up_waddr (up_waddr_s),
-  .up_wdata (up_wdata_s),
-  .up_wack (up_wack),
-  .up_rreq (up_rreq_s),
-  .up_raddr (up_raddr_s),
-  .up_rdata (up_rdata),
-  .up_rack (up_rack));
-
-generate
-if (INTERNAL_SYSMONE == 1) begin
-  SYSMONE4 #(
-    .COMMON_N_SOURCE(16'hFFFF),
-    .INIT_40(16'h1000), // config reg 0
-    .INIT_41(16'h2F9F), // config reg 1
-    .INIT_42(16'h1400), // config reg 2
-    .INIT_43(16'h200F), // config reg 3
-    .INIT_44(16'h0000), // config reg 4
-    .INIT_45(16'hE200), // Analog Bus Register
-    .INIT_46(16'h0000), // Sequencer Channel selection (Vuser0-3)
-    .INIT_47(16'h0000), // Sequencer Average selection (Vuser0-3)
-    .INIT_48(16'h0101), // Sequencer channel selection
-    .INIT_49(16'h0000), // Sequencer channel selection
-    .INIT_4A(16'h0000), // Sequencer Average selection
-    .INIT_4B(16'h0000), // Sequencer Average selection
-    .INIT_4C(16'h0000), // Sequencer Bipolar selection
-    .INIT_4D(16'h0000), // Sequencer Bipolar selection
-    .INIT_4E(16'h0000), // Sequencer Acq time selection
-    .INIT_4F(16'h0000), // Sequencer Acq time selection
-    .INIT_50(16'hB794), // Temp alarm trigger
-    .INIT_51(16'h4E81), // Vccint upper alarm limit
-    .INIT_52(16'hA147), // Vccaux upper alarm limit
-    .INIT_53(16'hBF13), // Temp alarm OT upper
-    .INIT_54(16'hAB02), // Temp alarm reset
-    .INIT_55(16'h4963), // Vccint lower alarm limit
-    .INIT_56(16'h9555), // Vccaux lower alarm limit
-    .INIT_57(16'hB00A), // Temp alarm OT reset
-    .INIT_58(16'h4E81), // VCCBRAM upper alarm limit
-    .INIT_5C(16'h4963), // VCCBRAM lower alarm limit
-    .INIT_59(16'h4963), // vccpsintlp upper alarm limit
-    .INIT_5D(16'h451E), // vccpsintlp lower alarm limit
-    .INIT_5A(16'h4963), // vccpsintfp upper alarm limit
-    .INIT_5E(16'h451E), // vccpsintfp lower alarm limit
-    .INIT_5B(16'h9A74), // vccpsaux upper alarm limit
-    .INIT_5F(16'h91EB), // vccpsaux lower alarm limit
-    .INIT_60(16'h4D39), // Vuser0 upper alarm limit
-    .INIT_61(16'h4DA7), // Vuser1 upper alarm limit
-    .INIT_62(16'h9A74), // Vuser2 upper alarm limit
-    .INIT_63(16'h9A74), // Vuser3 upper alarm limit
-    .INIT_68(16'h4C5E), // Vuser0 lower alarm limit
-    .INIT_69(16'h4BF2), // Vuser1 lower alarm limit
-    .INIT_6A(16'h98BF), // Vuser2 lower alarm limit
-    .INIT_6B(16'h98BF), // Vuser3 lower alarm limit
-    .INIT_7A(16'h0000), // DUAL0 Register
-    .INIT_7B(16'h0000), // DUAL1 Register
-    .INIT_7C(16'h0000), // DUAL2 Register
-    .INIT_7D(16'h0000), // DUAL3 Register
-    .SIM_DEVICE("ZYNQ_ULTRASCALE"),
-    .SIM_MONITOR_FILE("design.txt"))
-  inst_sysmon (
-    .DADDR(drp_daddr),
-    .DCLK(up_clk),
-    .DEN(drp_den_reg[0]),
-    .DI(drp_di),
-    .DWE(drp_dwe_reg[0]),
-    .RESET(!up_resetn),
-    .DO(drp_do),
-    .DRDY(drp_drdy),
-    .EOC(drp_eoc),
-    .EOS(drp_eos)
-  );
-end
-endgenerate
-
-//pulse generator instance
-util_pulse_gen #(
-  .PULSE_WIDTH(0),
-  .PULSE_PERIOD(0))
-util_pulse_gen_i(
-  .clk (up_clk),
-  .rstn (up_resetn),
-  .pulse_width (pwm_width),
-  .pulse_period (PWM_PERIOD),
-  .load_config (pulse_gen_load_config),
-  .pulse (pulse_gen_out)
+  input                   s_axi_rready
 );
 
-//state machine
-always @(posedge up_clk)
-  if (up_resetn == 1'b0) begin
-    tacho_alarm <= 'h0;
-    drp_den_reg <= 'h0;
-    drp_dwe_reg <= 'h0;
-    drp_di <= 'h0;
-    tacho_avg_cnt <= 'h0;
-    tacho_avg_sum <= 'h0;
-    tacho_meas_ack <= 'h0;
-    pulse_gen_load_config <= 'h0;
-    sysmone_temp <= 'h0;
-    pwm_width_req <= 'h0;
-    pwm_width <= 'h0;
-    up_tacho_avg_sum <= 'h0;
-    temp_increase_alarm <= 'h0;
-    tacho_meas_int <= 1'b0;
-    state <= INIT;
-  end else begin
+  //local parameters
+  localparam [31:0] CORE_VERSION            = {16'h0001,     /* MAJOR */
+                                                8'h00,       /* MINOR */
+                                                8'h61};      /* PATCH */ // 0.0.0
+  localparam [31:0] CORE_MAGIC              = 32'h46414E43;    // FANC
 
-    case (state)
+  localparam        CLK_FREQUENCY           = 100000000;
+  localparam        PWM_PERIOD              = CLK_FREQUENCY / PWM_FREQUENCY_HZ;
+  localparam        OVERFLOW_LIM            = CLK_FREQUENCY * 5;
+  localparam        AVERAGE_DIV             = 2**AVG_POW;
 
-      INIT : begin
-        if (INTERNAL_SYSMONE == 1) begin
-          drp_daddr <= 8'h40;
-          // performing read
-          drp_den_reg <= 2'h2;
+  localparam        THRESH_PWM_000          = (INTERNAL_SYSMONE == 1) ? (((TEMP_00_H + 280.2308787) * 65535) / 509.3140064) : ((TEMP_00_H * 41 + 11195) / 20);
+  localparam        THRESH_PWM_025_L        = (INTERNAL_SYSMONE == 1) ? (((TEMP_25_L + 280.2308787) * 65535) / 509.3140064) : ((TEMP_25_L * 41 + 11195) / 20);
+  localparam        THRESH_PWM_025_H        = (INTERNAL_SYSMONE == 1) ? (((TEMP_25_H + 280.2308787) * 65535) / 509.3140064) : ((TEMP_25_H * 41 + 11195) / 20);
+  localparam        THRESH_PWM_050_L        = (INTERNAL_SYSMONE == 1) ? (((TEMP_50_L + 280.2308787) * 65535) / 509.3140064) : ((TEMP_50_L * 41 + 11195) / 20);
+  localparam        THRESH_PWM_050_H        = (INTERNAL_SYSMONE == 1) ? (((TEMP_50_H + 280.2308787) * 65535) / 509.3140064) : ((TEMP_50_H * 41 + 11195) / 20);
+  localparam        THRESH_PWM_075_L        = (INTERNAL_SYSMONE == 1) ? (((TEMP_75_L + 280.2308787) * 65535) / 509.3140064) : ((TEMP_75_L * 41 + 11195) / 20);
+  localparam        THRESH_PWM_075_H        = (INTERNAL_SYSMONE == 1) ? (((TEMP_75_H + 280.2308787) * 65535) / 509.3140064) : ((TEMP_75_H * 41 + 11195) / 20);
+  localparam        THRESH_PWM_100          = (INTERNAL_SYSMONE == 1) ? (((TEMP_00_L + 280.2308787) * 65535) / 509.3140064) : ((TEMP_00_L * 41 + 11195) / 20);
+
+  //pwm params
+  localparam        PWM_ONTIME_25           = PWM_PERIOD / 4;
+  localparam        PWM_ONTIME_50           = PWM_PERIOD / 2;
+  localparam        PWM_ONTIME_75           = PWM_PERIOD * 3 / 4;
+
+  //tacho params
+  localparam        TACHO_T25_TOL           = TACHO_T25 * TACHO_TOL_PERCENT / 100;
+  localparam        TACHO_T50_TOL           = TACHO_T50 * TACHO_TOL_PERCENT / 100;
+  localparam        TACHO_T75_TOL           = TACHO_T75 * TACHO_TOL_PERCENT / 100;
+  localparam        TACHO_T100_TOL          = TACHO_T100 * TACHO_TOL_PERCENT / 100;
+
+  //state machine states
+  localparam        INIT                    = 8'h00;
+  localparam        DRP_WAIT_EOC            = 8'h01;
+  localparam        DRP_WAIT_DRDY           = 8'h02;
+  localparam        DRP_WAIT_FSM_EN         = 8'h03;
+  localparam        DRP_READ_TEMP           = 8'h04;
+  localparam        DRP_READ_TEMP_WAIT_DRDY = 8'h05;
+  localparam        GET_TACHO               = 8'h06;
+  localparam        EVAL_TEMP               = 8'h07;
+  localparam        SET_PWM                 = 8'h08;
+  localparam        EVAL_TACHO              = 8'h09;
+
+  reg   [31:0]  up_scratch = 'd0;
+  reg   [7:0]   state = INIT;
+  reg   [7:0]   drp_daddr = 'h0;
+  reg   [15:0]  drp_di = 'h0;
+  reg   [1:0]   drp_den_reg = 'h0;
+  reg   [1:0]   drp_dwe_reg = 'h0;
+  reg   [15:0]  sysmone_temp = 'h0;
+  reg           temp_increase_alarm = 'h0;
+  reg           tacho_alarm = 'h0;
+
+  reg   [31:0]  up_tacho_val = 'h0;
+  reg   [31:0]  up_tacho_tol = 'h0;
+  reg           up_tacho_en = 'h0;
+  reg   [7:0]   tacho_avg_cnt = 'h0;
+  reg   [31:0]  tacho_avg_sum = 'h0;
+  reg   [31:0]  tacho_meas = 'h0;
+  reg           tacho_delayed = 'h0;
+  reg           tacho_meas_new = 'h0;
+  reg           tacho_meas_ack = 'h0;
+  reg           tacho_edge_det = 'h0;
+  reg   [31:0]  up_tacho_avg_sum = 'h0;
+
+  reg   [31:0]  counter_reg = 'h0;
+  reg   [31:0]  pwm_width = 'h0;
+  reg   [31:0]  pwm_width_req = 'h0;
+  reg           counter_overflow = 'h0;
+  reg           pwm_change_done = 1'b1;
+  reg           pulse_gen_load_config = 'h0;
+  reg           tacho_meas_int = 'h0;
+
+  reg   [15:0]  presc_reg = 'h0;
+  reg   [31:0]  up_pwm_width = 'd0;
+
+  reg   [31:0]  up_temp_00_h  = THRESH_PWM_000  ;
+  reg   [31:0]  up_temp_25_l  = THRESH_PWM_025_L;
+  reg   [31:0]  up_temp_25_h  = THRESH_PWM_025_H;
+  reg   [31:0]  up_temp_50_l  = THRESH_PWM_050_L;
+  reg   [31:0]  up_temp_50_h  = THRESH_PWM_050_H;
+  reg   [31:0]  up_temp_75_l  = THRESH_PWM_075_L;
+  reg   [31:0]  up_temp_75_h  = THRESH_PWM_075_H;
+  reg   [31:0]  up_temp_100_l = THRESH_PWM_100  ;
+
+  reg   [31:0]  up_tacho_25 = TACHO_T25;
+  reg   [31:0]  up_tacho_50 = TACHO_T50;
+  reg   [31:0]  up_tacho_75 = TACHO_T75;
+  reg   [31:0]  up_tacho_100 = TACHO_T100;
+  reg   [31:0]  up_tacho_25_tol = TACHO_T25 * TACHO_TOL_PERCENT / 100;
+  reg   [31:0]  up_tacho_50_tol = TACHO_T50 * TACHO_TOL_PERCENT / 100;
+  reg   [31:0]  up_tacho_75_tol = TACHO_T75 * TACHO_TOL_PERCENT / 100;
+  reg   [31:0]  up_tacho_100_tol = TACHO_T100 * TACHO_TOL_PERCENT / 100;
+
+  reg           up_wack = 'd0;
+  reg   [31:0]  up_rdata = 'd0;
+  reg           up_rack = 'd0;
+  reg           up_resetn = 1'b0;
+  reg   [3:0]   up_irq_mask = 4'b1111;
+  reg   [3:0]   up_irq_source = 4'h0;
+
+  wire          counter_resetn;
+  wire  [15:0]  drp_do;
+  wire          drp_drdy;
+  wire          drp_eoc;
+  wire          drp_eos;
+
+  wire          pwm_change_done_int;
+  wire          pulse_gen_out;
+  wire          up_clk;
+  wire          up_rreq_s;
+  wire  [7:0]   up_raddr_s;
+  wire          up_wreq_s;
+  wire  [7:0]   up_waddr_s;
+  wire  [31:0]  up_wdata_s;
+  wire  [3:0]   up_irq_pending;
+  wire  [3:0]   up_irq_trigger;
+  wire  [3:0]   up_irq_source_clear;
+
+  assign up_clk = s_axi_aclk;
+  assign pwm = ~pulse_gen_out & up_resetn; //reverse polarity because the board is also reversing it
+  assign pwm_change_done_int = counter_overflow & !pwm_change_done;
+
+  //IRQ handling
+  assign up_irq_pending = ~up_irq_mask & up_irq_source;
+  assign up_irq_trigger  = {tacho_meas_int, temp_increase_alarm, tacho_alarm, pwm_change_done_int};
+  assign up_irq_source_clear = (up_wreq_s == 1'b1 && up_waddr_s == 8'h11) ? up_wdata_s[3:0] : 4'b0000;
+
+  //switching the reset signal for the counter
+  //counter is used to measure tacho and to provide delay between pwm_ontime changes
+  assign counter_resetn = (pwm_change_done ) ? (!tacho_edge_det) : ((!pwm_change_done) & (!counter_overflow));
+
+  up_axi #(
+    .AXI_ADDRESS_WIDTH(10)
+  ) i_up_axi (
+    .up_rstn (s_axi_aresetn),
+    .up_clk (up_clk),
+    .up_axi_awvalid (s_axi_awvalid),
+    .up_axi_awaddr (s_axi_awaddr),
+    .up_axi_awready (s_axi_awready),
+    .up_axi_wvalid (s_axi_wvalid),
+    .up_axi_wdata (s_axi_wdata),
+    .up_axi_wstrb (s_axi_wstrb),
+    .up_axi_wready (s_axi_wready),
+    .up_axi_bvalid (s_axi_bvalid),
+    .up_axi_bresp (s_axi_bresp),
+    .up_axi_bready (s_axi_bready),
+    .up_axi_arvalid (s_axi_arvalid),
+    .up_axi_araddr (s_axi_araddr),
+    .up_axi_arready (s_axi_arready),
+    .up_axi_rvalid (s_axi_rvalid),
+    .up_axi_rresp (s_axi_rresp),
+    .up_axi_rdata (s_axi_rdata),
+    .up_axi_rready (s_axi_rready),
+    .up_wreq (up_wreq_s),
+    .up_waddr (up_waddr_s),
+    .up_wdata (up_wdata_s),
+    .up_wack (up_wack),
+    .up_rreq (up_rreq_s),
+    .up_raddr (up_raddr_s),
+    .up_rdata (up_rdata),
+    .up_rack (up_rack));
+
+  generate
+  if (INTERNAL_SYSMONE == 1) begin
+    SYSMONE4 #(
+      .COMMON_N_SOURCE(16'hFFFF),
+      .INIT_40(16'h1000), // config reg 0
+      .INIT_41(16'h2F9F), // config reg 1
+      .INIT_42(16'h1400), // config reg 2
+      .INIT_43(16'h200F), // config reg 3
+      .INIT_44(16'h0000), // config reg 4
+      .INIT_45(16'hE200), // Analog Bus Register
+      .INIT_46(16'h0000), // Sequencer Channel selection (Vuser0-3)
+      .INIT_47(16'h0000), // Sequencer Average selection (Vuser0-3)
+      .INIT_48(16'h0101), // Sequencer channel selection
+      .INIT_49(16'h0000), // Sequencer channel selection
+      .INIT_4A(16'h0000), // Sequencer Average selection
+      .INIT_4B(16'h0000), // Sequencer Average selection
+      .INIT_4C(16'h0000), // Sequencer Bipolar selection
+      .INIT_4D(16'h0000), // Sequencer Bipolar selection
+      .INIT_4E(16'h0000), // Sequencer Acq time selection
+      .INIT_4F(16'h0000), // Sequencer Acq time selection
+      .INIT_50(16'hB794), // Temp alarm trigger
+      .INIT_51(16'h4E81), // Vccint upper alarm limit
+      .INIT_52(16'hA147), // Vccaux upper alarm limit
+      .INIT_53(16'hBF13), // Temp alarm OT upper
+      .INIT_54(16'hAB02), // Temp alarm reset
+      .INIT_55(16'h4963), // Vccint lower alarm limit
+      .INIT_56(16'h9555), // Vccaux lower alarm limit
+      .INIT_57(16'hB00A), // Temp alarm OT reset
+      .INIT_58(16'h4E81), // VCCBRAM upper alarm limit
+      .INIT_5C(16'h4963), // VCCBRAM lower alarm limit
+      .INIT_59(16'h4963), // vccpsintlp upper alarm limit
+      .INIT_5D(16'h451E), // vccpsintlp lower alarm limit
+      .INIT_5A(16'h4963), // vccpsintfp upper alarm limit
+      .INIT_5E(16'h451E), // vccpsintfp lower alarm limit
+      .INIT_5B(16'h9A74), // vccpsaux upper alarm limit
+      .INIT_5F(16'h91EB), // vccpsaux lower alarm limit
+      .INIT_60(16'h4D39), // Vuser0 upper alarm limit
+      .INIT_61(16'h4DA7), // Vuser1 upper alarm limit
+      .INIT_62(16'h9A74), // Vuser2 upper alarm limit
+      .INIT_63(16'h9A74), // Vuser3 upper alarm limit
+      .INIT_68(16'h4C5E), // Vuser0 lower alarm limit
+      .INIT_69(16'h4BF2), // Vuser1 lower alarm limit
+      .INIT_6A(16'h98BF), // Vuser2 lower alarm limit
+      .INIT_6B(16'h98BF), // Vuser3 lower alarm limit
+      .INIT_7A(16'h0000), // DUAL0 Register
+      .INIT_7B(16'h0000), // DUAL1 Register
+      .INIT_7C(16'h0000), // DUAL2 Register
+      .INIT_7D(16'h0000), // DUAL3 Register
+      .SIM_DEVICE("ZYNQ_ULTRASCALE"),
+      .SIM_MONITOR_FILE("design.txt")
+    ) inst_sysmon (
+      .DADDR(drp_daddr),
+      .DCLK(up_clk),
+      .DEN(drp_den_reg[0]),
+      .DI(drp_di),
+      .DWE(drp_dwe_reg[0]),
+      .RESET(!up_resetn),
+      .DO(drp_do),
+      .DRDY(drp_drdy),
+      .EOC(drp_eoc),
+      .EOS(drp_eos));
+  end
+  endgenerate
+
+  //pulse generator instance
+  util_pulse_gen #(
+    .PULSE_WIDTH(0),
+    .PULSE_PERIOD(0)
+  ) util_pulse_gen_i(
+    .clk (up_clk),
+    .rstn (up_resetn),
+    .pulse_width (pwm_width),
+    .pulse_period (PWM_PERIOD),
+    .load_config (pulse_gen_load_config),
+    .pulse (pulse_gen_out));
+
+  //state machine
+  always @(posedge up_clk)
+    if (up_resetn == 1'b0) begin
+      tacho_alarm <= 'h0;
+      drp_den_reg <= 'h0;
+      drp_dwe_reg <= 'h0;
+      drp_di <= 'h0;
+      tacho_avg_cnt <= 'h0;
+      tacho_avg_sum <= 'h0;
+      tacho_meas_ack <= 'h0;
+      pulse_gen_load_config <= 'h0;
+      sysmone_temp <= 'h0;
+      pwm_width_req <= 'h0;
+      pwm_width <= 'h0;
+      up_tacho_avg_sum <= 'h0;
+      temp_increase_alarm <= 'h0;
+      tacho_meas_int <= 1'b0;
+      state <= INIT;
+    end else begin
+
+      case (state)
+
+        INIT : begin
+          if (INTERNAL_SYSMONE == 1) begin
+            drp_daddr <= 8'h40;
+            // performing read
+            drp_den_reg <= 2'h2;
+            if (drp_eoc == 1'b1) begin
+              state <= DRP_WAIT_EOC;
+            end
+          end else begin
+            state <= DRP_READ_TEMP;
+          end
+        end
+
+        DRP_WAIT_EOC : begin
           if (drp_eoc == 1'b1) begin
-            state <= DRP_WAIT_EOC;
-          end
-        end else begin
-          state <= DRP_READ_TEMP;
-        end
-      end
-
-      DRP_WAIT_EOC : begin
-        if (drp_eoc == 1'b1) begin
-          //Clearing AVG bits for Configreg0
-          drp_di <= drp_do & 16'h03FF;
-          drp_daddr <= 8'h40;
-          drp_den_reg <= 2'h2;
-          // performing write
-          drp_dwe_reg <= 2'h2;
-          state <= DRP_WAIT_DRDY;
-        end else begin
-          drp_den_reg <= {1'b0, drp_den_reg[1]};
-          drp_dwe_reg <= {1'b0, drp_dwe_reg[1]};
-        end
-      end
-
-      DRP_WAIT_DRDY : begin
-        if (drp_drdy == 1'b1) begin
-          state <= DRP_READ_TEMP;
-        end else begin
-          drp_den_reg <= {1'b0, drp_den_reg[1]};
-          drp_dwe_reg <= {1'b0, drp_dwe_reg[1]};
-        end
-      end
-
-      DRP_WAIT_FSM_EN : begin
-        tacho_meas_int <= 1'b0;
-        tacho_alarm <= 1'b0;
-        pulse_gen_load_config <= 1'b0;
-        if (presc_reg[15] == 1'b1) begin
-          state <= DRP_READ_TEMP;
-        end
-      end
-
-      DRP_READ_TEMP : begin
-        if (INTERNAL_SYSMONE == 1) begin
-          drp_daddr <= 8'h00;
-          // performing read
-          drp_den_reg <= 2'h2;
-          if (drp_eos == 1'b1) begin
-            state <= DRP_READ_TEMP_WAIT_DRDY;
-          end
-        end else begin
-          state <= DRP_READ_TEMP_WAIT_DRDY;
-        end
-      end
-
-      DRP_READ_TEMP_WAIT_DRDY : begin
-        if (INTERNAL_SYSMONE == 1) begin
-          if (drp_drdy == 1'b1) begin
-            sysmone_temp <= drp_do;
-            state <= GET_TACHO;
+            //Clearing AVG bits for Configreg0
+            drp_di <= drp_do & 16'h03FF;
+            drp_daddr <= 8'h40;
+            drp_den_reg <= 2'h2;
+            // performing write
+            drp_dwe_reg <= 2'h2;
+            state <= DRP_WAIT_DRDY;
           end else begin
             drp_den_reg <= {1'b0, drp_den_reg[1]};
             drp_dwe_reg <= {1'b0, drp_dwe_reg[1]};
           end
-        end else begin
-          sysmone_temp <= temp_in;
-          state <= GET_TACHO;
         end
-      end
 
-      GET_TACHO : begin
-        //adding up tacho measurements in order to obtain a mean value from 32 samples
-        if ((tacho_avg_cnt == AVERAGE_DIV) || (counter_overflow) || (!pwm_change_done)) begin
-          //once a set measurements has been obtained, reset the values
-          tacho_avg_sum <= 1'b0;
-          tacho_avg_cnt <= 1'b0;
-          tacho_meas_ack <= 1'b0;
-        end else if ((tacho_meas_new) && (pwm_change_done)) begin
-          //tacho_meas_new and tacho_meas_ack ensure the value is read at the right time and only once
-          tacho_avg_sum <= tacho_avg_sum + tacho_meas;
-          tacho_avg_cnt <= tacho_avg_cnt + 1'b1;
-          //acknowledge tha the current values has been added
-          tacho_meas_ack <= 1'b1;
-        end else begin
-          tacho_meas_ack <= 1'b0;
-        end
-        state <= EVAL_TEMP;
-      end
-
-      EVAL_TEMP : begin
-        //pwm section
-        //the pwm only has to be changed when passing through these temperature intervals
-        if (sysmone_temp < up_temp_00_h) begin
-          //PWM DUTY should be 0%
-          pwm_width_req <= 1'b0;
-        end else if ((sysmone_temp > up_temp_25_l) && (sysmone_temp < up_temp_25_h)) begin
-          //PWM DUTY should be 25%
-          pwm_width_req <= PWM_ONTIME_25;
-        end else if ((sysmone_temp > up_temp_50_l) && (sysmone_temp < up_temp_50_h)) begin
-          //PWM DUTY should be 50%
-          pwm_width_req <= PWM_ONTIME_50;
-        end else if ((sysmone_temp > up_temp_75_l) && (sysmone_temp < up_temp_75_h)) begin
-          //PWM DUTY should be 75%
-          pwm_width_req <= PWM_ONTIME_75;
-        end else if (sysmone_temp > up_temp_100_l) begin
-          //PWM DUTY should be 100%
-          pwm_width_req <= PWM_PERIOD;
-          //default to 100% duty cycle after reset if not within temperature intervals described above
-        end else if ((sysmone_temp != 'h0) && (pwm_width == 'h0)) begin
-          pwm_width_req <= PWM_PERIOD;
-        end else begin
-          //if no changes are needed make sure to mantain current pwm
-          pwm_width_req <= pwm_width;
-        end
-        state <= SET_PWM;
-      end
-
-      SET_PWM : begin
-        if ((up_pwm_width != pwm_width) && (up_pwm_width >= pwm_width_req) && (up_pwm_width <= PWM_PERIOD) && (pwm_change_done)) begin
-          pwm_width <= up_pwm_width;
-          pulse_gen_load_config <= 1'b1;
-          //clear alarm when pwm duty changes
-        end else if ((pwm_width != pwm_width_req) && (pwm_width_req > up_pwm_width) && (pwm_change_done)) begin
-          pwm_width <= pwm_width_req;
-          pulse_gen_load_config <= 1'b1;
-          temp_increase_alarm <= 1'b1;
-          //clear alarm when pwm duty changes
-        end
-        state <= EVAL_TACHO;
-      end
-
-      EVAL_TACHO : begin
-        temp_increase_alarm <= 1'b0;
-        //tacho section
-        //check if the fan is turning then see if it is turning correctly
-        if(counter_overflow & pwm_change_done) begin
-          //if overflow is 1 then the fan is not turning so do something
-          tacho_alarm <= 1'b1;
-        end else if (tacho_avg_cnt == AVERAGE_DIV) begin
-          //check rpm according to the current pwm duty cycle
-          //tacho_alarm is only asserted for certain known pwm duty cycles and
-          //for timeout
-          up_tacho_avg_sum <= tacho_avg_sum [AVG_POW + 24 : AVG_POW];
-          tacho_meas_int <= 1'b1;
-          if ((pwm_width == PWM_ONTIME_25) && (up_tacho_en == 0)) begin
-            if ((tacho_avg_sum [AVG_POW + 24 : AVG_POW] > up_tacho_25 + up_tacho_25_tol) || (tacho_avg_sum [AVG_POW + 24 : AVG_POW] < up_tacho_25 - up_tacho_25_tol)) begin
-              //the fan is turning but not as expected
-              tacho_alarm <= 1'b1;
-            end
-          end else if ((pwm_width == PWM_ONTIME_50) && (up_tacho_en == 0)) begin
-            if ((tacho_avg_sum [AVG_POW + 24 : AVG_POW] > up_tacho_50 + up_tacho_50_tol) || (tacho_avg_sum [AVG_POW + 24 : AVG_POW] < up_tacho_50 - up_tacho_50_tol)) begin
-              //the fan is turning but not as expected
-              tacho_alarm <= 1'b1;
-            end
-          end else if ((pwm_width == PWM_ONTIME_75) && (up_tacho_en == 0)) begin
-            if ((tacho_avg_sum [AVG_POW + 24 : AVG_POW] > up_tacho_75 + up_tacho_75_tol) || (tacho_avg_sum [AVG_POW + 24 : AVG_POW] < up_tacho_75 - up_tacho_75_tol)) begin
-              //the fan is turning but not as expected
-              tacho_alarm <= 1'b1;
-            end
-          end else if ((pwm_width == PWM_PERIOD) && (up_tacho_en == 0)) begin
-            if ((tacho_avg_sum [AVG_POW + 24 : AVG_POW] > up_tacho_100 + up_tacho_100_tol) || (tacho_avg_sum [AVG_POW + 24 : AVG_POW] < up_tacho_100 - up_tacho_100_tol)) begin
-              //the fan is turning but not as expected
-              tacho_alarm <= 1'b1;
-            end
-          end else if ((pwm_width == up_pwm_width) && up_tacho_en) begin
-            if ((tacho_avg_sum [AVG_POW + 24 : AVG_POW] > up_tacho_val + up_tacho_tol) || (tacho_avg_sum [AVG_POW + 24 : AVG_POW] < up_tacho_val - up_tacho_tol)) begin
-              //the fan is turning but not as expected
-              tacho_alarm <= 1'b1;
-            end
+        DRP_WAIT_DRDY : begin
+          if (drp_drdy == 1'b1) begin
+            state <= DRP_READ_TEMP;
+          end else begin
+            drp_den_reg <= {1'b0, drp_den_reg[1]};
+            drp_dwe_reg <= {1'b0, drp_dwe_reg[1]};
           end
         end
-        state <= DRP_WAIT_FSM_EN;
-      end
-      default :
-        state <= DRP_WAIT_FSM_EN;
-    endcase
-  end
 
-//axi registers write
-always @(posedge up_clk) begin
-  if (up_resetn == 1'b0) begin
-    up_pwm_width <= 'd0;
-    up_tacho_val <= 'd0;
-    up_tacho_tol <= 'd0;
-    up_tacho_en <= 'd0;
-    up_scratch <= 'd0;
-    up_temp_00_h <= THRESH_PWM_000;
-    up_temp_25_l <= THRESH_PWM_025_L;
-    up_temp_25_h <= THRESH_PWM_025_H;
-    up_temp_50_l <= THRESH_PWM_050_L;
-    up_temp_50_h <= THRESH_PWM_050_H;
-    up_temp_75_l <= THRESH_PWM_075_L;
-    up_temp_75_h <= THRESH_PWM_075_H;
-    up_temp_100_l <= THRESH_PWM_100;
-    up_tacho_25 <= TACHO_T25;
-    up_tacho_50 <= TACHO_T50;
-    up_tacho_75 <= TACHO_T75;
-    up_tacho_100 <= TACHO_T100;
-    up_tacho_25_tol <= TACHO_T25 * TACHO_TOL_PERCENT / 100;
-    up_tacho_50_tol <= TACHO_T50 * TACHO_TOL_PERCENT / 100;
-    up_tacho_75_tol <= TACHO_T75 * TACHO_TOL_PERCENT / 100;
-    up_tacho_100_tol <= TACHO_T100 * TACHO_TOL_PERCENT / 100;
-    up_irq_mask <= 4'b1111;
-  end else begin
-    if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h02)) begin
-      up_scratch <= up_wdata_s;
-    end
-    if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h21)) begin
-      up_pwm_width <= up_wdata_s;
-      up_tacho_en <= 1'b0;
-    end
-    if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h22)) begin
-      up_tacho_val <= up_wdata_s;
-    end
-    if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h23)) begin
-      up_tacho_tol <= up_wdata_s;
-      up_tacho_en <= 1'b1;
-    end else if (temp_increase_alarm) begin
-      up_tacho_en <= 1'b0;
-    end
-    if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h40)) begin
-      up_temp_00_h <= up_wdata_s;
-    end
-    if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h41)) begin
-      up_temp_25_l <= up_wdata_s;
-    end
-    if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h42)) begin
-      up_temp_25_h <= up_wdata_s;
-    end
-    if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h43)) begin
-      up_temp_50_l <= up_wdata_s;
-    end
-    if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h44)) begin
-     up_temp_50_h <= up_wdata_s;
-    end
-    if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h45)) begin
-      up_temp_75_l <= up_wdata_s;
-    end
-    if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h46)) begin
-      up_temp_75_h <= up_wdata_s;
-    end
-    if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h47)) begin
-      up_temp_100_l <= up_wdata_s;
-    end
-    if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h50)) begin
-      up_tacho_25 <= up_wdata_s;
-    end
-    if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h51)) begin
-      up_tacho_50 <= up_wdata_s;
-    end
-    if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h52)) begin
-      up_tacho_75 <= up_wdata_s;
-    end
-    if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h53)) begin
-      up_tacho_100 <= up_wdata_s;
-    end
-    if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h54)) begin
-      up_tacho_25_tol <= up_wdata_s;
-    end
-    if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h55)) begin
-      up_tacho_50_tol <= up_wdata_s;
-    end
-    if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h56)) begin
-      up_tacho_75_tol <= up_wdata_s;
-    end
-    if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h57)) begin
-      up_tacho_100_tol <= up_wdata_s;
-    end
-    if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h10)) begin
-      up_irq_mask <= up_wdata_s[3:0];
-    end
-  end
-end
+        DRP_WAIT_FSM_EN : begin
+          tacho_meas_int <= 1'b0;
+          tacho_alarm <= 1'b0;
+          pulse_gen_load_config <= 1'b0;
+          if (presc_reg[15] == 1'b1) begin
+            state <= DRP_READ_TEMP;
+          end
+        end
 
-//writing reset
-always @(posedge up_clk) begin
-  if (s_axi_aresetn == 1'b0) begin
-    up_wack <= 'd0;
-    up_resetn <= 1'd0;
-  end else begin
-    up_wack <= up_wreq_s;
-    if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h20)) begin
-      up_resetn <= up_wdata_s[0];
-    end else begin
-      up_resetn <= 1'd1;
-    end
-  end
-end
+        DRP_READ_TEMP : begin
+          if (INTERNAL_SYSMONE == 1) begin
+            drp_daddr <= 8'h00;
+            // performing read
+            drp_den_reg <= 2'h2;
+            if (drp_eos == 1'b1) begin
+              state <= DRP_READ_TEMP_WAIT_DRDY;
+            end
+          end else begin
+            state <= DRP_READ_TEMP_WAIT_DRDY;
+          end
+        end
 
-//axi registers read
-always @(posedge up_clk) begin
-  if (s_axi_aresetn == 1'b0) begin
-    up_rack <= 'd0;
-    up_rdata <= 'd0;
-  end else begin
-    up_rack <= up_rreq_s;
-    if (up_rreq_s == 1'b1) begin
-      case (up_raddr_s)
-        8'h00: up_rdata <= CORE_VERSION;
-        8'h01: up_rdata <= ID;
-        8'h02: up_rdata <= up_scratch;
-        8'h03: up_rdata <= CORE_MAGIC;
-        8'h10: up_rdata <= up_irq_mask;
-        8'h11: up_rdata <= up_irq_pending;
-        8'h12: up_rdata <= up_irq_source;
-        8'h20: up_rdata <= up_resetn;
-        8'h21: up_rdata <= pwm_width;
-        8'h22: up_rdata <= up_tacho_val;
-        8'h23: up_rdata <= up_tacho_tol;
-        8'h24: up_rdata <= INTERNAL_SYSMONE;
-        8'h30: up_rdata <= PWM_PERIOD;
-        8'h31: up_rdata <= up_tacho_avg_sum;
-        8'h32: up_rdata <= sysmone_temp;
-        8'h40: up_rdata <= up_temp_00_h;
-        8'h41: up_rdata <= up_temp_25_l;
-        8'h42: up_rdata <= up_temp_25_h;
-        8'h43: up_rdata <= up_temp_50_l;
-        8'h44: up_rdata <= up_temp_50_h;
-        8'h45: up_rdata <= up_temp_75_l;
-        8'h46: up_rdata <= up_temp_75_h;
-        8'h47: up_rdata <= up_temp_100_l;
-        8'h50: up_rdata <= up_tacho_25;
-        8'h51: up_rdata <= up_tacho_50;
-        8'h52: up_rdata <= up_tacho_75;
-        8'h53: up_rdata <= up_tacho_100;
-        8'h54: up_rdata <= up_tacho_25_tol;
-        8'h55: up_rdata <= up_tacho_50_tol;
-        8'h56: up_rdata <= up_tacho_75_tol;
-        8'h57: up_rdata <= up_tacho_100_tol;
-        default: up_rdata <= 0;
+        DRP_READ_TEMP_WAIT_DRDY : begin
+          if (INTERNAL_SYSMONE == 1) begin
+            if (drp_drdy == 1'b1) begin
+              sysmone_temp <= drp_do;
+              state <= GET_TACHO;
+            end else begin
+              drp_den_reg <= {1'b0, drp_den_reg[1]};
+              drp_dwe_reg <= {1'b0, drp_dwe_reg[1]};
+            end
+          end else begin
+            sysmone_temp <= temp_in;
+            state <= GET_TACHO;
+          end
+        end
+
+        GET_TACHO : begin
+          //adding up tacho measurements in order to obtain a mean value from 32 samples
+          if ((tacho_avg_cnt == AVERAGE_DIV) || (counter_overflow) || (!pwm_change_done)) begin
+            //once a set measurements has been obtained, reset the values
+            tacho_avg_sum <= 1'b0;
+            tacho_avg_cnt <= 1'b0;
+            tacho_meas_ack <= 1'b0;
+          end else if ((tacho_meas_new) && (pwm_change_done)) begin
+            //tacho_meas_new and tacho_meas_ack ensure the value is read at the right time and only once
+            tacho_avg_sum <= tacho_avg_sum + tacho_meas;
+            tacho_avg_cnt <= tacho_avg_cnt + 1'b1;
+            //acknowledge tha the current values has been added
+            tacho_meas_ack <= 1'b1;
+          end else begin
+            tacho_meas_ack <= 1'b0;
+          end
+          state <= EVAL_TEMP;
+        end
+
+        EVAL_TEMP : begin
+          //pwm section
+          //the pwm only has to be changed when passing through these temperature intervals
+          if (sysmone_temp < up_temp_00_h) begin
+            //PWM DUTY should be 0%
+            pwm_width_req <= 1'b0;
+          end else if ((sysmone_temp > up_temp_25_l) && (sysmone_temp < up_temp_25_h)) begin
+            //PWM DUTY should be 25%
+            pwm_width_req <= PWM_ONTIME_25;
+          end else if ((sysmone_temp > up_temp_50_l) && (sysmone_temp < up_temp_50_h)) begin
+            //PWM DUTY should be 50%
+            pwm_width_req <= PWM_ONTIME_50;
+          end else if ((sysmone_temp > up_temp_75_l) && (sysmone_temp < up_temp_75_h)) begin
+            //PWM DUTY should be 75%
+            pwm_width_req <= PWM_ONTIME_75;
+          end else if (sysmone_temp > up_temp_100_l) begin
+            //PWM DUTY should be 100%
+            pwm_width_req <= PWM_PERIOD;
+            //default to 100% duty cycle after reset if not within temperature intervals described above
+          end else if ((sysmone_temp != 'h0) && (pwm_width == 'h0)) begin
+            pwm_width_req <= PWM_PERIOD;
+          end else begin
+            //if no changes are needed make sure to mantain current pwm
+            pwm_width_req <= pwm_width;
+          end
+          state <= SET_PWM;
+        end
+
+        SET_PWM : begin
+          if ((up_pwm_width != pwm_width) && (up_pwm_width >= pwm_width_req) && (up_pwm_width <= PWM_PERIOD) && (pwm_change_done)) begin
+            pwm_width <= up_pwm_width;
+            pulse_gen_load_config <= 1'b1;
+            //clear alarm when pwm duty changes
+          end else if ((pwm_width != pwm_width_req) && (pwm_width_req > up_pwm_width) && (pwm_change_done)) begin
+            pwm_width <= pwm_width_req;
+            pulse_gen_load_config <= 1'b1;
+            temp_increase_alarm <= 1'b1;
+            //clear alarm when pwm duty changes
+          end
+          state <= EVAL_TACHO;
+        end
+
+        EVAL_TACHO : begin
+          temp_increase_alarm <= 1'b0;
+          //tacho section
+          //check if the fan is turning then see if it is turning correctly
+          if(counter_overflow & pwm_change_done) begin
+            //if overflow is 1 then the fan is not turning so do something
+            tacho_alarm <= 1'b1;
+          end else if (tacho_avg_cnt == AVERAGE_DIV) begin
+            //check rpm according to the current pwm duty cycle
+            //tacho_alarm is only asserted for certain known pwm duty cycles and
+            //for timeout
+            up_tacho_avg_sum <= tacho_avg_sum [AVG_POW + 24 : AVG_POW];
+            tacho_meas_int <= 1'b1;
+            if ((pwm_width == PWM_ONTIME_25) && (up_tacho_en == 0)) begin
+              if ((tacho_avg_sum [AVG_POW + 24 : AVG_POW] > up_tacho_25 + up_tacho_25_tol) || (tacho_avg_sum [AVG_POW + 24 : AVG_POW] < up_tacho_25 - up_tacho_25_tol)) begin
+                //the fan is turning but not as expected
+                tacho_alarm <= 1'b1;
+              end
+            end else if ((pwm_width == PWM_ONTIME_50) && (up_tacho_en == 0)) begin
+              if ((tacho_avg_sum [AVG_POW + 24 : AVG_POW] > up_tacho_50 + up_tacho_50_tol) || (tacho_avg_sum [AVG_POW + 24 : AVG_POW] < up_tacho_50 - up_tacho_50_tol)) begin
+                //the fan is turning but not as expected
+                tacho_alarm <= 1'b1;
+              end
+            end else if ((pwm_width == PWM_ONTIME_75) && (up_tacho_en == 0)) begin
+              if ((tacho_avg_sum [AVG_POW + 24 : AVG_POW] > up_tacho_75 + up_tacho_75_tol) || (tacho_avg_sum [AVG_POW + 24 : AVG_POW] < up_tacho_75 - up_tacho_75_tol)) begin
+                //the fan is turning but not as expected
+                tacho_alarm <= 1'b1;
+              end
+            end else if ((pwm_width == PWM_PERIOD) && (up_tacho_en == 0)) begin
+              if ((tacho_avg_sum [AVG_POW + 24 : AVG_POW] > up_tacho_100 + up_tacho_100_tol) || (tacho_avg_sum [AVG_POW + 24 : AVG_POW] < up_tacho_100 - up_tacho_100_tol)) begin
+                //the fan is turning but not as expected
+                tacho_alarm <= 1'b1;
+              end
+            end else if ((pwm_width == up_pwm_width) && up_tacho_en) begin
+              if ((tacho_avg_sum [AVG_POW + 24 : AVG_POW] > up_tacho_val + up_tacho_tol) || (tacho_avg_sum [AVG_POW + 24 : AVG_POW] < up_tacho_val - up_tacho_tol)) begin
+                //the fan is turning but not as expected
+                tacho_alarm <= 1'b1;
+              end
+            end
+          end
+          state <= DRP_WAIT_FSM_EN;
+        end
+        default :
+          state <= DRP_WAIT_FSM_EN;
       endcase
+    end
+
+  //axi registers write
+  always @(posedge up_clk) begin
+    if (up_resetn == 1'b0) begin
+      up_pwm_width <= 'd0;
+      up_tacho_val <= 'd0;
+      up_tacho_tol <= 'd0;
+      up_tacho_en <= 'd0;
+      up_scratch <= 'd0;
+      up_temp_00_h <= THRESH_PWM_000;
+      up_temp_25_l <= THRESH_PWM_025_L;
+      up_temp_25_h <= THRESH_PWM_025_H;
+      up_temp_50_l <= THRESH_PWM_050_L;
+      up_temp_50_h <= THRESH_PWM_050_H;
+      up_temp_75_l <= THRESH_PWM_075_L;
+      up_temp_75_h <= THRESH_PWM_075_H;
+      up_temp_100_l <= THRESH_PWM_100;
+      up_tacho_25 <= TACHO_T25;
+      up_tacho_50 <= TACHO_T50;
+      up_tacho_75 <= TACHO_T75;
+      up_tacho_100 <= TACHO_T100;
+      up_tacho_25_tol <= TACHO_T25 * TACHO_TOL_PERCENT / 100;
+      up_tacho_50_tol <= TACHO_T50 * TACHO_TOL_PERCENT / 100;
+      up_tacho_75_tol <= TACHO_T75 * TACHO_TOL_PERCENT / 100;
+      up_tacho_100_tol <= TACHO_T100 * TACHO_TOL_PERCENT / 100;
+      up_irq_mask <= 4'b1111;
     end else begin
-      up_rdata <= 32'd0;
+      if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h02)) begin
+        up_scratch <= up_wdata_s;
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h21)) begin
+        up_pwm_width <= up_wdata_s;
+        up_tacho_en <= 1'b0;
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h22)) begin
+        up_tacho_val <= up_wdata_s;
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h23)) begin
+        up_tacho_tol <= up_wdata_s;
+        up_tacho_en <= 1'b1;
+      end else if (temp_increase_alarm) begin
+        up_tacho_en <= 1'b0;
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h40)) begin
+        up_temp_00_h <= up_wdata_s;
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h41)) begin
+        up_temp_25_l <= up_wdata_s;
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h42)) begin
+        up_temp_25_h <= up_wdata_s;
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h43)) begin
+        up_temp_50_l <= up_wdata_s;
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h44)) begin
+        up_temp_50_h <= up_wdata_s;
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h45)) begin
+        up_temp_75_l <= up_wdata_s;
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h46)) begin
+        up_temp_75_h <= up_wdata_s;
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h47)) begin
+        up_temp_100_l <= up_wdata_s;
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h50)) begin
+        up_tacho_25 <= up_wdata_s;
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h51)) begin
+        up_tacho_50 <= up_wdata_s;
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h52)) begin
+        up_tacho_75 <= up_wdata_s;
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h53)) begin
+        up_tacho_100 <= up_wdata_s;
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h54)) begin
+        up_tacho_25_tol <= up_wdata_s;
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h55)) begin
+        up_tacho_50_tol <= up_wdata_s;
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h56)) begin
+        up_tacho_75_tol <= up_wdata_s;
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h57)) begin
+        up_tacho_100_tol <= up_wdata_s;
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h10)) begin
+        up_irq_mask <= up_wdata_s[3:0];
+      end
     end
   end
-end
 
-//IRQ handling
-always @(posedge up_clk) begin
-  if (up_resetn == 1'b0) begin
-    irq <= 1'b0;
-  end else begin
-    irq <= |up_irq_pending;
+  //writing reset
+  always @(posedge up_clk) begin
+    if (s_axi_aresetn == 1'b0) begin
+      up_wack <= 'd0;
+      up_resetn <= 1'd0;
+    end else begin
+      up_wack <= up_wreq_s;
+      if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h20)) begin
+        up_resetn <= up_wdata_s[0];
+      end else begin
+        up_resetn <= 1'd1;
+      end
+    end
   end
-end
 
-always @(posedge up_clk) begin
-  if (up_resetn == 1'b0) begin
-    up_irq_source <= 4'b0000;
-  end else begin
-    up_irq_source <= up_irq_trigger | (up_irq_source & ~up_irq_source_clear);
+  //axi registers read
+  always @(posedge up_clk) begin
+    if (s_axi_aresetn == 1'b0) begin
+      up_rack <= 'd0;
+      up_rdata <= 'd0;
+    end else begin
+      up_rack <= up_rreq_s;
+      if (up_rreq_s == 1'b1) begin
+        case (up_raddr_s)
+          8'h00: up_rdata <= CORE_VERSION;
+          8'h01: up_rdata <= ID;
+          8'h02: up_rdata <= up_scratch;
+          8'h03: up_rdata <= CORE_MAGIC;
+          8'h10: up_rdata <= up_irq_mask;
+          8'h11: up_rdata <= up_irq_pending;
+          8'h12: up_rdata <= up_irq_source;
+          8'h20: up_rdata <= up_resetn;
+          8'h21: up_rdata <= pwm_width;
+          8'h22: up_rdata <= up_tacho_val;
+          8'h23: up_rdata <= up_tacho_tol;
+          8'h24: up_rdata <= INTERNAL_SYSMONE;
+          8'h30: up_rdata <= PWM_PERIOD;
+          8'h31: up_rdata <= up_tacho_avg_sum;
+          8'h32: up_rdata <= sysmone_temp;
+          8'h40: up_rdata <= up_temp_00_h;
+          8'h41: up_rdata <= up_temp_25_l;
+          8'h42: up_rdata <= up_temp_25_h;
+          8'h43: up_rdata <= up_temp_50_l;
+          8'h44: up_rdata <= up_temp_50_h;
+          8'h45: up_rdata <= up_temp_75_l;
+          8'h46: up_rdata <= up_temp_75_h;
+          8'h47: up_rdata <= up_temp_100_l;
+          8'h50: up_rdata <= up_tacho_25;
+          8'h51: up_rdata <= up_tacho_50;
+          8'h52: up_rdata <= up_tacho_75;
+          8'h53: up_rdata <= up_tacho_100;
+          8'h54: up_rdata <= up_tacho_25_tol;
+          8'h55: up_rdata <= up_tacho_50_tol;
+          8'h56: up_rdata <= up_tacho_75_tol;
+          8'h57: up_rdata <= up_tacho_100_tol;
+          default: up_rdata <= 0;
+        endcase
+      end else begin
+        up_rdata <= 32'd0;
+      end
+    end
   end
-end
 
-//tacho measurement logic
-always @(posedge up_clk) begin
-  if (up_resetn == 1'b0) begin
-    tacho_edge_det <= 'h0;
-    tacho_meas <= 'h0;
-    tacho_meas_new <= 'h0;
-    tacho_delayed <= 'h0;
-  end else begin
-    //edge detection of tacho signal
-    tacho_delayed <= tacho;
-    tacho_edge_det <= tacho & ~tacho_delayed;
-    if ((tacho_edge_det == 1'b1) && (pwm_change_done)) begin
-      //measurement is recorded
-      tacho_meas <= counter_reg;
-      //signal indicates new measurement completed
-      tacho_meas_new <= 1'b1;
-    end else if(tacho_meas_ack == 1'b1) begin
-      //acknowledge received from state machine
-      //resetting new measurement flag
+  //IRQ handling
+  always @(posedge up_clk) begin
+    if (up_resetn == 1'b0) begin
+      irq <= 1'b0;
+    end else begin
+      irq <= |up_irq_pending;
+    end
+  end
+
+  always @(posedge up_clk) begin
+    if (up_resetn == 1'b0) begin
+      up_irq_source <= 4'b0000;
+    end else begin
+      up_irq_source <= up_irq_trigger | (up_irq_source & ~up_irq_source_clear);
+    end
+  end
+
+  //tacho measurement logic
+  always @(posedge up_clk) begin
+    if (up_resetn == 1'b0) begin
+      tacho_edge_det <= 'h0;
+      tacho_meas <= 'h0;
       tacho_meas_new <= 'h0;
-    end
-  end
-end
-
-//pwm change proc
-always @(posedge up_clk) begin
-  if (up_resetn == 1'b0) begin
-    pwm_change_done <= 1'b1;
-  end else if (counter_overflow) begin
-    pwm_change_done <= 1'b1;
-  end else if (pulse_gen_load_config) begin
-    pwm_change_done <= 'h0;
-  end
-end
-
-//tacho measurement and pwm change delay counter
-always @(posedge up_clk) begin
-  if ((up_resetn & counter_resetn) == 1'b0) begin
-    counter_reg <= 'h0;
-    counter_overflow <= 1'b0;
-  end else begin
-    if (counter_reg == OVERFLOW_LIM) begin
-      counter_reg <= 'h0;
-      counter_overflow <= 1'b1;
+      tacho_delayed <= 'h0;
     end else begin
-      counter_reg <= counter_reg + 1'b1;
+      //edge detection of tacho signal
+      tacho_delayed <= tacho;
+      tacho_edge_det <= tacho & ~tacho_delayed;
+      if ((tacho_edge_det == 1'b1) && (pwm_change_done)) begin
+        //measurement is recorded
+        tacho_meas <= counter_reg;
+        //signal indicates new measurement completed
+        tacho_meas_new <= 1'b1;
+      end else if(tacho_meas_ack == 1'b1) begin
+        //acknowledge received from state machine
+        //resetting new measurement flag
+        tacho_meas_new <= 'h0;
+      end
     end
   end
-end
 
-//prescaler; sets the rate at which the fsm is run
-always @(posedge up_clk) begin
-  if (up_resetn  == 1'b0) begin
-    presc_reg <= 'h0;
-  end else begin
-    if (presc_reg == 'h8000) begin
+  //pwm change proc
+  always @(posedge up_clk) begin
+    if (up_resetn == 1'b0) begin
+      pwm_change_done <= 1'b1;
+    end else if (counter_overflow) begin
+      pwm_change_done <= 1'b1;
+    end else if (pulse_gen_load_config) begin
+      pwm_change_done <= 'h0;
+    end
+  end
+
+  //tacho measurement and pwm change delay counter
+  always @(posedge up_clk) begin
+    if ((up_resetn & counter_resetn) == 1'b0) begin
+      counter_reg <= 'h0;
+      counter_overflow <= 1'b0;
+    end else begin
+      if (counter_reg == OVERFLOW_LIM) begin
+        counter_reg <= 'h0;
+        counter_overflow <= 1'b1;
+      end else begin
+        counter_reg <= counter_reg + 1'b1;
+      end
+    end
+  end
+
+  //prescaler; sets the rate at which the fsm is run
+  always @(posedge up_clk) begin
+    if (up_resetn  == 1'b0) begin
       presc_reg <= 'h0;
     end else begin
-      presc_reg <= presc_reg + 1'b1;
+      if (presc_reg == 'h8000) begin
+        presc_reg <= 'h0;
+      end else begin
+        presc_reg <= presc_reg + 1'b1;
+      end
     end
   end
-end
 endmodule
diff --git a/library/axi_fmcadc5_sync/axi_fmcadc5_sync.v b/library/axi_fmcadc5_sync/axi_fmcadc5_sync.v
index 6230bcb00..d6f227227 100644
--- a/library/axi_fmcadc5_sync/axi_fmcadc5_sync.v
+++ b/library/axi_fmcadc5_sync/axi_fmcadc5_sync.v
@@ -45,8 +45,8 @@ module axi_fmcadc5_sync #(
   parameter [ 7:0]  FPGA_FAMILY = 0,
   parameter [ 7:0]  SPEED_GRADE = 0,
   parameter [ 7:0]  DEV_PACKAGE = 0,
-  parameter         DELAY_REFCLK_FREQUENCY = 200) (
-
+  parameter         DELAY_REFCLK_FREQUENCY = 200
+) (
     // receive interface
 
   input             rx_clk,
@@ -112,7 +112,8 @@ module axi_fmcadc5_sync #(
   output  [  1:0]   s_axi_rresp,
   input             s_axi_rready,
   input   [  2:0]   s_axi_awprot,
-  input   [  2:0]   s_axi_arprot);
+  input   [  2:0]   s_axi_arprot
+);
 
   // version
 
@@ -582,7 +583,7 @@ module axi_fmcadc5_sync #(
           14'h0001: up_rdata <= ID;
           14'h0002: up_rdata <= up_scratch;
           14'h0003: up_rdata <= up_timer;
-	  14'h0007: up_rdata <= {FPGA_TECHNOLOGY,FPGA_FAMILY,SPEED_GRADE,DEV_PACKAGE}; // [8,8,8,8]
+          14'h0007: up_rdata <= {FPGA_TECHNOLOGY,FPGA_FAMILY,SPEED_GRADE,DEV_PACKAGE}; // [8,8,8,8]
           14'h0010: up_rdata <= {31'd0, up_spi_req};
           14'h0011: up_rdata <= {31'd0, up_spi_gnt};
           14'h0012: up_rdata <= {24'd0, up_spi_csn};
@@ -770,8 +771,8 @@ module axi_fmcadc5_sync #(
     .IODELAY_ENABLE (1),
     .IODELAY_CTRL (1),
     .IODELAY_GROUP ("FMCADC5_SYSREF_IODELAY_GROUP"),
-    .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
-  i_rx_sysref (
+    .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
+  ) i_rx_sysref (
     .tx_clk (rx_clk),
     .tx_data_p (rx_sysref_e),
     .tx_data_n (rx_sysref_e),
@@ -817,6 +818,3 @@ module axi_fmcadc5_sync #(
     .up_rack (up_rack));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_fmcadc5_sync/axi_fmcadc5_sync_calcor.v b/library/axi_fmcadc5_sync/axi_fmcadc5_sync_calcor.v
index c3dbb7c04..7c71be7ac 100644
--- a/library/axi_fmcadc5_sync/axi_fmcadc5_sync_calcor.v
+++ b/library/axi_fmcadc5_sync/axi_fmcadc5_sync_calcor.v
@@ -61,7 +61,8 @@ module axi_fmcadc5_sync_calcor (
   input   [ 15:0]   rx_cor_scale_0,
   input   [ 15:0]   rx_cor_offset_0,
   input   [ 15:0]   rx_cor_scale_1,
-  input   [ 15:0]   rx_cor_offset_1);
+  input   [ 15:0]   rx_cor_offset_1
+);
 
   // internal registers
 
@@ -124,14 +125,19 @@ module axi_fmcadc5_sync_calcor (
 
   generate
   for (n = 0; n <= 15; n = n + 1) begin: g_rx_gain
-  ad_mul #(.DELAY_DATA_WIDTH(1)) i_rx_gain_0 (
+  ad_mul #(
+    .DELAY_DATA_WIDTH(1)
+  ) i_rx_gain_0 (
     .clk (rx_clk),
     .data_a ({rx_cor_data_0[n][15], rx_cor_data_0[n]}),
     .data_b ({1'b0, rx_cor_scale_0}),
     .data_p (rx_cor_data_0_s[n]),
     .ddata_in (1'd0),
     .ddata_out ());
-  ad_mul #(.DELAY_DATA_WIDTH(1)) i_rx_gain_1 (
+
+  ad_mul #(
+    .DELAY_DATA_WIDTH(1)
+  ) i_rx_gain_1 (
     .clk (rx_clk),
     .data_a ({rx_cor_data_1[n][15], rx_cor_data_1[n]}),
     .data_b ({1'b0, rx_cor_scale_1}),
@@ -317,6 +323,3 @@ module axi_fmcadc5_sync_calcor (
   endgenerate
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_generic_adc/axi_generic_adc.v b/library/axi_generic_adc/axi_generic_adc.v
index 4533d3e2a..ca506a904 100644
--- a/library/axi_generic_adc/axi_generic_adc.v
+++ b/library/axi_generic_adc/axi_generic_adc.v
@@ -38,8 +38,8 @@
 module axi_generic_adc #(
 
   parameter   NUM_OF_CHANNELS = 2,
-  parameter   ID = 0)(
-
+  parameter   ID = 0
+) (
   input adc_clk,
   output [NUM_OF_CHANNELS-1:0] adc_enable,
   input adc_dovf,
@@ -65,187 +65,188 @@ module axi_generic_adc #(
   input    s_axi_rready,
   input   [ 2:0]  s_axi_awprot,
   input   [ 2:0]  s_axi_arprot
-
 );
 
+  reg  [31:0] up_rdata = 'd0;
+  reg        up_rack = 'd0;
+  reg        up_wack = 'd0;
 
-reg  [31:0] up_rdata = 'd0;
-reg        up_rack = 'd0;
-reg        up_wack = 'd0;
+  wire adc_rst;
+  wire up_rstn;
+  wire up_clk;
+  wire [13:0] up_waddr_s;
+  wire [13:0] up_raddr_s;
 
-wire adc_rst;
-wire up_rstn;
-wire up_clk;
-wire [13:0] up_waddr_s;
-wire [13:0] up_raddr_s;
+  // internal signals
 
-// internal signals
+  wire        up_sel_s;
+  wire        up_wr_s;
+  wire [13:0] up_addr_s;
+  wire [31:0] up_wdata_s;
+  wire [31:0] up_rdata_s[0:NUM_OF_CHANNELS];
+  wire        up_rack_s[0:NUM_OF_CHANNELS];
+  wire        up_wack_s[0:NUM_OF_CHANNELS];
 
-wire        up_sel_s;
-wire        up_wr_s;
-wire [13:0] up_addr_s;
-wire [31:0] up_wdata_s;
-wire [31:0] up_rdata_s[0:NUM_OF_CHANNELS];
-wire        up_rack_s[0:NUM_OF_CHANNELS];
-wire        up_wack_s[0:NUM_OF_CHANNELS];
+  reg [31:0]  up_rdata_r;
+  reg         up_rack_r;
+  reg         up_wack_r;
 
-reg [31:0]  up_rdata_r;
-reg         up_rack_r;
-reg         up_wack_r;
+  assign up_clk = s_axi_aclk;
+  assign up_rstn = s_axi_aresetn;
 
-assign up_clk = s_axi_aclk;
-assign up_rstn = s_axi_aresetn;
-
-integer j;
-always @(*)
-begin
-  up_rdata_r = 'h00;
-  up_rack_r = 'h00;
-  up_wack_r = 'h00;
-  for (j = 0; j <= NUM_OF_CHANNELS; j=j+1) begin
-    up_rack_r = up_rack_r | up_rack_s[j];
-    up_wack_r = up_wack_r | up_wack_s[j];
-    up_rdata_r = up_rdata_r | up_rdata_s[j];
+  integer j;
+  always @(*) begin
+    up_rdata_r = 'h00;
+    up_rack_r = 'h00;
+    up_wack_r = 'h00;
+    for (j = 0; j <= NUM_OF_CHANNELS; j=j+1) begin
+      up_rack_r = up_rack_r | up_rack_s[j];
+      up_wack_r = up_wack_r | up_wack_s[j];
+      up_rdata_r = up_rdata_r | up_rdata_s[j];
+    end
   end
-end
 
-always @(negedge up_rstn or posedge up_clk) begin
-  if (up_rstn == 0) begin
-    up_rdata <= 'd0;
-    up_rack <= 'd0;
-    up_wack <= 'd0;
-  end else begin
-    up_rdata <= up_rdata_r;
-    up_rack <= up_rack_r;
-    up_wack <= up_wack_r;
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_rdata <= 'd0;
+      up_rack <= 'd0;
+      up_wack <= 'd0;
+    end else begin
+      up_rdata <= up_rdata_r;
+      up_rack <= up_rack_r;
+      up_wack <= up_wack_r;
+    end
   end
-end
 
-up_adc_common #(.ID(ID)) i_up_adc_common (
-  .mmcm_rst (),
-  .adc_clk (adc_clk),
-  .adc_rst (adc_rst),
-  .adc_r1_mode (),
-  .adc_ddr_edgesel (),
-  .adc_pin_mode (),
-  .adc_status ('h00),
-  .adc_sync_status (1'b1),
-  .adc_status_ovf (adc_dovf),
-  .adc_clk_ratio (32'd1),
-  .adc_start_code (),
-  .adc_sref_sync (),
-  .adc_sync (),
-  .up_pps_rcounter (32'b0),
-  .up_pps_status (1'b0),
-  .up_pps_irq_mask (),
-  .up_adc_ce (),
-  .up_status_pn_err (1'b0),
-  .up_status_pn_oos (1'b0),
-  .up_status_or (1'b0),
-  .up_drp_sel (),
-  .up_drp_wr (),
-  .up_drp_addr (),
-  .up_drp_wdata (),
-  .up_drp_rdata (32'd0),
-  .up_drp_ready (1'd0),
-  .up_drp_locked (1'd1),
-  .up_usr_chanmax_out (),
-  .up_usr_chanmax_in (NUM_OF_CHANNELS),
-  .up_adc_gpio_in (32'b0),
-  .up_adc_gpio_out (),
-  .up_rstn (up_rstn),
-  .up_clk (up_clk),
-  .up_wreq (up_wreq_s),
-  .up_waddr (up_waddr_s),
-  .up_wdata (up_wdata_s),
-  .up_wack (up_wack_s[NUM_OF_CHANNELS]),
-  .up_rreq (up_rreq_s),
-  .up_raddr (up_raddr_s),
-  .up_rdata (up_rdata_s[NUM_OF_CHANNELS]),
-  .up_rack (up_rack_s[NUM_OF_CHANNELS]));
-
-// up bus interface
-
-up_axi i_up_axi (
-  .up_rstn (up_rstn),
-  .up_clk (up_clk),
-  .up_axi_awvalid (s_axi_awvalid),
-  .up_axi_awaddr (s_axi_awaddr),
-  .up_axi_awready (s_axi_awready),
-  .up_axi_wvalid (s_axi_wvalid),
-  .up_axi_wdata (s_axi_wdata),
-  .up_axi_wstrb (s_axi_wstrb),
-  .up_axi_wready (s_axi_wready),
-  .up_axi_bvalid (s_axi_bvalid),
-  .up_axi_bresp (s_axi_bresp),
-  .up_axi_bready (s_axi_bready),
-  .up_axi_arvalid (s_axi_arvalid),
-  .up_axi_araddr (s_axi_araddr),
-  .up_axi_arready (s_axi_arready),
-  .up_axi_rvalid (s_axi_rvalid),
-  .up_axi_rresp (s_axi_rresp),
-  .up_axi_rdata (s_axi_rdata),
-  .up_axi_rready (s_axi_rready),
-  .up_wreq (up_wreq_s),
-  .up_waddr (up_waddr_s),
-  .up_wdata (up_wdata_s),
-  .up_wack (up_wack),
-  .up_rreq (up_rreq_s),
-  .up_raddr (up_raddr_s),
-  .up_rdata (up_rdata),
-  .up_rack (up_rack));
-
-generate
-genvar i;
-
-for (i = 0; i < NUM_OF_CHANNELS; i=i+1) begin
-  up_adc_channel #(.CHANNEL_ID(i)) i_up_adc_channel (
+  up_adc_common #(
+    .ID(ID)
+  ) i_up_adc_common (
+    .mmcm_rst (),
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
-    .adc_enable (adc_enable[i]),
-    .adc_iqcor_enb (),
-    .adc_dcfilt_enb (),
-    .adc_dfmt_se (),
-    .adc_dfmt_type (),
-    .adc_dfmt_enable (),
-    .adc_dcfilt_offset (),
-    .adc_dcfilt_coeff (),
-    .adc_iqcor_coeff_1 (),
-    .adc_iqcor_coeff_2 (),
-    .adc_pnseq_sel (),
-    .adc_data_sel (),
-    .adc_pn_err (1'b0),
-    .adc_pn_oos (1'b0),
-    .adc_or (1'b0),
-    .up_adc_pn_err (),
-    .up_adc_pn_oos (),
-    .up_adc_or (),
-    .up_usr_datatype_be (),
-    .up_usr_datatype_signed (),
-    .up_usr_datatype_shift (),
-    .up_usr_datatype_total_bits (),
-    .up_usr_datatype_bits (),
-    .up_usr_decimation_m (),
-    .up_usr_decimation_n (),
-    .adc_usr_datatype_be (1'b0),
-    .adc_usr_datatype_signed (1'b1),
-    .adc_usr_datatype_shift (8'd0),
-    .adc_usr_datatype_total_bits (8'd32),
-    .adc_usr_datatype_bits (8'd32),
-    .adc_usr_decimation_m (16'd1),
-    .adc_usr_decimation_n (16'd1),
+    .adc_r1_mode (),
+    .adc_ddr_edgesel (),
+    .adc_pin_mode (),
+    .adc_status ('h00),
+    .adc_sync_status (1'b1),
+    .adc_status_ovf (adc_dovf),
+    .adc_clk_ratio (32'd1),
+    .adc_start_code (),
+    .adc_sref_sync (),
+    .adc_sync (),
+    .up_pps_rcounter (32'b0),
+    .up_pps_status (1'b0),
+    .up_pps_irq_mask (),
+    .up_adc_ce (),
+    .up_status_pn_err (1'b0),
+    .up_status_pn_oos (1'b0),
+    .up_status_or (1'b0),
+    .up_drp_sel (),
+    .up_drp_wr (),
+    .up_drp_addr (),
+    .up_drp_wdata (),
+    .up_drp_rdata (32'd0),
+    .up_drp_ready (1'd0),
+    .up_drp_locked (1'd1),
+    .up_usr_chanmax_out (),
+    .up_usr_chanmax_in (NUM_OF_CHANNELS),
+    .up_adc_gpio_in (32'b0),
+    .up_adc_gpio_out (),
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_wreq (up_wreq_s),
     .up_waddr (up_waddr_s),
     .up_wdata (up_wdata_s),
-    .up_wack (up_wack_s[i]),
+    .up_wack (up_wack_s[NUM_OF_CHANNELS]),
     .up_rreq (up_rreq_s),
     .up_raddr (up_raddr_s),
-    .up_rdata (up_rdata_s[i]),
-    .up_rack (up_rack_s[i]));
-end
+    .up_rdata (up_rdata_s[NUM_OF_CHANNELS]),
+    .up_rack (up_rack_s[NUM_OF_CHANNELS]));
 
-endgenerate
+  // up bus interface
+
+  up_axi i_up_axi (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_axi_awvalid (s_axi_awvalid),
+    .up_axi_awaddr (s_axi_awaddr),
+    .up_axi_awready (s_axi_awready),
+    .up_axi_wvalid (s_axi_wvalid),
+    .up_axi_wdata (s_axi_wdata),
+    .up_axi_wstrb (s_axi_wstrb),
+    .up_axi_wready (s_axi_wready),
+    .up_axi_bvalid (s_axi_bvalid),
+    .up_axi_bresp (s_axi_bresp),
+    .up_axi_bready (s_axi_bready),
+    .up_axi_arvalid (s_axi_arvalid),
+    .up_axi_araddr (s_axi_araddr),
+    .up_axi_arready (s_axi_arready),
+    .up_axi_rvalid (s_axi_rvalid),
+    .up_axi_rresp (s_axi_rresp),
+    .up_axi_rdata (s_axi_rdata),
+    .up_axi_rready (s_axi_rready),
+    .up_wreq (up_wreq_s),
+    .up_waddr (up_waddr_s),
+    .up_wdata (up_wdata_s),
+    .up_wack (up_wack),
+    .up_rreq (up_rreq_s),
+    .up_raddr (up_raddr_s),
+    .up_rdata (up_rdata),
+    .up_rack (up_rack));
+
+  generate
+  genvar i;
+
+  for (i = 0; i < NUM_OF_CHANNELS; i=i+1) begin
+    up_adc_channel #(
+      .CHANNEL_ID(i)
+    ) i_up_adc_channel (
+      .adc_clk (adc_clk),
+      .adc_rst (adc_rst),
+      .adc_enable (adc_enable[i]),
+      .adc_iqcor_enb (),
+      .adc_dcfilt_enb (),
+      .adc_dfmt_se (),
+      .adc_dfmt_type (),
+      .adc_dfmt_enable (),
+      .adc_dcfilt_offset (),
+      .adc_dcfilt_coeff (),
+      .adc_iqcor_coeff_1 (),
+      .adc_iqcor_coeff_2 (),
+      .adc_pnseq_sel (),
+      .adc_data_sel (),
+      .adc_pn_err (1'b0),
+      .adc_pn_oos (1'b0),
+      .adc_or (1'b0),
+      .up_adc_pn_err (),
+      .up_adc_pn_oos (),
+      .up_adc_or (),
+      .up_usr_datatype_be (),
+      .up_usr_datatype_signed (),
+      .up_usr_datatype_shift (),
+      .up_usr_datatype_total_bits (),
+      .up_usr_datatype_bits (),
+      .up_usr_decimation_m (),
+      .up_usr_decimation_n (),
+      .adc_usr_datatype_be (1'b0),
+      .adc_usr_datatype_signed (1'b1),
+      .adc_usr_datatype_shift (8'd0),
+      .adc_usr_datatype_total_bits (8'd32),
+      .adc_usr_datatype_bits (8'd32),
+      .adc_usr_decimation_m (16'd1),
+      .adc_usr_decimation_n (16'd1),
+      .up_rstn (up_rstn),
+      .up_clk (up_clk),
+      .up_wreq (up_wreq_s),
+      .up_waddr (up_waddr_s),
+      .up_wdata (up_wdata_s),
+      .up_wack (up_wack_s[i]),
+      .up_rreq (up_rreq_s),
+      .up_raddr (up_raddr_s),
+      .up_rdata (up_rdata_s[i]),
+      .up_rack (up_rack_s[i]));
+  end
+
+  endgenerate
 
 endmodule
diff --git a/library/axi_gpreg/axi_gpreg.v b/library/axi_gpreg/axi_gpreg.v
index b8574ec23..83c797aa1 100644
--- a/library/axi_gpreg/axi_gpreg.v
+++ b/library/axi_gpreg/axi_gpreg.v
@@ -47,9 +47,8 @@ module axi_gpreg #(
   parameter   integer BUF_ENABLE_4 = 1,
   parameter   integer BUF_ENABLE_5 = 1,
   parameter   integer BUF_ENABLE_6 = 1,
-  parameter   integer BUF_ENABLE_7 = 1)
-
- (
+  parameter   integer BUF_ENABLE_7 = 1
+) (
 
   // io
 
@@ -111,8 +110,8 @@ module axi_gpreg #(
   output  [  1:0]   s_axi_rresp,
   input             s_axi_rready,
   input   [ 2:0]    s_axi_awprot,
-  input   [ 2:0]    s_axi_arprot);
-
+  input   [ 2:0]    s_axi_arprot
+);
 
   // version
 
@@ -258,64 +257,64 @@ module axi_gpreg #(
 
   genvar n;
   generate
+    // gpio
 
-  // gpio
+    if (NUM_OF_IO < 8) begin
+      for (n = NUM_OF_IO; n < 8; n = n + 1) begin: g_unused_io
+        assign up_gp_ioenb_s[n] = 32'd0;
+        assign up_gp_out_s[n] = 32'd0;
+        assign up_wack_s[n] = 1'd0;
+        assign up_rdata_s[n] = 32'd0;
+        assign up_rack_s[n] = 1'd0;
+      end
+    end
 
-  if (NUM_OF_IO < 8) begin
-  for (n = NUM_OF_IO; n < 8; n = n + 1) begin: g_unused_io
-  assign up_gp_ioenb_s[n] = 32'd0;
-  assign up_gp_out_s[n] = 32'd0;
-  assign up_wack_s[n] = 1'd0;
-  assign up_rdata_s[n] = 32'd0;
-  assign up_rack_s[n] = 1'd0;
-  end
-  end
+    for (n = 0; n < NUM_OF_IO; n = n + 1) begin: g_io
+      axi_gpreg_io #(
+        .ID (16+n)
+      ) i_gpreg_io (
+        .up_gp_ioenb (up_gp_ioenb_s[n]),
+        .up_gp_out (up_gp_out_s[n]),
+        .up_gp_in (up_gp_in_s[n]),
+        .up_rstn (up_rstn),
+        .up_clk (up_clk),
+        .up_wreq (up_wreq),
+        .up_waddr (up_waddr),
+        .up_wdata (up_wdata),
+        .up_wack (up_wack_s[n]),
+        .up_rreq (up_rreq),
+        .up_raddr (up_raddr),
+        .up_rdata (up_rdata_s[n]),
+        .up_rack (up_rack_s[n]));
+    end
 
-  for (n = 0; n < NUM_OF_IO; n = n + 1) begin: g_io
-  axi_gpreg_io #(.ID (16+n)) i_gpreg_io (
-    .up_gp_ioenb (up_gp_ioenb_s[n]),
-    .up_gp_out (up_gp_out_s[n]),
-    .up_gp_in (up_gp_in_s[n]),
-    .up_rstn (up_rstn),
-    .up_clk (up_clk),
-    .up_wreq (up_wreq),
-    .up_waddr (up_waddr),
-    .up_wdata (up_wdata),
-    .up_wack (up_wack_s[n]),
-    .up_rreq (up_rreq),
-    .up_raddr (up_raddr),
-    .up_rdata (up_rdata_s[n]),
-    .up_rack (up_rack_s[n]));
-  end
+    // clock monitors
 
-  // clock monitors
-
-  if (NUM_OF_CLK_MONS < 8) begin
-  for (n = NUM_OF_CLK_MONS; n < 8; n = n + 1) begin: g_unused_clock_mon
-  assign up_wack_s[(8+n)] = 1'd0;
-  assign up_rdata_s[(8+n)] = 32'd0;
-  assign up_rack_s[(8+n)] = 1'd0;
-  end
-  end
-
-  for (n = 0; n < NUM_OF_CLK_MONS; n = n + 1) begin: g_clock_mon
-  axi_gpreg_clock_mon #(
-    .ID (32+n),
-    .BUF_ENABLE (BUF_ENABLE[n]))
-  i_gpreg_clock_mon (
-    .d_clk (d_clk_s[n]),
-    .up_rstn (up_rstn),
-    .up_clk (up_clk),
-    .up_wreq (up_wreq),
-    .up_waddr (up_waddr),
-    .up_wdata (up_wdata),
-    .up_wack (up_wack_s[(8+n)]),
-    .up_rreq (up_rreq),
-    .up_raddr (up_raddr),
-    .up_rdata (up_rdata_s[(8+n)]),
-    .up_rack (up_rack_s[(8+n)]));
-  end
+    if (NUM_OF_CLK_MONS < 8) begin
+      for (n = NUM_OF_CLK_MONS; n < 8; n = n + 1) begin: g_unused_clock_mon
+        assign up_wack_s[(8+n)] = 1'd0;
+        assign up_rdata_s[(8+n)] = 32'd0;
+        assign up_rack_s[(8+n)] = 1'd0;
+      end
+    end
 
+    for (n = 0; n < NUM_OF_CLK_MONS; n = n + 1) begin: g_clock_mon
+      axi_gpreg_clock_mon #(
+        .ID (32+n),
+        .BUF_ENABLE (BUF_ENABLE[n])
+      ) i_gpreg_clock_mon (
+        .d_clk (d_clk_s[n]),
+        .up_rstn (up_rstn),
+        .up_clk (up_clk),
+        .up_wreq (up_wreq),
+        .up_waddr (up_waddr),
+        .up_wdata (up_wdata),
+        .up_wack (up_wack_s[(8+n)]),
+        .up_rreq (up_rreq),
+        .up_raddr (up_raddr),
+        .up_rdata (up_rdata_s[(8+n)]),
+        .up_rack (up_rack_s[(8+n)]));
+    end
   endgenerate
 
   up_axi i_up_axi (
@@ -348,6 +347,3 @@ module axi_gpreg #(
     .up_rack (up_rack_d));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_gpreg/axi_gpreg_clock_mon.v b/library/axi_gpreg/axi_gpreg_clock_mon.v
index ea6342c7f..bc3380bce 100644
--- a/library/axi_gpreg/axi_gpreg_clock_mon.v
+++ b/library/axi_gpreg/axi_gpreg_clock_mon.v
@@ -38,7 +38,8 @@
 module axi_gpreg_clock_mon #(
 
   parameter   ID = 0,
-  parameter   BUF_ENABLE = 0) (
+  parameter   BUF_ENABLE = 0
+) (
 
   // clock
 
@@ -55,8 +56,8 @@ module axi_gpreg_clock_mon #(
   input                   up_rreq,
   input       [13:0]      up_raddr,
   output  reg [31:0]      up_rdata,
-  output  reg             up_rack);
-
+  output  reg             up_rack
+);
 
   // internal registers
 
@@ -138,6 +139,3 @@ module axi_gpreg_clock_mon #(
   endgenerate
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_gpreg/axi_gpreg_io.v b/library/axi_gpreg/axi_gpreg_io.v
index e2c23228a..445fdc29c 100644
--- a/library/axi_gpreg/axi_gpreg_io.v
+++ b/library/axi_gpreg/axi_gpreg_io.v
@@ -37,7 +37,8 @@
 
 module axi_gpreg_io #(
 
-  parameter   ID = 0) (
+  parameter   ID = 0
+) (
 
   // gpio
 
@@ -56,8 +57,8 @@ module axi_gpreg_io #(
   input                   up_rreq,
   input       [13:0]      up_raddr,
   output  reg [31:0]      up_rdata,
-  output  reg             up_rack);
-
+  output  reg             up_rack
+);
 
   // internal registers
 
@@ -111,6 +112,3 @@ module axi_gpreg_io #(
   end
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_hdmi_rx/axi_hdmi_rx.v b/library/axi_hdmi_rx/axi_hdmi_rx.v
index 790d7134e..70f3de414 100644
--- a/library/axi_hdmi_rx/axi_hdmi_rx.v
+++ b/library/axi_hdmi_rx/axi_hdmi_rx.v
@@ -38,7 +38,8 @@
 module axi_hdmi_rx  #(
 
   parameter   ID = 0,
-  parameter   IO_INTERFACE = 1) (
+  parameter   IO_INTERFACE = 1
+) (
 
   // hdmi interface
 
@@ -76,7 +77,8 @@ module axi_hdmi_rx  #(
   output      [31:0]      s_axi_rdata,
   input                   s_axi_rready,
   input       [ 2:0]      s_axi_awprot,
-  input       [ 2:0]      s_axi_arprot);
+  input       [ 2:0]      s_axi_arprot
+);
 
   // internal signals
 
@@ -113,7 +115,7 @@ module axi_hdmi_rx  #(
 
   // axi interface
 
-  up_axi i_up_axi  (
+  up_axi i_up_axi (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_axi_awvalid (s_axi_awvalid),
@@ -144,7 +146,7 @@ module axi_hdmi_rx  #(
 
   // processor interface
 
-  up_hdmi_rx i_up  (
+  up_hdmi_rx i_up (
     .hdmi_clk (hdmi_clk),
     .hdmi_rst (hdmi_rst),
     .hdmi_edge_sel (hdmi_edge_sel_s),
@@ -176,7 +178,7 @@ module axi_hdmi_rx  #(
 
   // hdmi interface
 
-  axi_hdmi_rx_core i_rx_core  (
+  axi_hdmi_rx_core i_rx_core (
     .hdmi_clk (hdmi_clk),
     .hdmi_rst (hdmi_rst),
     .hdmi_data (hdmi_data),
@@ -198,6 +200,3 @@ module axi_hdmi_rx  #(
     .hdmi_dma_data (hdmi_dma_data));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_hdmi_rx/axi_hdmi_rx_core.v b/library/axi_hdmi_rx/axi_hdmi_rx_core.v
index f38c1faa3..abe93ad7c 100644
--- a/library/axi_hdmi_rx/axi_hdmi_rx_core.v
+++ b/library/axi_hdmi_rx/axi_hdmi_rx_core.v
@@ -38,7 +38,8 @@
 
 module axi_hdmi_rx_core #(
 
-  parameter   IO_INTERFACE = 1) (
+  parameter   IO_INTERFACE = 1
+) (
 
   // hdmi interface
 
@@ -63,7 +64,8 @@ module axi_hdmi_rx_core #(
 
   output  reg             hdmi_dma_sof,
   output  reg             hdmi_dma_de,
-  output  reg [63:0]      hdmi_dma_data);
+  output  reg [63:0]      hdmi_dma_data
+);
 
   // internal registers
 
@@ -282,8 +284,8 @@ module axi_hdmi_rx_core #(
     .DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"),
     .INIT_Q1 (1'b0),
     .INIT_Q2 (1'b0),
-    .SRTYPE ("ASYNC"))
-  i_rx_data_iddr (
+    .SRTYPE ("ASYNC")
+  ) i_rx_data_iddr (
     .CE (1'b1),
     .R (1'b0),
     .S (1'b0),
@@ -308,7 +310,10 @@ module axi_hdmi_rx_core #(
 
   // super sampling, 422 to 444
 
-  ad_ss_422to444 #(.CR_CB_N(0), .DELAY_DATA_WIDTH(2)) i_ss (
+  ad_ss_422to444 #(
+    .CR_CB_N(0),
+    .DELAY_DATA_WIDTH(2)
+  ) i_ss (
     .clk (hdmi_clk),
     .s422_de (hdmi_de_422),
     .s422_sync ({hdmi_sof_422, hdmi_de_422}),
@@ -318,7 +323,9 @@ module axi_hdmi_rx_core #(
 
   // color space conversion, CrYCb to RGB
 
-  ad_csc_CrYCb2RGB #(.DELAY_DATA_WIDTH(2)) i_csc (
+  ad_csc_CrYCb2RGB #(
+    .DELAY_DATA_WIDTH(2)
+  ) i_csc (
     .clk (hdmi_clk),
     .CrYCb_sync ({hdmi_sof_ss_s, hdmi_de_ss_s}),
     .CrYCb_data (hdmi_data_ss_s),
@@ -327,7 +334,9 @@ module axi_hdmi_rx_core #(
 
   // embedded sync
 
-  axi_hdmi_rx_es #(.DATA_WIDTH(16)) i_es (
+  axi_hdmi_rx_es #(
+    .DATA_WIDTH(16)
+  ) i_es (
     .hdmi_clk (hdmi_clk),
     .hdmi_data (hdmi_data_p),
     .hdmi_vs_de (hdmi_vs_de_s),
@@ -344,6 +353,3 @@ module axi_hdmi_rx_core #(
     .hdmi_tpm_oos(hdmi_tpm_oos));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_hdmi_rx/axi_hdmi_rx_es.v b/library/axi_hdmi_rx/axi_hdmi_rx_es.v
index 80567752f..416f91019 100644
--- a/library/axi_hdmi_rx/axi_hdmi_rx_es.v
+++ b/library/axi_hdmi_rx/axi_hdmi_rx_es.v
@@ -38,7 +38,8 @@
 
 module axi_hdmi_rx_es #(
 
-  parameter   DATA_WIDTH = 32) (
+  parameter   DATA_WIDTH = 32
+) (
 
   // hdmi interface
 
@@ -46,7 +47,8 @@ module axi_hdmi_rx_es #(
   input       [(DATA_WIDTH-1):0]  hdmi_data,
   output  reg             hdmi_vs_de,
   output  reg             hdmi_hs_de,
-  output  reg [(DATA_WIDTH-1):0]  hdmi_data_de);
+  output  reg [(DATA_WIDTH-1):0]  hdmi_data_de
+);
 
   localparam  BYTE_WIDTH = DATA_WIDTH/8;
 
@@ -129,6 +131,3 @@ module axi_hdmi_rx_es #(
   end
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_hdmi_rx/axi_hdmi_rx_tpm.v b/library/axi_hdmi_rx/axi_hdmi_rx_tpm.v
index ebf7475c4..c5a859eec 100644
--- a/library/axi_hdmi_rx/axi_hdmi_rx_tpm.v
+++ b/library/axi_hdmi_rx/axi_hdmi_rx_tpm.v
@@ -41,7 +41,8 @@ module axi_hdmi_rx_tpm (
   input                   hdmi_de,
   input       [15:0]      hdmi_data,
 
-  output  reg             hdmi_tpm_oos);
+  output  reg             hdmi_tpm_oos
+);
 
   wire    [15:0]  hdmi_tpm_lr_data_s;
   wire            hdmi_tpm_lr_mismatch_s;
diff --git a/library/axi_hdmi_tx/axi_hdmi_tx.v b/library/axi_hdmi_tx/axi_hdmi_tx.v
index 11edb7d00..c5df537ba 100644
--- a/library/axi_hdmi_tx/axi_hdmi_tx.v
+++ b/library/axi_hdmi_tx/axi_hdmi_tx.v
@@ -41,7 +41,8 @@ module axi_hdmi_tx #(
   parameter   CR_CB_N = 0,
   parameter   FPGA_TECHNOLOGY = 0,
   parameter   INTERFACE = "16_BIT",
-  parameter   OUT_CLK_POLARITY = 0) (
+  parameter   OUT_CLK_POLARITY = 0
+) (
 
   // hdmi interface
 
@@ -63,8 +64,8 @@ module axi_hdmi_tx #(
   output                  hdmi_24_vsync,
   output                  hdmi_24_data_e,
   output      [23:0]      hdmi_24_data,
-  
-  // VGA interface 
+
+  // VGA interface
 
   output                  vga_hsync,
   output                  vga_vsync,
@@ -109,7 +110,8 @@ module axi_hdmi_tx #(
   output                  s_axi_rvalid,
   output      [ 1:0]      s_axi_rresp,
   output      [31:0]      s_axi_rdata,
-  input                   s_axi_rready);
+  input                   s_axi_rready
+);
 
   /* 0 = Launch on rising edge, 1 = Launch on falling edge */
 
@@ -267,8 +269,8 @@ module axi_hdmi_tx #(
   axi_hdmi_tx_core #(
     .INTERFACE(INTERFACE),
     .CR_CB_N(CR_CB_N),
-    .EMBEDDED_SYNC(EMBEDDED_SYNC))
-  i_tx_core (
+    .EMBEDDED_SYNC(EMBEDDED_SYNC)
+  )  i_tx_core (
     .reference_clk (reference_clk),
     .reference_rst (reference_rst),
     .hdmi_16_hsync (hdmi_16_hsync),
@@ -320,7 +322,9 @@ module axi_hdmi_tx #(
 
   generate
   if (FPGA_TECHNOLOGY == XILINX_ULTRASCALE || FPGA_TECHNOLOGY == XILINX_ULTRASCALE_PLUS) begin
-  ODDRE1 #(.SRVAL(1'b0)) i_clk_oddr (
+  ODDRE1 #(
+    .SRVAL(1'b0)
+  ) i_clk_oddr (
     .SR (1'b0),
     .D1 (~OUT_CLK_POLARITY),
     .D2 (OUT_CLK_POLARITY),
@@ -328,7 +332,9 @@ module axi_hdmi_tx #(
     .Q (hdmi_out_clk));
   end
   if (FPGA_TECHNOLOGY == INTEL_5SERIES) begin
-  altddio_out #(.WIDTH(1)) i_clk_oddr (
+  altddio_out #(
+    .WIDTH(1)
+  ) i_clk_oddr (
     .aclr (1'b0),
     .aset (1'b0),
     .sclr (1'b0),
@@ -342,7 +348,9 @@ module axi_hdmi_tx #(
     .dataout (hdmi_out_clk));
   end
   if (FPGA_TECHNOLOGY == XILINX_7SERIES) begin
-  ODDR #(.INIT(1'b0)) i_clk_oddr (
+  ODDR #(
+    .INIT(1'b0)
+  ) i_clk_oddr (
     .R (1'b0),
     .S (1'b0),
     .CE (1'b1),
@@ -354,6 +362,3 @@ module axi_hdmi_tx #(
   endgenerate
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_hdmi_tx/axi_hdmi_tx_core.v b/library/axi_hdmi_tx/axi_hdmi_tx_core.v
index b0ff4159b..38f1ed298 100644
--- a/library/axi_hdmi_tx/axi_hdmi_tx_core.v
+++ b/library/axi_hdmi_tx/axi_hdmi_tx_core.v
@@ -40,7 +40,8 @@ module axi_hdmi_tx_core #(
 
   parameter   CR_CB_N = 0,
   parameter   EMBEDDED_SYNC = 0,
-  parameter   INTERFACE = "16_BIT") (
+  parameter   INTERFACE = "16_BIT"
+) (
 
   // hdmi interface
 
@@ -62,7 +63,7 @@ module axi_hdmi_tx_core #(
   output  reg             hdmi_24_data_e,
   output  reg [23:0]      hdmi_24_data,
 
-    // VGA interface 
+    // VGA interface
 
   output  reg             vga_hsync,
   output  reg             vga_vsync,
@@ -110,8 +111,8 @@ module axi_hdmi_tx_core #(
   input       [15:0]      hdmi_ve_max,
   input       [15:0]      hdmi_ve_min,
   input       [23:0]      hdmi_clip_max,
-  input       [23:0]      hdmi_clip_min);
-
+  input       [23:0]      hdmi_clip_min
+);
 
   // internal registers
 
@@ -384,7 +385,7 @@ module axi_hdmi_tx_core #(
       hdmi_tpm_data <= hdmi_tpm_data + 1'b1;
     end
     hdmi_tpm_oos <= hdmi_tpm_mismatch_s;
-    
+
   end
 
   // hdmi data select
@@ -479,7 +480,7 @@ module axi_hdmi_tx_core #(
     hdmi_24_data_e <= hdmi_clip_de_d;
     hdmi_24_data <= hdmi_clip_data;
 
-    //VGA INTERFACE SIGNALS 
+    //VGA INTERFACE SIGNALS
     vga_hsync <= hdmi_clip_hs_d;
     vga_vsync <= hdmi_clip_vs_d;
     vga_red   <= hdmi_clip_data[23:16];
@@ -528,7 +529,10 @@ module axi_hdmi_tx_core #(
 
   // data memory
 
-  ad_mem #(.DATA_WIDTH(48), .ADDRESS_WIDTH(9)) i_mem (
+  ad_mem #(
+    .DATA_WIDTH(48),
+    .ADDRESS_WIDTH(9)
+  ) i_mem (
     .clka (vdma_clk),
     .wea (vdma_wr),
     .addra (vdma_waddr),
@@ -540,7 +544,9 @@ module axi_hdmi_tx_core #(
 
   // color space coversion, RGB to CrYCb
 
-  ad_csc_RGB2CrYCb #(.DELAY_DATA_WIDTH(5)) i_csc_RGB2CrYCb (
+  ad_csc_RGB2CrYCb #(
+    .DELAY_DATA_WIDTH(5)
+  ) i_csc_RGB2CrYCb (
     .clk (reference_clk),
     .RGB_sync ({hdmi_hsync,
       hdmi_vsync,
@@ -557,7 +563,10 @@ module axi_hdmi_tx_core #(
 
   // sub sampling, 444 to 422
 
-  ad_ss_444to422 #(.DELAY_DATA_WIDTH(5), .CR_CB_N(CR_CB_N)) i_ss_444to422 (
+  ad_ss_444to422 #(
+    .DELAY_DATA_WIDTH(5),
+    .CR_CB_N(CR_CB_N)
+  ) i_ss_444to422 (
     .clk (reference_clk),
     .s444_de (hdmi_clip_de_d),
     .s444_sync ({hdmi_clip_hs_d,
@@ -575,7 +584,9 @@ module axi_hdmi_tx_core #(
 
   // embedded sync
 
-  axi_hdmi_tx_es #(.DATA_WIDTH(16)) i_es (
+  axi_hdmi_tx_es #(
+    .DATA_WIDTH(16)
+  ) i_es (
     .reference_clk (reference_clk),
     .hdmi_hs_de (hdmi_es_hs_de),
     .hdmi_vs_de (hdmi_es_vs_de),
@@ -583,6 +594,3 @@ module axi_hdmi_tx_core #(
     .hdmi_data (hdmi_es_data_s));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_hdmi_tx/axi_hdmi_tx_es.v b/library/axi_hdmi_tx/axi_hdmi_tx_es.v
index 67c52e975..46a6bf5a7 100644
--- a/library/axi_hdmi_tx/axi_hdmi_tx_es.v
+++ b/library/axi_hdmi_tx/axi_hdmi_tx_es.v
@@ -38,7 +38,8 @@
 
 module axi_hdmi_tx_es #(
 
-  parameter   DATA_WIDTH = 32) (
+  parameter   DATA_WIDTH = 32
+) (
 
   // hdmi interface
 
@@ -46,7 +47,8 @@ module axi_hdmi_tx_es #(
   input                   hdmi_hs_de,
   input                   hdmi_vs_de,
   input       [(DATA_WIDTH-1):0]  hdmi_data_de,
-  output  reg [(DATA_WIDTH-1):0]  hdmi_data);
+  output  reg [(DATA_WIDTH-1):0]  hdmi_data
+);
 
   localparam  BYTE_WIDTH = DATA_WIDTH/8;
 
@@ -102,6 +104,3 @@ module axi_hdmi_tx_es #(
   end
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_hdmi_tx/axi_hdmi_tx_vdma.v b/library/axi_hdmi_tx/axi_hdmi_tx_vdma.v
index a0bf35070..d8f7ae95f 100644
--- a/library/axi_hdmi_tx/axi_hdmi_tx_vdma.v
+++ b/library/axi_hdmi_tx/axi_hdmi_tx_vdma.v
@@ -58,7 +58,8 @@ module axi_hdmi_tx_vdma (
   output  reg [ 8:0]      vdma_fs_waddr,
   output  reg             vdma_tpm_oos,
   output  reg             vdma_ovf,
-  output  reg             vdma_unf);
+  output  reg             vdma_unf
+);
 
   localparam      BUF_THRESHOLD_LO = 9'd3;
   localparam      BUF_THRESHOLD_HI = 9'd509;
@@ -230,6 +231,3 @@ module axi_hdmi_tx_vdma (
   end
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_intr_monitor/axi_intr_monitor.v b/library/axi_intr_monitor/axi_intr_monitor.v
index 7e5c758fe..c3785158d 100644
--- a/library/axi_intr_monitor/axi_intr_monitor.v
+++ b/library/axi_intr_monitor/axi_intr_monitor.v
@@ -35,11 +35,10 @@
 
 `timescale 1ns/100ps
 
-module axi_intr_monitor
-(
+module axi_intr_monitor (
   output          irq,
 
-// axi interface
+  // axi interface
 
   input           s_axi_aclk,
   input           s_axi_aresetn,
@@ -62,177 +61,161 @@ module axi_intr_monitor
   input           s_axi_rready,
   input   [ 2:0]  s_axi_awprot,
   input   [ 2:0]  s_axi_arprot
-
 );
 
-parameter VERSION = 32'h00010000;
+  parameter VERSION = 32'h00010000;
 
-//------------------------------------------------------------------------------
-//----------- Registers Declarations -------------------------------------------
-//------------------------------------------------------------------------------
+  reg     [31:0]  up_rdata                    = 'd0;
+  reg             up_wack                     = 'd0;
+  reg             up_rack                     = 'd0;
+  reg             pwm_gen_clk                 = 'd0;
+  reg     [31:0]  scratch                     = 'd0;
+  reg     [31:0]  control                     = 'd0;
+  reg             interrupt                   = 'd0;
+  reg     [31:0]  counter_to_interrupt        = 'd0;
+  reg     [31:0]  counter_to_interrupt_cnt    = 'd0;
+  reg     [31:0]  counter_from_interrupt      = 'd0;
+  reg     [31:0]  counter_interrupt_handling  = 'd0;
+  reg     [31:0]  min_interrupt_handling      = 'd0;
+  reg     [31:0]  max_interrupt_handling      = 'd0;
+  reg             interrupt_d1                = 'd0;
+  reg             arm_counter                 = 'd0;
+  reg             counter_active              = 'd0;
 
-reg     [31:0]  up_rdata                    = 'd0;
-reg             up_wack                     = 'd0;
-reg             up_rack                     = 'd0;
-reg             pwm_gen_clk                 = 'd0;
-reg     [31:0]  scratch                     = 'd0;
-reg     [31:0]  control                     = 'd0;
-reg             interrupt                   = 'd0;
-reg     [31:0]  counter_to_interrupt        = 'd0;
-reg     [31:0]  counter_to_interrupt_cnt    = 'd0;
-reg     [31:0]  counter_from_interrupt      = 'd0;
-reg     [31:0]  counter_interrupt_handling  = 'd0;
-reg     [31:0]  min_interrupt_handling      = 'd0;
-reg     [31:0]  max_interrupt_handling      = 'd0;
-reg             interrupt_d1                = 'd0;
-reg             arm_counter                 = 'd0;
-reg             counter_active              = 'd0;
+  wire            up_rreq_s;
+  wire            up_wreq_s;
+  wire    [13:0]  up_raddr_s;
+  wire    [13:0]  up_waddr_s;
+  wire    [31:0]  up_wdata_s;
 
-//------------------------------------------------------------------------------
-//----------- Wires Declarations -----------------------------------------------
-//------------------------------------------------------------------------------
+  assign irq = interrupt;
 
-wire            up_rreq_s;
-wire            up_wreq_s;
-wire    [13:0]  up_raddr_s;
-wire    [13:0]  up_waddr_s;
-wire    [31:0]  up_wdata_s;
-
-//------------------------------------------------------------------------------
-//----------- Assign/Always Blocks ---------------------------------------------
-//------------------------------------------------------------------------------
-
-assign irq = interrupt;
-
-always @(negedge s_axi_aresetn or posedge s_axi_aclk) begin
-  if (s_axi_aresetn == 1'b0 || control[0] == 1'b0) begin
-    counter_to_interrupt_cnt <= 0;
-    counter_interrupt_handling <= 'd0;
-    counter_from_interrupt <= 32'h0;
-    min_interrupt_handling <= 'd0;
-    max_interrupt_handling <= 'd0;
-    interrupt_d1 <= 0;
-    counter_active <= 1'b0;
-  end else begin
-    interrupt_d1 <= irq;
-
-    if (arm_counter == 1'b1) begin
-      counter_to_interrupt_cnt <= counter_to_interrupt;
-      counter_active <= 1'b1;
-    end else if (counter_to_interrupt_cnt > 0) begin
-      counter_to_interrupt_cnt <= counter_to_interrupt_cnt - 1;
-    end else begin
-      counter_active <= 1'b0;
-    end
-
-    if (irq == 1'b1 && interrupt_d1 == 1'b0) begin
+  always @(negedge s_axi_aresetn or posedge s_axi_aclk) begin
+    if (s_axi_aresetn == 1'b0 || control[0] == 1'b0) begin
+      counter_to_interrupt_cnt <= 0;
+      counter_interrupt_handling <= 'd0;
       counter_from_interrupt <= 32'h0;
+      min_interrupt_handling <= 'd0;
+      max_interrupt_handling <= 'd0;
+      interrupt_d1 <= 0;
+      counter_active <= 1'b0;
     end else begin
-      counter_from_interrupt <= counter_from_interrupt + 1;
-    end
+      interrupt_d1 <= irq;
 
-    if (irq == 1'b0 && interrupt_d1 == 1'b1) begin
-      counter_interrupt_handling <= counter_from_interrupt;
-      if (min_interrupt_handling > counter_from_interrupt) begin
-        min_interrupt_handling <= counter_from_interrupt;
+      if (arm_counter == 1'b1) begin
+        counter_to_interrupt_cnt <= counter_to_interrupt;
+        counter_active <= 1'b1;
+      end else if (counter_to_interrupt_cnt > 0) begin
+        counter_to_interrupt_cnt <= counter_to_interrupt_cnt - 1;
+      end else begin
+        counter_active <= 1'b0;
       end
-      if (max_interrupt_handling < counter_from_interrupt) begin
-        max_interrupt_handling <= counter_from_interrupt;
+
+      if (irq == 1'b1 && interrupt_d1 == 1'b0) begin
+        counter_from_interrupt <= 32'h0;
+      end else begin
+        counter_from_interrupt <= counter_from_interrupt + 1;
+      end
+
+      if (irq == 1'b0 && interrupt_d1 == 1'b1) begin
+        counter_interrupt_handling <= counter_from_interrupt;
+        if (min_interrupt_handling > counter_from_interrupt) begin
+          min_interrupt_handling <= counter_from_interrupt;
+        end
+        if (max_interrupt_handling < counter_from_interrupt) begin
+          max_interrupt_handling <= counter_from_interrupt;
+        end
       end
     end
   end
-end
 
-always @(negedge s_axi_aresetn or posedge s_axi_aclk) begin
-  if (s_axi_aresetn == 0) begin
-    up_wack                    <= 1'b0;
-    scratch                    <= 'd0;
-    control                    <= 'd0;
-    interrupt                  <= 'd0;
-    counter_to_interrupt       <= 'd0;
-    arm_counter                <= 'd0;
-  end else begin
-    up_wack  <= up_wreq_s;
-    arm_counter <= 1'b0;
-    if ((up_wreq_s == 1'b1) && (up_waddr_s[3:0] == 4'h1)) begin
-      scratch <= up_wdata_s;
-    end
-    if ((up_wreq_s == 1'b1) && (up_waddr_s[3:0] == 4'h2)) begin
-      control <= up_wdata_s;
-    end
-    if (control[0] == 1'b0) begin
-      interrupt <= 1'b0;
-    end else if ((up_wreq_s == 1'b1) && (up_waddr_s[3:0] == 4'h3)) begin
-      interrupt <= interrupt & ~up_wdata_s[0];
+  always @(negedge s_axi_aresetn or posedge s_axi_aclk) begin
+    if (s_axi_aresetn == 0) begin
+      up_wack                    <= 1'b0;
+      scratch                    <= 'd0;
+      control                    <= 'd0;
+      interrupt                  <= 'd0;
+      counter_to_interrupt       <= 'd0;
+      arm_counter                <= 'd0;
     end else begin
-      if (counter_to_interrupt_cnt == 32'h0 && counter_active == 1'b1) begin
-        interrupt <= 1'b1;
+      up_wack  <= up_wreq_s;
+      arm_counter <= 1'b0;
+      if ((up_wreq_s == 1'b1) && (up_waddr_s[3:0] == 4'h1)) begin
+        scratch <= up_wdata_s;
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr_s[3:0] == 4'h2)) begin
+        control <= up_wdata_s;
+      end
+      if (control[0] == 1'b0) begin
+        interrupt <= 1'b0;
+      end else if ((up_wreq_s == 1'b1) && (up_waddr_s[3:0] == 4'h3)) begin
+        interrupt <= interrupt & ~up_wdata_s[0];
+      end else begin
+        if (counter_to_interrupt_cnt == 32'h0 && counter_active == 1'b1) begin
+          interrupt <= 1'b1;
+        end
+      end
+      if ((up_wreq_s == 1'b1) && (up_waddr_s[3:0] == 4'h4)) begin
+        counter_to_interrupt <= up_wdata_s;
+        arm_counter <= 1'b1;
       end
     end
-    if ((up_wreq_s == 1'b1) && (up_waddr_s[3:0] == 4'h4)) begin
-      counter_to_interrupt <= up_wdata_s;
-      arm_counter <= 1'b1;
-    end
   end
-end
 
-always @(negedge s_axi_aresetn or posedge s_axi_aclk) begin
-  if (s_axi_aresetn == 0) begin
-    up_rack <= 'd0;
-    up_rdata <= 'd0;
-  end else begin
-    up_rack <= up_rreq_s;
-    if (up_rreq_s == 1'b1) begin
-      case (up_raddr_s[3:0])
-        4'h0: up_rdata <= VERSION;
-        4'h1: up_rdata <= scratch;
-        4'h2: up_rdata <= control;
-        4'h3: up_rdata <= {31'h0,interrupt};
-        4'h4: up_rdata <= counter_to_interrupt;
-        4'h5: up_rdata <= counter_from_interrupt;
-        4'h6: up_rdata <= counter_interrupt_handling;
-        4'h7: up_rdata <= min_interrupt_handling;
-        4'h8: up_rdata <= max_interrupt_handling;
-        default: up_rdata <= 0;
-      endcase
+  always @(negedge s_axi_aresetn or posedge s_axi_aclk) begin
+    if (s_axi_aresetn == 0) begin
+      up_rack <= 'd0;
+      up_rdata <= 'd0;
     end else begin
-      up_rdata <= 32'd0;
+      up_rack <= up_rreq_s;
+      if (up_rreq_s == 1'b1) begin
+        case (up_raddr_s[3:0])
+          4'h0: up_rdata <= VERSION;
+          4'h1: up_rdata <= scratch;
+          4'h2: up_rdata <= control;
+          4'h3: up_rdata <= {31'h0,interrupt};
+          4'h4: up_rdata <= counter_to_interrupt;
+          4'h5: up_rdata <= counter_from_interrupt;
+          4'h6: up_rdata <= counter_interrupt_handling;
+          4'h7: up_rdata <= min_interrupt_handling;
+          4'h8: up_rdata <= max_interrupt_handling;
+          default: up_rdata <= 0;
+        endcase
+      end else begin
+        up_rdata <= 32'd0;
+      end
     end
   end
-end
 
-// up bus interface
+  // up bus interface
 
-up_axi i_up_axi(
-  .up_rstn(s_axi_aresetn),
-  .up_clk(s_axi_aclk),
-  .up_axi_awvalid(s_axi_awvalid),
-  .up_axi_awaddr(s_axi_awaddr),
-  .up_axi_awready(s_axi_awready),
-  .up_axi_wvalid(s_axi_wvalid),
-  .up_axi_wdata(s_axi_wdata),
-  .up_axi_wstrb(s_axi_wstrb),
-  .up_axi_wready(s_axi_wready),
-  .up_axi_bvalid(s_axi_bvalid),
-  .up_axi_bresp(s_axi_bresp),
-  .up_axi_bready(s_axi_bready),
-  .up_axi_arvalid(s_axi_arvalid),
-  .up_axi_araddr(s_axi_araddr),
-  .up_axi_arready(s_axi_arready),
-  .up_axi_rvalid(s_axi_rvalid),
-  .up_axi_rresp(s_axi_rresp),
-  .up_axi_rdata(s_axi_rdata),
-  .up_axi_rready(s_axi_rready),
-  .up_wreq (up_wreq_s),
-  .up_waddr (up_waddr_s),
-  .up_wdata (up_wdata_s),
-  .up_wack (up_wack),
-  .up_rreq (up_rreq_s),
-  .up_raddr (up_raddr_s),
-  .up_rdata (up_rdata),
-  .up_rack (up_rack));
+  up_axi i_up_axi (
+    .up_rstn(s_axi_aresetn),
+    .up_clk(s_axi_aclk),
+    .up_axi_awvalid(s_axi_awvalid),
+    .up_axi_awaddr(s_axi_awaddr),
+    .up_axi_awready(s_axi_awready),
+    .up_axi_wvalid(s_axi_wvalid),
+    .up_axi_wdata(s_axi_wdata),
+    .up_axi_wstrb(s_axi_wstrb),
+    .up_axi_wready(s_axi_wready),
+    .up_axi_bvalid(s_axi_bvalid),
+    .up_axi_bresp(s_axi_bresp),
+    .up_axi_bready(s_axi_bready),
+    .up_axi_arvalid(s_axi_arvalid),
+    .up_axi_araddr(s_axi_araddr),
+    .up_axi_arready(s_axi_arready),
+    .up_axi_rvalid(s_axi_rvalid),
+    .up_axi_rresp(s_axi_rresp),
+    .up_axi_rdata(s_axi_rdata),
+    .up_axi_rready(s_axi_rready),
+    .up_wreq (up_wreq_s),
+    .up_waddr (up_waddr_s),
+    .up_wdata (up_wdata_s),
+    .up_wack (up_wack),
+    .up_rreq (up_rreq_s),
+    .up_raddr (up_raddr_s),
+    .up_rdata (up_rdata),
+    .up_rack (up_rack));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_laser_driver/axi_laser_driver.v b/library/axi_laser_driver/axi_laser_driver.v
index 1d9d1d150..abb2c11b0 100644
--- a/library/axi_laser_driver/axi_laser_driver.v
+++ b/library/axi_laser_driver/axi_laser_driver.v
@@ -36,10 +36,11 @@
 
 module axi_laser_driver #(
 
-  parameter       ID = 0,
-  parameter [0:0] ASYNC_CLK_EN = 1,
-  parameter       PULSE_WIDTH = 7,
-  parameter       PULSE_PERIOD = 10 )(
+  parameter ID = 0,
+  parameter ASYNC_CLK_EN = 1,
+  parameter PULSE_WIDTH = 7,
+  parameter PULSE_PERIOD = 10
+) (
 
   // axi interface
 
@@ -76,7 +77,8 @@ module axi_laser_driver #(
 
   // interrupt
 
-  output                  irq);
+  output                  irq
+);
 
   // internal signals
 
@@ -136,8 +138,8 @@ module axi_laser_driver #(
     .CORE_VERSION (CORE_VERSION),
     .ASYNC_CLK_EN (ASYNC_CLK_EN),
     .PULSE_WIDTH (PULSE_WIDTH),
-    .PULSE_PERIOD (PULSE_PERIOD))
-  i_pwm_regmap (
+    .PULSE_PERIOD (PULSE_PERIOD)
+  ) i_pwm_regmap (
     .ext_clk (ext_clk),
     .clk_out (clk),
     .pulse_gen_resetn (pulse_gen_resetn),
@@ -157,8 +159,8 @@ module axi_laser_driver #(
 
   axi_laser_driver_regmap #(
     .ID (ID),
-    .LASER_DRIVER_ID (1))
-  i_laser_driver_regmap (
+    .LASER_DRIVER_ID (1)
+  ) i_laser_driver_regmap (
     .clk (clk),
     .driver_en_n (driver_en_n),
     .driver_otw_n (driver_otw_n),
@@ -202,8 +204,8 @@ module axi_laser_driver #(
 
   util_pulse_gen  #(
     .PULSE_WIDTH(PULSE_WIDTH),
-    .PULSE_PERIOD(PULSE_PERIOD))
-  i_laser_driver_pulse (
+    .PULSE_PERIOD(PULSE_PERIOD)
+  ) i_laser_driver_pulse (
     .clk (clk),
     .rstn (pulse_gen_resetn),
     .pulse_width (pulse_width_s),
@@ -268,8 +270,8 @@ module axi_laser_driver #(
   // AXI Memory Mapped Wrapper
 
   up_axi #(
-    .AXI_ADDRESS_WIDTH(16))
-  i_up_axi (
+    .AXI_ADDRESS_WIDTH(16)
+  ) i_up_axi (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_axi_awvalid (s_axi_awvalid),
diff --git a/library/axi_laser_driver/axi_laser_driver_regmap.v b/library/axi_laser_driver/axi_laser_driver_regmap.v
index 4793bb34e..c756a83ba 100644
--- a/library/axi_laser_driver/axi_laser_driver_regmap.v
+++ b/library/axi_laser_driver/axi_laser_driver_regmap.v
@@ -37,7 +37,8 @@
 module axi_laser_driver_regmap #(
 
   parameter       ID = 0,
-  parameter       LASER_DRIVER_ID = 1 )(
+  parameter       LASER_DRIVER_ID = 1
+) (
 
   // control and status signals
 
@@ -224,8 +225,8 @@ module axi_laser_driver_regmap #(
 
   sync_bits #(
     .NUM_OF_BITS (1),
-    .ASYNC_CLK (1))
-  i_driver_otw_sync (
+    .ASYNC_CLK (1)
+  ) i_driver_otw_sync (
     .in_bits (driver_otw_n),
     .out_clk (up_clk),
     .out_resetn (1'b1),
@@ -233,8 +234,8 @@ module axi_laser_driver_regmap #(
 
   sync_bits #(
     .NUM_OF_BITS (1),
-    .ASYNC_CLK (1))
-  i_pulse_sync (
+    .ASYNC_CLK (1)
+  ) i_pulse_sync (
     .in_bits (pulse),
     .out_clk (up_clk),
     .out_resetn (1'b1),
@@ -242,8 +243,8 @@ module axi_laser_driver_regmap #(
 
   sync_bits #(
     .NUM_OF_BITS (2),
-    .ASYNC_CLK (1))
-  i_sequence_control_sync (
+    .ASYNC_CLK (1)
+  ) i_sequence_control_sync (
     .in_bits ({up_auto_sequence, up_sequence_en}),
     .out_clk (clk),
     .out_resetn (1'b1),
@@ -251,8 +252,8 @@ module axi_laser_driver_regmap #(
 
   sync_bits #(
     .NUM_OF_BITS (16),
-    .ASYNC_CLK (1))
-  i_sequencer_sync (
+    .ASYNC_CLK (1)
+  ) i_sequencer_sync (
     .in_bits ({up_auto_seq3,
                up_auto_seq2,
                up_auto_seq1,
@@ -270,8 +271,8 @@ module axi_laser_driver_regmap #(
 
   sync_bits #(
     .NUM_OF_BITS (32),
-    .ASYNC_CLK (1))
-  i_sequence_offset_sync (
+    .ASYNC_CLK (1)
+  ) i_sequence_offset_sync (
     .in_bits (up_sequence_offset),
     .out_clk (clk),
     .out_resetn (1'b1),
diff --git a/library/axi_logic_analyzer/axi_logic_analyzer.v b/library/axi_logic_analyzer/axi_logic_analyzer.v
index 779870135..709b0bcf5 100644
--- a/library/axi_logic_analyzer/axi_logic_analyzer.v
+++ b/library/axi_logic_analyzer/axi_logic_analyzer.v
@@ -84,7 +84,8 @@ module axi_logic_analyzer (
   output                s_axi_rvalid,
   output      [31:0]    s_axi_rdata,
   output      [ 1:0]    s_axi_rresp,
-  input                 s_axi_rready);
+  input                 s_axi_rready
+);
 
   // internal registers
 
@@ -216,7 +217,6 @@ module axi_logic_analyzer (
     end
   end
 
-
   always @(posedge clk_out) begin
     if (sample_valid_la == 1'b1 && trigger_out_holdoff == 1'b1) begin
       up_triggered_set <= 1'b1;
@@ -452,8 +452,7 @@ module axi_logic_analyzer (
     .trigger_out_adc (trigger_out_adc),
     .trigger_out (trigger_out_s));
 
-   axi_logic_analyzer_reg i_registers (
-
+  axi_logic_analyzer_reg i_registers (
     .clk (clk_out),
     .reset (reset),
 
@@ -527,6 +526,3 @@ module axi_logic_analyzer (
     .up_rack (up_rack));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_logic_analyzer/axi_logic_analyzer_reg.v b/library/axi_logic_analyzer/axi_logic_analyzer_reg.v
index 0baa75b0e..582db1d0d 100644
--- a/library/axi_logic_analyzer/axi_logic_analyzer_reg.v
+++ b/library/axi_logic_analyzer/axi_logic_analyzer_reg.v
@@ -76,7 +76,8 @@ module axi_logic_analyzer_reg (
   input               up_rreq,
   input       [ 4:0]  up_raddr,
   output reg  [31:0]  up_rdata,
-  output reg          up_rack);
+  output reg          up_rack
+);
 
   // internal registers
 
@@ -241,9 +242,15 @@ module axi_logic_analyzer_reg (
     end
   end
 
-  ad_rst i_core_rst_reg (.rst_async(~up_rstn), .clk(clk), .rstn(), .rst(reset));
+  ad_rst i_core_rst_reg (
+    .rst_async(~up_rstn),
+    .clk(clk),
+    .rstn(),
+    .rst(reset));
 
-   up_xfer_cntrl #(.DATA_WIDTH(353)) i_xfer_cntrl (
+  up_xfer_cntrl #(
+    .DATA_WIDTH(353)
+  ) i_xfer_cntrl (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_data_cntrl ({ up_streaming,             // 1
@@ -289,22 +296,19 @@ module axi_logic_analyzer_reg (
                       divider_counter_la,     // 32
                       data_delay_control}));  // 10
 
- up_xfer_status #(.DATA_WIDTH(16)) i_xfer_status (
+  up_xfer_status #(
+    .DATA_WIDTH(16)
+  ) i_xfer_status (
+    // up interface
 
-  // up interface
+    .up_rstn(up_rstn),
+    .up_clk(up_clk),
+    .up_data_status(up_input_data),
 
-  .up_rstn(up_rstn),
-  .up_clk(up_clk),
-  .up_data_status(up_input_data),
+    // device interface
 
-  // device interface
-
-  .d_rst(1'd0),
-  .d_clk(clk),
-  .d_data_status(input_data));
+    .d_rst(1'd0),
+    .d_clk(clk),
+    .d_data_status(input_data));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
-
diff --git a/library/axi_logic_analyzer/axi_logic_analyzer_trigger.v b/library/axi_logic_analyzer/axi_logic_analyzer_trigger.v
index aa488070d..cb28b875c 100644
--- a/library/axi_logic_analyzer/axi_logic_analyzer_trigger.v
+++ b/library/axi_logic_analyzer/axi_logic_analyzer_trigger.v
@@ -54,7 +54,8 @@ module axi_logic_analyzer_trigger (
   input       [ 6:0]    trigger_logic,
 
   output  reg           trigger_out,
-  output  reg           trigger_out_adc);
+  output  reg           trigger_out_adc
+);
 
   reg     [  1:0]   ext_t_m = 'd0;
   reg     [  1:0]   ext_t_low_level_hold = 'd0;
@@ -91,7 +92,6 @@ module axi_logic_analyzer_trigger (
     end
   end
 
-
   // trigger logic:
   // 0 OR
   // 1 AND
@@ -185,6 +185,3 @@ module axi_logic_analyzer_trigger (
   end
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/axi_ltc2387/axi_ltc2387_channel.v b/library/axi_ltc2387/axi_ltc2387_channel.v
index f84029b16..b6cdcf94f 100644
--- a/library/axi_ltc2387/axi_ltc2387_channel.v
+++ b/library/axi_ltc2387/axi_ltc2387_channel.v
@@ -45,6 +45,7 @@ module axi_ltc2387_channel #(
   parameter   USERPORTS_DISABLE = 0,
   parameter   DATAFORMAT_DISABLE = 0
 ) (
+
   // adc interface
 
   input                   adc_clk,
diff --git a/library/axi_ltc2387/axi_ltc2387_if.v b/library/axi_ltc2387/axi_ltc2387_if.v
index c8c902535..1e99087d1 100644
--- a/library/axi_ltc2387/axi_ltc2387_if.v
+++ b/library/axi_ltc2387/axi_ltc2387_if.v
@@ -46,6 +46,7 @@ module axi_ltc2387_if #(
   parameter [0:0] TWOLANES = 1, // 0 for Single Lane, 1 for Two Lanes
   parameter RESOLUTION = 16     // 16 or 18 bits
 ) (
+
   // delay interface
 
   input                    up_clk,
diff --git a/library/axi_pulse_gen/axi_pulse_gen.v b/library/axi_pulse_gen/axi_pulse_gen.v
index 97ce76d93..80ddd5398 100644
--- a/library/axi_pulse_gen/axi_pulse_gen.v
+++ b/library/axi_pulse_gen/axi_pulse_gen.v
@@ -35,11 +35,11 @@
 `timescale 1ns/100ps
 
 module axi_pulse_gen #(
-
   parameter       ID = 0,
   parameter [0:0] ASYNC_CLK_EN = 1,
   parameter       PULSE_WIDTH = 7,
-  parameter       PULSE_PERIOD = 10 )(
+  parameter       PULSE_PERIOD = 10
+) (
 
   // axi interface
 
@@ -65,7 +65,8 @@ module axi_pulse_gen #(
   output      [31:0]      s_axi_rdata,
   input                   s_axi_rready,
   input                   ext_clk,
-  output                  pulse);
+  output                  pulse
+);
 
   // local parameters
 
@@ -101,8 +102,8 @@ module axi_pulse_gen #(
     .CORE_MAGIC (CORE_MAGIC),
     .CORE_VERSION (CORE_VERSION),
     .PULSE_WIDTH (PULSE_WIDTH),
-    .PULSE_PERIOD (PULSE_PERIOD))
-  i_regmap (
+    .PULSE_PERIOD (PULSE_PERIOD)
+  ) i_regmap (
     .ext_clk (ext_clk),
     .clk_out (clk),
     .pulse_gen_resetn (pulse_gen_resetn),
@@ -122,8 +123,8 @@ module axi_pulse_gen #(
 
   util_pulse_gen  #(
     .PULSE_WIDTH(PULSE_WIDTH),
-    .PULSE_PERIOD(PULSE_PERIOD))
-  util_pulse_gen_i(
+    .PULSE_PERIOD(PULSE_PERIOD)
+  ) util_pulse_gen_i (
     .clk (clk),
     .rstn (pulse_gen_resetn),
     .pulse_width (pulse_width_s),
@@ -132,8 +133,8 @@ module axi_pulse_gen #(
     .pulse (pulse));
 
   up_axi #(
-    .AXI_ADDRESS_WIDTH(16))
-  i_up_axi (
+    .AXI_ADDRESS_WIDTH(16)
+  ) i_up_axi (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_axi_awvalid (s_axi_awvalid),
diff --git a/library/axi_pulse_gen/axi_pulse_gen_regmap.v b/library/axi_pulse_gen/axi_pulse_gen_regmap.v
index e7f469670..678863eb7 100644
--- a/library/axi_pulse_gen/axi_pulse_gen_regmap.v
+++ b/library/axi_pulse_gen/axi_pulse_gen_regmap.v
@@ -41,7 +41,8 @@ module axi_pulse_gen_regmap #(
   parameter [31:0] CORE_VERSION = 0,
   parameter [ 0:0] ASYNC_CLK_EN = 1,
   parameter        PULSE_WIDTH = 7,
-  parameter        PULSE_PERIOD = 10 )(
+  parameter        PULSE_PERIOD = 10
+) (
 
   // external clock
 
@@ -141,8 +142,8 @@ module axi_pulse_gen_regmap #(
 
     sync_data #(
       .NUM_OF_BITS (32),
-      .ASYNC_CLK (1))
-    i_pulse_period_sync (
+      .ASYNC_CLK (1)
+    ) i_pulse_period_sync (
       .in_clk (up_clk),
       .in_data (up_pulse_period),
       .out_clk (clk_out),
@@ -150,8 +151,8 @@ module axi_pulse_gen_regmap #(
 
     sync_data #(
       .NUM_OF_BITS (32),
-      .ASYNC_CLK (1))
-    i_pulse_width_sync (
+      .ASYNC_CLK (1)
+    ) i_pulse_width_sync (
       .in_clk (up_clk),
       .in_data (up_pulse_width),
       .out_clk (clk_out),
@@ -159,8 +160,8 @@ module axi_pulse_gen_regmap #(
 
     sync_event #(
       .NUM_OF_EVENTS (1),
-      .ASYNC_CLK (1))
-    i_load_config_sync (
+      .ASYNC_CLK (1)
+    ) i_load_config_sync (
       .in_clk (up_clk),
       .in_event (up_load_config),
       .out_clk (clk_out),
diff --git a/library/axi_pwm_gen/axi_pwm_gen.v b/library/axi_pwm_gen/axi_pwm_gen.v
index 3c1dfb83e..1175aa33c 100644
--- a/library/axi_pwm_gen/axi_pwm_gen.v
+++ b/library/axi_pwm_gen/axi_pwm_gen.v
@@ -52,7 +52,8 @@ module axi_pwm_gen #(
   parameter  PULSE_0_OFFSET = 0,
   parameter  PULSE_1_OFFSET = 0,
   parameter  PULSE_2_OFFSET = 0,
-  parameter  PULSE_3_OFFSET = 0)(
+  parameter  PULSE_3_OFFSET = 0
+) (
 
   // axi interface
 
@@ -83,7 +84,8 @@ module axi_pwm_gen #(
   output                  pwm_0,
   output                  pwm_1,
   output                  pwm_2,
-  output                  pwm_3);
+  output                  pwm_3
+);
 
   // local parameters
 
@@ -145,8 +147,8 @@ module axi_pwm_gen #(
     .PULSE_0_OFFSET (PULSE_0_OFFSET),
     .PULSE_1_OFFSET (PULSE_1_OFFSET),
     .PULSE_2_OFFSET (PULSE_2_OFFSET),
-    .PULSE_3_OFFSET (PULSE_3_OFFSET))
-  i_regmap (
+    .PULSE_3_OFFSET (PULSE_3_OFFSET)
+  ) i_regmap (
     .ext_clk (ext_clk),
     .clk_out (clk),
     .pwm_gen_resetn (pwm_gen_resetn),
@@ -220,8 +222,8 @@ module axi_pwm_gen #(
 
   axi_pwm_gen_1  #(
     .PULSE_WIDTH (PULSE_0_WIDTH),
-    .PULSE_PERIOD (PULSE_0_PERIOD))
-  i0_axi_pwm_gen_1(
+    .PULSE_PERIOD (PULSE_0_PERIOD)
+  ) i0_axi_pwm_gen_1(
     .clk (clk),
     .rstn (pwm_gen_resetn),
     .pulse_width (pwm_width_s[31:0]),
@@ -244,8 +246,8 @@ module axi_pwm_gen #(
     if (N_PWMS >= 2) begin
       axi_pwm_gen_1  #(
         .PULSE_WIDTH (PULSE_1_WIDTH),
-        .PULSE_PERIOD (PULSE_1_PERIOD))
-      i1_axi_pwm_gen_1(
+        .PULSE_PERIOD (PULSE_1_PERIOD)
+      ) i1_axi_pwm_gen_1(
         .clk (clk),
         .rstn (pwm_gen_resetn),
         .pulse_width (pwm_width_s[63:32]),
@@ -270,8 +272,8 @@ module axi_pwm_gen #(
     if (N_PWMS >= 3) begin
       axi_pwm_gen_1  #(
         .PULSE_WIDTH (PULSE_2_WIDTH),
-        .PULSE_PERIOD (PULSE_2_PERIOD))
-      i2_axi_pwm_gen_1(
+        .PULSE_PERIOD (PULSE_2_PERIOD)
+      ) i2_axi_pwm_gen_1(
         .clk (clk),
         .rstn (pwm_gen_resetn),
         .pulse_width (pwm_width_s[95:64]),
@@ -296,8 +298,8 @@ module axi_pwm_gen #(
     if (N_PWMS >= 4) begin
       axi_pwm_gen_1  #(
         .PULSE_WIDTH (PULSE_3_WIDTH),
-        .PULSE_PERIOD (PULSE_3_PERIOD))
-      i3_axi_pwm_gen_1(
+        .PULSE_PERIOD (PULSE_3_PERIOD)
+      ) i3_axi_pwm_gen_1(
         .clk (clk),
         .rstn (pwm_gen_resetn),
         .pulse_width (pwm_width_s[127:96]),
@@ -321,8 +323,8 @@ module axi_pwm_gen #(
   endgenerate
 
   up_axi #(
-    .AXI_ADDRESS_WIDTH(16))
-  i_up_axi (
+    .AXI_ADDRESS_WIDTH(16)
+  ) i_up_axi (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_axi_awvalid (s_axi_awvalid),
diff --git a/library/axi_pwm_gen/axi_pwm_gen_1.v b/library/axi_pwm_gen/axi_pwm_gen_1.v
index 690b3aa8f..668139d0b 100644
--- a/library/axi_pwm_gen/axi_pwm_gen_1.v
+++ b/library/axi_pwm_gen/axi_pwm_gen_1.v
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (c) Analog Devices, Inc. All rights reserved.
+// Copyright 2021 (c) Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -35,11 +35,10 @@
 `timescale 1ns/1ps
 
 module axi_pwm_gen_1 #(
-
   // the width and period are defined in number of clock cycles
   parameter   PULSE_WIDTH = 7,
-  parameter   PULSE_PERIOD = 100000000) (
-
+  parameter   PULSE_PERIOD = 100000000
+) (
   input               clk,
   input               rstn,
 
diff --git a/library/axi_pwm_gen/axi_pwm_gen_regmap.v b/library/axi_pwm_gen/axi_pwm_gen_regmap.v
index 0f74c49cd..c1b03acb7 100644
--- a/library/axi_pwm_gen/axi_pwm_gen_regmap.v
+++ b/library/axi_pwm_gen/axi_pwm_gen_regmap.v
@@ -53,7 +53,8 @@ module axi_pwm_gen_regmap #(
   parameter  PULSE_0_OFFSET = 0,
   parameter  PULSE_1_OFFSET = 0,
   parameter  PULSE_2_OFFSET = 0,
-  parameter  PULSE_3_OFFSET = 0)(
+  parameter  PULSE_3_OFFSET = 0
+) (
 
   // external clock
 
@@ -215,8 +216,8 @@ module axi_pwm_gen_regmap #(
 
     sync_data #(
       .NUM_OF_BITS (128),
-      .ASYNC_CLK (1))
-    i_pwm_period_sync (
+      .ASYNC_CLK (1)
+    ) i_pwm_period_sync (
       .in_clk (up_clk),
       .in_data ({up_pwm_period_3,
                  up_pwm_period_2,
@@ -227,8 +228,8 @@ module axi_pwm_gen_regmap #(
 
     sync_data #(
       .NUM_OF_BITS (128),
-      .ASYNC_CLK (1))
-    i_pwm_width_sync (
+      .ASYNC_CLK (1)
+    ) i_pwm_width_sync (
       .in_clk (up_clk),
       .in_data ({up_pwm_width_3,
                  up_pwm_width_2,
@@ -239,8 +240,8 @@ module axi_pwm_gen_regmap #(
 
     sync_data #(
       .NUM_OF_BITS (128),
-      .ASYNC_CLK (1))
-    i_pwm_offset_sync (
+      .ASYNC_CLK (1)
+    ) i_pwm_offset_sync (
       .in_clk (up_clk),
       .in_data ({up_pwm_offset_3,
                  up_pwm_offset_2,
@@ -251,8 +252,8 @@ module axi_pwm_gen_regmap #(
 
     sync_event #(
       .NUM_OF_EVENTS (1),
-      .ASYNC_CLK (1))
-    i_load_config_sync (
+      .ASYNC_CLK (1)
+    ) i_load_config_sync (
       .in_clk (up_clk),
       .in_event (up_load_config),
       .out_clk (clk_out),
diff --git a/library/axi_rd_wr_combiner/axi_rd_wr_combiner.v b/library/axi_rd_wr_combiner/axi_rd_wr_combiner.v
index 76601c399..a5c69019e 100644
--- a/library/axi_rd_wr_combiner/axi_rd_wr_combiner.v
+++ b/library/axi_rd_wr_combiner/axi_rd_wr_combiner.v
@@ -122,38 +122,38 @@ module axi_rd_wr_combiner (
   input                         s_rd_axi_rready
 );
 
-assign m_axi_awaddr = s_wr_axi_awaddr;
-assign m_axi_awlen = s_wr_axi_awlen;
-assign m_axi_awsize = s_wr_axi_awsize;
-assign m_axi_awburst = s_wr_axi_awburst;
-assign m_axi_awprot = s_wr_axi_awprot;
-assign m_axi_awcache = s_wr_axi_awcache;
-assign m_axi_awvalid = s_wr_axi_awvalid;
-assign s_wr_axi_awready = m_axi_awready;
+  assign m_axi_awaddr = s_wr_axi_awaddr;
+  assign m_axi_awlen = s_wr_axi_awlen;
+  assign m_axi_awsize = s_wr_axi_awsize;
+  assign m_axi_awburst = s_wr_axi_awburst;
+  assign m_axi_awprot = s_wr_axi_awprot;
+  assign m_axi_awcache = s_wr_axi_awcache;
+  assign m_axi_awvalid = s_wr_axi_awvalid;
+  assign s_wr_axi_awready = m_axi_awready;
 
-assign m_axi_wdata = s_wr_axi_wdata;
-assign m_axi_wstrb = s_wr_axi_wstrb;
-assign s_wr_axi_wready = m_axi_wready;
-assign m_axi_wvalid = s_wr_axi_wvalid;
-assign m_axi_wlast = s_wr_axi_wlast;
+  assign m_axi_wdata = s_wr_axi_wdata;
+  assign m_axi_wstrb = s_wr_axi_wstrb;
+  assign s_wr_axi_wready = m_axi_wready;
+  assign m_axi_wvalid = s_wr_axi_wvalid;
+  assign m_axi_wlast = s_wr_axi_wlast;
 
-assign s_wr_axi_bvalid = m_axi_bvalid;
-assign s_wr_axi_bresp = m_axi_bresp;
-assign m_axi_bready = s_wr_axi_bready;
+  assign s_wr_axi_bvalid = m_axi_bvalid;
+  assign s_wr_axi_bresp = m_axi_bresp;
+  assign m_axi_bready = s_wr_axi_bready;
 
-assign m_axi_arvalid = s_rd_axi_arvalid;
-assign m_axi_araddr = s_rd_axi_araddr;
-assign m_axi_arlen = s_rd_axi_arlen;
-assign m_axi_arsize = s_rd_axi_arsize;
-assign m_axi_arburst = s_rd_axi_arburst;
-assign m_axi_arcache = s_rd_axi_arcache;
-assign m_axi_arprot = s_rd_axi_arprot;
-assign s_rd_axi_arready = m_axi_arready;
+  assign m_axi_arvalid = s_rd_axi_arvalid;
+  assign m_axi_araddr = s_rd_axi_araddr;
+  assign m_axi_arlen = s_rd_axi_arlen;
+  assign m_axi_arsize = s_rd_axi_arsize;
+  assign m_axi_arburst = s_rd_axi_arburst;
+  assign m_axi_arcache = s_rd_axi_arcache;
+  assign m_axi_arprot = s_rd_axi_arprot;
+  assign s_rd_axi_arready = m_axi_arready;
 
-assign s_rd_axi_rvalid = m_axi_rvalid;
-assign s_rd_axi_rresp = m_axi_rresp;
-assign s_rd_axi_rdata = m_axi_rdata;
-assign s_rd_axi_rlast = m_axi_rlast;
-assign m_axi_rready = s_rd_axi_rready;
+  assign s_rd_axi_rvalid = m_axi_rvalid;
+  assign s_rd_axi_rresp = m_axi_rresp;
+  assign s_rd_axi_rdata = m_axi_rdata;
+  assign s_rd_axi_rlast = m_axi_rlast;
+  assign m_axi_rready = s_rd_axi_rready;
 
 endmodule
diff --git a/library/axi_sysid/axi_sysid.v b/library/axi_sysid/axi_sysid.v
index 13dcf650d..b80eada8c 100755
--- a/library/axi_sysid/axi_sysid.v
+++ b/library/axi_sysid/axi_sysid.v
@@ -1,10 +1,45 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2019 - 2022 (c) Analog Devices, Inc. All rights reserved.
+//
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
+//
+// The user should read each of these license terms, and understand the
+// freedoms and responsibilities that he or she has by using this source/core.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+//   1. The GNU General Public License version 2 as published by the
+//      Free Software Foundation, which can be found in the top level directory
+//      of this repository (LICENSE_GPL2), and also online at:
+//      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+//
+// OR
+//
+//   2. An ADI specific BSD license, which can be found in the top level directory
+//      of this repository (LICENSE_ADIBSD), and also on-line at:
+//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      This will allow to generate bit files and not release the source code,
+//      as long as it attaches to an ADI device.
+//
+// ***************************************************************************
+
 `timescale 1ns / 1ps
 
 module axi_sysid #(
   parameter ROM_WIDTH = 32,
-  parameter ROM_ADDR_BITS = 9)(
-
+  parameter ROM_ADDR_BITS = 9
+) (
    //axi interface
+
   input           s_axi_aclk,
   input           s_axi_aresetn,
   input           s_axi_awvalid,
@@ -29,107 +64,108 @@ module axi_sysid #(
 
   input   [ROM_WIDTH-1:0]           sys_rom_data,
   input   [ROM_WIDTH-1:0]           pr_rom_data,
-  output  [ROM_ADDR_BITS-1:0]       rom_addr);
+  output  [ROM_ADDR_BITS-1:0]       rom_addr
+);
 
-localparam          AXI_ADDRESS_WIDTH    = 12;
-localparam  [31:0]  CORE_VERSION         = {16'h0001,     /* MAJOR */
-                                              8'h01,      /* MINOR */
-                                              8'h61};     /* PATCH */
-localparam  [31:0]  CORE_MAGIC           = 32'h53594944;  // SYID
+  localparam          AXI_ADDRESS_WIDTH    = 12;
+  localparam  [31:0]  CORE_VERSION         = {16'h0001,     /* MAJOR */
+                                                8'h01,      /* MINOR */
+                                                8'h61};     /* PATCH */
+  localparam  [31:0]  CORE_MAGIC           = 32'h53594944;  // SYID
 
-reg                             up_wack = 'd0;
-reg   [31:0]                    up_rdata_s = 'd0;
-reg                             up_rack_s = 'd0;
-reg                             up_rreq_s_d = 'd0;
-reg   [31:0]                    up_scratch = 'd0;
+  reg                             up_wack = 'd0;
+  reg   [31:0]                    up_rdata_s = 'd0;
+  reg                             up_rack_s = 'd0;
+  reg                             up_rreq_s_d = 'd0;
+  reg   [31:0]                    up_scratch = 'd0;
 
-wire                            up_clk;
-wire                            up_rstn;
-wire                            up_rreq_s;
-wire  [(ROM_ADDR_BITS+1):0]     up_raddr_s;
-wire                            up_wreq_s;
-wire  [(ROM_ADDR_BITS+1):0]     up_waddr_s;
-wire  [31:0]                    up_wdata_s;
-wire  [31:0]                    rom_data_s;
+  wire                            up_clk;
+  wire                            up_rstn;
+  wire                            up_rreq_s;
+  wire  [(ROM_ADDR_BITS+1):0]     up_raddr_s;
+  wire                            up_wreq_s;
+  wire  [(ROM_ADDR_BITS+1):0]     up_waddr_s;
+  wire  [31:0]                    up_wdata_s;
+  wire  [31:0]                    rom_data_s;
 
-assign up_clk = s_axi_aclk;
-assign up_rstn = s_axi_aresetn;
+  assign up_clk = s_axi_aclk;
+  assign up_rstn = s_axi_aresetn;
 
-assign rom_addr = up_raddr_s [ROM_ADDR_BITS-1:0];
-assign rom_data_s = (up_raddr_s [ROM_ADDR_BITS + 1'h1: ROM_ADDR_BITS] == 2'h1) ? sys_rom_data :
-                  (up_raddr_s [ROM_ADDR_BITS + 1'h1: ROM_ADDR_BITS] == 2'h2) ? pr_rom_data : 'h0;
+  assign rom_addr = up_raddr_s [ROM_ADDR_BITS-1:0];
+  assign rom_data_s = (up_raddr_s [ROM_ADDR_BITS + 1'h1: ROM_ADDR_BITS] == 2'h1) ? sys_rom_data :
+                    (up_raddr_s [ROM_ADDR_BITS + 1'h1: ROM_ADDR_BITS] == 2'h2) ? pr_rom_data : 'h0;
 
-up_axi #(
-  .AXI_ADDRESS_WIDTH(ROM_ADDR_BITS+4))
-i_up_axi (
-  .up_rstn (up_rstn),
-  .up_clk (up_clk),
-  .up_axi_awvalid (s_axi_awvalid),
-  .up_axi_awaddr (s_axi_awaddr[ROM_ADDR_BITS+3:0]),
-  .up_axi_awready (s_axi_awready),
-  .up_axi_wvalid (s_axi_wvalid),
-  .up_axi_wdata (s_axi_wdata),
-  .up_axi_wstrb (s_axi_wstrb),
-  .up_axi_wready (s_axi_wready),
-  .up_axi_bvalid (s_axi_bvalid),
-  .up_axi_bresp (s_axi_bresp),
-  .up_axi_bready (s_axi_bready),
-  .up_axi_arvalid (s_axi_arvalid),
-  .up_axi_araddr (s_axi_araddr[ROM_ADDR_BITS+3:0]),
-  .up_axi_arready (s_axi_arready),
-  .up_axi_rvalid (s_axi_rvalid),
-  .up_axi_rresp (s_axi_rresp),
-  .up_axi_rdata (s_axi_rdata),
-  .up_axi_rready (s_axi_rready),
-  .up_wreq (up_wreq_s),
-  .up_waddr (up_waddr_s),
-  .up_wdata (up_wdata_s),
-  .up_wack (up_wack),
-  .up_rreq (up_rreq_s),
-  .up_raddr (up_raddr_s),
-  .up_rdata (up_rdata_s),
-  .up_rack (up_rack_s));
+  up_axi #(
+    .AXI_ADDRESS_WIDTH(ROM_ADDR_BITS+4)
+  ) i_up_axi (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_axi_awvalid (s_axi_awvalid),
+    .up_axi_awaddr (s_axi_awaddr[ROM_ADDR_BITS+3:0]),
+    .up_axi_awready (s_axi_awready),
+    .up_axi_wvalid (s_axi_wvalid),
+    .up_axi_wdata (s_axi_wdata),
+    .up_axi_wstrb (s_axi_wstrb),
+    .up_axi_wready (s_axi_wready),
+    .up_axi_bvalid (s_axi_bvalid),
+    .up_axi_bresp (s_axi_bresp),
+    .up_axi_bready (s_axi_bready),
+    .up_axi_arvalid (s_axi_arvalid),
+    .up_axi_araddr (s_axi_araddr[ROM_ADDR_BITS+3:0]),
+    .up_axi_arready (s_axi_arready),
+    .up_axi_rvalid (s_axi_rvalid),
+    .up_axi_rresp (s_axi_rresp),
+    .up_axi_rdata (s_axi_rdata),
+    .up_axi_rready (s_axi_rready),
+    .up_wreq (up_wreq_s),
+    .up_waddr (up_waddr_s),
+    .up_wdata (up_wdata_s),
+    .up_wack (up_wack),
+    .up_rreq (up_rreq_s),
+    .up_raddr (up_raddr_s),
+    .up_rdata (up_rdata_s),
+    .up_rack (up_rack_s));
 
-//delaying data read with 1 tck to compensate for the ROM latency
-always @(posedge up_clk) begin
-  up_rreq_s_d <= up_rreq_s;
-end
+  //delaying data read with 1 tck to compensate for the ROM latency
+  always @(posedge up_clk) begin
+    up_rreq_s_d <= up_rreq_s;
+  end
 
-//axi registers read
-always @(posedge up_clk) begin
-  if (up_rstn == 1'b0) begin
-    up_rack_s <= 'd0;
-    up_rdata_s <= 'd0;
-  end else begin
-    up_rack_s <= up_rreq_s_d;
-    if (up_rreq_s_d == 1'b1) begin
-      case (up_raddr_s)
-        8'h00: up_rdata_s <= CORE_VERSION;
-        8'h01: up_rdata_s <= 0;
-        8'h02: up_rdata_s <= up_scratch;
-        8'h03: up_rdata_s <= CORE_MAGIC;
-        8'h10: up_rdata_s <= ROM_ADDR_BITS;
-        default: begin
-          up_rdata_s <= rom_data_s;
-        end
-      endcase
+  //axi registers read
+  always @(posedge up_clk) begin
+    if (up_rstn == 1'b0) begin
+      up_rack_s <= 'd0;
+      up_rdata_s <= 'd0;
     end else begin
-      up_rdata_s <= 32'd0;
+      up_rack_s <= up_rreq_s_d;
+      if (up_rreq_s_d == 1'b1) begin
+        case (up_raddr_s)
+          8'h00: up_rdata_s <= CORE_VERSION;
+          8'h01: up_rdata_s <= 0;
+          8'h02: up_rdata_s <= up_scratch;
+          8'h03: up_rdata_s <= CORE_MAGIC;
+          8'h10: up_rdata_s <= ROM_ADDR_BITS;
+          default: begin
+            up_rdata_s <= rom_data_s;
+          end
+        endcase
+      end else begin
+        up_rdata_s <= 32'd0;
+      end
     end
   end
-end
 
-//axi registers write
-always @(posedge up_clk) begin
-  if (up_rstn == 1'b0) begin
-    up_wack <= 'd0;
-    up_scratch <= 'd0;
-  end else begin
-    up_wack <= up_wreq_s;
-    if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h02)) begin
-      up_scratch <= up_wdata_s;
+  //axi registers write
+  always @(posedge up_clk) begin
+    if (up_rstn == 1'b0) begin
+      up_wack <= 'd0;
+      up_scratch <= 'd0;
+    end else begin
+      up_wack <= up_wreq_s;
+      if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h02)) begin
+        up_scratch <= up_wdata_s;
+      end
     end
   end
-end
 
 endmodule
diff --git a/library/axi_tdd/axi_tdd.v b/library/axi_tdd/axi_tdd.v
index f9c440eae..90fd51fd1 100644
--- a/library/axi_tdd/axi_tdd.v
+++ b/library/axi_tdd/axi_tdd.v
@@ -89,7 +89,7 @@ module axi_tdd #(
   output      [ 1:0]      s_axi_rresp,
   output      [31:0]      s_axi_rdata,
   input                   s_axi_rready
-  );
+);
 
   // internal signals
 
@@ -167,7 +167,7 @@ module axi_tdd #(
   // tx/rx data flow control
 
   always @(posedge clk) begin
-    if((tdd_enable_s == 1) && (tdd_gated_tx_dmapath_s == 1)) begin
+    if ((tdd_enable_s == 1) && (tdd_gated_tx_dmapath_s == 1)) begin
       tdd_tx_valid <= tdd_tx_dp_en_s;
     end else begin
       tdd_tx_valid <= 1'b1;
@@ -175,7 +175,7 @@ module axi_tdd #(
   end
 
   always @(posedge clk) begin
-    if((tdd_enable_s == 1) && (tdd_gated_rx_dmapath_s == 1)) begin
+    if ((tdd_enable_s == 1) && (tdd_gated_rx_dmapath_s == 1)) begin
       tdd_rx_valid <= tdd_rx_dp_en_s;
     end else begin
       tdd_rx_valid <= 1'b1;
@@ -183,7 +183,7 @@ module axi_tdd #(
   end
 
   always @(posedge clk) begin
-    if(rst == 1'b1) begin
+    if (rst == 1'b1) begin
       tdd_vco_overlap <= 1'b0;
       tdd_rf_overlap <= 1'b0;
     end else begin
@@ -197,8 +197,8 @@ module axi_tdd #(
   // instantiations
 
   up_tdd_cntrl #(
-    .BASE_ADDRESS('h0))
-  i_up_tdd_cntrl(
+    .BASE_ADDRESS('h0)
+  ) i_up_tdd_cntrl(
     .clk(clk),
     .rst(rst),
     .tdd_enable(tdd_enable_s),
@@ -249,8 +249,8 @@ module axi_tdd #(
 
   ad_tdd_control #(
     .TX_DATA_PATH_DELAY(0),
-    .CONTROL_PATH_DELAY(0))
-  i_tdd_control(
+    .CONTROL_PATH_DELAY(0)
+  ) i_tdd_control (
     .clk(clk),
     .rst(rst),
     .tdd_enable(tdd_enable_s),
@@ -294,8 +294,8 @@ module axi_tdd #(
     .tdd_counter_status(tdd_counter_status));
 
   up_axi #(
-    .AXI_ADDRESS_WIDTH(16))
-  i_up_axi (
+    .AXI_ADDRESS_WIDTH(16)
+  ) i_up_axi (
     .up_rstn(s_axi_aresetn),
     .up_clk(s_axi_aclk),
 
@@ -324,7 +324,6 @@ module axi_tdd #(
     .up_rreq(up_rreq),
     .up_raddr(up_raddr),
     .up_rdata(up_rdata),
-    .up_rack(up_rack)
-  );
+    .up_rack(up_rack));
 
 endmodule
diff --git a/library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer.v b/library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer.v
index 5e432b9cb..07d73f6a8 100644
--- a/library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer.v
+++ b/library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer.v
@@ -72,126 +72,126 @@ module cn0363_dma_sequencer (
   output processing_resetn
 );
 
-reg [3:0] count = 'h00;
+  reg [3:0] count = 'h00;
 
-assign overflow = dma_wr_overflow;
-assign processing_resetn = dma_wr_xfer_req;
+  assign overflow = dma_wr_overflow;
+  assign processing_resetn = dma_wr_xfer_req;
 
-always @(posedge clk) begin
-  if (processing_resetn == 1'b0) begin
-    count <= 'h0;
-  end else begin
+  always @(posedge clk) begin
+    if (processing_resetn == 1'b0) begin
+      count <= 'h0;
+    end else begin
+      case (count)
+        'h0: if (phase_valid) count <= count + 1;
+        'h1: if (data_valid) count <= count + 1;
+        'h2: if (data_filtered_valid) count <= count + 1;
+        'h3: if (i_q_valid) count <= count + 1;
+        'h4: if (i_q_valid) count <= count + 1;
+        'h5: if (i_q_filtered_valid) count <= count + 1;
+        'h6: if (i_q_filtered_valid) count <= count + 1;
+        'h7: if (phase_valid) count <= count + 1;
+        'h8: if (data_valid) count <= count + 1;
+        'h9: if (data_filtered_valid) count <= count + 1;
+        'ha: if (i_q_valid) count <= count + 1;
+        'hb: if (i_q_valid) count <= count + 1;
+        'hc: if (i_q_filtered_valid) count <= count + 1;
+        'hd: if (i_q_filtered_valid) count <= 'h00;
+      endcase
+    end
+  end
+
+  always @(posedge clk) begin
     case (count)
-    'h0: if (phase_valid) count <= count + 1;
-    'h1: if (data_valid) count <= count + 1;
-    'h2: if (data_filtered_valid) count <= count + 1;
-    'h3: if (i_q_valid) count <= count + 1;
-    'h4: if (i_q_valid) count <= count + 1;
-    'h5: if (i_q_filtered_valid) count <= count + 1;
-    'h6: if (i_q_filtered_valid) count <= count + 1;
-    'h7: if (phase_valid) count <= count + 1;
-    'h8: if (data_valid) count <= count + 1;
-    'h9: if (data_filtered_valid) count <= count + 1;
-    'ha: if (i_q_valid) count <= count + 1;
-    'hb: if (i_q_valid) count <= count + 1;
-    'hc: if (i_q_filtered_valid) count <= count + 1;
-    'hd: if (i_q_filtered_valid) count <= 'h00;
+      'h0: dma_wr_data <= phase;
+      'h1: dma_wr_data <= {8'h00,data[23:0]};
+      'h2: dma_wr_data <= data_filtered;
+      'h3: dma_wr_data <= i_q;
+      'h4: dma_wr_data <= i_q;
+      'h5: dma_wr_data <= i_q_filtered;
+      'h6: dma_wr_data <= i_q_filtered;
+      'h7: dma_wr_data <= phase;
+      'h8: dma_wr_data <= {8'h00,data[23:0]};
+      'h9: dma_wr_data <= data_filtered;
+      'ha: dma_wr_data <= i_q;
+      'hb: dma_wr_data <= i_q;
+      'hc: dma_wr_data <= i_q_filtered;
+      'hd: dma_wr_data <= i_q_filtered;
     endcase
   end
-end
 
-always @(posedge clk) begin
-  case (count)
-  'h0: dma_wr_data <= phase;
-  'h1: dma_wr_data <= {8'h00,data[23:0]};
-  'h2: dma_wr_data <= data_filtered;
-  'h3: dma_wr_data <= i_q;
-  'h4: dma_wr_data <= i_q;
-  'h5: dma_wr_data <= i_q_filtered;
-  'h6: dma_wr_data <= i_q_filtered;
-  'h7: dma_wr_data <= phase;
-  'h8: dma_wr_data <= {8'h00,data[23:0]};
-  'h9: dma_wr_data <= data_filtered;
-  'ha: dma_wr_data <= i_q;
-  'hb: dma_wr_data <= i_q;
-  'hc: dma_wr_data <= i_q_filtered;
-  'hd: dma_wr_data <= i_q_filtered;
-  endcase
-end
+  always @(posedge clk) begin
+    if (processing_resetn == 1'b0 || channel_enable[count] == 1'b0) begin
+      dma_wr_en <= 1'b0;
+    end else begin
+      case (count)
+        'h0: dma_wr_en <= phase_valid;
+        'h1: dma_wr_en <= data_valid;
+        'h2: dma_wr_en <= data_filtered_valid;
+        'h3: dma_wr_en <= i_q_valid;
+        'h4: dma_wr_en <= i_q_valid;
+        'h5: dma_wr_en <= i_q_filtered_valid;
+        'h6: dma_wr_en <= i_q_filtered_valid;
+        'h7: dma_wr_en <= phase_valid;
+        'h8: dma_wr_en <= data_valid;
+        'h9: dma_wr_en <= data_filtered_valid;
+        'ha: dma_wr_en <= i_q_valid;
+        'hb: dma_wr_en <= i_q_valid;
+        'hc: dma_wr_en <= i_q_filtered_valid;
+        'hd: dma_wr_en <= i_q_filtered_valid;
+      endcase
+    end
+  end
 
-always @(posedge clk) begin
-  if (processing_resetn == 1'b0 || channel_enable[count] == 1'b0) begin
-    dma_wr_en <= 1'b0;
-  end else begin
+  always @(posedge clk) begin
+    if (count == 'h00) begin
+      dma_wr_sync <= 1'b1;
+    end else if (dma_wr_en == 1'b1) begin
+      dma_wr_sync = 1'b0;
+    end
+  end
+
+  always @(*) begin
     case (count)
-    'h0: dma_wr_en <= phase_valid;
-    'h1: dma_wr_en <= data_valid;
-    'h2: dma_wr_en <= data_filtered_valid;
-    'h3: dma_wr_en <= i_q_valid;
-    'h4: dma_wr_en <= i_q_valid;
-    'h5: dma_wr_en <= i_q_filtered_valid;
-    'h6: dma_wr_en <= i_q_filtered_valid;
-    'h7: dma_wr_en <= phase_valid;
-    'h8: dma_wr_en <= data_valid;
-    'h9: dma_wr_en <= data_filtered_valid;
-    'ha: dma_wr_en <= i_q_valid;
-    'hb: dma_wr_en <= i_q_valid;
-    'hc: dma_wr_en <= i_q_filtered_valid;
-    'hd: dma_wr_en <= i_q_filtered_valid;
+      'h0: phase_ready <= 1'b1;
+      'h7: phase_ready <= 1'b1;
+      default: phase_ready <= 1'b0;
     endcase
   end
-end
 
-always @(posedge clk) begin
-  if (count == 'h00) begin
-    dma_wr_sync <= 1'b1;
-  end else if (dma_wr_en == 1'b1) begin
-    dma_wr_sync = 1'b0;
+  always @(*) begin
+    case (count)
+      'h1: data_ready <= 1'b1;
+      'h8: data_ready <= 1'b1;
+      default: data_ready <= 1'b0;
+    endcase
   end
-end
 
-always @(*) begin
-  case (count)
-  'h0: phase_ready <= 1'b1;
-  'h7: phase_ready <= 1'b1;
-  default: phase_ready <= 1'b0;
-  endcase
-end
+  always @(*) begin
+    case (count)
+      'h2: data_filtered_ready <= 1'b1;
+      'h9: data_filtered_ready <= 1'b1;
+      default: data_filtered_ready <= 1'b0;
+    endcase
+  end
 
-always @(*) begin
-  case (count)
-  'h1: data_ready <= 1'b1;
-  'h8: data_ready <= 1'b1;
-  default: data_ready <= 1'b0;
-  endcase
-end
+  always @(*) begin
+    case (count)
+      'h3: i_q_ready <= 1'b1;
+      'h4: i_q_ready <= 1'b1;
+      'ha: i_q_ready <= 1'b1;
+      'hb: i_q_ready <= 1'b1;
+      default: i_q_ready <= 1'b0;
+    endcase
+  end
 
-always @(*) begin
-  case (count)
-  'h2: data_filtered_ready <= 1'b1;
-  'h9: data_filtered_ready <= 1'b1;
-  default: data_filtered_ready <= 1'b0;
-  endcase
-end
-
-always @(*) begin
-  case (count)
-  'h3: i_q_ready <= 1'b1;
-  'h4: i_q_ready <= 1'b1;
-  'ha: i_q_ready <= 1'b1;
-  'hb: i_q_ready <= 1'b1;
-  default: i_q_ready <= 1'b0;
-  endcase
-end
-
-always @(*) begin
-  case (count)
-  'h5: i_q_filtered_ready <= 1'b1;
-  'h6: i_q_filtered_ready <= 1'b1;
-  'hc: i_q_filtered_ready <= 1'b1;
-  'hd: i_q_filtered_ready <= 1'b1;
-  default: i_q_filtered_ready <= 1'b0;
-  endcase
-end
+  always @(*) begin
+    case (count)
+      'h5: i_q_filtered_ready <= 1'b1;
+      'h6: i_q_filtered_ready <= 1'b1;
+      'hc: i_q_filtered_ready <= 1'b1;
+      'hd: i_q_filtered_ready <= 1'b1;
+      default: i_q_filtered_ready <= 1'b0;
+    endcase
+  end
 
 endmodule
diff --git a/library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync.v b/library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync.v
index 678002382..086ef87b9 100644
--- a/library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync.v
+++ b/library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync.v
@@ -61,106 +61,106 @@ module cn0363_phase_data_sync (
   output reg overflow
 );
 
-reg [1:0] data_counter = 'h00;
+  reg [1:0] data_counter = 'h00;
 
-reg [31:0] phase_hold = 'h00;
-reg [23:0] sample_hold = 'h00;
-reg sample_hold_valid = 1'b0;
-reg conv_done_d1 = 1'b0;
+  reg [31:0] phase_hold = 'h00;
+  reg [23:0] sample_hold = 'h00;
+  reg sample_hold_valid = 1'b0;
+  reg conv_done_d1 = 1'b0;
 
-reg synced = 1'b0;
-wire sync;
+  reg synced = 1'b0;
+  wire sync;
 
-/* The ADC will do conversions regardless of whether the pipeline is ready or
-   not. So we'll always accept new samples and assert overflow if necessary if
-   the pipeline is not ready. */
-assign s_axis_sample_ready = 1'b1;
+  /* The ADC will do conversions regardless of whether the pipeline is ready or
+     not. So we'll always accept new samples and assert overflow if necessary if
+     the pipeline is not ready. */
+  assign s_axis_sample_ready = 1'b1;
 
-// Conversion from offset binary to signed on data
-assign m_axis_sample_data = {~sample_hold[23],sample_hold[22:0]};
-assign m_axis_phase_data = phase_hold;
+  // Conversion from offset binary to signed on data
+  assign m_axis_sample_data = {~sample_hold[23],sample_hold[22:0]};
+  assign m_axis_phase_data = phase_hold;
 
-always @(posedge clk) begin
-  if (conv_done_d1 == 1'b0 && conv_done == 1'b1) begin
-    // Is the processing pipeline ready to accept data?
-    if (m_axis_sample_valid | m_axis_phase_valid | ~processing_resetn) begin
-      overflow <= 1'b1;
+  always @(posedge clk) begin
+    if (conv_done_d1 == 1'b0 && conv_done == 1'b1) begin
+      // Is the processing pipeline ready to accept data?
+      if (m_axis_sample_valid | m_axis_phase_valid | ~processing_resetn) begin
+        overflow <= 1'b1;
+      end else begin
+        phase_hold <= phase;
+        overflow <= 1'b0;
+      end
     end else begin
-      phase_hold <= phase;
       overflow <= 1'b0;
     end
-  end else begin
-    overflow <= 1'b0;
+    conv_done_d1 <= conv_done;
   end
-  conv_done_d1 <= conv_done;
-end
 
-always @(posedge clk) begin
-  if (processing_resetn == 1'b0) begin
-    m_axis_phase_valid <= 1'b0;
-    m_axis_sample_valid <= 1'b0;
-  end else begin
-    /* Data and phase become valid once we have both */
-    if (sample_hold_valid == 1'b1) begin
-      m_axis_phase_valid <= 1'b1;
-      m_axis_sample_valid <= 1'b1;
+  always @(posedge clk) begin
+    if (processing_resetn == 1'b0) begin
+      m_axis_phase_valid <= 1'b0;
+      m_axis_sample_valid <= 1'b0;
     end else begin
-      if (m_axis_phase_ready == 1'b1) begin
-        m_axis_phase_valid <= 1'b0;
-      end
-      if (m_axis_sample_ready == 1'b1) begin
-        m_axis_sample_valid <= 1'b0;
+      /* Data and phase become valid once we have both */
+      if (sample_hold_valid == 1'b1) begin
+        m_axis_phase_valid <= 1'b1;
+        m_axis_sample_valid <= 1'b1;
+      end else begin
+        if (m_axis_phase_ready == 1'b1) begin
+          m_axis_phase_valid <= 1'b0;
+        end
+        if (m_axis_sample_ready == 1'b1) begin
+          m_axis_sample_valid <= 1'b0;
+        end
       end
     end
   end
-end
 
-/* If the STAT register is included in the sample we get 4 bytes per sample and
- * are able to detect channel swaps and synchronize the first output sample to
- * the first channel. If the STAT register is not included we only get 3 bytes
- * per sample and rely on that the first sample will always be from the first
- * channel */
+  /* If the STAT register is included in the sample we get 4 bytes per sample and
+   * are able to detect channel swaps and synchronize the first output sample to
+   * the first channel. If the STAT register is not included we only get 3 bytes
+   * per sample and rely on that the first sample will always be from the first
+   * channel */
 
-always @(posedge clk) begin
-  sample_hold_valid <= 1'b0;
-  if (sample_has_stat == 1'b0) begin
-    if (s_axis_sample_valid == 1'b1 && data_counter == 2'h2) begin
-      sample_hold_valid <= 1'b1;
-    end
-  end else begin
-    if (s_axis_sample_valid == 1'b1 && data_counter == 2'h3 &&
-      (sync == 1'b1 || synced == 1'b1)) begin
-      sample_hold_valid <= 1'b1;
-    end
-  end
-end
-
-always @(posedge clk) begin
-  if (s_axis_sample_valid == 1'b1 && data_counter != 2'h3) begin
-    sample_hold <= {sample_hold[15:0],s_axis_sample_data};
-  end
-end
-
-always @(posedge clk) begin
-  if (s_axis_sample_valid == 1'b1) begin
-    if (data_counter == 2'h2 && sample_has_stat == 1'b0) begin
-      data_counter <= 2'h0;
+  always @(posedge clk) begin
+    sample_hold_valid <= 1'b0;
+    if (sample_has_stat == 1'b0) begin
+      if (s_axis_sample_valid == 1'b1 && data_counter == 2'h2) begin
+        sample_hold_valid <= 1'b1;
+      end
     end else begin
-      data_counter <= data_counter + 1'b1;
+      if (s_axis_sample_valid == 1'b1 && data_counter == 2'h3 &&
+        (sync == 1'b1 || synced == 1'b1)) begin
+        sample_hold_valid <= 1'b1;
+      end
     end
   end
-end
 
-assign sync = s_axis_sample_data[3:0] == 'h00 && data_counter == 'h3;
-
-always @(posedge clk) begin
-  if (processing_resetn == 1'b0) begin
-    synced <= ~sample_has_stat;
-  end else begin
-    if (s_axis_sample_valid == 1'b1 && sync == 1'b1) begin
-      synced <= 1'b1;
+  always @(posedge clk) begin
+    if (s_axis_sample_valid == 1'b1 && data_counter != 2'h3) begin
+      sample_hold <= {sample_hold[15:0],s_axis_sample_data};
+    end
+  end
+
+  always @(posedge clk) begin
+    if (s_axis_sample_valid == 1'b1) begin
+      if (data_counter == 2'h2 && sample_has_stat == 1'b0) begin
+        data_counter <= 2'h0;
+      end else begin
+        data_counter <= data_counter + 1'b1;
+      end
+    end
+  end
+
+  assign sync = s_axis_sample_data[3:0] == 'h00 && data_counter == 'h3;
+
+  always @(posedge clk) begin
+    if (processing_resetn == 1'b0) begin
+      synced <= ~sample_has_stat;
+    end else begin
+      if (s_axis_sample_valid == 1'b1 && sync == 1'b1) begin
+        synced <= 1'b1;
+      end
     end
   end
-end
 
 endmodule
diff --git a/library/common/ad_3w_spi.v b/library/common/ad_3w_spi.v
index ca422c39a..e5c72e10b 100644
--- a/library/common/ad_3w_spi.v
+++ b/library/common/ad_3w_spi.v
@@ -47,15 +47,16 @@
 
 module ad_3w_spi #(
 
-  parameter NUM_OF_SLAVES=8) (
-
+  parameter NUM_OF_SLAVES = 8
+) (
   input       [NUM_OF_SLAVES-1:0] spi_csn,
   input                           spi_clk,
   input                           spi_mosi,
   output                          spi_miso,
 
   inout                           spi_sdio,
-  output                          spi_dir);
+  output                          spi_dir
+);
 
   // internal registers
 
@@ -102,6 +103,3 @@ module ad_3w_spi #(
   assign spi_sdio = (spi_enable_s == 1'b1) ? 1'bz : spi_mosi;
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/common/ad_addsub.v b/library/common/ad_addsub.v
index 250f45766..e149e088c 100644
--- a/library/common/ad_addsub.v
+++ b/library/common/ad_addsub.v
@@ -43,13 +43,14 @@ module ad_addsub #(
 
   parameter   A_DATA_WIDTH = 32,
   parameter   B_DATA_VALUE = 32'h1,
-  parameter   ADD_OR_SUB_N = 0) (
+  parameter   ADD_OR_SUB_N = 0
+) (
   input                   clk,
   input       [(A_DATA_WIDTH-1):0]  A,
   input       [(A_DATA_WIDTH-1):0]  Amax,
   output  reg [(A_DATA_WIDTH-1):0]  out,
-  input                   CE);
-
+  input                   CE
+);
 
   localparam  ADDER = 1;
   localparam  SUBSTRACTER = 0;
diff --git a/library/common/ad_adl5904_rst.v b/library/common/ad_adl5904_rst.v
index ce5f7aa25..c0300293b 100644
--- a/library/common/ad_adl5904_rst.v
+++ b/library/common/ad_adl5904_rst.v
@@ -39,7 +39,8 @@ module ad_adl5904_rst (
 
   input           sys_cpu_clk,
   input           rf_peak_det_n,
-  output          rf_peak_rst);
+  output          rf_peak_rst
+);
 
   // internal registers
 
@@ -73,6 +74,3 @@ module ad_adl5904_rst (
   end
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/common/ad_axis_inf_rx.v b/library/common/ad_axis_inf_rx.v
index 1dcf508d6..5f6d2c514 100644
--- a/library/common/ad_axis_inf_rx.v
+++ b/library/common/ad_axis_inf_rx.v
@@ -37,7 +37,8 @@
 
 module ad_axis_inf_rx #(
 
-  parameter   DATA_WIDTH = 16) (
+  parameter   DATA_WIDTH = 16
+) (
 
   // adi interface
 
@@ -54,7 +55,8 @@ module ad_axis_inf_rx #(
   output  reg [(DATA_WIDTH-1):0]  inf_data = {DATA_WIDTH{1'b0}},
   input                           inf_ready,
 
-  output                          int_not_full);
+  output                          int_not_full
+);
 
   // internal registers
 
@@ -191,6 +193,3 @@ module ad_axis_inf_rx #(
   end
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/common/ad_b2g.v b/library/common/ad_b2g.v
index 15f68c0ff..db0aaa604 100644
--- a/library/common/ad_b2g.v
+++ b/library/common/ad_b2g.v
@@ -37,10 +37,11 @@
 
 module ad_b2g #(
 
-  parameter DATA_WIDTH = 8) (
-
+  parameter DATA_WIDTH = 8
+) (
   input       [DATA_WIDTH-1:0]    din,
-  output      [DATA_WIDTH-1:0]    dout);
+  output      [DATA_WIDTH-1:0]    dout
+);
 
   function [DATA_WIDTH-1:0] b2g;
     input [DATA_WIDTH-1:0] b;
@@ -56,4 +57,3 @@ module ad_b2g #(
   assign dout = b2g(din);
 
 endmodule
-
diff --git a/library/common/ad_bus_mux.v b/library/common/ad_bus_mux.v
index 95933568e..656da1c3e 100644
--- a/library/common/ad_bus_mux.v
+++ b/library/common/ad_bus_mux.v
@@ -38,8 +38,8 @@
 module ad_bus_mux #(
 
   // Channel data width
-  parameter DATA_WIDTH = 16) (
-
+  parameter DATA_WIDTH = 16
+) (
   input                    select_path,
 
   input                    valid_in_0,
@@ -52,7 +52,8 @@ module ad_bus_mux #(
 
   output                   valid_out,
   output                   enable_out,
-  output [DATA_WIDTH-1:0]  data_out);
+  output [DATA_WIDTH-1:0]  data_out
+);
 
   assign valid_out  = (select_path == 0) ? valid_in_0   : valid_in_1;
   assign enable_out = (select_path == 0) ? enable_in_0  : enable_in_1;
diff --git a/library/common/ad_csc.v b/library/common/ad_csc.v
index 02bc941f2..05a923815 100644
--- a/library/common/ad_csc.v
+++ b/library/common/ad_csc.v
@@ -41,7 +41,8 @@ module ad_csc #(
   parameter   DELAY_DW    = 16,
   parameter   MUL_COEF_DW = 17,
   parameter   SUM_COEF_DW = 24,
-  parameter   YCbCr_2_RGB = 0) (
+  parameter   YCbCr_2_RGB = 0
+) (
 
   // data
 
@@ -59,8 +60,8 @@ module ad_csc #(
   // sync is delay matched
 
   output       [   DELAY_DW-1:0]    csc_sync,
-  output       [            7:0]    csc_data);
-
+  output       [            7:0]    csc_data
+);
 
   localparam PIXEL_WD = 9; // sign extended
   localparam MUL_DW = MUL_COEF_DW + PIXEL_WD -1;
@@ -81,7 +82,6 @@ module ad_csc #(
   reg         [DELAY_DW-1:0]  sync_4_m;
   reg         [         7:0]  csc_data_d;
 
-
   wire signed [8:0]  color1;
   wire signed [8:0]  color2;
   wire signed [8:0]  color3;
@@ -141,6 +141,3 @@ module ad_csc #(
   endgenerate
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/common/ad_csc_CrYCb2RGB.v b/library/common/ad_csc_CrYCb2RGB.v
index dd46fe95f..8400edd0f 100644
--- a/library/common/ad_csc_CrYCb2RGB.v
+++ b/library/common/ad_csc_CrYCb2RGB.v
@@ -43,7 +43,8 @@
 
 module ad_csc_CrYCb2RGB #(
 
-  parameter   DELAY_DATA_WIDTH = 16) (
+  parameter   DELAY_DATA_WIDTH = 16
+) (
 
   // Cr-Y-Cb inputs
 
@@ -54,7 +55,8 @@ module ad_csc_CrYCb2RGB #(
   // R-G-B outputs
 
   output      [DELAY_DATA_WIDTH-1:0]  RGB_sync,
-  output      [23:0]                  RGB_data);
+  output      [23:0]                  RGB_data
+);
 
   localparam  DW = DELAY_DATA_WIDTH - 1;
 
@@ -64,8 +66,8 @@ module ad_csc_CrYCb2RGB #(
     .DELAY_DW (DELAY_DATA_WIDTH),
     .MUL_COEF_DW (18),
     .SUM_COEF_DW (28),
-    .YCbCr_2_RGB (1))
-  i_csc_R (
+    .YCbCr_2_RGB (1)
+  ) i_csc_R (
     .clk (clk),
     .sync (CrYCb_sync),
     .data (CrYCb_data),
@@ -81,8 +83,8 @@ module ad_csc_CrYCb2RGB #(
   ad_csc  #(
     .MUL_COEF_DW (18),
     .SUM_COEF_DW (28),
-    .YCbCr_2_RGB (1))
-  i_csc_G (
+    .YCbCr_2_RGB (1)
+  ) i_csc_G (
     .clk (clk),
     .sync (1'd0),
     .data (CrYCb_data),
@@ -98,8 +100,8 @@ module ad_csc_CrYCb2RGB #(
   ad_csc #(
     .MUL_COEF_DW (18),
     .SUM_COEF_DW (28),
-    .YCbCr_2_RGB (1))
-  i_csc_B (
+    .YCbCr_2_RGB (1)
+  ) i_csc_B (
     .clk (clk),
     .sync (1'd0),
     .data (CrYCb_data),
@@ -111,6 +113,3 @@ module ad_csc_CrYCb2RGB #(
     .csc_data (RGB_data[7:0]));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/common/ad_csc_RGB2CrYCb.v b/library/common/ad_csc_RGB2CrYCb.v
index d1b15fb87..40bc77ffe 100644
--- a/library/common/ad_csc_RGB2CrYCb.v
+++ b/library/common/ad_csc_RGB2CrYCb.v
@@ -43,7 +43,8 @@
 
 module ad_csc_RGB2CrYCb #(
 
-  parameter   DELAY_DATA_WIDTH = 16) (
+  parameter   DELAY_DATA_WIDTH = 16
+) (
 
   // R-G-B inputs
 
@@ -54,15 +55,16 @@ module ad_csc_RGB2CrYCb #(
   // Cr-Y-Cb outputs
 
   output      [DELAY_DATA_WIDTH-1:0]  CrYCb_sync,
-  output      [23:0]                  CrYCb_data);
+  output      [23:0]                  CrYCb_data
+);
 
   localparam  DW = DELAY_DATA_WIDTH - 1;
 
   // Cr (red-diff)
 
   ad_csc #(
-    .DELAY_DW(DELAY_DATA_WIDTH))
-  j_csc_1_Cr (
+    .DELAY_DW(DELAY_DATA_WIDTH)
+  ) j_csc_1_Cr (
     .clk (clk),
     .sync (RGB_sync),
     .data (RGB_data),
@@ -76,8 +78,8 @@ module ad_csc_RGB2CrYCb #(
   // Y (luma)
 
   ad_csc #(
-    .DELAY_DW(0))
-  j_csc_1_Y (
+    .DELAY_DW(0)
+  ) j_csc_1_Y (
     .clk (clk),
     .sync (1'd0),
     .data (RGB_data),
@@ -91,8 +93,8 @@ module ad_csc_RGB2CrYCb #(
   // Cb (blue-diff)
 
   ad_csc #(
-    .DELAY_DW(0))
-  j_csc_1_Cb (
+    .DELAY_DW(0)
+  ) j_csc_1_Cb (
     .clk (clk),
     .sync (1'd0),
     .data (RGB_data),
@@ -104,6 +106,3 @@ module ad_csc_RGB2CrYCb #(
     .csc_data (CrYCb_data[7:0]));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/common/ad_datafmt.v b/library/common/ad_datafmt.v
index 1abadd860..7c12853ee 100644
--- a/library/common/ad_datafmt.v
+++ b/library/common/ad_datafmt.v
@@ -42,7 +42,8 @@ module ad_datafmt #(
 
   parameter   DATA_WIDTH = 16,
   parameter   OCTETS_PER_SAMPLE = 2,
-  parameter   DISABLE = 0) (
+  parameter   DISABLE = 0
+) (
 
   // data path
 
@@ -56,7 +57,8 @@ module ad_datafmt #(
 
   input                       dfmt_enable,
   input                       dfmt_type,
-  input                       dfmt_se);
+  input                       dfmt_se
+);
 
   // internal registers
 
@@ -104,6 +106,3 @@ module ad_datafmt #(
   end
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/common/ad_dds.v b/library/common/ad_dds.v
index f378b39ad..39ed6d8ed 100644
--- a/library/common/ad_dds.v
+++ b/library/common/ad_dds.v
@@ -51,7 +51,8 @@ module ad_dds #(
   parameter CORDIC_PHASE_DW = 16,
   // the clock radtio between the device clock(sample rate) and the dac_core clock
   // 2^N, 1<N<6
-  parameter CLK_RATIO = 1) (
+  parameter CLK_RATIO = 1
+) (
 
   // interface
 
@@ -66,7 +67,7 @@ module ad_dds #(
   input       [        PHASE_DW-1:0]  tone_1_freq_word,
   input       [        PHASE_DW-1:0]  tone_2_freq_word,
   output  reg [DDS_DW*CLK_RATIO-1:0]  dac_dds_data
-  );
+);
 
   wire [DDS_DW*CLK_RATIO-1:0] dac_dds_data_s;
 
@@ -146,13 +147,13 @@ module ad_dds #(
         end
 
         // phase to amplitude convertor
-         ad_dds_2 #(
-           .DDS_DW (DDS_DW),
-           .PHASE_DW (PHASE_DW),
-           .DDS_TYPE (DDS_TYPE),
-           .CORDIC_DW (CORDIC_DW),
-           .CORDIC_PHASE_DW (CORDIC_PHASE_DW))
-         i_dds_2 (
+        ad_dds_2 #(
+          .DDS_DW (DDS_DW),
+          .PHASE_DW (PHASE_DW),
+          .DDS_TYPE (DDS_TYPE),
+          .CORDIC_DW (CORDIC_DW),
+          .CORDIC_PHASE_DW (CORDIC_PHASE_DW)
+        ) i_dds_2 (
           .clk (clk),
           .dds_format (dac_dds_format),
           .dds_phase_0 (dac_dds_phase_0_m[i]),
diff --git a/library/common/ad_dds_1.v b/library/common/ad_dds_1.v
index 7c41b15e1..e511bb779 100644
--- a/library/common/ad_dds_1.v
+++ b/library/common/ad_dds_1.v
@@ -41,14 +41,16 @@ module ad_dds_1 #(
 
   parameter   DDS_TYPE = 1,
   parameter   DDS_D_DW = 16,
-  parameter   DDS_P_DW = 16) (
+  parameter   DDS_P_DW = 16
+) (
 
   // interface
 
   input                       clk,
   input       [DDS_P_DW-1:0]  angle,
   input       [        15:0]  scale,
-  output  reg [DDS_D_DW-1:0]  dds_data);
+  output  reg [DDS_D_DW-1:0]  dds_data
+);
 
   // local parameters
 
@@ -68,8 +70,8 @@ module ad_dds_1 #(
       ad_dds_sine_cordic #(
         .CORDIC_DW(DDS_D_DW),
         .PHASE_DW(DDS_P_DW),
-        .DELAY_DW(1))
-      i_dds_sine (
+        .DELAY_DW(1)
+      ) i_dds_sine (
         .clk (clk),
         .angle (angle),
         .sine (sine_s),
@@ -93,8 +95,8 @@ module ad_dds_1 #(
   ad_mul #(
     .A_DATA_WIDTH(DDS_D_DW + 1),
     .B_DATA_WIDTH(17),
-    .DELAY_DATA_WIDTH(1))
-  i_dds_scale (
+    .DELAY_DATA_WIDTH(1)
+  ) i_dds_scale (
     .clk (clk),
     .data_a ({sine_s[DDS_D_DW-1], sine_s}),
     .data_b ({scale[15], scale}),
@@ -110,6 +112,3 @@ module ad_dds_1 #(
   end
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/common/ad_dds_2.v b/library/common/ad_dds_2.v
index 3f965bc30..04ba1e981 100644
--- a/library/common/ad_dds_2.v
+++ b/library/common/ad_dds_2.v
@@ -46,7 +46,8 @@ module ad_dds_2 #(
   // Range = 8-24
   parameter   CORDIC_DW = 16,
   // Range = 8-24 ( make sure CORDIC_PHASE_DW < CORDIC_DW)
-  parameter   CORDIC_PHASE_DW = 16) (
+  parameter   CORDIC_PHASE_DW = 16
+) (
 
   // interface
 
@@ -56,18 +57,19 @@ module ad_dds_2 #(
   input   [        15:0]  dds_scale_0,
   input   [PHASE_DW-1:0]  dds_phase_1,
   input   [        15:0]  dds_scale_1,
-  output  [  DDS_DW-1:0]  dds_data);
+  output  [  DDS_DW-1:0]  dds_data
+);
 
- // Local parameters
+  // Local parameters
 
- localparam CORDIC = 1;
- localparam POLYNOMIAL = 2;
+  localparam CORDIC = 1;
+  localparam POLYNOMIAL = 2;
 
- // The width for Polynomial DDS is fixed (16)
- localparam DDS_D_DW = (DDS_TYPE == CORDIC) ? CORDIC_DW : 16;
- localparam DDS_P_DW = (DDS_TYPE == CORDIC) ? CORDIC_PHASE_DW : 16;
- // concatenation or truncation width
- localparam C_T_WIDTH = (DDS_D_DW > DDS_DW) ? (DDS_D_DW - DDS_DW) : (DDS_DW - DDS_D_DW);
+  // The width for Polynomial DDS is fixed (16)
+  localparam DDS_D_DW = (DDS_TYPE == CORDIC) ? CORDIC_DW : 16;
+  localparam DDS_P_DW = (DDS_TYPE == CORDIC) ? CORDIC_PHASE_DW : 16;
+  // concatenation or truncation width
+  localparam C_T_WIDTH = (DDS_D_DW > DDS_DW) ? (DDS_D_DW - DDS_DW) : (DDS_DW - DDS_D_DW);
 
   // internal registers
 
@@ -111,46 +113,43 @@ module ad_dds_2 #(
       dds_data_int <= dds_data_0_s + dds_data_1_s;
     end
 
-     always @(posedge clk) begin
-       dds_scale_0_d <= dds_scale_0;
-       dds_scale_1_d <= dds_scale_1;
-     end
+    always @(posedge clk) begin
+      dds_scale_0_d <= dds_scale_0;
+      dds_scale_1_d <= dds_scale_1;
+    end
 
-     // phase
-      if (DDS_P_DW > PHASE_DW) begin
-        assign dds_phase_0_s = {dds_phase_0,{DDS_P_DW-PHASE_DW{1'b0}}};
-        assign dds_phase_1_s = {dds_phase_1,{DDS_P_DW-PHASE_DW{1'b0}}};
-      end else begin
-        assign dds_phase_0_s = dds_phase_0[(PHASE_DW-1):PHASE_DW-DDS_P_DW];
-        assign dds_phase_1_s = dds_phase_1[(PHASE_DW-1):PHASE_DW-DDS_P_DW];
-      end
+    // phase
+    if (DDS_P_DW > PHASE_DW) begin
+      assign dds_phase_0_s = {dds_phase_0,{DDS_P_DW-PHASE_DW{1'b0}}};
+      assign dds_phase_1_s = {dds_phase_1,{DDS_P_DW-PHASE_DW{1'b0}}};
+    end else begin
+      assign dds_phase_0_s = dds_phase_0[(PHASE_DW-1):PHASE_DW-DDS_P_DW];
+      assign dds_phase_1_s = dds_phase_1[(PHASE_DW-1):PHASE_DW-DDS_P_DW];
+    end
 
-     // dds-1
+    // dds-1
 
-     ad_dds_1 #(
-       .DDS_TYPE(DDS_TYPE),
-       .DDS_D_DW(DDS_D_DW),
-       .DDS_P_DW(DDS_P_DW))
-     i_dds_1_0 (
-       .clk (clk),
-       .angle (dds_phase_0_s),
-       .scale (dds_scale_0_d),
-       .dds_data (dds_data_0_s));
+    ad_dds_1 #(
+      .DDS_TYPE(DDS_TYPE),
+      .DDS_D_DW(DDS_D_DW),
+      .DDS_P_DW(DDS_P_DW)
+    ) i_dds_1_0 (
+      .clk (clk),
+      .angle (dds_phase_0_s),
+      .scale (dds_scale_0_d),
+      .dds_data (dds_data_0_s));
 
-     // dds-2
+    // dds-2
 
-     ad_dds_1 #(
-       .DDS_TYPE(DDS_TYPE),
-       .DDS_D_DW(DDS_D_DW),
-       .DDS_P_DW(DDS_P_DW))
-     i_dds_1_1 (
-       .clk (clk),
-       .angle (dds_phase_1_s),
-       .scale (dds_scale_1_d),
-       .dds_data (dds_data_1_s));
+    ad_dds_1 #(
+      .DDS_TYPE(DDS_TYPE),
+      .DDS_D_DW(DDS_D_DW),
+      .DDS_P_DW(DDS_P_DW)
+    ) i_dds_1_1 (
+      .clk (clk),
+      .angle (dds_phase_1_s),
+      .scale (dds_scale_1_d),
+      .dds_data (dds_data_1_s));
   endgenerate
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/common/ad_dds_cordic_pipe.v b/library/common/ad_dds_cordic_pipe.v
index 926c47d17..47d0e4ef2 100644
--- a/library/common/ad_dds_cordic_pipe.v
+++ b/library/common/ad_dds_cordic_pipe.v
@@ -46,7 +46,8 @@ module ad_dds_cordic_pipe#(
   // Range = N/A
   parameter DELAY_DW = 1,
   // Range = 0-(DW - 1)
-  parameter SHIFT = 0) (
+  parameter SHIFT = 0
+) (
 
   // Interface
 
@@ -60,7 +61,8 @@ module ad_dds_cordic_pipe#(
   (* keep = "TRUE" *) output reg        [  D_DW-1:0] result_y,
   (* keep = "TRUE" *) output reg        [  P_DW-1:0] result_z,
                       input             [DELAY_DW:1] data_delay_in,
-                      output            [DELAY_DW:1] data_delay_out);
+                      output            [DELAY_DW:1] data_delay_out
+);
 
   // Registers Declarations
 
diff --git a/library/common/ad_dds_sine.v b/library/common/ad_dds_sine.v
index b1755a0fe..40dbb84ab 100644
--- a/library/common/ad_dds_sine.v
+++ b/library/common/ad_dds_sine.v
@@ -39,7 +39,8 @@
 
 module ad_dds_sine #(
 
-  parameter   DELAY_DATA_WIDTH = 16) (
+  parameter   DELAY_DATA_WIDTH = 16
+) (
 
   // sine = sin(angle)
 
@@ -47,7 +48,8 @@ module ad_dds_sine #(
   input   [15:0]                    angle,
   output  [15:0]                    sine,
   input   [(DELAY_DATA_WIDTH-1):0]  ddata_in,
-  output  [(DELAY_DATA_WIDTH-1):0]  ddata_out);
+  output  [(DELAY_DATA_WIDTH-1):0]  ddata_out
+);
 
   // internal registers
 
@@ -96,7 +98,9 @@ module ad_dds_sine #(
 
   // level 1 - intermediate
 
-  ad_mul #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH+16)) i_mul_s1 (
+  ad_mul #(
+    .DELAY_DATA_WIDTH(DELAY_DATA_WIDTH+16)
+  ) i_mul_s1 (
     .clk (clk),
     .data_a ({angle_s[15], angle_s}),
     .data_b ({angle_s[15], angle_s}),
@@ -130,7 +134,9 @@ module ad_dds_sine #(
 
   // level 2 - final
 
-  ad_mul #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH+17)) i_mul_s2 (
+  ad_mul #(
+    .DELAY_DATA_WIDTH(DELAY_DATA_WIDTH+17)
+  ) i_mul_s2 (
     .clk (clk),
     .data_a (s3_data[16:0]),
     .data_b (s3_data[16:0]),
@@ -167,7 +173,9 @@ module ad_dds_sine #(
 
   // full-scale
 
-  ad_mul #(.DELAY_DATA_WIDTH(1)) i_mul_s3_2 (
+  ad_mul #(
+    .DELAY_DATA_WIDTH(1)
+  ) i_mul_s3_2 (
     .clk (clk),
     .data_a (s6_data2),
     .data_b (17'h1d08),
@@ -175,7 +183,9 @@ module ad_dds_sine #(
     .ddata_in (1'b0),
     .ddata_out ());
 
-  ad_mul #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH)) i_mul_s3_1 (
+  ad_mul #(
+    .DELAY_DATA_WIDTH(DELAY_DATA_WIDTH)
+  ) i_mul_s3_1 (
     .clk (clk),
     .data_a (s6_data1),
     .data_b (17'h7fff),
@@ -201,6 +211,3 @@ module ad_dds_sine #(
   end
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/common/ad_dds_sine_cordic.v b/library/common/ad_dds_sine_cordic.v
index 66eba7e38..2ba6ce0bf 100644
--- a/library/common/ad_dds_sine_cordic.v
+++ b/library/common/ad_dds_sine_cordic.v
@@ -42,7 +42,8 @@ module ad_dds_sine_cordic #(
   // Range = 8-24
   parameter   CORDIC_DW = 16,
   // Range = N/A
-  parameter   DELAY_DW  = 1) (
+  parameter   DELAY_DW  = 1
+) (
 
   // interface
 
@@ -51,7 +52,8 @@ module ad_dds_sine_cordic #(
   output reg [CORDIC_DW-1:0]   sine,
   output reg [CORDIC_DW-1:0]   cosine,
   input      [ DELAY_DW-1:0]   ddata_in,
-  output reg [ DELAY_DW-1:0]   ddata_out);
+  output reg [ DELAY_DW-1:0]   ddata_out
+);
 
   // Local Parameters
   localparam LUT_FSCALE = 1 << (PHASE_DW);
@@ -399,8 +401,8 @@ module ad_dds_sine_cordic #(
         .P_DW (PHASE_DW),
         .D_DW (CORDIC_DW),
         .DELAY_DW (DELAY_DW),
-        .SHIFT(i))
-      pipe (
+        .SHIFT(i)
+      ) pipe (
         .clk (clk),
         .dataa_x (x_s[i]),
         .dataa_y (y_s[i]),
@@ -411,8 +413,7 @@ module ad_dds_sine_cordic #(
         .result_y (y_s[i+1]),
         .result_z (z_s[i+1]),
         .data_delay_in (data_in_d[i]),
-        .data_delay_out (data_in_d[i+1])
-      );
+        .data_delay_out (data_in_d[i+1]));
     end
   endgenerate
 
@@ -425,6 +426,3 @@ module ad_dds_sine_cordic #(
   end
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/common/ad_edge_detect.v b/library/common/ad_edge_detect.v
index ddbc7319e..1cffa0449 100644
--- a/library/common/ad_edge_detect.v
+++ b/library/common/ad_edge_detect.v
@@ -39,14 +39,14 @@
 
 module ad_edge_detect #(
 
-  parameter   EDGE = 0) (
-
+  parameter   EDGE = 0
+) (
   input                   clk,
   input                   rst,
 
   input                   signal_in,
-  output  reg             signal_out);
-
+  output  reg             signal_out
+);
 
   localparam  POS_EDGE = 0;
   localparam  NEG_EDGE = 1;
@@ -80,4 +80,3 @@ module ad_edge_detect #(
   end
 
 endmodule
-
diff --git a/library/common/ad_g2b.v b/library/common/ad_g2b.v
index 7d6ada661..d0f3e57b5 100644
--- a/library/common/ad_g2b.v
+++ b/library/common/ad_g2b.v
@@ -37,10 +37,11 @@
 
 module ad_g2b #(
 
-  parameter DATA_WIDTH = 8) (
-
+  parameter DATA_WIDTH = 8
+) (
   input       [DATA_WIDTH-1:0]    din,
-  output      [DATA_WIDTH-1:0]    dout);
+  output      [DATA_WIDTH-1:0]    dout
+);
 
   function [DATA_WIDTH-1:0] g2b;
     input [DATA_WIDTH-1:0] g;
@@ -56,4 +57,3 @@ module ad_g2b #(
   assign dout = g2b(din);
 
 endmodule
-
diff --git a/library/common/ad_iobuf.v b/library/common/ad_iobuf.v
index 7711fa1b1..a93628201 100644
--- a/library/common/ad_iobuf.v
+++ b/library/common/ad_iobuf.v
@@ -37,13 +37,13 @@
 
 module ad_iobuf #(
 
-  parameter     DATA_WIDTH = 1) (
-
+  parameter     DATA_WIDTH = 1
+) (
   input       [(DATA_WIDTH-1):0]  dio_t,
   input       [(DATA_WIDTH-1):0]  dio_i,
   output      [(DATA_WIDTH-1):0]  dio_o,
-  inout       [(DATA_WIDTH-1):0]  dio_p);
-
+  inout       [(DATA_WIDTH-1):0]  dio_p
+);
 
   genvar n;
   generate
@@ -54,6 +54,3 @@ module ad_iobuf #(
   endgenerate
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/common/ad_iqcor.v b/library/common/ad_iqcor.v
index 1ebcf57db..b8737f40b 100644
--- a/library/common/ad_iqcor.v
+++ b/library/common/ad_iqcor.v
@@ -76,7 +76,6 @@ module ad_iqcor #(
   wire [DPW-1:0]    valid_int_loc;
   wire [DPW*CR-1:0] data_int_loc;
 
-
   // data-path disable
 
   generate
@@ -89,7 +88,6 @@ module ad_iqcor #(
   end
   endgenerate
 
-
   // coefficients are flopped to remove warnings from vivado
 
   always @(posedge clk) begin
@@ -122,7 +120,9 @@ module ad_iqcor #(
 
       // scaling functions - i
 
-      ad_mul #(.DELAY_DATA_WIDTH(CR+1)) i_mul_i (
+      ad_mul #(
+        .DELAY_DATA_WIDTH(CR+1)
+      ) i_mul_i (
         .clk (clk),
         .data_a ({data_i_s[CR-1], data_i_s, {16-CR{1'b0}}}),
         .data_b ({iqcor_coeff_1_r[15], iqcor_coeff_1_r}),
@@ -133,7 +133,9 @@ module ad_iqcor #(
       if (SCALE_ONLY == 0) begin
         // scaling functions - q
 
-        ad_mul #(.DELAY_DATA_WIDTH(CR)) i_mul_q (
+        ad_mul #(
+          .DELAY_DATA_WIDTH(CR)
+        ) i_mul_q (
           .clk (clk),
           .data_a ({data_q_s[CR-1], data_q_s, {16-CR{1'b0}}}),
           .data_b ({iqcor_coeff_2_r[15], iqcor_coeff_2_r}),
@@ -147,7 +149,6 @@ module ad_iqcor #(
         assign p1_data_q_s = {CR{1'b0}};
       end
 
-
       if (Q_OR_I_N == 1 && SCALE_ONLY == 0) begin
         reg [CR-1:0]  p1_data_q = 'd0;
 
@@ -195,6 +196,3 @@ module ad_iqcor #(
   endgenerate
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/common/ad_mem.v b/library/common/ad_mem.v
index 0843d4a17..f3825d2b4 100644
--- a/library/common/ad_mem.v
+++ b/library/common/ad_mem.v
@@ -38,8 +38,8 @@
 module ad_mem #(
 
   parameter  DATA_WIDTH = 16,
-  parameter  ADDRESS_WIDTH = 5) (
-
+  parameter  ADDRESS_WIDTH = 5
+) (
   input                               clka,
   input                               wea,
   input       [(ADDRESS_WIDTH-1):0]   addra,
@@ -48,7 +48,8 @@ module ad_mem #(
   input                               clkb,
   input                               reb,
   input       [(ADDRESS_WIDTH-1):0]   addrb,
-  output  reg [(DATA_WIDTH-1):0]      doutb);
+  output  reg [(DATA_WIDTH-1):0]      doutb
+);
 
   (* ram_style = "block" *)
   reg         [(DATA_WIDTH-1):0]      m_ram[0:((2**ADDRESS_WIDTH)-1)];
@@ -66,6 +67,3 @@ module ad_mem #(
   end
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/common/ad_mem_asym.v b/library/common/ad_mem_asym.v
index 1ebb6ded5..196365037 100644
--- a/library/common/ad_mem_asym.v
+++ b/library/common/ad_mem_asym.v
@@ -44,8 +44,8 @@ module ad_mem_asym #(
   parameter   A_DATA_WIDTH = 256,
   parameter   B_ADDRESS_WIDTH =   10,
   parameter   B_DATA_WIDTH =  64,
-  parameter   CASCADE_HEIGHT = -1) (
-
+  parameter   CASCADE_HEIGHT = -1
+) (
   input                             clka,
   input                             wea,
   input       [A_ADDRESS_WIDTH-1:0] addra,
@@ -54,8 +54,8 @@ module ad_mem_asym #(
   input                             clkb,
   input                             reb,
   input       [B_ADDRESS_WIDTH-1:0] addrb,
-  output  reg [B_DATA_WIDTH-1:0]    doutb);
-
+  output  reg [B_DATA_WIDTH-1:0]    doutb
+);
 
   `define max(a,b) {(a) > (b) ? (a) : (b)}
   `define min(a,b) {(a) < (b) ? (a) : (b)}
@@ -145,6 +145,3 @@ module ad_mem_asym #(
   endgenerate
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/common/ad_mux.v b/library/common/ad_mux.v
index e5ecfdc34..e0842e38d 100644
--- a/library/common/ad_mux.v
+++ b/library/common/ad_mux.v
@@ -46,7 +46,6 @@ module ad_mux #(
   parameter REQ_MUX_SZ = 8,  // Size of mux which acts as a building block
   parameter EN_REG = 1,  // Enable register at output of each mux
   parameter DW = CH_W*CH_CNT
-
 ) (
   input clk,
   input [DW-1:0] data_in,
@@ -54,70 +53,65 @@ module ad_mux #(
   output [CH_W-1:0] data_out
 );
 
-`define MIN(A,B) (A<B?A:B)
+  `define MIN(A,B) (A<B?A:B)
 
-localparam MUX_SZ = CH_CNT < REQ_MUX_SZ ? CH_CNT : REQ_MUX_SZ;
-localparam CLOG2_CH_CNT = $clog2(CH_CNT);
-localparam CLOG2_MUX_SZ = $clog2(MUX_SZ);
-localparam NUM_STAGES = ($clog2(CH_CNT) / $clog2(MUX_SZ)) + // divide and round up
-                       |($clog2(CH_CNT) % $clog2(MUX_SZ));
+  localparam MUX_SZ = CH_CNT < REQ_MUX_SZ ? CH_CNT : REQ_MUX_SZ;
+  localparam CLOG2_CH_CNT = $clog2(CH_CNT);
+  localparam CLOG2_MUX_SZ = $clog2(MUX_SZ);
+  localparam NUM_STAGES = ($clog2(CH_CNT) / $clog2(MUX_SZ)) + // divide and round up
+                         |($clog2(CH_CNT) % $clog2(MUX_SZ));
 
-wire [NUM_STAGES*DW+CH_W-1:0] mux_in;
-wire [NUM_STAGES*CLOG2_CH_CNT-1:0] ch_sel_pln;
+  wire [NUM_STAGES*DW+CH_W-1:0] mux_in;
+  wire [NUM_STAGES*CLOG2_CH_CNT-1:0] ch_sel_pln;
 
+  assign mux_in[DW-1:0] = data_in;
+  assign ch_sel_pln[CLOG2_CH_CNT-1:0] = ch_sel;
 
-assign mux_in[DW-1:0] = data_in;
-assign ch_sel_pln[CLOG2_CH_CNT-1:0] = ch_sel;
+  genvar i;
+  genvar j;
 
-genvar i;
-genvar j;
+  generate
 
-generate
+    for (i = 0; i < NUM_STAGES; i = i + 1) begin: g_stage
 
+      wire [CLOG2_CH_CNT-1:0] ch_sel_cur;
+      assign ch_sel_cur = ch_sel_pln[i*CLOG2_CH_CNT+:CLOG2_CH_CNT];
 
-  for (i = 0; i < NUM_STAGES; i = i + 1) begin: g_stage
+      wire [CLOG2_MUX_SZ-1:0] ch_sel_w;
+      assign ch_sel_w = ch_sel_cur >> i*CLOG2_MUX_SZ;
 
-    wire [CLOG2_CH_CNT-1:0] ch_sel_cur;
-    assign ch_sel_cur = ch_sel_pln[i*CLOG2_CH_CNT+:CLOG2_CH_CNT];
-
-    wire [CLOG2_MUX_SZ-1:0] ch_sel_w;
-    assign ch_sel_w = ch_sel_cur >> i*CLOG2_MUX_SZ;
-
-    if (EN_REG) begin
-      reg [CLOG2_CH_CNT-1:0] ch_sel_d;
-      always @(posedge clk) begin
-        ch_sel_d <= ch_sel_cur;
+      if (EN_REG) begin
+        reg [CLOG2_CH_CNT-1:0] ch_sel_d;
+        always @(posedge clk) begin
+          ch_sel_d <= ch_sel_cur;
+        end
+        if (i<NUM_STAGES-1) begin
+          assign ch_sel_pln[(i+1)*CLOG2_CH_CNT+:CLOG2_CH_CNT] = ch_sel_d;
+        end
+      end else begin
+        if (i<NUM_STAGES-1) begin
+          assign ch_sel_pln[(i+1)*CLOG2_CH_CNT+:CLOG2_CH_CNT] = ch_sel_cur;
+        end
       end
-      if (i<NUM_STAGES-1) begin
-        assign ch_sel_pln[(i+1)*CLOG2_CH_CNT+:CLOG2_CH_CNT] = ch_sel_d;
-      end
-    end else begin
-      if (i<NUM_STAGES-1) begin
-        assign ch_sel_pln[(i+1)*CLOG2_CH_CNT+:CLOG2_CH_CNT] = ch_sel_cur;
+
+      localparam MAX_RANGE_PER_STAGE=MUX_SZ**(NUM_STAGES-i);
+
+      for (j = 0; j < `MIN(MAX_RANGE_PER_STAGE,CH_CNT); j = j + MUX_SZ) begin: g_mux
+
+        ad_mux_core #(
+          .CH_W (CH_W),
+          .CH_CNT (MUX_SZ),
+          .EN_REG (EN_REG)
+        ) i_mux (
+          .clk (clk),
+          .data_in (mux_in[i*DW+j*CH_W+:MUX_SZ*CH_W]),
+          .ch_sel (ch_sel_w),
+          .data_out (mux_in[(i+1)*DW+(j/MUX_SZ)*CH_W+:CH_W]));
       end
     end
 
-    localparam MAX_RANGE_PER_STAGE=MUX_SZ**(NUM_STAGES-i);
+  endgenerate
 
-    for (j = 0; j < `MIN(MAX_RANGE_PER_STAGE,CH_CNT); j = j + MUX_SZ) begin: g_mux
-
-      ad_mux_core #(
-        .CH_W (CH_W),
-        .CH_CNT (MUX_SZ),
-        .EN_REG (EN_REG)
-      ) i_mux (
-        .clk (clk),
-        .data_in (mux_in[i*DW+j*CH_W+:MUX_SZ*CH_W]),
-        .ch_sel (ch_sel_w),
-        .data_out (mux_in[(i+1)*DW+(j/MUX_SZ)*CH_W+:CH_W])
-      );
-
-    end
-  end
-
-endgenerate
-
-assign data_out = mux_in[NUM_STAGES*DW+:CH_W];
+  assign data_out = mux_in[NUM_STAGES*DW+:CH_W];
 
 endmodule
-
diff --git a/library/common/ad_mux_core.v b/library/common/ad_mux_core.v
index 99f879cab..7663b247c 100644
--- a/library/common/ad_mux_core.v
+++ b/library/common/ad_mux_core.v
@@ -46,21 +46,19 @@ module ad_mux_core #(
   output [CH_W-1:0] data_out
 );
 
-wire [CH_W-1:0] data_out_loc;
+  wire [CH_W-1:0] data_out_loc;
 
-assign data_out_loc = data_in >> CH_W*ch_sel;
+  assign data_out_loc = data_in >> CH_W*ch_sel;
 
-generate if (EN_REG) begin
-  reg [CH_W-1:0] data_out_reg;
-  always @(posedge clk) begin
-    data_out_reg <= data_out_loc;
+  generate if (EN_REG) begin
+    reg [CH_W-1:0] data_out_reg;
+    always @(posedge clk) begin
+      data_out_reg <= data_out_loc;
+    end
+    assign data_out = data_out_reg;
+  end else begin
+    assign data_out = data_out_loc;
   end
-  assign data_out = data_out_reg;
-end else begin
-  assign data_out = data_out_loc;
-end
-endgenerate
+  endgenerate
 
 endmodule
-
-
diff --git a/library/common/ad_pack.v b/library/common/ad_pack.v
index 342969d2e..4d8d91b40 100644
--- a/library/common/ad_pack.v
+++ b/library/common/ad_pack.v
@@ -45,9 +45,9 @@
 //
 // Data format:
 //  idata  [U(I_W-1) .... U(0)]
-//  odata [U(O_W-1) .... U(0)] 
+//  odata [U(O_W-1) .... U(0)]
 //
-// e.g 
+// e.g
 //  I_W = 4
 //  O_W = 6
 //  UNIT_W = 8
@@ -72,101 +72,100 @@ module ad_pack #(
   output reg                  ovalid = 'b0
 );
 
-// Width of shift reg is integer multiple of input data width
-localparam SH_W = ((O_W/I_W)+|(O_W % I_W))*I_W;
-localparam STEP = O_W % I_W;
+  // Width of shift reg is integer multiple of input data width
+  localparam SH_W = ((O_W/I_W)+|(O_W % I_W))*I_W;
+  localparam STEP = O_W % I_W;
 
-reg [O_W*UNIT_W-1:0] idata_packed;
-reg [SH_W*UNIT_W-1:0] idata_d = 'h0;
-reg ivalid_d  = 'h0;
-reg [SH_W*UNIT_W-1:0] idata_dd = 'h0;
-reg [SH_W-1:0] in_use = 'b0;
-reg [SH_W-1:0] out_mask;
+  reg [O_W*UNIT_W-1:0] idata_packed;
+  reg [SH_W*UNIT_W-1:0] idata_d = 'h0;
+  reg ivalid_d  = 'h0;
+  reg [SH_W*UNIT_W-1:0] idata_dd = 'h0;
+  reg [SH_W-1:0] in_use = 'b0;
+  reg [SH_W-1:0] out_mask;
 
-wire [SH_W*UNIT_W-1:0] idata_dd_nx;
-wire [SH_W-1:0] in_use_nx;
-wire pack_wr;
+  wire [SH_W*UNIT_W-1:0] idata_dd_nx;
+  wire [SH_W-1:0] in_use_nx;
+  wire pack_wr;
 
-generate
-  if (I_REG) begin : i_reg
+  generate
+    if (I_REG) begin : i_reg
+
+      always @(posedge clk) begin
+        ivalid_d <= ivalid;
+        idata_d <= idata;
+      end
+
+    end else begin
+
+      always @(*) begin
+        ivalid_d = ivalid;
+        idata_d = idata;
+      end
 
-    always @(posedge clk) begin
-      ivalid_d <= ivalid;
-      idata_d <= idata;
     end
+  endgenerate
 
-  end else begin
+  assign idata_dd_nx = {idata_d,idata_dd[SH_W*UNIT_W-1:I_W*UNIT_W]};
+  assign in_use_nx = {{I_W{ivalid_d}},in_use[SH_W-1:I_W]};
 
-    always @(*) begin
-      ivalid_d = ivalid;
-      idata_d = idata;
+  always @(posedge clk) begin
+    if (reset) begin
+      in_use <= 'h0;
+    end else if (ivalid_d) begin
+      in_use <= in_use_nx &(~out_mask);
     end
-
   end
-endgenerate
 
-assign idata_dd_nx = {idata_d,idata_dd[SH_W*UNIT_W-1:I_W*UNIT_W]};
-assign in_use_nx = {{I_W{ivalid_d}},in_use[SH_W-1:I_W]};
-
-always @(posedge clk) begin
-  if (reset) begin
-    in_use <= 'h0;
-  end else if (ivalid_d) begin
-    in_use <= in_use_nx &(~out_mask);
+  always @(posedge clk) begin
+    if (ivalid_d) begin
+      idata_dd <= idata_dd_nx;
+    end
   end
-end
 
-always @(posedge clk) begin
-  if (ivalid_d) begin
-    idata_dd <= idata_dd_nx;
-  end
-end
-
-integer i;
-always @(*) begin
-  out_mask = 'b0;
-  idata_packed = 'bx;
-  if (STEP>0) begin
-    for (i = SH_W-O_W; i >= 0; i=i-STEP) begin
-      if (in_use_nx[i]) begin
-        out_mask = {O_W{1'b1}} << i;
-        idata_packed = idata_dd_nx >> i*UNIT_W;
+  integer i;
+  always @(*) begin
+    out_mask = 'b0;
+    idata_packed = 'bx;
+    if (STEP>0) begin
+      for (i = SH_W-O_W; i >= 0; i=i-STEP) begin
+        if (in_use_nx[i]) begin
+          out_mask = {O_W{1'b1}} << i;
+          idata_packed = idata_dd_nx >> i*UNIT_W;
+        end
+      end
+    end else begin
+      if (in_use_nx[0]) begin
+        out_mask = {O_W{1'b1}};
+        idata_packed = idata_dd_nx;
       end
     end
-  end else begin
-    if (in_use_nx[0]) begin
-      out_mask = {O_W{1'b1}};
-      idata_packed = idata_dd_nx;
-    end
   end
-end
 
-assign pack_wr = ivalid_d & |in_use_nx[SH_W-O_W:0];
+  assign pack_wr = ivalid_d & |in_use_nx[SH_W-O_W:0];
 
-generate
-  if (O_REG) begin : o_reg
+  generate
+    if (O_REG) begin : o_reg
 
-    always @(posedge clk) begin
-      if (reset) begin
-        ovalid <= 1'b0;
-      end else begin
-        ovalid <= pack_wr;
+      always @(posedge clk) begin
+        if (reset) begin
+          ovalid <= 1'b0;
+        end else begin
+          ovalid <= pack_wr;
+        end
       end
+
+      always @(posedge clk) begin
+        odata <= idata_packed;
+      end
+
+    end else begin
+
+      always @(*) begin
+        ovalid = pack_wr;
+        odata = idata_packed;
+      end
+
     end
-
-    always @(posedge clk) begin
-      odata <= idata_packed;
-    end
-
-  end else begin
-
-    always @(*) begin
-      ovalid = pack_wr;
-      odata = idata_packed;
-    end
-
-  end
-endgenerate
+  endgenerate
 
 endmodule
-
diff --git a/library/common/ad_pngen.v b/library/common/ad_pngen.v
index e7903cb47..c3c59263a 100644
--- a/library/common/ad_pngen.v
+++ b/library/common/ad_pngen.v
@@ -45,7 +45,6 @@ module ad_pngen #(
   // Input stream to synchronize to (Optional)
   input           pn_init,
   input  [DW-1:0] pn_data_in
-
 );
 
   /* We need at least enough bits to store the PN state */
@@ -59,7 +58,6 @@ module ad_pngen #(
   wire [PN_W-1:0] pn_state_;
   wire [PN_W-1:0] pn_init_data;
 
-
   // pn init data selection
   generate if (PN_W > DW) begin
     reg [PN_W-DW-1:0] pn_data_in_d = 'd0;
@@ -72,7 +70,6 @@ module ad_pngen #(
   end
   endgenerate
 
-
   // PRBS logic
   assign pn_state_ = pn_init ? pn_init_data : pn_state;
   generate
@@ -103,4 +100,3 @@ module ad_pngen #(
   assign pn_data_out = pn_state[PN_W-1 -: DW];
 
 endmodule
-
diff --git a/library/common/ad_pnmon.v b/library/common/ad_pnmon.v
index 6c051c2b2..f44f2c81e 100644
--- a/library/common/ad_pnmon.v
+++ b/library/common/ad_pnmon.v
@@ -40,7 +40,8 @@ module ad_pnmon #(
 
   parameter DATA_WIDTH = 16,
   parameter OOS_THRESHOLD = 16,
-  parameter ALLOW_ZERO_MASKING = 0) (
+  parameter ALLOW_ZERO_MASKING = 0
+) (
 
   // adc interface
 
@@ -91,7 +92,6 @@ module ad_pnmon #(
                           ~adc_pn_oos_int & adc_pn_match_z_s;
   assign adc_pn_err_s = ~(adc_pn_oos_int | adc_pn_match_s | adc_valid_zero_d);
 
-
   // pn oos and counters (16 to clear and set).
 
   assign adc_pn_oos = adc_pn_oos_int;
@@ -116,7 +116,3 @@ module ad_pnmon #(
   end
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
-
diff --git a/library/common/ad_pps_receiver.v b/library/common/ad_pps_receiver.v
index 7a9c1b28c..9927cf1f2 100644
--- a/library/common/ad_pps_receiver.v
+++ b/library/common/ad_pps_receiver.v
@@ -44,7 +44,8 @@ module ad_pps_receiver (
   output  reg [31:0]    up_pps_rcounter,
   output  reg           up_pps_status,
   input                 up_irq_mask,
-  output  reg           up_irq);
+  output  reg           up_irq
+);
 
   // *************************************************************************
   // 1PPS reception and reporting counter implementation
diff --git a/library/common/ad_rst.v b/library/common/ad_rst.v
index 431096332..f0d75aaac 100644
--- a/library/common/ad_rst.v
+++ b/library/common/ad_rst.v
@@ -42,7 +42,8 @@ module ad_rst (
   input                   rst_async,
   input                   clk,
   output                  rstn,
-  output  reg             rst);
+  output  reg             rst
+);
 
   // internal registers
   reg             rst_async_d1 = 1'd1;
@@ -72,6 +73,3 @@ module ad_rst (
   assign rstn = ~rst;
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/common/ad_ss_422to444.v b/library/common/ad_ss_422to444.v
index 874d64a05..78c369689 100644
--- a/library/common/ad_ss_422to444.v
+++ b/library/common/ad_ss_422to444.v
@@ -39,7 +39,8 @@
 module ad_ss_422to444 #(
 
   parameter   CR_CB_N = 0,
-  parameter   DELAY_DATA_WIDTH = 16) (
+  parameter   DELAY_DATA_WIDTH = 16
+) (
 
   // 422 inputs
 
@@ -51,7 +52,8 @@ module ad_ss_422to444 #(
   // 444 outputs
 
   output  reg [DELAY_DATA_WIDTH-1:0]  s444_sync,
-  output  reg [                23:0]  s444_data);
+  output  reg [                23:0]  s444_data
+);
 
   localparam  DW = DELAY_DATA_WIDTH - 1;
 
@@ -133,6 +135,3 @@ module ad_ss_422to444 #(
   end
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/common/ad_ss_444to422.v b/library/common/ad_ss_444to422.v
index 9d7f1c3e5..9e91cae70 100644
--- a/library/common/ad_ss_444to422.v
+++ b/library/common/ad_ss_444to422.v
@@ -39,7 +39,8 @@
 module ad_ss_444to422 #(
 
   parameter   CR_CB_N = 0,
-  parameter   DELAY_DATA_WIDTH = 16) (
+  parameter   DELAY_DATA_WIDTH = 16
+) (
 
   // 444 inputs
 
@@ -51,7 +52,8 @@ module ad_ss_444to422 #(
   // 422 outputs
 
   output  reg [DELAY_DATA_WIDTH-1:0]  s422_sync,
-  output  reg [15:0]                  s422_data);
+  output  reg [15:0]                  s422_data
+);
 
   localparam  DW = DELAY_DATA_WIDTH - 1;
 
@@ -129,6 +131,3 @@ module ad_ss_444to422 #(
   end
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/common/ad_sysref_gen.v b/library/common/ad_sysref_gen.v
index 1b255eab2..aa951d2ec 100644
--- a/library/common/ad_sysref_gen.v
+++ b/library/common/ad_sysref_gen.v
@@ -36,11 +36,10 @@
 `timescale 1ns/100ps
 
 module ad_sysref_gen (
+  input       core_clk,
 
-    input       core_clk,
-
-    input       sysref_en,
-    output reg  sysref_out
+  input       sysref_en,
+  output reg  sysref_out
 );
 
   // SYSREF period is multiple of core_clk, and has a duty cycle of 50%
diff --git a/library/common/ad_tdd_control.v b/library/common/ad_tdd_control.v
index aa0958d9d..edd5046fc 100644
--- a/library/common/ad_tdd_control.v
+++ b/library/common/ad_tdd_control.v
@@ -38,7 +38,8 @@
 module ad_tdd_control#(
 
   parameter   integer TX_DATA_PATH_DELAY = 0,
-  parameter   integer CONTROL_PATH_DELAY = 0) (
+  parameter   integer CONTROL_PATH_DELAY = 0
+) (
 
   // clock and reset
 
@@ -89,8 +90,8 @@ module ad_tdd_control#(
   output  reg             tdd_rx_rf_en,
   output  reg             tdd_tx_rf_en,
 
-  output      [23:0]      tdd_counter_status);
-
+  output      [23:0]      tdd_counter_status
+);
 
   localparam  [ 0:0]      ON = 1;
   localparam  [ 0:0]      OFF = 0;
@@ -509,8 +510,7 @@ module ad_tdd_control#(
     .A(tdd_vco_rx_on_1),
     .Amax(tdd_frame_length),
     .out(tdd_vco_rx_on_1_s),
-    .CE(1'b1)
-  );
+    .CE(1'b1));
 
   ad_addsub #(
     .A_DATA_WIDTH(24),
@@ -521,8 +521,7 @@ module ad_tdd_control#(
     .A(tdd_vco_rx_off_1),
     .Amax(tdd_frame_length),
     .out(tdd_vco_rx_off_1_s),
-    .CE(1'b1)
-  );
+    .CE(1'b1));
 
   ad_addsub #(
     .A_DATA_WIDTH(24),
@@ -533,8 +532,7 @@ module ad_tdd_control#(
     .A(tdd_vco_tx_on_1),
     .Amax(tdd_frame_length),
     .out(tdd_vco_tx_on_1_s),
-    .CE(1'b1)
-  );
+    .CE(1'b1));
 
   ad_addsub #(
     .A_DATA_WIDTH(24),
@@ -545,8 +543,7 @@ module ad_tdd_control#(
     .A(tdd_vco_tx_off_1),
     .Amax(tdd_frame_length),
     .out(tdd_vco_tx_off_1_s),
-    .CE(1'b1)
-  );
+    .CE(1'b1));
 
   ad_addsub #(
     .A_DATA_WIDTH(24),
@@ -557,8 +554,7 @@ module ad_tdd_control#(
     .A(tdd_rx_on_1),
     .Amax(tdd_frame_length),
     .out(tdd_rx_on_1_s),
-    .CE(1'b1)
-  );
+    .CE(1'b1));
 
   ad_addsub #(
     .A_DATA_WIDTH(24),
@@ -569,8 +565,7 @@ module ad_tdd_control#(
     .A(tdd_rx_off_1),
     .Amax(tdd_frame_length),
     .out(tdd_rx_off_1_s),
-    .CE(1'b1)
-  );
+    .CE(1'b1));
 
   ad_addsub #(
     .A_DATA_WIDTH(24),
@@ -581,8 +576,7 @@ module ad_tdd_control#(
     .A(tdd_tx_on_1),
     .Amax(tdd_frame_length),
     .out(tdd_tx_on_1_s),
-    .CE(1'b1)
-  );
+    .CE(1'b1));
 
   ad_addsub #(
     .A_DATA_WIDTH(24),
@@ -593,8 +587,7 @@ module ad_tdd_control#(
     .A(tdd_tx_off_1),
     .Amax(tdd_frame_length),
     .out(tdd_tx_off_1_s),
-    .CE(1'b1)
-  );
+    .CE(1'b1));
 
   ad_addsub #(
     .A_DATA_WIDTH(24),
@@ -605,8 +598,7 @@ module ad_tdd_control#(
     .A(tdd_vco_rx_on_2),
     .Amax(tdd_frame_length),
     .out(tdd_vco_rx_on_2_s),
-    .CE(1'b1)
-  );
+    .CE(1'b1));
 
   ad_addsub #(
     .A_DATA_WIDTH(24),
@@ -617,8 +609,7 @@ module ad_tdd_control#(
     .A(tdd_vco_rx_off_2),
     .Amax(tdd_frame_length),
     .out(tdd_vco_rx_off_2_s),
-    .CE(1'b1)
-  );
+    .CE(1'b1));
 
   ad_addsub #(
     .A_DATA_WIDTH(24),
@@ -629,8 +620,7 @@ module ad_tdd_control#(
     .A(tdd_vco_tx_on_2),
     .Amax(tdd_frame_length),
     .out(tdd_vco_tx_on_2_s),
-    .CE(1'b1)
-  );
+    .CE(1'b1));
 
   ad_addsub #(
     .A_DATA_WIDTH(24),
@@ -641,8 +631,7 @@ module ad_tdd_control#(
     .A(tdd_vco_tx_off_2),
     .Amax(tdd_frame_length),
     .out(tdd_vco_tx_off_2_s),
-    .CE(1'b1)
-  );
+    .CE(1'b1));
 
   ad_addsub #(
     .A_DATA_WIDTH(24),
@@ -653,8 +642,7 @@ module ad_tdd_control#(
     .A(tdd_rx_on_2),
     .Amax(tdd_frame_length),
     .out(tdd_rx_on_2_s),
-    .CE(1'b1)
-  );
+    .CE(1'b1));
 
   ad_addsub #(
     .A_DATA_WIDTH(24),
@@ -665,8 +653,7 @@ module ad_tdd_control#(
     .A(tdd_rx_off_2),
     .Amax(tdd_frame_length),
     .out(tdd_rx_off_2_s),
-    .CE(1'b1)
-  );
+    .CE(1'b1));
 
   ad_addsub #(
     .A_DATA_WIDTH(24),
@@ -677,8 +664,7 @@ module ad_tdd_control#(
     .A(tdd_tx_on_2),
     .Amax(tdd_frame_length),
     .out(tdd_tx_on_2_s),
-    .CE(1'b1)
-  );
+    .CE(1'b1));
 
   ad_addsub #(
     .A_DATA_WIDTH(24),
@@ -689,8 +675,7 @@ module ad_tdd_control#(
     .A(tdd_tx_off_2),
     .Amax(tdd_frame_length),
     .out(tdd_tx_off_2_s),
-    .CE(1'b1)
-  );
+    .CE(1'b1));
 
   // internal data-path delay compensation
 
@@ -703,8 +688,7 @@ module ad_tdd_control#(
     .A(tdd_tx_dp_on_1),
     .Amax(tdd_frame_length),
     .out(tdd_tx_dp_on_1_s),
-    .CE(1'b1)
-  );
+    .CE(1'b1));
 
   ad_addsub #(
     .A_DATA_WIDTH(24),
@@ -715,8 +699,7 @@ module ad_tdd_control#(
     .A(tdd_tx_dp_on_2),
     .Amax(tdd_frame_length),
     .out(tdd_tx_dp_on_2_s),
-    .CE(1'b1)
-  );
+    .CE(1'b1));
 
   ad_addsub #(
     .A_DATA_WIDTH(24),
@@ -727,8 +710,7 @@ module ad_tdd_control#(
     .A(tdd_tx_dp_off_1),
     .Amax(tdd_frame_length),
     .out(tdd_tx_dp_off_1_s),
-    .CE(1'b1)
-  );
+    .CE(1'b1));
 
   ad_addsub #(
     .A_DATA_WIDTH(24),
@@ -739,8 +721,7 @@ module ad_tdd_control#(
     .A(tdd_tx_dp_off_2),
     .Amax(tdd_frame_length),
     .out(tdd_tx_dp_off_2_s),
-    .CE(1'b1)
-  );
+    .CE(1'b1));
 
   // output logic
 
@@ -831,4 +812,3 @@ module ad_tdd_control#(
   end
 
 endmodule
-
diff --git a/library/common/ad_upack.v b/library/common/ad_upack.v
index 83479d319..9d52be3a5 100644
--- a/library/common/ad_upack.v
+++ b/library/common/ad_upack.v
@@ -41,7 +41,7 @@
 //
 // Constraints:
 //   - O_W <= I_W
-//   - LATENCY 1 
+//   - LATENCY 1
 //   - no backpressure
 //
 // Data format:
@@ -73,96 +73,96 @@ module ad_upack #(
   output reg                  ovalid = 'b0
 );
 
-// Width of shift reg is integer multiple of output data width
-localparam SH_W = ((I_W/O_W)+1)*O_W;
-localparam STEP = I_W % O_W;
+  // Width of shift reg is integer multiple of output data width
+  localparam SH_W = ((I_W/O_W)+1)*O_W;
+  localparam STEP = I_W % O_W;
 
-localparam LATENCY = 1; // Minimum input latency from iready to ivalid 
+  localparam LATENCY = 1; // Minimum input latency from iready to ivalid
 
-integer i;
+  integer i;
 
-reg [SH_W*UNIT_W-1:0] idata_sh;
-reg [SH_W*UNIT_W-1:0] idata_d = 'h0;
-reg [SH_W*UNIT_W-1:0] idata_d_nx;
-reg [SH_W-1:0] in_use = 'h0;
-reg [SH_W-1:0] inmask;
+  reg [SH_W*UNIT_W-1:0] idata_sh;
+  reg [SH_W*UNIT_W-1:0] idata_d = 'h0;
+  reg [SH_W*UNIT_W-1:0] idata_d_nx;
+  reg [SH_W-1:0] in_use = 'h0;
+  reg [SH_W-1:0] inmask;
 
-wire [SH_W-1:0] out_mask = {O_W{1'b1}};
-wire [SH_W-1:0] in_use_nx;
-wire [SH_W-1:0] unit_valid;
-wire [O_W*UNIT_W-1:0] odata_s;
-wire                  ovalid_s;
+  wire [SH_W-1:0] out_mask = {O_W{1'b1}};
+  wire [SH_W-1:0] in_use_nx;
+  wire [SH_W-1:0] unit_valid;
+  wire [O_W*UNIT_W-1:0] odata_s;
+  wire                  ovalid_s;
 
-assign unit_valid = (in_use | inmask);
-assign in_use_nx = unit_valid >> O_W;
+  assign unit_valid = (in_use | inmask);
+  assign in_use_nx = unit_valid >> O_W;
 
-always @(posedge clk) begin
-  if (reset) begin
-    in_use <= 'h0;
-  end else if (ovalid_s) begin
-    in_use <= in_use_nx;
-  end
-end
-
-always @(*) begin
-  inmask = {I_W{ivalid}};
-  if (STEP>0) begin
-    for (i = STEP; i < O_W; i=i+STEP) begin
-      if (in_use[i-1]) begin
-        inmask = {I_W{ivalid}} << i;
-      end
+  always @(posedge clk) begin
+    if (reset) begin
+      in_use <= 'h0;
+    end else if (ovalid_s) begin
+      in_use <= in_use_nx;
     end
   end
-end
 
-always @(*) begin
-  idata_d_nx = idata_d;
-  if (ivalid) begin
-    idata_d_nx = {{(SH_W-I_W)*UNIT_W{1'b0}},idata};
+  always @(*) begin
+    inmask = {I_W{ivalid}};
     if (STEP>0) begin
       for (i = STEP; i < O_W; i=i+STEP) begin
         if (in_use[i-1]) begin
-          idata_d_nx = (idata << UNIT_W*i) | idata_d;
+          inmask = {I_W{ivalid}} << i;
         end
       end
     end
   end
-end
 
-always @(posedge clk) begin
-  if (ovalid_s) begin
-    idata_d <= idata_d_nx >> O_W*UNIT_W;
-  end
-end
-
-assign iready = ~unit_valid[LATENCY*O_W + O_W -1];
-
-assign odata_s = idata_d_nx[O_W*UNIT_W-1:0];
-assign ovalid_s = unit_valid[O_W-1];
-
-generate
-  if (O_REG) begin : o_reg
-
-    always @(posedge clk) begin
-      if (reset) begin
-        ovalid <= 1'b0;
-      end else begin
-        ovalid <= ovalid_s;
+  always @(*) begin
+    idata_d_nx = idata_d;
+    if (ivalid) begin
+      idata_d_nx = {{(SH_W-I_W)*UNIT_W{1'b0}},idata};
+      if (STEP>0) begin
+        for (i = STEP; i < O_W; i=i+STEP) begin
+          if (in_use[i-1]) begin
+            idata_d_nx = (idata << UNIT_W*i) | idata_d;
+          end
+        end
       end
     end
-
-    always @(posedge clk) begin
-      odata <= odata_s;
-    end
-
-  end else begin
-
-    always @(*) begin
-      odata = odata_s;
-      ovalid = ovalid_s;
-    end
-
   end
-endgenerate
+
+  always @(posedge clk) begin
+    if (ovalid_s) begin
+      idata_d <= idata_d_nx >> O_W*UNIT_W;
+    end
+  end
+
+  assign iready = ~unit_valid[LATENCY*O_W + O_W -1];
+
+  assign odata_s = idata_d_nx[O_W*UNIT_W-1:0];
+  assign ovalid_s = unit_valid[O_W-1];
+
+  generate
+    if (O_REG) begin : o_reg
+
+      always @(posedge clk) begin
+        if (reset) begin
+          ovalid <= 1'b0;
+        end else begin
+          ovalid <= ovalid_s;
+        end
+      end
+
+      always @(posedge clk) begin
+        odata <= odata_s;
+      end
+
+    end else begin
+
+      always @(*) begin
+        odata = odata_s;
+        ovalid = ovalid_s;
+      end
+
+    end
+  endgenerate
 
 endmodule
diff --git a/library/common/ad_xcvr_rx_if.v b/library/common/ad_xcvr_rx_if.v
index 7bf6c46e5..0764a1760 100644
--- a/library/common/ad_xcvr_rx_if.v
+++ b/library/common/ad_xcvr_rx_if.v
@@ -38,7 +38,7 @@
 module ad_xcvr_rx_if #(
   parameter OCTETS_PER_BEAT = 4,
   parameter DW = OCTETS_PER_BEAT * 8
-)(
+) (
 
   // jesd interface
 
@@ -46,7 +46,8 @@ module ad_xcvr_rx_if #(
   input [OCTETS_PER_BEAT-1:0] rx_ip_sof,
   input [DW-1:0] rx_ip_data,
   output reg rx_sof,
-  output reg [DW-1:0] rx_data);
+  output reg [DW-1:0] rx_data
+);
 
   // rx_ip_sof:
   // The input beat may contain more than one frame per clock, a sof bit is set for
@@ -97,6 +98,3 @@ module ad_xcvr_rx_if #(
   end
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/common/tb/ad_mux_tb.v b/library/common/tb/ad_mux_tb.v
index c037fca6e..126c11d36 100644
--- a/library/common/tb/ad_mux_tb.v
+++ b/library/common/tb/ad_mux_tb.v
@@ -27,8 +27,7 @@ module ad_mux_tb;
     .clk(clk),
     .data_in(data_in),
     .ch_sel(ch_sel),
-    .data_out(data_out)
-  );
+    .data_out(data_out));
 
   wire [CH_W-1:0] ref_data;
   generate
diff --git a/library/common/tb/ad_pack_tb.v b/library/common/tb/ad_pack_tb.v
index a84b419c8..32e4be084 100644
--- a/library/common/tb/ad_pack_tb.v
+++ b/library/common/tb/ad_pack_tb.v
@@ -29,8 +29,7 @@ module ad_pack_tb;
     .idata(idata),
     .ivalid(ivalid),
     .odata(odata),
-    .ovalid(ovalid)
-  );
+    .ovalid(ovalid));
 
   task test();
   begin
diff --git a/library/common/tb/ad_upack_tb.v b/library/common/tb/ad_upack_tb.v
index 420a484c9..0acf61e65 100644
--- a/library/common/tb/ad_upack_tb.v
+++ b/library/common/tb/ad_upack_tb.v
@@ -30,8 +30,7 @@ module ad_upack_tb;
     .iready(iready),
     .ivalid(ivalid),
     .odata(odata),
-    .ovalid(ovalid)
-  );
+    .ovalid(ovalid));
 
   task test(input no_random);
   begin
diff --git a/library/common/tb/tb_base.v b/library/common/tb/tb_base.v
index b3908d1e4..a40b88915 100644
--- a/library/common/tb/tb_base.v
+++ b/library/common/tb/tb_base.v
@@ -76,8 +76,6 @@
 
   assign reset = reset_shift[3];
 
-
-
   task do_trigger_reset;
   begin
     @(posedge clk) trigger_reset <= 1'b1;
diff --git a/library/common/up_adc_channel.v b/library/common/up_adc_channel.v
index f81d9bf15..847097332 100644
--- a/library/common/up_adc_channel.v
+++ b/library/common/up_adc_channel.v
@@ -44,7 +44,8 @@ module up_adc_channel #(
   parameter   USERPORTS_DISABLE = 0,
   parameter   DATAFORMAT_DISABLE = 0,
   parameter   DCFILTER_DISABLE = 0,
-  parameter   IQCORRECTION_DISABLE = 0) (
+  parameter   IQCORRECTION_DISABLE = 0
+) (
 
   // adc interface
 
@@ -97,7 +98,8 @@ module up_adc_channel #(
   input           up_rreq,
   input   [13:0]  up_raddr,
   output  [31:0]  up_rdata,
-  output          up_rack);
+  output          up_rack
+);
 
   // internal registers
 
@@ -442,7 +444,9 @@ module up_adc_channel #(
 
   // adc control & status
 
-  up_xfer_cntrl #(.DATA_WIDTH(78)) i_xfer_cntrl (
+  up_xfer_cntrl #(
+    .DATA_WIDTH(78)
+  ) i_xfer_cntrl (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_data_cntrl ({ up_adc_iqcor_enb,
@@ -473,7 +477,9 @@ module up_adc_channel #(
                       adc_pnseq_sel,
                       adc_data_sel}));
 
-  up_xfer_status #(.DATA_WIDTH(3)) i_xfer_status (
+  up_xfer_status #(
+    .DATA_WIDTH(3)
+  ) i_xfer_status (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_data_status ({up_adc_pn_err_s,
@@ -486,6 +492,3 @@ module up_adc_channel #(
                       adc_or}));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/common/up_adc_common.v b/library/common/up_adc_common.v
index dfdb2510b..c7e278537 100644
--- a/library/common/up_adc_common.v
+++ b/library/common/up_adc_common.v
@@ -49,7 +49,8 @@ module up_adc_common #(
   parameter         DRP_DISABLE = 0,
   parameter         USERPORTS_DISABLE = 0,
   parameter         GPIO_DISABLE = 0,
-  parameter         START_CODE_DISABLE = 0) (
+  parameter         START_CODE_DISABLE = 0
+) (
 
   // clock reset
 
@@ -117,7 +118,8 @@ module up_adc_common #(
   input               up_rreq,
   input       [13:0]  up_raddr,
   output      [31:0]  up_rdata,
-  output              up_rack);
+  output              up_rack
+);
 
   // parameters
 
@@ -151,7 +153,7 @@ module up_adc_common #(
   reg         [31:0]  up_timer = 'd0;
   reg                 up_rack_int = 'd0;
   reg         [31:0]  up_rdata_int = 'd0;
-  reg         [ 7:0]  up_adc_custom_control = 'd0;  
+  reg         [ 7:0]  up_adc_custom_control = 'd0;
 
   // internal signals
 
@@ -442,7 +444,7 @@ module up_adc_common #(
                                   3'b0, up_adc_ext_sync_manual_req,
                                   4'b0,
                                   1'b0, up_adc_ext_sync_disarm, up_adc_ext_sync_arm, 1'b0};
-          7'h13: up_rdata_int <= {24'd0, up_adc_custom_control};                        
+          7'h13: up_rdata_int <= {24'd0, up_adc_custom_control};
           7'h15: up_rdata_int <= up_adc_clk_count_s;
           7'h16: up_rdata_int <= adc_clk_ratio;
           7'h17: up_rdata_int <= {28'd0, up_status_pn_err, up_status_pn_oos, up_status_or, up_status_s};
@@ -470,13 +472,22 @@ module up_adc_common #(
 
   // resets
 
-  ad_rst i_mmcm_rst_reg (.rst_async(up_mmcm_preset), .clk(up_clk),  .rstn(), .rst(mmcm_rst));
-  ad_rst i_core_rst_reg (.rst_async(up_core_preset), .clk(adc_clk), .rstn(), .rst(adc_rst_s));
+  ad_rst i_mmcm_rst_reg (
+    .rst_async(up_mmcm_preset),
+    .clk(up_clk),
+    .rstn(),
+    .rst(mmcm_rst));
+
+  ad_rst i_core_rst_reg (
+    .rst_async(up_core_preset),
+    .clk(adc_clk),
+    .rstn(),
+    .rst(adc_rst_s));
 
   // adc control & status
 
   up_xfer_cntrl #(
-    .DATA_WIDTH(57) 
+    .DATA_WIDTH(57)
   ) i_xfer_cntrl (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
@@ -544,6 +555,3 @@ module up_adc_common #(
     .d_clk (adc_clk));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/common/up_axi.v b/library/common/up_axi.v
index 40acb17bd..118fb80c2 100644
--- a/library/common/up_axi.v
+++ b/library/common/up_axi.v
@@ -37,7 +37,8 @@
 
 module up_axi #(
 
-  parameter   AXI_ADDRESS_WIDTH = 16) (
+  parameter   AXI_ADDRESS_WIDTH = 16
+) (
 
   // reset and clocks
 
@@ -73,7 +74,8 @@ module up_axi #(
   output                            up_rreq,
   output  [(AXI_ADDRESS_WIDTH-3):0] up_raddr,
   input   [31:0]                    up_rdata,
-  input                             up_rack);
+  input                             up_rack
+);
 
   // internal registers
 
@@ -234,6 +236,3 @@ module up_axi #(
   end
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/common/up_clkgen.v b/library/common/up_clkgen.v
index 26d989e16..30548dc20 100644
--- a/library/common/up_clkgen.v
+++ b/library/common/up_clkgen.v
@@ -42,7 +42,8 @@ module up_clkgen #(
   parameter [ 7:0]  FPGA_FAMILY = 0,
   parameter [ 7:0]  SPEED_GRADE = 0,
   parameter [ 7:0]  DEV_PACKAGE = 0,
-  parameter [15:0]  FPGA_VOLTAGE = 0) (
+  parameter [15:0]  FPGA_VOLTAGE = 0
+) (
 
   // mmcm reset
 
@@ -73,7 +74,8 @@ module up_clkgen #(
   input                   up_rreq,
   input       [13:0]      up_raddr,
   output  reg [31:0]      up_rdata,
-  output  reg             up_rack);
+  output  reg             up_rack
+);
 
   localparam  PCORE_VERSION = 32'h00050063;
 
@@ -183,9 +185,10 @@ module up_clkgen #(
 
   // resets
 
-  ad_rst i_mmcm_rst_reg (.rst_async(up_mmcm_preset), .clk(up_clk), .rstn(), .rst(mmcm_rst));
+  ad_rst i_mmcm_rst_reg (
+    .rst_async(up_mmcm_preset),
+    .clk(up_clk),
+    .rstn(),
+    .rst(mmcm_rst));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/common/up_clock_mon.v b/library/common/up_clock_mon.v
index 01a8258c6..272c4e719 100644
--- a/library/common/up_clock_mon.v
+++ b/library/common/up_clock_mon.v
@@ -48,7 +48,8 @@ module up_clock_mon #(
   // device interface
 
   input                              d_rst,
-  input                              d_clk);
+  input                              d_clk
+);
 
   // internal registers
 
@@ -141,6 +142,3 @@ module up_clock_mon #(
   end
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/common/up_dac_channel.v b/library/common/up_dac_channel.v
index 89f41f979..269e8a080 100644
--- a/library/common/up_dac_channel.v
+++ b/library/common/up_dac_channel.v
@@ -96,7 +96,8 @@ module up_dac_channel #(
   input           up_rreq,
   input   [13:0]  up_raddr,
   output  [31:0]  up_rdata,
-  output          up_rack);
+  output          up_rack
+);
 
   // internal registers
 
@@ -402,7 +403,9 @@ module up_dac_channel #(
 
   // dac control & status
 
-  up_xfer_cntrl #(.DATA_WIDTH(177)) i_xfer_cntrl (
+  up_xfer_cntrl #(
+    .DATA_WIDTH(177)
+  ) i_xfer_cntrl (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_data_cntrl ({ up_dac_iq_mode,
@@ -440,6 +443,3 @@ module up_dac_channel #(
                       dac_src_chan_sel}));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/common/up_dac_common.v b/library/common/up_dac_common.v
index ebff7a505..de18ea57f 100644
--- a/library/common/up_dac_common.v
+++ b/library/common/up_dac_common.v
@@ -49,7 +49,8 @@ module up_dac_common #(
   parameter         COMMON_ID = 6'h10,
   parameter         DRP_DISABLE = 0,
   parameter         USERPORTS_DISABLE = 0,
-  parameter         GPIO_DISABLE = 0) (
+  parameter         GPIO_DISABLE = 0
+) (
 
   // mmcm reset
 
@@ -112,7 +113,8 @@ module up_dac_common #(
   input               up_rreq,
   input       [13:0]  up_raddr,
   output      [31:0]  up_rdata,
-  output              up_rack);
+  output              up_rack
+);
 
   // parameters
 
@@ -470,12 +472,23 @@ module up_dac_common #(
 
   // resets
 
-  ad_rst i_mmcm_rst_reg (.rst_async(up_mmcm_preset), .clk(up_clk),  .rstn(), .rst(mmcm_rst));
-  ad_rst i_core_rst_reg (.rst_async(up_core_preset), .clk(dac_clk), .rstn(), .rst(dac_rst_s));
+  ad_rst i_mmcm_rst_reg (
+    .rst_async(up_mmcm_preset),
+    .clk(up_clk),
+    .rstn(),
+    .rst(mmcm_rst));
+
+  ad_rst i_core_rst_reg (
+    .rst_async(up_core_preset),
+    .clk(dac_clk),
+    .rstn(),
+    .rst(dac_rst_s));
 
   // dac control & status
 
-  up_xfer_cntrl #(.DATA_WIDTH(35)) i_xfer_cntrl (
+  up_xfer_cntrl #(
+    .DATA_WIDTH(35)
+  ) i_xfer_cntrl (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_data_cntrl ({ up_dac_sdr_ddr_n,
@@ -519,7 +532,9 @@ module up_dac_common #(
   // This is important at start-up when stable set of controls is required.
   assign dac_rst = ~dac_rst_n;
 
-  up_xfer_status #(.DATA_WIDTH(3)) i_xfer_status (
+  up_xfer_status #(
+    .DATA_WIDTH(3)
+  ) i_xfer_status (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_data_status ({up_sync_in_status,
@@ -560,6 +575,3 @@ module up_dac_common #(
     .d_clk (dac_clk));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/common/up_delay_cntrl.v b/library/common/up_delay_cntrl.v
index fa17aedea..9c3af4466 100644
--- a/library/common/up_delay_cntrl.v
+++ b/library/common/up_delay_cntrl.v
@@ -43,7 +43,8 @@ module up_delay_cntrl #(
   parameter   INIT_DELAY = 0,
   parameter   DATA_WIDTH = 8,
   parameter   DRP_WIDTH = 5,
-  parameter   BASE_ADDRESS = 6'h02) (
+  parameter   BASE_ADDRESS = 6'h02
+) (
 
   // delay interface
 
@@ -68,7 +69,8 @@ module up_delay_cntrl #(
   input                           up_rreq,
   input   [13:0]                  up_raddr,
   output  [31:0]                  up_rdata,
-  output                          up_rack);
+  output                          up_rack
+);
 
   generate
   if (DISABLE == 1) begin
@@ -203,6 +205,3 @@ module up_delay_cntrl #(
   endgenerate
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/common/up_hdmi_rx.v b/library/common/up_hdmi_rx.v
index 68955588d..fc714e49b 100644
--- a/library/common/up_hdmi_rx.v
+++ b/library/common/up_hdmi_rx.v
@@ -37,7 +37,8 @@
 
 module up_hdmi_rx #(
 
-  parameter   ID = 0) (
+  parameter   ID = 0
+) (
 
   // hdmi interface
 
@@ -71,7 +72,8 @@ module up_hdmi_rx #(
   input                   up_rreq,
   input       [13:0]      up_raddr,
   output  reg [31:0]      up_rdata,
-  output  reg             up_rack);
+  output  reg             up_rack
+);
 
   localparam  PCORE_VERSION = 32'h00040063;
 
@@ -230,7 +232,9 @@ module up_hdmi_rx #(
 
   // hdmi control & status
 
-  up_xfer_cntrl #(.DATA_WIDTH(36)) i_hdmi_xfer_cntrl (
+  up_xfer_cntrl #(
+    .DATA_WIDTH(36)
+  ) i_hdmi_xfer_cntrl (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_data_cntrl ({ up_edge_sel,
@@ -249,7 +253,9 @@ module up_hdmi_rx #(
                       hdmi_vs_count,
                       hdmi_hs_count}));
 
-  up_xfer_status #(.DATA_WIDTH(39)) i_hdmi_xfer_status (
+  up_xfer_status #(
+    .DATA_WIDTH(39)
+  ) i_hdmi_xfer_status (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_data_status ({  up_dma_ovf_s,
@@ -281,6 +287,3 @@ module up_hdmi_rx #(
     .d_clk (hdmi_clk));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/common/up_hdmi_tx.v b/library/common/up_hdmi_tx.v
index 964e2b8e9..09d1b28d1 100644
--- a/library/common/up_hdmi_tx.v
+++ b/library/common/up_hdmi_tx.v
@@ -37,7 +37,8 @@
 
 module up_hdmi_tx #(
 
-  parameter   ID = 0) (
+  parameter   ID = 0
+) (
 
   // hdmi interface
 
@@ -82,7 +83,8 @@ module up_hdmi_tx #(
   input                   up_rreq,
   input       [13:0]      up_raddr,
   output  reg [31:0]      up_rdata,
-  output  reg             up_rack);
+  output  reg             up_rack
+);
 
   localparam  PCORE_VERSION = 32'h00040063;
 
@@ -267,12 +269,23 @@ module up_hdmi_tx #(
 
   // resets
 
-  ad_rst i_core_rst_reg (.rst_async(up_core_preset), .clk(hdmi_clk), .rstn(), .rst(hdmi_rst));
-  ad_rst i_vdma_rst_reg (.rst_async(up_core_preset), .clk(vdma_clk), .rstn(), .rst(vdma_rst));
+  ad_rst i_core_rst_reg (
+    .rst_async(up_core_preset),
+    .clk(hdmi_clk),
+    .rstn(),
+    .rst(hdmi_rst));
+
+  ad_rst i_vdma_rst_reg (
+    .rst_async(up_core_preset),
+    .clk(vdma_clk),
+    .rstn(),
+    .rst(vdma_rst));
 
   // hdmi control & status
 
-  up_xfer_cntrl #(.DATA_WIDTH(236)) i_xfer_cntrl (
+  up_xfer_cntrl #(
+    .DATA_WIDTH(236)
+  ) i_xfer_cntrl (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_data_cntrl ({ up_ss_bypass,
@@ -311,7 +324,9 @@ module up_hdmi_tx #(
                       hdmi_clip_max,
                       hdmi_clip_min}));
 
-  up_xfer_status #(.DATA_WIDTH(2)) i_xfer_status (
+  up_xfer_status #(
+    .DATA_WIDTH(2)
+  ) i_xfer_status (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_data_status ({up_hdmi_status_s,
@@ -332,7 +347,9 @@ module up_hdmi_tx #(
 
   // vdma control & status
 
-  up_xfer_status #(.DATA_WIDTH(3)) i_vdma_xfer_status (
+  up_xfer_status #(
+    .DATA_WIDTH(3)
+  ) i_vdma_xfer_status (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_data_status ({up_vdma_ovf_s,
@@ -345,6 +362,3 @@ module up_hdmi_tx #(
                       vdma_tpm_oos}));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/common/up_pmod.v b/library/common/up_pmod.v
index defe31cbf..7a8e6565c 100644
--- a/library/common/up_pmod.v
+++ b/library/common/up_pmod.v
@@ -37,8 +37,8 @@
 
 module up_pmod #(
 
-  parameter       ID = 0) (
-
+  parameter       ID = 0
+) (
   input                   pmod_clk,
   output                  pmod_rst,
   input       [31:0]      pmod_signal_freq,
@@ -54,7 +54,8 @@ module up_pmod #(
   input                   up_rreq,
   input       [13:0]      up_raddr,
   output  reg [31:0]      up_rdata,
-  output  reg             up_rack);
+  output  reg             up_rack
+);
 
   localparam      PCORE_VERSION = 32'h00010001;
 
@@ -118,11 +119,17 @@ module up_pmod #(
 
   // resets
 
-  ad_rst i_adc_rst_reg (.rst_async(up_preset_s), .clk(pmod_clk), .rstn(), .rst(pmod_rst));
+  ad_rst i_adc_rst_reg (
+    .rst_async(up_preset_s),
+    .clk(pmod_clk),
+    .rstn(),
+    .rst(pmod_rst));
 
   // adc control & status
 
-  up_xfer_status #(.DATA_WIDTH(32)) i_pmod_xfer_status (
+  up_xfer_status #(
+    .DATA_WIDTH(32)
+  ) i_pmod_xfer_status (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_data_status (up_pmod_signal_freq_s),
@@ -131,6 +138,3 @@ module up_pmod #(
     .d_data_status (pmod_signal_freq));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/common/up_tdd_cntrl.v b/library/common/up_tdd_cntrl.v
index deb64ca48..d44e6b89a 100644
--- a/library/common/up_tdd_cntrl.v
+++ b/library/common/up_tdd_cntrl.v
@@ -39,7 +39,6 @@ module up_tdd_cntrl #(
   parameter   ID = 0,
   parameter   BASE_ADDRESS = 6'h20
 ) (
-
   input                   clk,
   input                   rst,
 
@@ -93,7 +92,8 @@ module up_tdd_cntrl #(
   input                   up_rreq,
   input       [13:0]      up_raddr,
   output  reg [31:0]      up_rdata,
-  output  reg             up_rack);
+  output  reg             up_rack
+);
 
   localparam  PCORE_VERSION = 32'h00010061;
   localparam  PCORE_MAGIC = 32'h54444443; // "TDDC", big endian
@@ -350,7 +350,9 @@ module up_tdd_cntrl #(
 
   // rf tdd control signal CDC
 
-  up_xfer_cntrl #(.DATA_WIDTH(63)) i_xfer_tdd_control (
+  up_xfer_cntrl #(
+    .DATA_WIDTH(63)
+  ) i_xfer_tdd_control (
     .up_rstn(up_rstn),
     .up_clk(up_clk),
     .up_data_cntrl({up_tdd_counter_init,
@@ -362,8 +364,7 @@ module up_tdd_cntrl #(
                     up_tdd_gated_rx_dmapath,
                     up_tdd_gated_tx_dmapath,
                     up_tdd_burst_count,
-                    up_tdd_terminal_type
-                  }),
+                    up_tdd_terminal_type}),
     .up_xfer_done(),
     .d_rst(rst),
     .d_clk(clk),
@@ -376,10 +377,11 @@ module up_tdd_cntrl #(
                    tdd_gated_rx_dmapath,
                    tdd_gated_tx_dmapath,
                    tdd_burst_count,
-                   tdd_terminal_type
-    }));
+                   tdd_terminal_type}));
 
-  up_xfer_cntrl #(.DATA_WIDTH(144)) i_xfer_tdd_counter_values_rx_1 (
+  up_xfer_cntrl #(
+    .DATA_WIDTH(144)
+  ) i_xfer_tdd_counter_values_rx_1 (
     .up_rstn(up_rstn),
     .up_clk(up_clk),
     .up_data_cntrl({
@@ -388,8 +390,7 @@ module up_tdd_cntrl #(
                     up_tdd_rx_on_1,
                     up_tdd_rx_off_1,
                     up_tdd_rx_dp_on_1,
-                    up_tdd_rx_dp_off_1
-    }),
+                    up_tdd_rx_dp_off_1}),
     .up_xfer_done(),
     .d_rst(rst),
     .d_clk(clk),
@@ -399,10 +400,11 @@ module up_tdd_cntrl #(
                    tdd_rx_on_1,
                    tdd_rx_off_1,
                    tdd_rx_dp_on_1,
-                   tdd_rx_dp_off_1
-    }));
+                   tdd_rx_dp_off_1}));
 
-  up_xfer_cntrl #(.DATA_WIDTH(144)) i_xfer_tdd_counter_values_tx_1 (
+  up_xfer_cntrl #(
+    .DATA_WIDTH(144)
+  ) i_xfer_tdd_counter_values_tx_1 (
     .up_rstn(up_rstn),
     .up_clk(up_clk),
     .up_data_cntrl({
@@ -411,8 +413,7 @@ module up_tdd_cntrl #(
                     up_tdd_tx_on_1,
                     up_tdd_tx_off_1,
                     up_tdd_tx_dp_on_1,
-                    up_tdd_tx_dp_off_1
-    }),
+                    up_tdd_tx_dp_off_1}),
     .up_xfer_done(),
     .d_rst(rst),
     .d_clk(clk),
@@ -422,10 +423,11 @@ module up_tdd_cntrl #(
                    tdd_tx_on_1,
                    tdd_tx_off_1,
                    tdd_tx_dp_on_1,
-                   tdd_tx_dp_off_1
-    }));
+                   tdd_tx_dp_off_1}));
 
-  up_xfer_cntrl #(.DATA_WIDTH(144)) i_xfer_tdd_counter_values_rx_2 (
+  up_xfer_cntrl #(
+    .DATA_WIDTH(144)
+  ) i_xfer_tdd_counter_values_rx_2 (
     .up_rstn(up_rstn),
     .up_clk(up_clk),
     .up_data_cntrl({
@@ -434,8 +436,7 @@ module up_tdd_cntrl #(
                     up_tdd_rx_on_2,
                     up_tdd_rx_off_2,
                     up_tdd_rx_dp_on_2,
-                    up_tdd_rx_dp_off_2
-    }),
+                    up_tdd_rx_dp_off_2}),
     .up_xfer_done(),
     .d_rst(rst),
     .d_clk(clk),
@@ -445,10 +446,11 @@ module up_tdd_cntrl #(
                    tdd_rx_on_2,
                    tdd_rx_off_2,
                    tdd_rx_dp_on_2,
-                   tdd_rx_dp_off_2
-    }));
+                   tdd_rx_dp_off_2}));
 
-  up_xfer_cntrl #(.DATA_WIDTH(144)) i_xfer_tdd_counter_values_tx_2 (
+  up_xfer_cntrl #(
+    .DATA_WIDTH(144)
+  ) i_xfer_tdd_counter_values_tx_2 (
     .up_rstn(up_rstn),
     .up_clk(up_clk),
     .up_data_cntrl({
@@ -457,8 +459,7 @@ module up_tdd_cntrl #(
                     up_tdd_tx_on_2,
                     up_tdd_tx_off_2,
                     up_tdd_tx_dp_on_2,
-                    up_tdd_tx_dp_off_2
-    }),
+                    up_tdd_tx_dp_off_2}),
     .up_xfer_done(),
     .d_rst(rst),
     .d_clk(clk),
@@ -468,10 +469,11 @@ module up_tdd_cntrl #(
                    tdd_tx_on_2,
                    tdd_tx_off_2,
                    tdd_tx_dp_on_2,
-                   tdd_tx_dp_off_2
-    }));
+                   tdd_tx_dp_off_2}));
 
-  up_xfer_status #(.DATA_WIDTH(8)) i_xfer_tdd_status (
+  up_xfer_status #(
+    .DATA_WIDTH(8)
+  ) i_xfer_tdd_status (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_data_status (up_tdd_status_s),
@@ -480,6 +482,3 @@ module up_tdd_cntrl #(
     .d_data_status (tdd_status));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/common/up_xfer_cntrl.v b/library/common/up_xfer_cntrl.v
index 38db9d3eb..f38e9b048 100644
--- a/library/common/up_xfer_cntrl.v
+++ b/library/common/up_xfer_cntrl.v
@@ -37,7 +37,8 @@
 
 module up_xfer_cntrl #(
 
-  parameter     DATA_WIDTH = 8) (
+  parameter     DATA_WIDTH = 8
+) (
 
   // up interface
 
@@ -50,7 +51,8 @@ module up_xfer_cntrl #(
 
   input                       d_rst,
   input                       d_clk,
-  output  [(DATA_WIDTH-1):0]  d_data_cntrl);
+  output  [(DATA_WIDTH-1):0]  d_data_cntrl
+);
 
   // internal registers
 
@@ -121,6 +123,3 @@ module up_xfer_cntrl #(
   end
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/common/up_xfer_status.v b/library/common/up_xfer_status.v
index 59c5f9f2d..3b0bafe3d 100644
--- a/library/common/up_xfer_status.v
+++ b/library/common/up_xfer_status.v
@@ -37,7 +37,8 @@
 
 module up_xfer_status #(
 
-  parameter     DATA_WIDTH = 8) (
+  parameter     DATA_WIDTH = 8
+) (
 
   // up interface
 
@@ -49,7 +50,8 @@ module up_xfer_status #(
 
   input                       d_rst,
   input                       d_clk,
-  input   [(DATA_WIDTH-1):0]  d_data_status);
+  input   [(DATA_WIDTH-1):0]  d_data_status
+);
 
   // internal registers
 
@@ -123,6 +125,3 @@ module up_xfer_status #(
   end
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/common/util_axis_upscale.v b/library/common/util_axis_upscale.v
index d4a00db42..1822b4120 100644
--- a/library/common/util_axis_upscale.v
+++ b/library/common/util_axis_upscale.v
@@ -40,12 +40,12 @@
 
 `timescale 1ns/100ps
 
-module util_axis_upscale # (
+module util_axis_upscale #(
 
   parameter NUM_OF_CHANNELS = 4,
   parameter DATA_WIDTH = 24,
-  parameter UDATA_WIDTH = 32)(
-
+  parameter UDATA_WIDTH = 32
+) (
   input                                           clk,
   input                                           resetn,
 
@@ -59,7 +59,8 @@ module util_axis_upscale # (
 
   input                                           dfmt_enable,
   input                                           dfmt_type,
-  input                                           dfmt_se);
+  input                                           dfmt_se
+);
 
   wire                                        type_s;
   wire                                        signext_s;
@@ -72,16 +73,14 @@ module util_axis_upscale # (
 
   genvar i;
   generate
-  for (i=1; i <= NUM_OF_CHANNELS; i=i+1) begin : signext_data
+    for (i=1; i <= NUM_OF_CHANNELS; i=i+1) begin : signext_data
+      wire sign_s;
 
-    wire sign_s;
-
-    assign sign_s = signext_s & (type_s ^ s_axis_data[(i*DATA_WIDTH-1)]);
-    assign data_out_s[(i*UDATA_WIDTH-1):(i*UDATA_WIDTH-MSB_WIDTH)] = {(MSB_WIDTH){sign_s}};
-    assign data_out_s[((i-1)*UDATA_WIDTH+DATA_WIDTH-1)] = type_s ^ s_axis_data[(i*DATA_WIDTH-1)];
-    assign data_out_s[((i-1)*UDATA_WIDTH+DATA_WIDTH-2):((i-1)*UDATA_WIDTH)] = s_axis_data[(i*DATA_WIDTH-2):((i-1)*DATA_WIDTH)];
-
-  end
+      assign sign_s = signext_s & (type_s ^ s_axis_data[(i*DATA_WIDTH-1)]);
+      assign data_out_s[(i*UDATA_WIDTH-1):(i*UDATA_WIDTH-MSB_WIDTH)] = {(MSB_WIDTH){sign_s}};
+      assign data_out_s[((i-1)*UDATA_WIDTH+DATA_WIDTH-1)] = type_s ^ s_axis_data[(i*DATA_WIDTH-1)];
+      assign data_out_s[((i-1)*UDATA_WIDTH+DATA_WIDTH-2):((i-1)*UDATA_WIDTH)] = s_axis_data[(i*DATA_WIDTH-2):((i-1)*DATA_WIDTH)];
+    end
   endgenerate
 
   always @(posedge clk) begin
diff --git a/library/common/util_dec256sinc24b.v b/library/common/util_dec256sinc24b.v
index 38d6e94b3..c7f63b894 100644
--- a/library/common/util_dec256sinc24b.v
+++ b/library/common/util_dec256sinc24b.v
@@ -42,7 +42,8 @@ module util_dec256sinc24b (
   input               data_in,      /* input data to be filtered */
   output reg [15:0]   data_out,     /* filtered output */
   output reg          data_en,
-  input      [15:0]   dec_rate);
+  input      [15:0]   dec_rate
+);
 
   /* Data is read on positive clk edge */
 
diff --git a/library/common/util_delay.v b/library/common/util_delay.v
index c7a298a0f..b19395948 100644
--- a/library/common/util_delay.v
+++ b/library/common/util_delay.v
@@ -39,12 +39,13 @@ module util_delay #(
 
   parameter DATA_WIDTH = 1,
   // the minimum valid value for DELAY_CYCLES is 1
-  parameter DELAY_CYCLES = 1) (
-
+  parameter DELAY_CYCLES = 1
+) (
   input                             clk,
   input                             reset,
   input                             din,
-  output  [DATA_WIDTH-1:0]          dout);
+  output  [DATA_WIDTH-1:0]          dout
+);
 
   reg     [DATA_WIDTH-1:0]          dbuf[0:(DELAY_CYCLES-1)];
 
diff --git a/library/common/util_ext_sync.v b/library/common/util_ext_sync.v
index e68736872..6a3002fb9 100644
--- a/library/common/util_ext_sync.v
+++ b/library/common/util_ext_sync.v
@@ -34,7 +34,6 @@ module util_ext_sync #(
   input sync_in,
 
   output reg sync_armed = 1'b0
-
 );
 
   reg sync_in_d1 = 1'b0;
@@ -62,4 +61,3 @@ module util_ext_sync #(
   end
 
 endmodule
-
diff --git a/library/common/util_pulse_gen.v b/library/common/util_pulse_gen.v
index 89f5cc12c..be1209fd9 100644
--- a/library/common/util_pulse_gen.v
+++ b/library/common/util_pulse_gen.v
@@ -37,8 +37,8 @@
 module util_pulse_gen #(
 
   parameter   PULSE_WIDTH = 7,
-  parameter   PULSE_PERIOD = 100000000)(         // t_period * clk_freq
-
+  parameter   PULSE_PERIOD = 100000000         // t_period * clk_freq
+) (
   input               clk,
   input               rstn,
 
diff --git a/library/cordic_demod/cordic_demod.v b/library/cordic_demod/cordic_demod.v
index 71925aeb8..029c5a692 100644
--- a/library/cordic_demod/cordic_demod.v
+++ b/library/cordic_demod/cordic_demod.v
@@ -48,158 +48,158 @@ module cordic_demod (
   output [63:0] m_axis_data
 );
 
-reg [4:0] step_counter;
-reg [4:0] shift_counter;
-reg [30:0] phase;
-reg [2:0] state;
+  reg [4:0] step_counter;
+  reg [4:0] shift_counter;
+  reg [30:0] phase;
+  reg [2:0] state;
 
-reg [32:0] i;
-reg [32:0] q;
-reg [32:0] i_shift;
-reg [32:0] q_shift;
+  reg [32:0] i;
+  reg [32:0] q;
+  reg [32:0] i_shift;
+  reg [32:0] q_shift;
 
-assign s_axis_ready = state == STATE_IDLE;
-assign m_axis_data = {q[32:1],i[32:1]};
-assign m_axis_valid = state == STATE_DONE;
+  assign s_axis_ready = state == STATE_IDLE;
+  assign m_axis_data = {q[32:1],i[32:1]};
+  assign m_axis_valid = state == STATE_DONE;
 
-localparam STATE_IDLE = 0;
-localparam STATE_SHIFT_LOAD = 1;
-localparam STATE_SHIFT = 2;
-localparam STATE_ADD = 3;
-localparam STATE_DONE = 4;
+  localparam STATE_IDLE = 0;
+  localparam STATE_SHIFT_LOAD = 1;
+  localparam STATE_SHIFT = 2;
+  localparam STATE_ADD = 3;
+  localparam STATE_DONE = 4;
 
-reg [31:0] angle[0:30];
+  reg [31:0] angle[0:30];
 
-initial begin
-  angle[0] = 32'h20000000;
-  angle[1] = 32'h12e4051e;
-  angle[2] = 32'h09fb385b;
-  angle[3] = 32'h051111d4;
-  angle[4] = 32'h028b0d43;
-  angle[5] = 32'h0145d7e1;
-  angle[6] = 32'h00a2f61e;
-  angle[7] = 32'h00517c55;
-  angle[8] = 32'h0028be53;
-  angle[9] = 32'h00145f2f;
-  angle[10] = 32'h000a2f98;
-  angle[11] = 32'h000517cc;
-  angle[12] = 32'h00028be6;
-  angle[13] = 32'h000145f3;
-  angle[14] = 32'h0000a2fa;
-  angle[15] = 32'h0000517d;
-  angle[16] = 32'h000028be;
-  angle[17] = 32'h0000145f;
-  angle[18] = 32'h00000a30;
-  angle[19] = 32'h00000518;
-  angle[20] = 32'h0000028c;
-  angle[21] = 32'h00000146;
-  angle[22] = 32'h000000a3;
-  angle[23] = 32'h00000051;
-  angle[24] = 32'h00000029;
-  angle[25] = 32'h00000014;
-  angle[26] = 32'h0000000a;
-  angle[27] = 32'h00000005;
-  angle[28] = 32'h00000003;
-  angle[29] = 32'h00000001;
-  angle[30] = 32'h00000001;
-end
-
-always @(posedge clk) begin
-  if (resetn == 1'b0) begin
-    state <= STATE_IDLE;
-  end else begin
-    case (state)
-    STATE_IDLE: begin
-      if (s_axis_valid == 1'b1) begin
-        state <= STATE_SHIFT_LOAD;
-      end
-    end
-    STATE_SHIFT_LOAD: begin
-      if (step_counter == 'h00) begin
-        state <= STATE_ADD;
-      end else begin
-        state <= STATE_SHIFT;
-      end
-    end
-    STATE_SHIFT: begin
-      if (shift_counter == 'h01) begin
-        state <= STATE_ADD;
-      end
-    end
-    STATE_ADD: begin
-      if (step_counter == 'd30) begin
-        state <= STATE_DONE;
-      end else begin
-        state <= STATE_SHIFT_LOAD;
-      end
-    end
-    STATE_DONE: begin
-      if (m_axis_ready == 1'b1)
-        state <= STATE_IDLE;
-    end
-    endcase
+  initial begin
+    angle[0] = 32'h20000000;
+    angle[1] = 32'h12e4051e;
+    angle[2] = 32'h09fb385b;
+    angle[3] = 32'h051111d4;
+    angle[4] = 32'h028b0d43;
+    angle[5] = 32'h0145d7e1;
+    angle[6] = 32'h00a2f61e;
+    angle[7] = 32'h00517c55;
+    angle[8] = 32'h0028be53;
+    angle[9] = 32'h00145f2f;
+    angle[10] = 32'h000a2f98;
+    angle[11] = 32'h000517cc;
+    angle[12] = 32'h00028be6;
+    angle[13] = 32'h000145f3;
+    angle[14] = 32'h0000a2fa;
+    angle[15] = 32'h0000517d;
+    angle[16] = 32'h000028be;
+    angle[17] = 32'h0000145f;
+    angle[18] = 32'h00000a30;
+    angle[19] = 32'h00000518;
+    angle[20] = 32'h0000028c;
+    angle[21] = 32'h00000146;
+    angle[22] = 32'h000000a3;
+    angle[23] = 32'h00000051;
+    angle[24] = 32'h00000029;
+    angle[25] = 32'h00000014;
+    angle[26] = 32'h0000000a;
+    angle[27] = 32'h00000005;
+    angle[28] = 32'h00000003;
+    angle[29] = 32'h00000001;
+    angle[30] = 32'h00000001;
   end
-end
 
-always @(posedge clk) begin
-  case(state)
-  STATE_SHIFT_LOAD: begin
-    shift_counter <= step_counter;
-  end
-  STATE_SHIFT: begin
-    shift_counter <= shift_counter - 1'b1;
-  end
-  endcase
-end
-
-always @(posedge clk)
-begin
-  case(state)
-  STATE_IDLE:
-    if (s_axis_valid == 1'b1) begin
-      step_counter <= 'h00;
-      phase <= {1'b0,s_axis_data[61:32]};
-      step_counter <= 'h00;
-      case (s_axis_data[63:62])
-      2'b00: begin
-        i <= {s_axis_data[31],s_axis_data[31:0]};
-        q <= 'h00;
+  always @(posedge clk) begin
+    if (resetn == 1'b0) begin
+      state <= STATE_IDLE;
+    end else begin
+      case (state)
+      STATE_IDLE: begin
+        if (s_axis_valid == 1'b1) begin
+          state <= STATE_SHIFT_LOAD;
+        end
       end
-      2'b01: begin
-        i <= 'h00;
-        q <= ~{s_axis_data[31],s_axis_data[31:0]};
+      STATE_SHIFT_LOAD: begin
+        if (step_counter == 'h00) begin
+          state <= STATE_ADD;
+        end else begin
+          state <= STATE_SHIFT;
+        end
       end
-      2'b10: begin
-        i <= ~{s_axis_data[31],s_axis_data[31:0]};
-        q <= 'h00;
+      STATE_SHIFT: begin
+        if (shift_counter == 'h01) begin
+          state <= STATE_ADD;
+        end
       end
-      2'b11: begin
-        i <= 'h00;
-        q <= {s_axis_data[31],s_axis_data[31:0]};
+      STATE_ADD: begin
+        if (step_counter == 'd30) begin
+          state <= STATE_DONE;
+        end else begin
+          state <= STATE_SHIFT_LOAD;
+        end
+      end
+      STATE_DONE: begin
+        if (m_axis_ready == 1'b1)
+          state <= STATE_IDLE;
       end
       endcase
     end
-  STATE_SHIFT_LOAD: begin
-    i_shift <= i;
-    q_shift <= q;
   end
-  STATE_SHIFT: begin
-    i_shift <= {i_shift[32],i_shift[32:1]};
-    q_shift <= {q_shift[32],q_shift[32:1]};
-  end
-  STATE_ADD: begin
-    if (phase[30] == 1'b0) begin
-      i <= i + q_shift;
-      q <= q - i_shift;
-      phase <= phase - angle[step_counter];
-    end else begin
-      i <= i - q_shift;
-      q <= q + i_shift;
-      phase <= phase + angle[step_counter];
+
+  always @(posedge clk) begin
+    case(state)
+    STATE_SHIFT_LOAD: begin
+      shift_counter <= step_counter;
     end
-    step_counter <= step_counter + 1'b1;
+    STATE_SHIFT: begin
+      shift_counter <= shift_counter - 1'b1;
+    end
+    endcase
+  end
+
+  always @(posedge clk)
+  begin
+    case(state)
+    STATE_IDLE:
+      if (s_axis_valid == 1'b1) begin
+        step_counter <= 'h00;
+        phase <= {1'b0,s_axis_data[61:32]};
+        step_counter <= 'h00;
+        case (s_axis_data[63:62])
+        2'b00: begin
+          i <= {s_axis_data[31],s_axis_data[31:0]};
+          q <= 'h00;
+        end
+        2'b01: begin
+          i <= 'h00;
+          q <= ~{s_axis_data[31],s_axis_data[31:0]};
+        end
+        2'b10: begin
+          i <= ~{s_axis_data[31],s_axis_data[31:0]};
+          q <= 'h00;
+        end
+        2'b11: begin
+          i <= 'h00;
+          q <= {s_axis_data[31],s_axis_data[31:0]};
+        end
+        endcase
+      end
+    STATE_SHIFT_LOAD: begin
+      i_shift <= i;
+      q_shift <= q;
+    end
+    STATE_SHIFT: begin
+      i_shift <= {i_shift[32],i_shift[32:1]};
+      q_shift <= {q_shift[32],q_shift[32:1]};
+    end
+    STATE_ADD: begin
+      if (phase[30] == 1'b0) begin
+        i <= i + q_shift;
+        q <= q - i_shift;
+        phase <= phase - angle[step_counter];
+      end else begin
+        i <= i - q_shift;
+        q <= q + i_shift;
+        phase <= phase + angle[step_counter];
+      end
+      step_counter <= step_counter + 1'b1;
+    end
+    endcase
   end
-  endcase
-end
 
 endmodule
diff --git a/library/data_offload/data_offload.v b/library/data_offload/data_offload.v
index 2e12b88cf..5fe068a6c 100644
--- a/library/data_offload/data_offload.v
+++ b/library/data_offload/data_offload.v
@@ -199,8 +199,8 @@ module data_offload #(
   // Offload FSM and control
   data_offload_fsm #(
     .TX_OR_RXN_PATH (TX_OR_RXN_PATH),
-    .SYNC_EXT_ADD_INTERNAL_CDC (SYNC_EXT_ADD_INTERNAL_CDC))
-  i_data_offload_fsm (
+    .SYNC_EXT_ADD_INTERNAL_CDC (SYNC_EXT_ADD_INTERNAL_CDC)
+  ) i_data_offload_fsm (
     .up_clk (up_clk),
     .wr_clk (src_clk),
     .wr_resetn_in (src_rstn),
@@ -226,8 +226,7 @@ module data_offload #(
     .sync_external (sync_ext),
     .sync_internal (sync_int_s),
     .wr_fsm_state_out (src_fsm_status_s),
-    .rd_fsm_state_out (dst_fsm_status_s)
-  );
+    .rd_fsm_state_out (dst_fsm_status_s));
 
   assign m_axis_valid = rd_ready & ((dst_bypass_s) ? valid_bypass_s : s_storage_axis_valid);
   // For DAC paths set zero as IDLE data on the axis bus, avoid repeating last
@@ -246,7 +245,6 @@ module data_offload #(
 
   assign s_storage_axis_ready = rd_ready & m_axis_ready;
 
-
   // Bypass module instance -- the same FIFO, just a smaller depth
   // NOTE: Generating an overflow is making sense just in BYPASS mode, and
   // it's supported just with the FIFO interface
@@ -254,8 +252,8 @@ module data_offload #(
     .S_DATA_WIDTH (SRC_DATA_WIDTH),
     .S_ADDRESS_WIDTH (SRC_ADDR_WIDTH_BYPASS),
     .M_DATA_WIDTH (DST_DATA_WIDTH),
-    .ASYNC_CLK (1))
-  i_bypass_fifo (
+    .ASYNC_CLK (1)
+  ) i_bypass_fifo (
     .m_axis_aclk (m_axis_aclk),
     .m_axis_aresetn (dst_rstn),
     .m_axis_ready (m_axis_ready),
@@ -275,8 +273,7 @@ module data_offload #(
     .s_axis_full  (),
     .s_axis_almost_full (),
     .s_axis_tkeep (),
-    .s_axis_room ()
-  );
+    .s_axis_room ());
 
   // register map
 
@@ -287,7 +284,7 @@ module data_offload #(
     .TX_OR_RXN_PATH (TX_OR_RXN_PATH),
     .AUTO_BRINGUP (AUTO_BRINGUP),
     .HAS_BYPASS (HAS_BYPASS)
-) i_regmap (
+  ) i_regmap (
     .up_clk (up_clk),
     .up_rstn (up_rstn),
     .up_rreq (up_rreq_s),
@@ -313,8 +310,7 @@ module data_offload #(
     .src_fsm_status (src_fsm_status_s),
     .dst_fsm_status (dst_fsm_status_s),
     .src_overflow (wr_overflow),
-    .dst_underflow (rd_underflow)
-  );
+    .dst_underflow (rd_underflow));
 
   // axi interface wrapper
 
@@ -322,8 +318,8 @@ module data_offload #(
   assign up_rstn = s_axi_aresetn;
 
   up_axi #(
-    .AXI_ADDRESS_WIDTH (16))
-  i_up_axi (
+    .AXI_ADDRESS_WIDTH (16)
+  ) i_up_axi (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_axi_awvalid (s_axi_awvalid),
@@ -352,39 +348,37 @@ module data_offload #(
     .up_rdata (up_rdata_s),
     .up_rack (up_rack_s));
 
-// Measured length handshake CDC
-util_axis_fifo #(
-  .DATA_WIDTH(MEM_SIZE_LOG2),
-  .ADDRESS_WIDTH(0),
-  .ASYNC_CLK(1)
-) i_measured_length_cdc (
-  .s_axis_aclk(s_axis_aclk),
-  .s_axis_aresetn(s_axis_aresetn),
-  .s_axis_valid(wr_response_eot),
-  .s_axis_ready(),
-  .s_axis_full(),
-  .s_axis_data(wr_response_measured_length),
-  .s_axis_room(),
-  .s_axis_tkeep(),
-  .s_axis_tlast(),
-  .s_axis_almost_full(),
+  // Measured length handshake CDC
+  util_axis_fifo #(
+    .DATA_WIDTH(MEM_SIZE_LOG2),
+    .ADDRESS_WIDTH(0),
+    .ASYNC_CLK(1)
+  ) i_measured_length_cdc (
+    .s_axis_aclk(s_axis_aclk),
+    .s_axis_aresetn(s_axis_aresetn),
+    .s_axis_valid(wr_response_eot),
+    .s_axis_ready(),
+    .s_axis_full(),
+    .s_axis_data(wr_response_measured_length),
+    .s_axis_room(),
+    .s_axis_tkeep(),
+    .s_axis_tlast(),
+    .s_axis_almost_full(),
 
-  .m_axis_aclk(m_axis_aclk),
-  .m_axis_aresetn(m_axis_aresetn),
-  .m_axis_valid(rd_ml_valid),
-  .m_axis_ready(rd_ml_ready),
-  .m_axis_data(rd_wr_response_measured_length),
-  .m_axis_level(),
-  .m_axis_empty(),
-  .m_axis_tkeep(),
-  .m_axis_tlast(),
-  .m_axis_almost_empty()
-);
+    .m_axis_aclk(m_axis_aclk),
+    .m_axis_aresetn(m_axis_aresetn),
+    .m_axis_valid(rd_ml_valid),
+    .m_axis_ready(rd_ml_ready),
+    .m_axis_data(rd_wr_response_measured_length),
+    .m_axis_level(),
+    .m_axis_empty(),
+    .m_axis_tkeep(),
+    .m_axis_tlast(),
+    .m_axis_almost_empty());
 
-always @(posedge m_axis_aclk) begin
-  if (rd_ml_valid & rd_ml_ready)
-   rd_request_length <= rd_wr_response_measured_length;
-end
+  always @(posedge m_axis_aclk) begin
+    if (rd_ml_valid & rd_ml_ready)
+     rd_request_length <= rd_wr_response_measured_length;
+  end
 
 endmodule
-
diff --git a/library/data_offload/data_offload_fsm.v b/library/data_offload/data_offload_fsm.v
index 5d6ccfb79..242ee374b 100644
--- a/library/data_offload/data_offload_fsm.v
+++ b/library/data_offload/data_offload_fsm.v
@@ -41,8 +41,8 @@
 module data_offload_fsm #(
 
   parameter TX_OR_RXN_PATH = 0,
-  parameter SYNC_EXT_ADD_INTERNAL_CDC = 1) (
-
+  parameter SYNC_EXT_ADD_INTERNAL_CDC = 1
+) (
   input                               up_clk,
 
   // Control interface for storage for m_storage_axis interface
@@ -85,8 +85,7 @@ module data_offload_fsm #(
   // FSM debug
   output      [ 4:0]                  wr_fsm_state_out,
   output      [ 3:0]                  rd_fsm_state_out
-
-  );
+);
 
   // FSM states
 
@@ -273,56 +272,50 @@ module data_offload_fsm #(
   // CDC circuits
   sync_event #(
     .NUM_OF_EVENTS (1),
-    .ASYNC_CLK (1))
-  i_wr_empty_sync (
+    .ASYNC_CLK (1)
+  ) i_wr_empty_sync (
     .in_clk (rd_clk),
     .in_event (rd_last_eot && rd_fsm_state[RD_BIT_RD]),
     .out_clk (wr_clk),
-    .out_event (wr_rd_response_eot)
-  );
+    .out_event (wr_rd_response_eot));
 
   sync_bits #(
     .NUM_OF_BITS (1),
-    .ASYNC_CLK (TX_OR_RXN_PATH[0]))
-  i_rd_init_req_sync (
+    .ASYNC_CLK (TX_OR_RXN_PATH[0])
+  ) i_rd_init_req_sync (
     .in_bits (init_req),
     .out_clk (rd_clk),
     .out_resetn (1'b1),
-    .out_bits (rd_init_req_s)
-  );
+    .out_bits (rd_init_req_s));
 
   sync_bits #(
     .NUM_OF_BITS (1),
-    .ASYNC_CLK (~TX_OR_RXN_PATH[0]))
-  i_wr_init_req_sync (
+    .ASYNC_CLK (~TX_OR_RXN_PATH[0])
+  ) i_wr_init_req_sync (
     .in_bits (init_req),
     .out_clk (wr_clk),
     .out_resetn (1'b1),
-    .out_bits (wr_init_req_s)
-  );
+    .out_bits (wr_init_req_s));
 
   // When SYNC_EXT_ADD_INTERNAL_CDC is deasserted, one of these signals will end
   // up being synchronized to the "wrong" clock domain. This shouldn't matter
   // because the incorrectly synchronized signal is guarded by a synthesis constant.
   sync_bits #(
     .NUM_OF_BITS (1),
-    .ASYNC_CLK (SYNC_EXT_ADD_INTERNAL_CDC))
-  i_sync_wr_sync (
+    .ASYNC_CLK (SYNC_EXT_ADD_INTERNAL_CDC)
+  ) i_sync_wr_sync (
     .in_bits ({ sync_external }),
     .out_clk (wr_clk),
     .out_resetn (1'b1),
-    .out_bits ({ wr_sync_external_s })
-  );
+    .out_bits ({wr_sync_external_s}));
 
   sync_bits #(
     .NUM_OF_BITS (1),
-    .ASYNC_CLK (SYNC_EXT_ADD_INTERNAL_CDC))
-  i_sync_rd_sync (
+    .ASYNC_CLK (SYNC_EXT_ADD_INTERNAL_CDC)
+  ) i_sync_rd_sync (
     .in_bits ({ sync_external }),
     .out_clk (rd_clk),
     .out_resetn (1'b1),
-    .out_bits ({ rd_sync_external_s })
-  );
+    .out_bits ({ rd_sync_external_s }));
 
 endmodule
-
diff --git a/library/data_offload/data_offload_regmap.v b/library/data_offload/data_offload_regmap.v
index 9cf46bdcc..23d740053 100644
--- a/library/data_offload/data_offload_regmap.v
+++ b/library/data_offload/data_offload_regmap.v
@@ -88,7 +88,6 @@ module data_offload_regmap #(
 
   input                   src_overflow,
   input                   dst_underflow
-
 );
 
   // local parameters
@@ -275,114 +274,105 @@ module data_offload_regmap #(
 
   sync_data #(
     .NUM_OF_BITS (4),
-    .ASYNC_CLK (1))
-  i_dst_fsm_status (
+    .ASYNC_CLK (1)
+  ) i_dst_fsm_status (
     .in_clk (dst_clk),
     .in_data (dst_fsm_status),
     .out_clk (up_clk),
-    .out_data (up_rd_fsm_status_s)
-  );
+    .out_data (up_rd_fsm_status_s));
 
   sync_data #(
     .NUM_OF_BITS (5),
-    .ASYNC_CLK (1))
-  i_src_fsm_status (
+    .ASYNC_CLK (1)
+  ) i_src_fsm_status (
     .in_clk (src_clk),
     .in_data (src_fsm_status),
     .out_clk (up_clk),
-    .out_data (up_wr_fsm_status_s)
-  );
+    .out_data (up_wr_fsm_status_s));
 
   generate
   if (TX_OR_RXN_PATH) begin : sync_tx_path
 
     sync_data #(
       .NUM_OF_BITS (3),
-      .ASYNC_CLK (1))
-    i_sync_xfer_control (
+      .ASYNC_CLK (1)
+    ) i_sync_xfer_control (
       .in_clk (up_clk),
       .in_data ({up_sync_config,
                  up_sync}),
       .out_clk (dst_clk),
       .out_data ({sync_config,
-                  sync})
-    );
+                  sync}));
 
   end else begin : sync_rx_path
 
     sync_data #(
       .NUM_OF_BITS (3),
-      .ASYNC_CLK (1))
-    i_sync_xfer_control (
+      .ASYNC_CLK (1)
+    ) i_sync_xfer_control (
       .in_clk (up_clk),
       .in_data ({up_sync_config,
                  up_sync}),
       .out_clk (src_clk),
       .out_data ({sync_config,
-                  sync})
-    );
+                  sync}));
 
   end
   endgenerate
 
   sync_bits #(
     .NUM_OF_BITS (2),
-    .ASYNC_CLK (1))
-  i_src_xfer_control (
+    .ASYNC_CLK (1)
+  ) i_src_xfer_control (
     .in_bits ({ up_sw_resetn, up_bypass }),
     .out_clk (src_clk),
     .out_resetn (1'b1),
-    .out_bits ({ src_sw_resetn_s, src_bypass })
-  );
+    .out_bits ({ src_sw_resetn_s, src_bypass }));
 
   sync_bits #(
     .NUM_OF_BITS (2),
-    .ASYNC_CLK (1))
-  i_dst_xfer_control (
+    .ASYNC_CLK (1)
+  ) i_dst_xfer_control (
     .in_bits ({ up_sw_resetn, up_bypass }),
     .out_clk (dst_clk),
     .out_resetn (1'b1),
-    .out_bits ({ dst_sw_resetn_s, dst_bypass })
-  );
+    .out_bits ({ dst_sw_resetn_s, dst_bypass }));
 
   sync_bits #(
     .NUM_OF_BITS (1),
-    .ASYNC_CLK (1))
-  i_ddr_calib_done_sync (
+    .ASYNC_CLK (1)
+  ) i_ddr_calib_done_sync (
     .in_bits (ddr_calib_done),
     .out_clk (up_clk),
     .out_resetn (1'b1),
-    .out_bits (up_ddr_calib_done_s)
-  );
+    .out_bits (up_ddr_calib_done_s));
 
   sync_bits #(
     .NUM_OF_BITS (1),
-    .ASYNC_CLK (1))
-  i_dst_oneshot_sync (
+    .ASYNC_CLK (1)
+  ) i_dst_oneshot_sync (
     .in_bits (up_oneshot),
     .out_clk (dst_clk),
     .out_resetn (1'b1),
-    .out_bits (oneshot)
-  );
+    .out_bits (oneshot));
 
   sync_data #(
     .NUM_OF_BITS (MEM_SIZE_LOG2),
-    .ASYNC_CLK (1))
-  i_sync_src_transfer_length (
+    .ASYNC_CLK (1)
+  ) i_sync_src_transfer_length (
     .in_clk (up_clk),
     .in_data (up_transfer_length),
     .out_clk (src_clk),
-    .out_data (src_transfer_length)
-  );
+    .out_data (src_transfer_length));
+
   sync_data #(
     .NUM_OF_BITS (MEM_SIZE_LOG2),
-    .ASYNC_CLK (1))
-  i_sync_dst_transfer_length (
+    .ASYNC_CLK (1)
+  ) i_sync_dst_transfer_length (
     .in_clk (up_clk),
     .in_data (up_transfer_length),
     .out_clk (dst_clk),
-    .out_data (dst_transfer_length)
-  );
+    .out_data (dst_transfer_length));
 
   always @(posedge src_clk) begin
     src_sw_resetn <= src_sw_resetn_s;
@@ -395,24 +385,22 @@ module data_offload_regmap #(
   generate if (TX_OR_RXN_PATH == 0) begin
     sync_event #(
       .NUM_OF_EVENTS (1),
-      .ASYNC_CLK (1))
-    i_wr_overflow_sync (
+      .ASYNC_CLK (1)
+    ) i_wr_overflow_sync (
       .in_clk (src_clk),
       .in_event (src_overflow),
       .out_clk (up_clk),
-      .out_event (up_src_overflow_set_s)
-    );
+      .out_event (up_src_overflow_set_s));
     assign up_dst_underflow_set_s = 1'b0;
   end else begin
     sync_event #(
       .NUM_OF_EVENTS (1),
-      .ASYNC_CLK (1))
-    i_rd_underflow_sync (
+      .ASYNC_CLK (1)
+    ) i_rd_underflow_sync (
       .in_clk (dst_clk),
       .in_event (dst_underflow),
       .out_clk (up_clk),
-      .out_event (up_dst_underflow_set_s)
-    );
+      .out_event (up_dst_underflow_set_s));
     assign up_src_overflow_set_s = 1'b0;
   end
   endgenerate
diff --git a/library/intel/adi_jesd204/adi_jesd204_glue.v b/library/intel/adi_jesd204/adi_jesd204_glue.v
index 3f7978571..a293c7959 100644
--- a/library/intel/adi_jesd204/adi_jesd204_glue.v
+++ b/library/intel/adi_jesd204/adi_jesd204_glue.v
@@ -42,8 +42,8 @@ module adi_jesd204_glue (
   output out_pll_select_gnd
 );
 
-assign out_pll_powerdown = in_pll_powerdown;
-assign out_mcgb_rst = in_pll_powerdown;
-assign out_pll_select_gnd = 1'b0;
+  assign out_pll_powerdown = in_pll_powerdown;
+  assign out_mcgb_rst = in_pll_powerdown;
+  assign out_pll_select_gnd = 1'b0;
 
 endmodule
diff --git a/library/intel/avl_adxcfg/avl_adxcfg.v b/library/intel/avl_adxcfg/avl_adxcfg.v
index ef35110a9..47f4df107 100644
--- a/library/intel/avl_adxcfg/avl_adxcfg.v
+++ b/library/intel/avl_adxcfg/avl_adxcfg.v
@@ -37,7 +37,8 @@
 
 module avl_adxcfg #(
 
-  parameter ADDRESS_WIDTH = 10) (
+  parameter ADDRESS_WIDTH = 10
+) (
 
   // reconfig sharing
 
@@ -70,7 +71,8 @@ module avl_adxcfg #(
   output  [ADDRESS_WIDTH-1:0]  rcfg_out_address_1,
   output  [31:0]  rcfg_out_writedata_1,
   input   [31:0]  rcfg_out_readdata_1,
-  input           rcfg_out_waitrequest_1);
+  input           rcfg_out_waitrequest_1
+);
 
   // internal registers
 
@@ -160,7 +162,3 @@ module avl_adxcfg #(
   end
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
-
diff --git a/library/intel/avl_adxcvr_octet_swap/avl_adxcvr_octet_swap.v b/library/intel/avl_adxcvr_octet_swap/avl_adxcvr_octet_swap.v
index e959ab298..6008de3bf 100644
--- a/library/intel/avl_adxcvr_octet_swap/avl_adxcvr_octet_swap.v
+++ b/library/intel/avl_adxcvr_octet_swap/avl_adxcvr_octet_swap.v
@@ -52,19 +52,19 @@ module avl_adxcvr_octet_swap #(
   output [3:0] out_sof
 );
 
-assign in_ready = out_ready;
-assign out_valid = in_valid;
+  assign in_ready = out_ready;
+  assign out_valid = in_valid;
 
-generate
-  genvar i;
-  genvar j;
+  generate
+    genvar i;
+    genvar j;
 
-  for (j = 0; j < 4; j = j + 1) begin: gen_octet
-    for (i = 0; i < NUM_OF_LANES; i = i + 1) begin: gen_lane
-      assign out_data[i*32+j*8+7:i*32+j*8] = in_data[i*32+(3-j)*8+7:i*32+(3-j)*8];
+    for (j = 0; j < 4; j = j + 1) begin: gen_octet
+      for (i = 0; i < NUM_OF_LANES; i = i + 1) begin: gen_lane
+        assign out_data[i*32+j*8+7:i*32+j*8] = in_data[i*32+(3-j)*8+7:i*32+(3-j)*8];
+      end
+      assign out_sof[j] = in_sof[3-j];
     end
-    assign out_sof[j] = in_sof[3-j];
-  end
-endgenerate
+  endgenerate
 
 endmodule
diff --git a/library/intel/avl_adxphy/avl_adxphy.v b/library/intel/avl_adxphy/avl_adxphy.v
index b598bdc8a..bb74ee78c 100644
--- a/library/intel/avl_adxphy/avl_adxphy.v
+++ b/library/intel/avl_adxphy/avl_adxphy.v
@@ -40,7 +40,8 @@ module avl_adxphy #(
 
   // parameters
 
-  parameter   integer NUM_OF_LANES = 4) (
+  parameter   integer NUM_OF_LANES = 4
+) (
 
   // rx-ip interface
 
@@ -217,7 +218,6 @@ module avl_adxphy #(
   input                               tx_ip_bit_reversal,
   input                               tx_ip_byte_reversal,
 
-
   // tx-phy interface
 
   input                               tx_phy_cal_busy_0,
@@ -328,7 +328,8 @@ module avl_adxphy #(
 
   input   [((NUM_OF_LANES* 1)-1):0]   tx_core_analogreset,
   input   [((NUM_OF_LANES* 1)-1):0]   tx_core_digitalreset,
-  output  [((NUM_OF_LANES* 1)-1):0]   tx_core_cal_busy);
+  output  [((NUM_OF_LANES* 1)-1):0]   tx_core_cal_busy
+);
 
   // rx assignments
 
@@ -919,7 +920,3 @@ module avl_adxphy #(
   assign tx_phy_byte_reversal_7 = tx_ip_byte_reversal;
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
-
diff --git a/library/intel/avl_dacfifo/avl_dacfifo.v b/library/intel/avl_dacfifo/avl_dacfifo.v
index e6565970e..7d2bb2216 100644
--- a/library/intel/avl_dacfifo/avl_dacfifo.v
+++ b/library/intel/avl_dacfifo/avl_dacfifo.v
@@ -45,7 +45,8 @@ module avl_dacfifo #(
   parameter   AVL_ADDRESS_WIDTH = 25,
   parameter   AVL_BURST_LENGTH = 127,
   parameter   AVL_BASE_ADDRESS = 32'h00000000,
-  parameter   AVL_ADDRESS_LIMIT = 32'h1fffffff) (
+  parameter   AVL_ADDRESS_LIMIT = 32'h1fffffff
+) (
 
   // dma interface
 
@@ -81,7 +82,8 @@ module avl_dacfifo #(
   input                                 avl_readdata_valid,
   input                                 avl_ready,
   output                                avl_write,
-  output      [(AVL_DATA_WIDTH-1):0]    avl_writedata);
+  output      [(AVL_DATA_WIDTH-1):0]    avl_writedata
+);
 
   localparam  FIFO_BYPASS = (DAC_DATA_WIDTH == DMA_DATA_WIDTH) ? 1 : 0;
 
@@ -210,8 +212,7 @@ module avl_dacfifo #(
       .dac_rst(dac_rst),
       .dac_valid(dac_valid),
       .dac_data(dac_data_bypass_s),
-      .dac_dunf(dac_dunf_bypass_s)
-    );
+      .dac_dunf(dac_dunf_bypass_s));
 
     always @(posedge dma_clk) begin
       dma_bypass_m1 <= bypass;
@@ -258,4 +259,3 @@ module avl_dacfifo #(
   endgenerate
 
 endmodule
-
diff --git a/library/intel/avl_dacfifo/avl_dacfifo_rd.v b/library/intel/avl_dacfifo/avl_dacfifo_rd.v
index 1f34801d5..93d7e8ce7 100644
--- a/library/intel/avl_dacfifo/avl_dacfifo_rd.v
+++ b/library/intel/avl_dacfifo/avl_dacfifo_rd.v
@@ -42,8 +42,8 @@ module avl_dacfifo_rd #(
   parameter     AVL_BURST_LENGTH = 127,
   parameter     AVL_DDR_BASE_ADDRESS = 0,
   parameter     AVL_DDR_ADDRESS_LIMIT = 33554432,
-  parameter     DAC_MEM_ADDRESS_WIDTH = 8)(
-
+  parameter     DAC_MEM_ADDRESS_WIDTH = 8
+) (
   input                                     dac_clk,
   input                                     dac_reset,
   input                                     dac_valid,
@@ -65,7 +65,8 @@ module avl_dacfifo_rd #(
   input       [ 6:0]                        avl_last_burstcount,
   input       [ 7:0]                        dma_last_beats,
   input                                     avl_xfer_req_in,
-  output  reg                               avl_xfer_req_out);
+  output  reg                               avl_xfer_req_out
+);
 
   // Max supported MEM_RATIO is 16
   localparam  MEM_RATIO = AVL_DATA_WIDTH/DAC_DATA_WIDTH;
@@ -192,8 +193,8 @@ module avl_dacfifo_rd #(
 
   always @(posedge avl_clk) begin
     if (avl_fifo_reset_s == 1'b1) begin
-       avl_read_state <= IDLE;
-       avl_burstcount <= AVL_BURST_LENGTH;
+      avl_read_state <= IDLE;
+      avl_burstcount <= AVL_BURST_LENGTH;
     end else begin
       case (avl_read_state)
         IDLE : begin
@@ -432,8 +433,8 @@ module avl_dacfifo_rd #(
   end
   ad_mem #(
     .DATA_WIDTH (DAC_MEM_ADDRESS_WIDTH),
-    .ADDRESS_WIDTH (8))
-  i_mem (
+    .ADDRESS_WIDTH (8)
+  ) i_mem (
     .clka (dac_clk),
     .wea (dac_mem_laddr_wea_s),
     .addra (dac_mem_laddr_waddr),
@@ -537,4 +538,3 @@ module avl_dacfifo_rd #(
   end
 
 endmodule
-
diff --git a/library/intel/avl_dacfifo/avl_dacfifo_wr.v b/library/intel/avl_dacfifo/avl_dacfifo_wr.v
index 9d8f006d1..079e7b385 100644
--- a/library/intel/avl_dacfifo/avl_dacfifo_wr.v
+++ b/library/intel/avl_dacfifo/avl_dacfifo_wr.v
@@ -42,8 +42,8 @@ module avl_dacfifo_wr #(
   parameter     AVL_BURST_LENGTH = 128,
   parameter     AVL_DDR_BASE_ADDRESS = 0,
   parameter     AVL_DDR_ADDRESS_LIMIT = 33554432,
-  parameter     DMA_MEM_ADDRESS_WIDTH = 10)(
-
+  parameter     DMA_MEM_ADDRESS_WIDTH = 10
+) (
   input                                 dma_clk,
   input       [DMA_DATA_WIDTH-1:0]      dma_data,
   input                                 dma_ready,
@@ -66,7 +66,8 @@ module avl_dacfifo_wr #(
   output  reg [24:0]                    avl_last_address,
   output  reg [ 6:0]                    avl_last_burstcount,
   output  reg                           avl_xfer_req_out,
-  input                                 avl_xfer_req_in);
+  input                                 avl_xfer_req_in
+);
 
   localparam  MEM_RATIO = AVL_DATA_WIDTH/DMA_DATA_WIDTH;  // Max supported MEM_RATIO is 16
   localparam  AVL_MEM_ADDRESS_WIDTH = (MEM_RATIO ==  1) ?  DMA_MEM_ADDRESS_WIDTH :
@@ -211,7 +212,7 @@ module avl_dacfifo_wr #(
     end
   end
 
-  ad_b2g # (
+  ad_b2g #(
     .DATA_WIDTH(DMA_MEM_ADDRESS_WIDTH)
   ) i_dma_mem_waddr_b2g (
     .din (dma_mem_waddr),
@@ -367,8 +368,8 @@ module avl_dacfifo_wr #(
     end
   end
 
-  ad_g2b # (
-    .DATA_WIDTH(DMA_MEM_ADDRESS_WIDTH)
+  ad_g2b #(
+    .DATA_WIDTH (DMA_MEM_ADDRESS_WIDTH)
   ) i_avl_mem_waddr_g2b (
     .din (avl_mem_waddr_m2),
     .dout (avl_mem_waddr_m2_g2b_s));
diff --git a/library/intel/avl_dacfifo/util_dacfifo_bypass.v b/library/intel/avl_dacfifo/util_dacfifo_bypass.v
index bfd70118c..fcde2b10b 100644
--- a/library/intel/avl_dacfifo/util_dacfifo_bypass.v
+++ b/library/intel/avl_dacfifo/util_dacfifo_bypass.v
@@ -38,7 +38,8 @@
 module util_dacfifo_bypass #(
 
   parameter   DAC_DATA_WIDTH = 64,
-  parameter   DMA_DATA_WIDTH = 64) (
+  parameter   DMA_DATA_WIDTH = 64
+) (
 
   // DMA FIFO interface
 
@@ -142,8 +143,8 @@ module util_dacfifo_bypass #(
   end
 
   ad_b2g #(
-    .DATA_WIDTH (DMA_ADDRESS_WIDTH))
-  i_dma_mem_waddr_b2g (
+    .DATA_WIDTH (DMA_ADDRESS_WIDTH)
+  ) i_dma_mem_waddr_b2g (
     .din (dma_mem_waddr),
     .dout (dma_mem_waddr_b2g_s));
 
@@ -170,8 +171,8 @@ module util_dacfifo_bypass #(
   end
 
   ad_g2b #(
-    .DATA_WIDTH (DAC_ADDRESS_WIDTH))
-  i_dma_mem_raddr_g2b (
+    .DATA_WIDTH (DAC_ADDRESS_WIDTH)
+  ) i_dma_mem_raddr_g2b (
     .din (dma_mem_raddr_m2),
     .dout (dma_mem_raddr_m2_g2b_s));
 
@@ -185,7 +186,6 @@ module util_dacfifo_bypass #(
                                  (MEM_RATIO == 2) ? ({dma_mem_raddr, 1'b0}) :
                                  (MEM_RATIO == 4) ? ({dma_mem_raddr, 2'b0}) : ({dma_mem_raddr, 3'b0}));
 
-
   // relative address offset on dac domain
   assign dac_address_diff_s = {1'b1, dac_mem_waddr_s} - dac_mem_raddr;
   assign dac_mem_waddr_s = (DAC_DATA_WIDTH>DMA_DATA_WIDTH) ?
@@ -220,8 +220,8 @@ module util_dacfifo_bypass #(
   end
 
   ad_b2g #(
-    .DATA_WIDTH (DAC_ADDRESS_WIDTH))
-  i_dac_mem_raddr_b2g (
+    .DATA_WIDTH (DAC_ADDRESS_WIDTH)
+  ) i_dac_mem_raddr_b2g (
     .din (dac_mem_raddr),
     .dout (dac_mem_raddr_b2g_s));
 
@@ -240,8 +240,8 @@ module util_dacfifo_bypass #(
   end
 
   ad_g2b #(
-    .DATA_WIDTH (DMA_ADDRESS_WIDTH))
-  i_dac_mem_waddr_g2b (
+    .DATA_WIDTH (DMA_ADDRESS_WIDTH)
+  ) i_dac_mem_waddr_g2b (
     .din (dac_mem_waddr_m2),
     .dout (dac_mem_waddr_m2_g2b_s));
 
@@ -273,4 +273,3 @@ module util_dacfifo_bypass #(
   end
 
 endmodule
-
diff --git a/library/intel/axi_adxcvr/axi_adxcvr.v b/library/intel/axi_adxcvr/axi_adxcvr.v
index 5b4c3e6d2..fb794926c 100644
--- a/library/intel/axi_adxcvr/axi_adxcvr.v
+++ b/library/intel/axi_adxcvr/axi_adxcvr.v
@@ -47,7 +47,8 @@ module axi_adxcvr #(
   parameter   [15:0]  FPGA_VOLTAGE = 0,
   parameter   integer XCVR_TYPE = 0,
   parameter   integer TX_OR_RX_N = 0,
-  parameter   integer NUM_OF_LANES = 4) (
+  parameter   integer NUM_OF_LANES = 4
+) (
 
   // xcvr, lane-pll and ref-pll are shared
 
@@ -75,7 +76,8 @@ module axi_adxcvr #(
   output                        s_axi_rvalid,
   output  [ 1:0]                s_axi_rresp,
   output  [31:0]                s_axi_rdata,
-  input                         s_axi_rready);
+  input                         s_axi_rready
+);
 
   // internal signals
 
@@ -106,8 +108,8 @@ module axi_adxcvr #(
     .DEV_PACKAGE (DEV_PACKAGE),
     .FPGA_VOLTAGE (FPGA_VOLTAGE),
     .TX_OR_RX_N (TX_OR_RX_N),
-    .NUM_OF_LANES (NUM_OF_LANES))
-  i_up (
+    .NUM_OF_LANES (NUM_OF_LANES)
+  ) i_up (
     .up_rst (up_rst),
     .up_pll_locked (up_pll_locked),
     .up_ready (up_ready),
@@ -154,7 +156,3 @@ module axi_adxcvr #(
     .up_rack (up_rack));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
-
diff --git a/library/intel/axi_adxcvr/axi_adxcvr_up.v b/library/intel/axi_adxcvr/axi_adxcvr_up.v
index b9864b1a4..4afec634b 100644
--- a/library/intel/axi_adxcvr/axi_adxcvr_up.v
+++ b/library/intel/axi_adxcvr/axi_adxcvr_up.v
@@ -47,7 +47,8 @@ module axi_adxcvr_up #(
   parameter   [15:0]  FPGA_VOLTAGE = 0,
   parameter   integer XCVR_TYPE = 0,
   parameter   integer TX_OR_RX_N = 0,
-  parameter   integer NUM_OF_LANES = 4) (
+  parameter   integer NUM_OF_LANES = 4
+) (
 
   // xcvr, lane-pll and ref-pll are shared
 
@@ -66,7 +67,8 @@ module axi_adxcvr_up #(
   input                         up_rreq,
   input   [ 9:0]                up_raddr,
   output  [31:0]                up_rdata,
-  output                        up_rack);
+  output                        up_rack
+);
 
   // parameters
 
@@ -186,6 +188,3 @@ module axi_adxcvr_up #(
   end
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/intel/common/ad_dcfilter.v b/library/intel/common/ad_dcfilter.v
index 2cd19c3e3..188f08529 100644
--- a/library/intel/common/ad_dcfilter.v
+++ b/library/intel/common/ad_dcfilter.v
@@ -41,7 +41,8 @@ module ad_dcfilter #(
 
   // data path disable
 
-  parameter   DISABLE = 0) (
+  parameter   DISABLE = 0
+) (
 
   // data interface
 
@@ -55,7 +56,8 @@ module ad_dcfilter #(
 
   input           dcfilt_enb,
   input   [15:0]  dcfilt_coeff,
-  input   [15:0]  dcfilt_offset);
+  input   [15:0]  dcfilt_offset
+);
 
   // internal registers
 
@@ -80,6 +82,3 @@ module ad_dcfilter #(
   end
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/intel/common/ad_mul.v b/library/intel/common/ad_mul.v
index eaaef8b79..3757b52b4 100644
--- a/library/intel/common/ad_mul.v
+++ b/library/intel/common/ad_mul.v
@@ -39,7 +39,8 @@ module ad_mul #(
 
   parameter   A_DATA_WIDTH = 17,
   parameter   B_DATA_WIDTH = 17,
-  parameter   DELAY_DATA_WIDTH = 16) (
+  parameter   DELAY_DATA_WIDTH = 16
+) (
 
   // data_p = data_a * data_b;
 
@@ -51,8 +52,8 @@ module ad_mul #(
   // delay interface
 
   input       [(DELAY_DATA_WIDTH-1):0]  ddata_in,
-  output  reg [(DELAY_DATA_WIDTH-1):0]  ddata_out);
-
+  output  reg [(DELAY_DATA_WIDTH-1):0]  ddata_out
+);
 
   // internal registers
 
@@ -85,6 +86,3 @@ module ad_mul #(
     .result (data_p));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/intel/jesd204_phy/jesd204_phy_glue.v b/library/intel/jesd204_phy/jesd204_phy_glue.v
index 8c8f4d58f..6dce1717c 100644
--- a/library/intel/jesd204_phy/jesd204_phy_glue.v
+++ b/library/intel/jesd204_phy/jesd204_phy_glue.v
@@ -49,8 +49,8 @@ module jesd204_phy_glue #(
 
 /* There really should be a standard component in Qsys that allows to do this */
 
-assign out = in;
-assign const_out = {CONST_WIDTH{1'b0}};
-assign polinv = LANE_INVERT[NUM_OF_LANES-1:0];
+  assign out = in;
+  assign const_out = {CONST_WIDTH{1'b0}};
+  assign polinv = LANE_INVERT[NUM_OF_LANES-1:0];
 
 endmodule
diff --git a/library/intel/util_clkdiv/util_clkdiv.v b/library/intel/util_clkdiv/util_clkdiv.v
index 318ad238e..acd334c63 100644
--- a/library/intel/util_clkdiv/util_clkdiv.v
+++ b/library/intel/util_clkdiv/util_clkdiv.v
@@ -41,39 +41,39 @@
 
 module util_clkdiv #(
   parameter SIM_DEVICE = "CYCLONE5",
-  parameter CLOCK_TYPE = "Global Clock") (
-
+  parameter CLOCK_TYPE = "Global Clock"
+) (
   input   clk,
   input   reset,
   output  clk_out,
   output  reset_out
- );
+);
 
-reg enable;
-reg reset_d1;
+  reg enable;
+  reg reset_d1;
 
-assign reset_out = reset | reset_d1;
+  assign reset_out = reset | reset_d1;
 
-always @(posedge clk) begin
-  reset_d1 <= reset;
-end
+  always @(posedge clk) begin
+    reset_d1 <= reset;
+  end
 
-always @(posedge clk) begin
-  enable <= ~enable;
-end
+  always @(posedge clk) begin
+    enable <= ~enable;
+  end
 
-generate if (SIM_DEVICE == "CYCLONE5") begin
-	cyclonev_clkena #(
-		.clock_type ("Global Clock"),
-		.ena_register_mode ("falling edge"),
-		.lpm_type ("cyclonev_clkena")
-  ) clock_divider_by_2 (
-	.ena(enable),
-	.enaout(),
-	.inclk(clk),
-//	.clkselect (2'b0),
-	.outclk(clk_out));
+  generate if (SIM_DEVICE == "CYCLONE5") begin
+    cyclonev_clkena #(
+      .clock_type ("Global Clock"),
+      .ena_register_mode ("falling edge"),
+      .lpm_type ("cyclonev_clkena")
+    ) clock_divider_by_2 (
+      .ena(enable),
+      .enaout(),
+      .inclk(clk),
+      // .clkselect (2'b0),
+      .outclk(clk_out));
 
-end endgenerate
+  end endgenerate
 
-endmodule  // util_clkdiv
+endmodule
diff --git a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.v b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.v
index 7621a2c26..ba326ad4f 100644
--- a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.v
+++ b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.v
@@ -40,6 +40,7 @@ module ad_ip_jesd204_tpl_adc #(
   parameter TWOS_COMPLEMENT = 1,
   parameter EXT_SYNC = 0
 ) (
+
   // jesd interface
   // link_clk is (line-rate/40)
   input link_clk,
@@ -177,8 +178,7 @@ module ad_ip_jesd204_tpl_adc #(
     .jesd_f (BYTES_PER_FRAME),
     .jesd_n (CONVERTER_RESOLUTION),
     .jesd_np (BITS_PER_SAMPLE),
-    .up_profile_sel ()
-  );
+    .up_profile_sel ());
 
   ad_ip_jesd204_tpl_adc_core #(
     .NUM_LANES (NUM_LANES),
@@ -218,9 +218,7 @@ module ad_ip_jesd204_tpl_adc #(
     .adc_sync_manual_req (adc_sync_manual_req_in),
     .adc_rst_sync (adc_rst_sync_s),
 
-
     .adc_valid (adc_valid),
-    .adc_data (adc_data)
-  );
+    .adc_data (adc_data));
 
 endmodule
diff --git a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_channel.v b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_channel.v
index 63da04c95..affeba06b 100644
--- a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_channel.v
+++ b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_channel.v
@@ -59,8 +59,7 @@ module ad_ip_jesd204_tpl_adc_channel #(
 
     .pn_seq_sel (pn_seq_sel),
     .pn_oos (pn_oos),
-    .pn_err (pn_err)
-  );
+    .pn_err (pn_err));
 
   generate
   genvar n;
@@ -78,8 +77,7 @@ module ad_ip_jesd204_tpl_adc_channel #(
 
       .dfmt_enable (dfmt_enable),
       .dfmt_type (dfmt_type),
-      .dfmt_se (dfmt_sign_extend)
-    );
+      .dfmt_se (dfmt_sign_extend));
   end
   endgenerate
 
diff --git a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_core.v b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_core.v
index d5f88e14e..75eb2ee88 100644
--- a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_core.v
+++ b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_core.v
@@ -94,8 +94,7 @@ module ad_ip_jesd204_tpl_adc_core #(
     .ext_sync_arm (adc_ext_sync_arm),
     .ext_sync_disarm (adc_ext_sync_disarm),
     .sync_in (adc_sync_in | adc_sync_manual_req),
-    .sync_armed (adc_sync_armed)
-  );
+    .sync_armed (adc_sync_armed));
 
   ad_ip_jesd204_tpl_adc_deframer #(
     .NUM_LANES (NUM_LANES),
@@ -111,8 +110,7 @@ module ad_ip_jesd204_tpl_adc_core #(
     .clk (clk),
     .link_sof (link_sof),
     .link_data (link_data),
-    .adc_data (raw_data_s)
-  );
+    .adc_data (raw_data_s));
 
   generate
   genvar i;
@@ -134,8 +132,7 @@ module ad_ip_jesd204_tpl_adc_core #(
 
       .pn_seq_sel (pn_seq_sel[i*4+:4]),
       .pn_err (pn_err[i]),
-      .pn_oos (pn_oos[i])
-    );
+      .pn_oos (pn_oos[i]));
   end
   endgenerate
 
diff --git a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_deframer.v b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_deframer.v
index d922a8ad8..197a10976 100644
--- a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_deframer.v
+++ b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_deframer.v
@@ -34,6 +34,7 @@ module ad_ip_jesd204_tpl_adc_deframer #(
   parameter LINK_DATA_WIDTH = OCTETS_PER_BEAT * 8 * NUM_LANES,
   parameter ADC_DATA_WIDTH = LINK_DATA_WIDTH * CONVERTER_RESOLUTION / BITS_PER_SAMPLE
 ) (
+
   // jesd interface
   // clk is (line-rate/40)
 
@@ -44,8 +45,7 @@ module ad_ip_jesd204_tpl_adc_deframer #(
    // adc data output
 
    output [ADC_DATA_WIDTH-1:0] adc_data
- );
-
+);
 
   localparam SAMPLES_PER_BEAT = ADC_DATA_WIDTH / CONVERTER_RESOLUTION;
   localparam BITS_PER_CHANNEL_PER_FRAME = BITS_PER_SAMPLE * SAMPLES_PER_FRAME;
@@ -75,8 +75,7 @@ module ad_ip_jesd204_tpl_adc_deframer #(
       .WORD_WIDTH (BITS_PER_LANE_PER_FRAME)
     ) i_lanes_to_frames (
       .data_in (link_data_msb_s),
-      .data_out (frame_data_s)
-    );
+      .data_out (frame_data_s));
 
     /* Slice frames into channels */
     ad_perfect_shuffle #(
@@ -85,8 +84,7 @@ module ad_ip_jesd204_tpl_adc_deframer #(
       .WORD_WIDTH (BITS_PER_CHANNEL_PER_FRAME)
     ) i_frames_to_channels (
       .data_in (frame_data_s),
-      .data_out (adc_data_msb)
-    );
+      .data_out (adc_data_msb));
 
     /* Reorder samples LSB first and remove tail bits */
     for (i = 0; i < SAMPLES_PER_BEAT; i = i + 1) begin: g_dac_data_msb
@@ -113,8 +111,7 @@ module ad_ip_jesd204_tpl_adc_deframer #(
       .rx_ip_sof (link_sof),
       .rx_ip_data (link_data[n*DW+:DW]),
       .rx_sof (),
-      .rx_data (link_data_s[n*DW+:DW])
-    );
+      .rx_data (link_data_s[n*DW+:DW]));
   end
   end else begin
     assign link_data_s = link_data;
diff --git a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_pnmon.v b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_pnmon.v
index 16b6cbe73..c0c9df446 100644
--- a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_pnmon.v
+++ b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_pnmon.v
@@ -104,7 +104,6 @@ module ad_ip_jesd204_tpl_adc_pnmon #(
     end
   end
 
-
   // pn oos & pn err
 
   ad_pnmon #(
@@ -115,7 +114,6 @@ module ad_ip_jesd204_tpl_adc_pnmon #(
     .adc_data_in (pn_data_in_s),
     .adc_data_pn (pn_data_pn[DW:0]),
     .adc_pn_oos (pn_oos),
-    .adc_pn_err (pn_err)
-  );
+    .adc_pn_err (pn_err));
 
 endmodule
diff --git a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v
index e08f3669b..125a11bff 100644
--- a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v
+++ b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v
@@ -34,6 +34,7 @@ module ad_ip_jesd204_tpl_adc_regmap #(
   parameter NUM_PROFILES = 1,    // Number of supported JESD profiles
   parameter EXT_SYNC = 0
 ) (
+
   // axi interface
   input s_axi_aclk,
   input s_axi_aresetn,
@@ -169,8 +170,7 @@ module ad_ip_jesd204_tpl_adc_regmap #(
     .up_rreq (up_rreq_s),
     .up_raddr (up_raddr_s),
     .up_rdata (up_rdata),
-    .up_rack (up_rack)
-  );
+    .up_rack (up_rack));
 
   integer n;
 
@@ -202,7 +202,6 @@ module ad_ip_jesd204_tpl_adc_regmap #(
   //
   localparam CONFIG = (EXT_SYNC << 12);
 
-
   up_adc_common #(
     .COMMON_ID (6'h0),
     .ID (ID),
@@ -261,8 +260,7 @@ module ad_ip_jesd204_tpl_adc_regmap #(
     .up_rreq (up_rreq_s),
     .up_raddr ({3'b0,up_raddr_s}),
     .up_rdata (up_rdata_s[0]),
-    .up_rack (up_rack_s[0])
-  );
+    .up_rack (up_rack_s[0]));
 
   generate
   genvar i;
@@ -319,16 +317,14 @@ module ad_ip_jesd204_tpl_adc_regmap #(
       .up_rreq (up_rreq_s),
       .up_raddr ({3'b0,up_raddr_s}),
       .up_rdata (up_rdata_s[i+1]),
-      .up_rack (up_rack_s[i+1])
-    );
+      .up_rack (up_rack_s[i+1]));
   end
   endgenerate
 
   up_tpl_common #(
-     .COMMON_ID(2'h0),            // Offset of regmap
-     .NUM_PROFILES(NUM_PROFILES)  // Number of JESD profiles
-    ) i_up_tpl_adc (
-
+    .COMMON_ID(2'h0),            // Offset of regmap
+    .NUM_PROFILES(NUM_PROFILES)  // Number of JESD profiles
+  ) i_up_tpl_adc (
     .jesd_m (jesd_m),
     .jesd_l (jesd_l),
     .jesd_s (jesd_s),
@@ -349,7 +345,6 @@ module ad_ip_jesd204_tpl_adc_regmap #(
     .up_rreq (up_rreq_s),
     .up_raddr (up_raddr_s),
     .up_rdata (up_rdata_s[NUM_CHANNELS+1]),
-    .up_rack (up_rack_s[NUM_CHANNELS+1])
-  );
+    .up_rack (up_rack_s[NUM_CHANNELS+1]));
 
 endmodule
diff --git a/library/jesd204/ad_ip_jesd204_tpl_common/up_tpl_common.v b/library/jesd204/ad_ip_jesd204_tpl_common/up_tpl_common.v
index c48fc466d..545155b00 100644
--- a/library/jesd204/ad_ip_jesd204_tpl_common/up_tpl_common.v
+++ b/library/jesd204/ad_ip_jesd204_tpl_common/up_tpl_common.v
@@ -38,10 +38,9 @@
 module up_tpl_common #(
 
   // parameters
-  parameter COMMON_ID = 2'h0,  // Offset of regmap
-  parameter NUM_PROFILES = 1   // Number of JESD profiles
-  )(
-
+  parameter COMMON_ID = 2'h0,   // Offset of regmap
+  parameter NUM_PROFILES = 1 // Number of JESD profiles
+) (
   input [NUM_PROFILES*8-1: 0] jesd_m,
   input [NUM_PROFILES*8-1: 0] jesd_l,
   input [NUM_PROFILES*8-1: 0] jesd_s,
@@ -88,7 +87,7 @@ module up_tpl_common #(
     if (up_rstn == 0) begin
       up_wack_int <= 'd0;
       up_profile_sel <= 'd0;
-   end else begin
+    end else begin
       up_wack_int <= up_wreq_s;
       if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h00)) begin
         up_profile_sel <= up_wdata[$clog2(NUM_PROFILES):0];
@@ -111,7 +110,7 @@ module up_tpl_common #(
         case (up_raddr[6:0])
           7'h00: up_rdata_int <= up_profile_sel;
           7'h01: up_rdata_int <= NUM_PROFILES;
-         default: up_rdata_int <= up_rdata_jesd_params;
+          default: up_rdata_int <= up_rdata_jesd_params;
         endcase
       end else begin
         up_rdata_int <= 32'd0;
@@ -136,6 +135,3 @@ module up_tpl_common #(
   end
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.v b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.v
index dd29f0628..5ebf90207 100644
--- a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.v
+++ b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.v
@@ -45,6 +45,7 @@ module ad_ip_jesd204_tpl_dac #(
   parameter EXT_SYNC = 0,
   parameter XBAR_ENABLE = 0
 ) (
+
   // jesd interface
   // link_clk is (line-rate/40)
 
@@ -202,8 +203,7 @@ module ad_ip_jesd204_tpl_dac #(
     .jesd_f (BYTES_PER_FRAME),
     .jesd_n (CONVERTER_RESOLUTION),
     .jesd_np (BITS_PER_SAMPLE),
-    .up_profile_sel ()
-  );
+    .up_profile_sel ());
 
   // core
 
@@ -259,9 +259,7 @@ module ad_ip_jesd204_tpl_dac #(
     .dac_iqcor_coeff_1 (dac_iqcor_coeff_1),
     .dac_iqcor_coeff_2 (dac_iqcor_coeff_2),
 
-    .dac_src_chan_sel (dac_src_chan_sel)
-
-  );
+    .dac_src_chan_sel (dac_src_chan_sel));
 
   // Drop DMA padding bits from the LSB or MSB based on configuration
   integer i;
diff --git a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_channel.v b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_channel.v
index cc03c453d..adb952613 100644
--- a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_channel.v
+++ b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_channel.v
@@ -34,6 +34,7 @@ module ad_ip_jesd204_tpl_dac_channel #(
   parameter DDS_CORDIC_PHASE_DW = 16,
   parameter Q_OR_I_N = 0
 ) (
+
   // dac interface
 
   input clk,
@@ -62,7 +63,7 @@ module ad_ip_jesd204_tpl_dac_channel #(
   input [15:0] dac_dds_incr_1,
 
   input [15:0] dac_pat_data_0,
-  input [15:0] dac_pat_data_1, 
+  input [15:0] dac_pat_data_1,
 
   input        dac_iqcor_enb,
   input [15:0] dac_iqcor_coeff_1,
@@ -124,7 +125,6 @@ module ad_ip_jesd204_tpl_dac_channel #(
     .iqcor_coeff_1 (dac_iqcor_coeff_1),
     .iqcor_coeff_2 (dac_iqcor_coeff_2));
 
-
   // dac data select
 
   always @(posedge clk) begin
@@ -144,15 +144,15 @@ module ad_ip_jesd204_tpl_dac_channel #(
 
   // dds
 
-    ad_dds #(
+  ad_dds #(
     .DISABLE (DATAPATH_DISABLE),
     .DDS_DW (CONVERTER_RESOLUTION),
     .PHASE_DW (16),
     .DDS_TYPE (DDS_TYPE),
     .CORDIC_DW (DDS_CORDIC_DW),
     .CORDIC_PHASE_DW (DDS_CORDIC_PHASE_DW),
-    .CLK_RATIO (DATA_PATH_WIDTH))
-  i_dds (
+    .CLK_RATIO (DATA_PATH_WIDTH)
+  ) i_dds (
     .clk (clk),
     .dac_dds_format (dac_dds_format),
     .dac_data_sync (dac_data_sync),
diff --git a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_core.v b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_core.v
index eeeeaae97..24ed27b8b 100644
--- a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_core.v
+++ b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_core.v
@@ -40,6 +40,7 @@ module ad_ip_jesd204_tpl_dac_core #(
   parameter DDS_CORDIC_PHASE_DW = 16,
   parameter EXT_SYNC = 0
 ) (
+
   // dac interface
   input clk,
 
@@ -108,8 +109,7 @@ module ad_ip_jesd204_tpl_dac_core #(
     .ext_sync_arm (dac_ext_sync_arm),
     .ext_sync_disarm (dac_ext_sync_disarm),
     .sync_in (dac_sync_in | dac_sync_manual_req),
-    .sync_armed (dac_sync_armed)
-  );
+    .sync_armed (dac_sync_armed));
 
   // Sync either from external or software source
   assign dac_sync_int = dac_sync_armed | dac_sync;
@@ -127,8 +127,7 @@ module ad_ip_jesd204_tpl_dac_core #(
     .DAC_DATA_WIDTH (DAC_DATA_WIDTH)
   ) i_framer (
     .link_data (link_data),
-    .dac_data (dac_data_s)
-  );
+    .dac_data (dac_data_s));
 
   // PN generator
   ad_ip_jesd204_tpl_dac_pn #(
@@ -139,15 +138,14 @@ module ad_ip_jesd204_tpl_dac_core #(
     .reset (dac_sync_int),
 
     .pn7_data (pn7_data),
-    .pn15_data (pn15_data)
-  );
+    .pn15_data (pn15_data));
 
   // dac valid
 
   assign dac_valid = {NUM_CHANNELS{~dac_sync_armed}};
   assign dac_rst = dac_sync_armed;
 
-  // Gate input data 
+  // Gate input data
   assign dac_ddata_int = dac_sync_armed ? {LINK_DATA_WIDTH{1'b0}} : dac_ddata;
 
   generate
@@ -171,8 +169,7 @@ module ad_ip_jesd204_tpl_dac_core #(
         .clk (clk),
         .data_in (dac_ddata_int),
         .ch_sel (dac_src_chan_sel[8*i+:8]),
-        .data_out (dac_ddata_muxed[DAC_CDW*i+:DAC_CDW])
-      );
+        .data_out (dac_ddata_muxed[DAC_CDW*i+:DAC_CDW]));
 
     end else begin
       assign dac_ddata_muxed[DAC_CDW*i+:DAC_CDW] = dac_ddata_int[DAC_CDW*i+:DAC_CDW];
@@ -216,9 +213,7 @@ module ad_ip_jesd204_tpl_dac_core #(
       .dac_iqcor_enb (dac_iqcor_enb[i]),
       .dac_iqcor_coeff_1 (dac_iqcor_coeff_1[16*i+:16]),
       .dac_iqcor_coeff_2 (dac_iqcor_coeff_2[16*i+:16]),
-      .dac_iqcor_data_in (dac_ddata_muxed[DAC_CDW*IQ_PAIR_CH_INDEX+:DAC_CDW])
-
-    );
+      .dac_iqcor_data_in (dac_ddata_muxed[DAC_CDW*IQ_PAIR_CH_INDEX+:DAC_CDW]));
   end
   endgenerate
 
diff --git a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_framer.v b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_framer.v
index 87843290c..9a84574cd 100644
--- a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_framer.v
+++ b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_framer.v
@@ -33,6 +33,7 @@ module ad_ip_jesd204_tpl_dac_framer #(
   parameter LINK_DATA_WIDTH = OCTETS_PER_BEAT * 8 * NUM_LANES,
   parameter DAC_DATA_WIDTH = LINK_DATA_WIDTH * CONVERTER_RESOLUTION / BITS_PER_SAMPLE
 ) (
+
   // jesd interface
 
   output [LINK_DATA_WIDTH-1:0] link_data,
@@ -123,8 +124,7 @@ module ad_ip_jesd204_tpl_dac_framer #(
       .WORD_WIDTH (BITS_PER_CHANNEL_PER_FRAME)
     ) i_channels_to_frames (
       .data_in (dac_data_msb),
-      .data_out (frame_data_s)
-    );
+      .data_out (frame_data_s));
 
     /* Slice frame and pack it into lanes */
     ad_perfect_shuffle #(
@@ -133,8 +133,7 @@ module ad_ip_jesd204_tpl_dac_framer #(
       .WORD_WIDTH (BITS_PER_LANE_PER_FRAME)
     ) i_frames_to_lanes (
       .data_in (frame_data_s),
-      .data_out (link_data_msb_s)
-    );
+      .data_out (link_data_msb_s));
 
     /* Reorder octets LSB first */
     for (i = 0; i < LINK_DATA_WIDTH; i = i + 8) begin: g_link_data
diff --git a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v
index 5888f01aa..16d24329e 100644
--- a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v
+++ b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v
@@ -113,7 +113,6 @@ module ad_ip_jesd204_tpl_dac_regmap #(
   reg [31:0] up_rdata = 32'h00;
   reg [31:0] up_rdata_all;
 
-
   wire up_wreq_s;
   wire [10:0] up_waddr_s;
   wire [31:0] up_wdata_s;
@@ -167,8 +166,7 @@ module ad_ip_jesd204_tpl_dac_regmap #(
     .up_rreq (up_rreq_s),
     .up_raddr (up_raddr_s),
     .up_rdata (up_rdata),
-    .up_rack (up_rack)
-  );
+    .up_rack (up_rack));
 
   integer n;
 
@@ -176,7 +174,7 @@ module ad_ip_jesd204_tpl_dac_regmap #(
     up_rdata_all = 'h00;
     for (n = 0; n < NUM_CHANNELS + 2; n = n + 1) begin
       up_rdata_all = up_rdata_all | up_rdata_s[n];
-     end
+    end
   end
 
   always @(posedge up_clk) begin
@@ -192,7 +190,7 @@ module ad_ip_jesd204_tpl_dac_regmap #(
   end
 
   // dac common processor interface
-  //
+
   localparam CONFIG = (EXT_SYNC << 12) |
                       (PADDING_TO_MSB_LSB_N << 11) |
                       (XBAR_ENABLE << 10) |
@@ -255,8 +253,7 @@ module ad_ip_jesd204_tpl_dac_regmap #(
     .up_rreq (up_rreq_s),
     .up_raddr ({3'b0,up_raddr_s}),
     .up_rdata (up_rdata_s[0]),
-    .up_rack (up_rack_s[0])
-  );
+    .up_rack (up_rack_s[0]));
 
   generate
   genvar i;
@@ -310,16 +307,14 @@ module ad_ip_jesd204_tpl_dac_regmap #(
       .up_rreq (up_rreq_s),
       .up_raddr ({3'b0,up_raddr_s}),
       .up_rdata (up_rdata_s[i+1]),
-      .up_rack (up_rack_s[i+1])
-    );
+      .up_rack (up_rack_s[i+1]));
   end
   endgenerate
 
   up_tpl_common #(
-     .COMMON_ID(2'h0),            // Offset of regmap
-     .NUM_PROFILES(NUM_PROFILES)  // Number of JESD profiles
-    ) i_up_tpl_dac (
-
+    .COMMON_ID(2'h0),            // Offset of regmap
+    .NUM_PROFILES(NUM_PROFILES)  // Number of JESD profiles
+  ) i_up_tpl_dac (
     .jesd_m (jesd_m),
     .jesd_l (jesd_l),
     .jesd_s (jesd_s),
@@ -340,7 +335,6 @@ module ad_ip_jesd204_tpl_dac_regmap #(
     .up_rreq (up_rreq_s),
     .up_raddr (up_raddr_s),
     .up_rdata (up_rdata_s[NUM_CHANNELS+1]),
-    .up_rack (up_rack_s[NUM_CHANNELS+1])
-  );
+    .up_rack (up_rack_s[NUM_CHANNELS+1]));
 
 endmodule
diff --git a/library/jesd204/axi_jesd204_common/jesd204_up_common.v b/library/jesd204/axi_jesd204_common/jesd204_up_common.v
index 8c00a5598..c0f6c58e8 100755
--- a/library/jesd204/axi_jesd204_common/jesd204_up_common.v
+++ b/library/jesd204/axi_jesd204_common/jesd204_up_common.v
@@ -44,7 +44,7 @@
 
 `timescale 1ns/100ps
 
-module jesd204_up_common # (
+module jesd204_up_common #(
   parameter PCORE_VERSION = 0,
   parameter PCORE_MAGIC = 0,
   parameter ID = 0,
@@ -104,335 +104,333 @@ module jesd204_up_common # (
   input [31:0] status_synth_params2
 );
 
-reg [31:0] up_scratch = 32'h00000000;
+  reg [31:0] up_scratch = 32'h00000000;
 
-reg [7:0] up_cfg_octets_per_frame = 'h00;
-reg [9:0] up_cfg_octets_per_multiframe = {DATA_PATH_WIDTH_LOG2{1'b1}};
-reg [7:0] up_cfg_beats_per_multiframe = 'h00;
-reg [NUM_LANES-1:0] up_cfg_lanes_disable = {NUM_LANES{1'b0}};
-reg [NUM_LINKS-1:0] up_cfg_links_disable = {NUM_LINKS{1'b0}};
-reg up_cfg_disable_char_replacement = 1'b0;
-reg up_cfg_disable_scrambler = 1'b0;
+  reg [7:0] up_cfg_octets_per_frame = 'h00;
+  reg [9:0] up_cfg_octets_per_multiframe = {DATA_PATH_WIDTH_LOG2{1'b1}};
+  reg [7:0] up_cfg_beats_per_multiframe = 'h00;
+  reg [NUM_LANES-1:0] up_cfg_lanes_disable = {NUM_LANES{1'b0}};
+  reg [NUM_LINKS-1:0] up_cfg_links_disable = {NUM_LINKS{1'b0}};
+  reg up_cfg_disable_char_replacement = 1'b0;
+  reg up_cfg_disable_scrambler = 1'b0;
 
-/* Reset for the register map */
-reg [2:0] up_reset_vector = 3'b111;
-assign up_reset = up_reset_vector[0];
+  /* Reset for the register map */
+  reg [2:0] up_reset_vector = 3'b111;
+  assign up_reset = up_reset_vector[0];
 
-/* Reset signal generation for the JESD core */
-reg [4:0] core_reset_vector = 5'b11111;
-assign core_reset = core_reset_vector[0];
+  /* Reset signal generation for the JESD core */
+  reg [4:0] core_reset_vector = 5'b11111;
+  assign core_reset = core_reset_vector[0];
 
-reg [4:0] device_reset_vector = 5'b11111;
-assign device_reset = device_reset_vector[0];
+  reg [4:0] device_reset_vector = 5'b11111;
+  assign device_reset = device_reset_vector[0];
 
-/* Transfer the reset signal back to the up domain, used to keep the
- * synchronizers in reset until the core is ready. This is done in order to
- * prevent bogus data to propagate to the register map. */
-reg [1:0] up_reset_synchronizer_vector = 2'b11;
-assign up_reset_synchronizer = up_reset_synchronizer_vector[0];
+  /* Transfer the reset signal back to the up domain, used to keep the
+   * synchronizers in reset until the core is ready. This is done in order to
+   * prevent bogus data to propagate to the register map. */
+  reg [1:0] up_reset_synchronizer_vector = 2'b11;
+  assign up_reset_synchronizer = up_reset_synchronizer_vector[0];
 
-/*
- * Synchronize the external core reset to the register map domain so the status
- * can be shown in the register map. This is useful for debugging.
- */
-reg [1:0] up_core_reset_ext_synchronizer_vector = 2'b11;
-wire up_core_reset_ext;
+  /*
+   * Synchronize the external core reset to the register map domain so the status
+   * can be shown in the register map. This is useful for debugging.
+   */
+  reg [1:0] up_core_reset_ext_synchronizer_vector = 2'b11;
+  wire up_core_reset_ext;
 
-assign up_core_reset_ext = up_core_reset_ext_synchronizer_vector[0];
+  assign up_core_reset_ext = up_core_reset_ext_synchronizer_vector[0];
 
-/* Transfer two cycles before the core comes out of reset */
-wire core_cfg_transfer_en;
-assign core_cfg_transfer_en = core_reset_vector[2] ^ core_reset_vector[1];
+  /* Transfer two cycles before the core comes out of reset */
+  wire core_cfg_transfer_en;
+  assign core_cfg_transfer_en = core_reset_vector[2] ^ core_reset_vector[1];
 
-wire device_cfg_transfer_en;
-assign device_cfg_transfer_en = device_reset_vector[2] ^ device_reset_vector[1];
+  wire device_cfg_transfer_en;
+  assign device_cfg_transfer_en = device_reset_vector[2] ^ device_reset_vector[1];
 
-reg up_reset_core = 1'b1;
+  reg up_reset_core = 1'b1;
 
-assign up_cfg_is_writeable = up_reset_core;
+  assign up_cfg_is_writeable = up_reset_core;
 
-always @(posedge up_clk or negedge ext_resetn) begin
-  if (ext_resetn == 1'b0) begin
-    up_reset_vector <= 3'b111;
-  end else begin
-    up_reset_vector <= {1'b0,up_reset_vector[2:1]};
+  always @(posedge up_clk or negedge ext_resetn) begin
+    if (ext_resetn == 1'b0) begin
+      up_reset_vector <= 3'b111;
+    end else begin
+      up_reset_vector <= {1'b0,up_reset_vector[2:1]};
+    end
   end
-end
 
-wire core_reset_all = up_reset_core | core_reset_ext;
+  wire core_reset_all = up_reset_core | core_reset_ext;
 
-always @(posedge core_clk or posedge core_reset_all) begin
-  if (core_reset_all == 1'b1) begin
-    core_reset_vector <= 5'b11111;
-  end else begin
-    core_reset_vector <= {1'b0,core_reset_vector[4:1]};
+  always @(posedge core_clk or posedge core_reset_all) begin
+    if (core_reset_all == 1'b1) begin
+      core_reset_vector <= 5'b11111;
+    end else begin
+      core_reset_vector <= {1'b0,core_reset_vector[4:1]};
+    end
   end
-end
 
-always @(posedge device_clk or posedge core_reset_all) begin
-  if (core_reset_all == 1'b1) begin
-    device_reset_vector <= 5'b11111;
-  end else begin
-    device_reset_vector <= {1'b0,device_reset_vector[4:1]};
+  always @(posedge device_clk or posedge core_reset_all) begin
+    if (core_reset_all == 1'b1) begin
+      device_reset_vector <= 5'b11111;
+    end else begin
+      device_reset_vector <= {1'b0,device_reset_vector[4:1]};
+    end
   end
-end
 
-always @(posedge up_clk or posedge core_reset) begin
-  if (core_reset == 1'b1) begin
-    up_reset_synchronizer_vector <= 2'b11;
-  end else begin
-    up_reset_synchronizer_vector <= {1'b0,up_reset_synchronizer_vector[1]};
+  always @(posedge up_clk or posedge core_reset) begin
+    if (core_reset == 1'b1) begin
+      up_reset_synchronizer_vector <= 2'b11;
+    end else begin
+      up_reset_synchronizer_vector <= {1'b0,up_reset_synchronizer_vector[1]};
+    end
   end
-end
 
-always @(posedge up_clk or posedge core_reset_ext) begin
-  if (core_reset_ext == 1'b1) begin
-    up_core_reset_ext_synchronizer_vector <= 2'b11;
-  end else begin
-    up_core_reset_ext_synchronizer_vector <= {1'b0,up_core_reset_ext_synchronizer_vector[1]};
+  always @(posedge up_clk or posedge core_reset_ext) begin
+    if (core_reset_ext == 1'b1) begin
+      up_core_reset_ext_synchronizer_vector <= 2'b11;
+    end else begin
+      up_core_reset_ext_synchronizer_vector <= {1'b0,up_core_reset_ext_synchronizer_vector[1]};
+    end
   end
-end
 
-always @(posedge core_clk) begin
-  if (core_cfg_transfer_en == 1'b1) begin
-    core_cfg_octets_per_multiframe <= up_cfg_octets_per_multiframe;
-    core_cfg_octets_per_frame <= up_cfg_octets_per_frame;
-    core_cfg_lanes_disable <= up_cfg_lanes_disable;
-    core_cfg_links_disable <= up_cfg_links_disable;
-    core_cfg_disable_scrambler <= up_cfg_disable_scrambler;
-    core_cfg_disable_char_replacement <= up_cfg_disable_char_replacement;
-    core_extra_cfg <= up_extra_cfg;
+  always @(posedge core_clk) begin
+    if (core_cfg_transfer_en == 1'b1) begin
+      core_cfg_octets_per_multiframe <= up_cfg_octets_per_multiframe;
+      core_cfg_octets_per_frame <= up_cfg_octets_per_frame;
+      core_cfg_lanes_disable <= up_cfg_lanes_disable;
+      core_cfg_links_disable <= up_cfg_links_disable;
+      core_cfg_disable_scrambler <= up_cfg_disable_scrambler;
+      core_cfg_disable_char_replacement <= up_cfg_disable_char_replacement;
+      core_extra_cfg <= up_extra_cfg;
+    end
   end
-end
 
-always @(posedge device_clk) begin
-  if (device_cfg_transfer_en == 1'b1) begin
-    device_cfg_octets_per_multiframe <= up_cfg_octets_per_multiframe;
-    device_cfg_octets_per_frame <= up_cfg_octets_per_frame;
-    device_cfg_beats_per_multiframe <= up_cfg_beats_per_multiframe;
-    device_extra_cfg <= up_dev_extra_cfg;
+  always @(posedge device_clk) begin
+    if (device_cfg_transfer_en == 1'b1) begin
+      device_cfg_octets_per_multiframe <= up_cfg_octets_per_multiframe;
+      device_cfg_octets_per_frame <= up_cfg_octets_per_frame;
+      device_cfg_beats_per_multiframe <= up_cfg_beats_per_multiframe;
+      device_extra_cfg <= up_dev_extra_cfg;
+    end
   end
-end
 
-/* Interupt handling */
-reg [NUM_IRQS-1:0] up_irq_enable = {NUM_IRQS{1'b0}};
-reg [NUM_IRQS-1:0] up_irq_source = 'h00;
-reg [NUM_IRQS-1:0] up_irq_clear;
-wire [NUM_IRQS-1:0] up_irq_pending;
+  /* Interupt handling */
+  reg [NUM_IRQS-1:0] up_irq_enable = {NUM_IRQS{1'b0}};
+  reg [NUM_IRQS-1:0] up_irq_source = 'h00;
+  reg [NUM_IRQS-1:0] up_irq_clear;
+  wire [NUM_IRQS-1:0] up_irq_pending;
 
-assign up_irq_pending = up_irq_source & up_irq_enable;
-
-always @(posedge up_clk) begin
-  if (up_reset == 1'b1) begin
-    irq <= 1'b0;
-  end else begin
-    irq <= |up_irq_pending;
-  end
-end
-
-always @(posedge up_clk) begin
-  if (up_reset == 1'b1) begin
-    up_irq_source <= 'h00;
-  end else begin
-    up_irq_source <= (up_irq_source & ~up_irq_clear) | up_irq_trigger;
-  end
-end
-
-/* Count link enable */
-wire [8*16-1:0] up_irq_event_cnt_bus;
-wire [15:0] up_link_enable_cnt_s;
-
-genvar i;
-generate if (ENABLE_LINK_STATS == 1) begin : g_link_stats
-
-  reg [15:0] up_link_enable_cnt = 'h0;
-  reg up_reset_core_d1 = 'b1;
-
-  wire up_stat_clear;
-
-  assign up_stat_clear = (up_waddr == 12'h0b0 && up_wreq && up_wdata[0]);
+  assign up_irq_pending = up_irq_source & up_irq_enable;
 
   always @(posedge up_clk) begin
-    up_reset_core_d1 <= up_reset_core;
-    if (up_stat_clear) begin
-      up_link_enable_cnt <= 'h0;
+    if (up_reset == 1'b1) begin
+      irq <= 1'b0;
     end else begin
-      if (~up_reset_core & up_reset_core_d1) begin
-        up_link_enable_cnt <= up_link_enable_cnt + 16'd1;
-      end
+      irq <= |up_irq_pending;
     end
   end
-  assign up_link_enable_cnt_s = up_link_enable_cnt;
 
-  /* Count IRQ events for max 8 interrupt sources */
+  always @(posedge up_clk) begin
+    if (up_reset == 1'b1) begin
+      up_irq_source <= 'h00;
+    end else begin
+      up_irq_source <= (up_irq_source & ~up_irq_clear) | up_irq_trigger;
+    end
+  end
 
-  for (i = 0; i < NUM_IRQS; i=i+1) begin : irq_cnt
+  /* Count link enable */
+  wire [8*16-1:0] up_irq_event_cnt_bus;
+  wire [15:0] up_link_enable_cnt_s;
 
-    reg [15:0] up_irq_event_cnt = 'h0;
+  genvar i;
+  generate if (ENABLE_LINK_STATS == 1) begin : g_link_stats
+
+    reg [15:0] up_link_enable_cnt = 'h0;
+    reg up_reset_core_d1 = 'b1;
+
+    wire up_stat_clear;
+
+    assign up_stat_clear = (up_waddr == 12'h0b0 && up_wreq && up_wdata[0]);
 
     always @(posedge up_clk) begin
+      up_reset_core_d1 <= up_reset_core;
       if (up_stat_clear) begin
-        up_irq_event_cnt <= 'h0;
-      end else if (up_irq_trigger[i]) begin
-        up_irq_event_cnt <= up_irq_event_cnt + 16'd1;
+        up_link_enable_cnt <= 'h0;
+      end else begin
+        if (~up_reset_core & up_reset_core_d1) begin
+          up_link_enable_cnt <= up_link_enable_cnt + 16'd1;
+        end
       end
     end
 
-    assign up_irq_event_cnt_bus[i*16 +: 16] = up_irq_event_cnt;
+    assign up_link_enable_cnt_s = up_link_enable_cnt;
 
+    /* Count IRQ events for max 8 interrupt sources */
+
+    for (i = 0; i < NUM_IRQS; i=i+1) begin : irq_cnt
+
+      reg [15:0] up_irq_event_cnt = 'h0;
+
+      always @(posedge up_clk) begin
+        if (up_stat_clear) begin
+          up_irq_event_cnt <= 'h0;
+        end else if (up_irq_trigger[i]) begin
+          up_irq_event_cnt <= up_irq_event_cnt + 16'd1;
+        end
+      end
+
+      assign up_irq_event_cnt_bus[i*16 +: 16] = up_irq_event_cnt;
+
+    end
+  end else begin : g_no_link_stats
+    assign up_irq_event_cnt_bus = 'h0;
+    assign up_link_enable_cnt_s = 'h0;
   end
-end else begin : g_no_link_stats
-  assign up_irq_event_cnt_bus = 'h0;
-  assign up_link_enable_cnt_s = 'h0;
-end
-endgenerate
+  endgenerate
 
-wire [20:0] clk_mon_count;
-wire [20:0] device_clk_mon_count;
+  wire [20:0] clk_mon_count;
+  wire [20:0] device_clk_mon_count;
 
-always @(*) begin
-  case (up_raddr)
-  /* Standard registers */
-  12'h000: up_rdata = PCORE_VERSION;
-  12'h001: up_rdata = ID;
-  12'h002: up_rdata = up_scratch;
-  12'h003: up_rdata = PCORE_MAGIC;
+  always @(*) begin
+    case (up_raddr)
+      /* Standard registers */
+      12'h000: up_rdata = PCORE_VERSION;
+      12'h001: up_rdata = ID;
+      12'h002: up_rdata = up_scratch;
+      12'h003: up_rdata = PCORE_MAGIC;
 
-  /* Core configuration */
-  12'h004: up_rdata = status_synth_params0;
-  12'h005: up_rdata = status_synth_params1;
-  12'h006: up_rdata = status_synth_params2;
-  /* 0x07-0x0f reserved for future use */
-  /* 0x10-0x1f reserved for core specific HDL configuration information */
+      /* Core configuration */
+      12'h004: up_rdata = status_synth_params0;
+      12'h005: up_rdata = status_synth_params1;
+      12'h006: up_rdata = status_synth_params2;
+      /* 0x07-0x0f reserved for future use */
+      /* 0x10-0x1f reserved for core specific HDL configuration information */
 
-  /* IRQ block */
-  12'h020: up_rdata = up_irq_enable;
-  12'h021: up_rdata = up_irq_pending;
-  12'h022: up_rdata = up_irq_source;
-  /* 0x23-0x30 reserved for future use */
+      /* IRQ block */
+      12'h020: up_rdata = up_irq_enable;
+      12'h021: up_rdata = up_irq_pending;
+      12'h022: up_rdata = up_irq_source;
+      /* 0x23-0x30 reserved for future use */
 
-  /* JESD common control */
-  12'h030: up_rdata = up_reset_core;
-  12'h031: up_rdata = {up_core_reset_ext, up_reset_synchronizer}; /* core ready */
-  12'h032: up_rdata = {11'h00, clk_mon_count}; /* Make it 16.16 */
-  12'h033: up_rdata = {11'h00, device_clk_mon_count}; /* Make it 16.16 */
-  /* 0x34-0x34 reserver for future use */
+      /* JESD common control */
+      12'h030: up_rdata = up_reset_core;
+      12'h031: up_rdata = {up_core_reset_ext, up_reset_synchronizer}; /* core ready */
+      12'h032: up_rdata = {11'h00, clk_mon_count}; /* Make it 16.16 */
+      12'h033: up_rdata = {11'h00, device_clk_mon_count}; /* Make it 16.16 */
+      /* 0x34-0x34 reserver for future use */
 
-  12'h080: up_rdata = up_cfg_lanes_disable;
-  /* 0x82-0x83 reserved for future lane disable bits (max 128 lanes) */
-  12'h084: up_rdata = {
-    /* 24-31 */ 8'h00, /* Reserved for future extensions of octets_per_frame */
-    /* 16-23 */ up_cfg_octets_per_frame,
-    /* 10-15 */ 6'b000000, /* Reserved for future extensions of beats_per_multiframe */
-    /* 00-09 */ up_cfg_octets_per_multiframe
-  };
-  12'h85: up_rdata = {
-    /* 02-31 */ 30'h00, /* Reserved for future additions */
-    /*    01 */ up_cfg_disable_char_replacement, /* Disable character replacement */
-    /*    00 */ up_cfg_disable_scrambler /* Disable scrambler */
-  };
-  12'h086: up_rdata = up_cfg_links_disable;
-  12'h087: up_rdata = up_cfg_beats_per_multiframe;
-  /* 0x88-0x8f reserved for future use */
+      12'h080: up_rdata = up_cfg_lanes_disable;
+      /* 0x82-0x83 reserved for future lane disable bits (max 128 lanes) */
+      12'h084: up_rdata = {
+        /* 24-31 */ 8'h00, /* Reserved for future extensions of octets_per_frame */
+        /* 16-23 */ up_cfg_octets_per_frame,
+        /* 10-15 */ 6'b000000, /* Reserved for future extensions of beats_per_multiframe */
+        /* 00-09 */ up_cfg_octets_per_multiframe
+      };
+      12'h85: up_rdata = {
+        /* 02-31 */ 30'h00, /* Reserved for future additions */
+        /*    01 */ up_cfg_disable_char_replacement, /* Disable character replacement */
+        /*    00 */ up_cfg_disable_scrambler /* Disable scrambler */
+      };
+      12'h086: up_rdata = up_cfg_links_disable;
+      12'h087: up_rdata = up_cfg_beats_per_multiframe;
+      /* 0x88-0x8f reserved for future use */
 
-  /* 0x90-0x9f reserved for core specific configuration options */
+      /* 0x90-0x9f reserved for core specific configuration options */
 
-  /* 0xb0 Stat control */
-  12'h0b1: up_rdata = up_link_enable_cnt_s;
-  /* 0xb4-0xb7 IRQ Stat, max 8 interrupt sources */
-  12'h0b4: up_rdata = up_irq_event_cnt_bus[0*32 +: 32];
-  12'h0b5: up_rdata = up_irq_event_cnt_bus[1*32 +: 32];
-  12'h0b6: up_rdata = up_irq_event_cnt_bus[2*32 +: 32];
-  12'h0b7: up_rdata = up_irq_event_cnt_bus[3*32 +: 32];
-
-  default: up_rdata = 'h00;
-  endcase
-end
-
-/* IRQ pending register is write-1-to-clear */
-always @(*) begin
-  if (up_wreq == 1'b1 && up_waddr == 12'h21) begin
-    up_irq_clear = up_wdata[NUM_IRQS-1:0];
-  end else begin
-    up_irq_clear = {NUM_IRQS{1'b0}};
-  end
-end
-
-always @(posedge up_clk) begin
-  if (up_reset == 1'b1) begin
-    up_scratch <= 'h00;
-    up_irq_enable <= {NUM_IRQS{1'b0}};
-    up_reset_core <= 1'b1;
-
-    up_cfg_octets_per_frame <= 'h00;
-    up_cfg_octets_per_multiframe <= {DATA_PATH_WIDTH_LOG2{1'b1}};
-    up_cfg_lanes_disable <= {NUM_LANES{1'b0}};
-    up_cfg_links_disable <= {NUM_LINKS{1'b0}};
-    up_cfg_beats_per_multiframe <= 'h00;
-
-    up_cfg_disable_char_replacement <= 1'b0;
-    up_cfg_disable_scrambler <= 1'b0;
-  end else if (up_wreq == 1'b1) begin
-    case (up_waddr)
-    /* Standard registers */
-    12'h002: up_scratch <= up_wdata;
-
-    /* IRQ block */
-    12'h020: up_irq_enable <= up_wdata[NUM_IRQS-1:0];
-
-    /* JESD common control */
-    12'h030: up_reset_core <= up_wdata[0];
+      /* 0xb0 Stat control */
+      12'h0b1: up_rdata = up_link_enable_cnt_s;
+      /* 0xb4-0xb7 IRQ Stat, max 8 interrupt sources */
+      12'h0b4: up_rdata = up_irq_event_cnt_bus[0*32 +: 32];
+      12'h0b5: up_rdata = up_irq_event_cnt_bus[1*32 +: 32];
+      12'h0b6: up_rdata = up_irq_event_cnt_bus[2*32 +: 32];
+      12'h0b7: up_rdata = up_irq_event_cnt_bus[3*32 +: 32];
 
+      default: up_rdata = 'h00;
     endcase
+  end
 
-    /*
-     * The configuration needs to be static while the core is
-     * active. To enforce this writes to configuration registers
-     * will be ignored while the core is out of reset.
-     */
-    if (up_cfg_is_writeable == 1'b1) begin
-      case (up_waddr)
-      12'h080: begin
-        up_cfg_lanes_disable <= up_wdata[NUM_LANES-1:0];
-      end
-      12'h084: begin
-        up_cfg_octets_per_frame <= up_wdata[23:16];
-        up_cfg_octets_per_multiframe <= {up_wdata[9:DATA_PATH_WIDTH_LOG2],
-                                        {DATA_PATH_WIDTH_LOG2{1'b1}}};
-      end
-      12'h085: begin
-        up_cfg_disable_char_replacement <= up_wdata[1];
-        up_cfg_disable_scrambler <= up_wdata[0];
-      end
-      12'h086: begin
-        up_cfg_links_disable <= up_wdata[NUM_LINKS-1:0];
-      end
-      12'h087: begin
-        up_cfg_beats_per_multiframe <= up_wdata[7:0];
-      end
-      endcase
+  /* IRQ pending register is write-1-to-clear */
+  always @(*) begin
+    if (up_wreq == 1'b1 && up_waddr == 12'h21) begin
+      up_irq_clear = up_wdata[NUM_IRQS-1:0];
+    end else begin
+      up_irq_clear = {NUM_IRQS{1'b0}};
     end
   end
-end
 
-up_clock_mon #(
-  .TOTAL_WIDTH(21)
-) i_clock_mon (
-  .up_rstn(~up_reset),
-  .up_clk(up_clk),
-  .up_d_count(clk_mon_count),
-  .d_rst(1'b0),
-  .d_clk(core_clk)
-);
+  always @(posedge up_clk) begin
+    if (up_reset == 1'b1) begin
+      up_scratch <= 'h00;
+      up_irq_enable <= {NUM_IRQS{1'b0}};
+      up_reset_core <= 1'b1;
 
-up_clock_mon #(
-  .TOTAL_WIDTH(21)
-) i_dev_clock_mon (
-  .up_rstn(~up_reset),
-  .up_clk(up_clk),
-  .up_d_count(device_clk_mon_count),
-  .d_rst(1'b0),
-  .d_clk(device_clk)
-);
+      up_cfg_octets_per_frame <= 'h00;
+      up_cfg_octets_per_multiframe <= {DATA_PATH_WIDTH_LOG2{1'b1}};
+      up_cfg_lanes_disable <= {NUM_LANES{1'b0}};
+      up_cfg_links_disable <= {NUM_LINKS{1'b0}};
+      up_cfg_beats_per_multiframe <= 'h00;
+
+      up_cfg_disable_char_replacement <= 1'b0;
+      up_cfg_disable_scrambler <= 1'b0;
+    end else if (up_wreq == 1'b1) begin
+      case (up_waddr)
+        /* Standard registers */
+        12'h002: up_scratch <= up_wdata;
+
+        /* IRQ block */
+        12'h020: up_irq_enable <= up_wdata[NUM_IRQS-1:0];
+
+        /* JESD common control */
+        12'h030: up_reset_core <= up_wdata[0];
+      endcase
+
+      /*
+       * The configuration needs to be static while the core is
+       * active. To enforce this writes to configuration registers
+       * will be ignored while the core is out of reset.
+       */
+      if (up_cfg_is_writeable == 1'b1) begin
+        case (up_waddr)
+          12'h080: begin
+            up_cfg_lanes_disable <= up_wdata[NUM_LANES-1:0];
+          end
+          12'h084: begin
+            up_cfg_octets_per_frame <= up_wdata[23:16];
+            up_cfg_octets_per_multiframe <= {up_wdata[9:DATA_PATH_WIDTH_LOG2],
+                                            {DATA_PATH_WIDTH_LOG2{1'b1}}};
+          end
+          12'h085: begin
+            up_cfg_disable_char_replacement <= up_wdata[1];
+            up_cfg_disable_scrambler <= up_wdata[0];
+          end
+          12'h086: begin
+            up_cfg_links_disable <= up_wdata[NUM_LINKS-1:0];
+          end
+          12'h087: begin
+            up_cfg_beats_per_multiframe <= up_wdata[7:0];
+          end
+        endcase
+      end
+    end
+  end
+
+  up_clock_mon #(
+    .TOTAL_WIDTH(21)
+  ) i_clock_mon (
+    .up_rstn(~up_reset),
+    .up_clk(up_clk),
+    .up_d_count(clk_mon_count),
+    .d_rst(1'b0),
+    .d_clk(core_clk));
+
+  up_clock_mon #(
+    .TOTAL_WIDTH(21)
+  ) i_dev_clock_mon (
+    .up_rstn(~up_reset),
+    .up_clk(up_clk),
+    .up_d_count(device_clk_mon_count),
+    .d_rst(1'b0),
+    .d_clk(device_clk));
 
 endmodule
diff --git a/library/jesd204/axi_jesd204_common/jesd204_up_sysref.v b/library/jesd204/axi_jesd204_common/jesd204_up_sysref.v
index 9e402b2f6..e128f20cf 100755
--- a/library/jesd204/axi_jesd204_common/jesd204_up_sysref.v
+++ b/library/jesd204/axi_jesd204_common/jesd204_up_sysref.v
@@ -71,77 +71,76 @@ module jesd204_up_sysref #(
   input device_event_sysref_edge
 );
 
-reg [1:0] up_sysref_status;
-reg [1:0] up_sysref_status_clear;
-wire [1:0] up_sysref_event;
+  reg [1:0] up_sysref_status;
+  reg [1:0] up_sysref_status_clear;
+  wire [1:0] up_sysref_event;
 
-sync_event #(
-  .NUM_OF_EVENTS(2)
-) i_cdc_sysref_event (
-  .in_clk(device_clk),
-  .in_event({
-    device_event_sysref_alignment_error,
-    device_event_sysref_edge
-  }),
-  .out_clk(up_clk),
-  .out_event(up_sysref_event)
-);
+  sync_event #(
+    .NUM_OF_EVENTS(2)
+  ) i_cdc_sysref_event (
+    .in_clk(device_clk),
+    .in_event({
+      device_event_sysref_alignment_error,
+      device_event_sysref_edge
+    }),
+    .out_clk(up_clk),
+    .out_event(up_sysref_event));
 
-always @(posedge up_clk) begin
-  if (up_reset == 1'b1) begin
-    up_sysref_status <= 2'b00;
-  end else begin
-    up_sysref_status <= (up_sysref_status & ~up_sysref_status_clear) | up_sysref_event;
+  always @(posedge up_clk) begin
+    if (up_reset == 1'b1) begin
+      up_sysref_status <= 2'b00;
+    end else begin
+      up_sysref_status <= (up_sysref_status & ~up_sysref_status_clear) | up_sysref_event;
+    end
   end
-end
 
-always @(*) begin
-  case (up_raddr)
-  /* JESD SYSREF configuraton */
-  12'h040: up_rdata = {
-    /* 02-31 */ 30'h00, /* Reserved for future use */
-    /*    01 */ up_cfg_sysref_oneshot,
-    /*    00 */ up_cfg_sysref_disable
-  };
-  12'h041: up_rdata = {
-    /* 10-31 */ 22'h00, /* Reserved for future use */
-    /* 02-09 */ up_cfg_lmfc_offset,
-    /* 00-01 */ 2'b00 /* data path alignment for cfg_lmfc_offset */
-  };
-  12'h042: up_rdata = {
-    /* 02-31 */ 30'h00,
-    /* 00-01 */ up_sysref_status
-  };
-  default: up_rdata = 32'h00000000;
-  endcase
-end
-
-always @(posedge up_clk) begin
-  if (up_reset == 1'b1) begin
-    up_cfg_sysref_oneshot <= 1'b0;
-    up_cfg_lmfc_offset <= 'h00;
-    up_cfg_sysref_disable <= 1'b0;
-  end else if (up_wreq == 1'b1 && up_cfg_is_writeable == 1'b1) begin
-    case (up_waddr)
-    /* JESD SYSREF configuraton */
-    12'h040: begin
-      up_cfg_sysref_oneshot <= up_wdata[1];
-      up_cfg_sysref_disable <= up_wdata[0];
-    end
-    12'h041: begin
-      /* Must be aligned to data path width */
-      up_cfg_lmfc_offset <= up_wdata;
-    end
+  always @(*) begin
+    case (up_raddr)
+      /* JESD SYSREF configuraton */
+      12'h040: up_rdata = {
+        /* 02-31 */ 30'h00, /* Reserved for future use */
+        /*    01 */ up_cfg_sysref_oneshot,
+        /*    00 */ up_cfg_sysref_disable
+      };
+      12'h041: up_rdata = {
+        /* 10-31 */ 22'h00, /* Reserved for future use */
+        /* 02-09 */ up_cfg_lmfc_offset,
+        /* 00-01 */ 2'b00 /* data path alignment for cfg_lmfc_offset */
+      };
+      12'h042: up_rdata = {
+        /* 02-31 */ 30'h00,
+        /* 00-01 */ up_sysref_status
+      };
+      default: up_rdata = 32'h00000000;
     endcase
   end
-end
 
-always @(*) begin
-  if (up_wreq == 1'b1 && up_waddr == 12'h042) begin
-    up_sysref_status_clear = up_wdata[1:0];
-  end else begin
-    up_sysref_status_clear = 2'b00;
+  always @(posedge up_clk) begin
+    if (up_reset == 1'b1) begin
+      up_cfg_sysref_oneshot <= 1'b0;
+      up_cfg_lmfc_offset <= 'h00;
+      up_cfg_sysref_disable <= 1'b0;
+    end else if (up_wreq == 1'b1 && up_cfg_is_writeable == 1'b1) begin
+      case (up_waddr)
+        /* JESD SYSREF configuraton */
+        12'h040: begin
+          up_cfg_sysref_oneshot <= up_wdata[1];
+          up_cfg_sysref_disable <= up_wdata[0];
+        end
+        12'h041: begin
+          /* Must be aligned to data path width */
+          up_cfg_lmfc_offset <= up_wdata;
+        end
+      endcase
+    end
+  end
+
+  always @(*) begin
+    if (up_wreq == 1'b1 && up_waddr == 12'h042) begin
+      up_sysref_status_clear = up_wdata[1:0];
+    end else begin
+      up_sysref_status_clear = 2'b00;
+    end
   end
-end
 
 endmodule
diff --git a/library/jesd204/axi_jesd204_rx/axi_jesd204_rx.v b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx.v
index 797570bf2..c13fe4f8e 100755
--- a/library/jesd204/axi_jesd204_rx/axi_jesd204_rx.v
+++ b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx.v
@@ -127,239 +127,233 @@ module axi_jesd204_rx #(
   input [31:0] status_synth_params2
 );
 
-localparam PCORE_VERSION = 32'h00010761; // 1.07.a
-localparam PCORE_MAGIC = 32'h32303452; // 204R
+  localparam PCORE_VERSION = 32'h00010761; // 1.07.a
+  localparam PCORE_MAGIC = 32'h32303452; // 204R
 
-localparam DATA_PATH_WIDTH_LOG2 = (DATA_PATH_WIDTH == 8) ? 3 : 2;
+  localparam DATA_PATH_WIDTH_LOG2 = (DATA_PATH_WIDTH == 8) ? 3 : 2;
 
-/* Register interface signals */
-reg [31:0] up_rdata = 'h0;
-reg up_wack = 1'b0;
-reg up_rack = 1'b0;
-reg up_rreq_d1 = 1'b0;
-wire up_wreq;
-wire up_rreq;
-wire [31:0] up_wdata;
-wire [11:0] up_waddr;
-wire [11:0] up_raddr;
-wire [31:0] up_rdata_common;
-wire [31:0] up_rdata_sysref;
-wire [31:0] up_rdata_rx;
+  /* Register interface signals */
+  reg [31:0] up_rdata = 'h0;
+  reg up_wack = 1'b0;
+  reg up_rack = 1'b0;
+  reg up_rreq_d1 = 1'b0;
+  wire up_wreq;
+  wire up_rreq;
+  wire [31:0] up_wdata;
+  wire [11:0] up_waddr;
+  wire [11:0] up_raddr;
+  wire [31:0] up_rdata_common;
+  wire [31:0] up_rdata_sysref;
+  wire [31:0] up_rdata_rx;
 
-wire [4:0] up_irq_trigger;
+  wire [4:0] up_irq_trigger;
 
-wire up_cfg_is_writeable;
-wire up_cfg_sysref_oneshot;
-wire up_cfg_sysref_disable;
-wire up_cfg_buffer_early_release;
-wire [7:0] up_cfg_buffer_delay;
-wire [7:0] up_cfg_lmfc_offset;
-wire [7:0] up_cfg_frame_align_err_threshold;
+  wire up_cfg_is_writeable;
+  wire up_cfg_sysref_oneshot;
+  wire up_cfg_sysref_disable;
+  wire up_cfg_buffer_early_release;
+  wire [7:0] up_cfg_buffer_delay;
+  wire [7:0] up_cfg_lmfc_offset;
+  wire [7:0] up_cfg_frame_align_err_threshold;
 
-wire up_reset;
-wire up_reset_synchronizer;
-wire up_event_frame_alignment_error;
-wire up_event_unexpected_lane_state_error;
+  wire up_reset;
+  wire up_reset_synchronizer;
+  wire up_event_frame_alignment_error;
+  wire up_event_unexpected_lane_state_error;
 
-sync_event #(
-  .NUM_OF_EVENTS (2)
-) i_sync_frame_align_err (
-  .in_clk(core_clk),
-  .in_event({core_event_unexpected_lane_state_error,
-             core_event_frame_alignment_error}),
-  .out_clk(s_axi_aclk),
-  .out_event({up_event_unexpected_lane_state_error,
-              up_event_frame_alignment_error})
-);
+  sync_event #(
+    .NUM_OF_EVENTS (2)
+  ) i_sync_frame_align_err (
+    .in_clk(core_clk),
+    .in_event({core_event_unexpected_lane_state_error,
+               core_event_frame_alignment_error}),
+    .out_clk(s_axi_aclk),
+    .out_event({up_event_unexpected_lane_state_error,
+                up_event_frame_alignment_error}));
 
-assign up_irq_trigger = {3'b0,
-                         up_event_unexpected_lane_state_error,
-                         up_event_frame_alignment_error} &
-                        {5{~up_cfg_is_writeable}};
+  assign up_irq_trigger = {3'b0,
+                           up_event_unexpected_lane_state_error,
+                           up_event_frame_alignment_error} &
+                          {5{~up_cfg_is_writeable}};
 
-up_axi #(
-  .AXI_ADDRESS_WIDTH (14)
-) i_up_axi (
-  .up_rstn(~up_reset),
-  .up_clk(s_axi_aclk),
-  .up_axi_awvalid(s_axi_awvalid),
-  .up_axi_awaddr(s_axi_awaddr),
-  .up_axi_awready(s_axi_awready),
-  .up_axi_wvalid(s_axi_wvalid),
-  .up_axi_wdata(s_axi_wdata),
-  .up_axi_wstrb(s_axi_wstrb),
-  .up_axi_wready(s_axi_wready),
-  .up_axi_bvalid(s_axi_bvalid),
-  .up_axi_bresp(s_axi_bresp),
-  .up_axi_bready(s_axi_bready),
-  .up_axi_arvalid(s_axi_arvalid),
-  .up_axi_araddr(s_axi_araddr),
-  .up_axi_arready(s_axi_arready),
-  .up_axi_rvalid(s_axi_rvalid),
-  .up_axi_rresp(s_axi_rresp),
-  .up_axi_rdata(s_axi_rdata),
-  .up_axi_rready(s_axi_rready),
-  .up_wreq(up_wreq),
-  .up_waddr(up_waddr),
-  .up_wdata(up_wdata),
-  .up_wack(up_wack),
-  .up_rreq(up_rreq),
-  .up_raddr(up_raddr),
-  .up_rdata(up_rdata),
-  .up_rack(up_rack)
-);
+  up_axi #(
+    .AXI_ADDRESS_WIDTH (14)
+  ) i_up_axi (
+    .up_rstn(~up_reset),
+    .up_clk(s_axi_aclk),
+    .up_axi_awvalid(s_axi_awvalid),
+    .up_axi_awaddr(s_axi_awaddr),
+    .up_axi_awready(s_axi_awready),
+    .up_axi_wvalid(s_axi_wvalid),
+    .up_axi_wdata(s_axi_wdata),
+    .up_axi_wstrb(s_axi_wstrb),
+    .up_axi_wready(s_axi_wready),
+    .up_axi_bvalid(s_axi_bvalid),
+    .up_axi_bresp(s_axi_bresp),
+    .up_axi_bready(s_axi_bready),
+    .up_axi_arvalid(s_axi_arvalid),
+    .up_axi_araddr(s_axi_araddr),
+    .up_axi_arready(s_axi_arready),
+    .up_axi_rvalid(s_axi_rvalid),
+    .up_axi_rresp(s_axi_rresp),
+    .up_axi_rdata(s_axi_rdata),
+    .up_axi_rready(s_axi_rready),
+    .up_wreq(up_wreq),
+    .up_waddr(up_waddr),
+    .up_wdata(up_wdata),
+    .up_wack(up_wack),
+    .up_rreq(up_rreq),
+    .up_raddr(up_raddr),
+    .up_rdata(up_rdata),
+    .up_rack(up_rack));
 
-jesd204_up_common #(
-  .PCORE_VERSION(PCORE_VERSION),
-  .PCORE_MAGIC(PCORE_MAGIC),
-  .ID(ID),
-  .NUM_LANES(NUM_LANES),
-  .NUM_LINKS(NUM_LINKS),
-  .NUM_IRQS(5),
-  .EXTRA_CFG_WIDTH(8),
-  .DEV_EXTRA_CFG_WIDTH(19),
-  .ENABLE_LINK_STATS(ENABLE_LINK_STATS)
-) i_up_common (
-  .up_clk(s_axi_aclk),
-  .ext_resetn(s_axi_aresetn),
+  jesd204_up_common #(
+    .PCORE_VERSION(PCORE_VERSION),
+    .PCORE_MAGIC(PCORE_MAGIC),
+    .ID(ID),
+    .NUM_LANES(NUM_LANES),
+    .NUM_LINKS(NUM_LINKS),
+    .NUM_IRQS(5),
+    .EXTRA_CFG_WIDTH(8),
+    .DEV_EXTRA_CFG_WIDTH(19),
+    .ENABLE_LINK_STATS(ENABLE_LINK_STATS)
+  ) i_up_common (
+    .up_clk(s_axi_aclk),
+    .ext_resetn(s_axi_aresetn),
 
-  .up_reset(up_reset),
-  .up_reset_synchronizer(up_reset_synchronizer),
+    .up_reset(up_reset),
+    .up_reset_synchronizer(up_reset_synchronizer),
 
-  .core_clk(core_clk),
-  .core_reset_ext(core_reset_ext),
-  .core_reset(core_reset),
+    .core_clk(core_clk),
+    .core_reset_ext(core_reset_ext),
+    .core_reset(core_reset),
 
-  .device_clk(device_clk),
-  .device_reset(device_reset),
+    .device_clk(device_clk),
+    .device_reset(device_reset),
 
-  .up_raddr(up_raddr),
-  .up_rdata(up_rdata_common),
-  .up_wreq(up_wreq),
-  .up_waddr(up_waddr),
-  .up_wdata(up_wdata),
+    .up_raddr(up_raddr),
+    .up_rdata(up_rdata_common),
+    .up_wreq(up_wreq),
+    .up_waddr(up_waddr),
+    .up_wdata(up_wdata),
 
-  .up_cfg_is_writeable(up_cfg_is_writeable),
+    .up_cfg_is_writeable(up_cfg_is_writeable),
 
-  .up_irq_trigger(up_irq_trigger),
-  .irq(irq),
+    .up_irq_trigger(up_irq_trigger),
+    .irq(irq),
 
-  .core_cfg_octets_per_multiframe(core_cfg_octets_per_multiframe),
-  .core_cfg_octets_per_frame(core_cfg_octets_per_frame),
-  .core_cfg_lanes_disable(core_cfg_lanes_disable),
-  .core_cfg_links_disable(core_cfg_links_disable),
-  .core_cfg_disable_scrambler(core_cfg_disable_scrambler),
-  .core_cfg_disable_char_replacement(core_cfg_disable_char_replacement),
+    .core_cfg_octets_per_multiframe(core_cfg_octets_per_multiframe),
+    .core_cfg_octets_per_frame(core_cfg_octets_per_frame),
+    .core_cfg_lanes_disable(core_cfg_lanes_disable),
+    .core_cfg_links_disable(core_cfg_links_disable),
+    .core_cfg_disable_scrambler(core_cfg_disable_scrambler),
+    .core_cfg_disable_char_replacement(core_cfg_disable_char_replacement),
 
-  .up_extra_cfg({
-    /* 00-07 */ up_cfg_frame_align_err_threshold
-  }),
-  .core_extra_cfg({
-    /* 00-07 */ core_cfg_frame_align_err_threshold
-  }),
+    .up_extra_cfg({
+      /* 00-07 */ up_cfg_frame_align_err_threshold
+    }),
+    .core_extra_cfg({
+      /* 00-07 */ core_cfg_frame_align_err_threshold
+    }),
 
-  .device_cfg_octets_per_multiframe(device_cfg_octets_per_multiframe),
-  .device_cfg_octets_per_frame(device_cfg_octets_per_frame),
-  .device_cfg_beats_per_multiframe(device_cfg_beats_per_multiframe),
+    .device_cfg_octets_per_multiframe(device_cfg_octets_per_multiframe),
+    .device_cfg_octets_per_frame(device_cfg_octets_per_frame),
+    .device_cfg_beats_per_multiframe(device_cfg_beats_per_multiframe),
 
-  .up_dev_extra_cfg({
-    /*    18 */ up_cfg_sysref_disable,
-    /*    17 */ up_cfg_sysref_oneshot,
-    /*    16 */ up_cfg_buffer_early_release,
-    /* 15-08 */ up_cfg_buffer_delay,
-    /* 00-07 */ up_cfg_lmfc_offset
-  }),
-  .device_extra_cfg({
-    /*    18 */ device_cfg_sysref_disable,
-    /*    17 */ device_cfg_sysref_oneshot,
-    /*    16 */ device_cfg_buffer_early_release,
-    /* 15-08 */ device_cfg_buffer_delay,
-    /* 00-07 */ device_cfg_lmfc_offset
-  }),
+    .up_dev_extra_cfg({
+      /*    18 */ up_cfg_sysref_disable,
+      /*    17 */ up_cfg_sysref_oneshot,
+      /*    16 */ up_cfg_buffer_early_release,
+      /* 15-08 */ up_cfg_buffer_delay,
+      /* 00-07 */ up_cfg_lmfc_offset
+    }),
+    .device_extra_cfg({
+      /*    18 */ device_cfg_sysref_disable,
+      /*    17 */ device_cfg_sysref_oneshot,
+      /*    16 */ device_cfg_buffer_early_release,
+      /* 15-08 */ device_cfg_buffer_delay,
+      /* 00-07 */ device_cfg_lmfc_offset
+    }),
 
-  .status_synth_params0(status_synth_params0),
-  .status_synth_params1(status_synth_params1),
-  .status_synth_params2(status_synth_params2)
+    .status_synth_params0(status_synth_params0),
+    .status_synth_params1(status_synth_params1),
+    .status_synth_params2(status_synth_params2));
 
-);
+  jesd204_up_sysref #(
+    .DATA_PATH_WIDTH_LOG2(DATA_PATH_WIDTH_LOG2)
+  ) i_up_sysref (
+    .up_clk(s_axi_aclk),
+    .up_reset(up_reset),
 
-jesd204_up_sysref #(
-  .DATA_PATH_WIDTH_LOG2(DATA_PATH_WIDTH_LOG2)
-) i_up_sysref (
-  .up_clk(s_axi_aclk),
-  .up_reset(up_reset),
+    .core_clk(core_clk),
+    .device_clk(device_clk),
+    .device_event_sysref_edge(device_event_sysref_edge),
+    .device_event_sysref_alignment_error(device_event_sysref_alignment_error),
 
-  .core_clk(core_clk),
-  .device_clk(device_clk),
-  .device_event_sysref_edge(device_event_sysref_edge),
-  .device_event_sysref_alignment_error(device_event_sysref_alignment_error),
+    .up_raddr(up_raddr),
+    .up_rdata(up_rdata_sysref),
+    .up_wreq(up_wreq),
+    .up_waddr(up_waddr),
+    .up_wdata(up_wdata),
 
-  .up_raddr(up_raddr),
-  .up_rdata(up_rdata_sysref),
-  .up_wreq(up_wreq),
-  .up_waddr(up_waddr),
-  .up_wdata(up_wdata),
+    .up_cfg_is_writeable(up_cfg_is_writeable),
 
-  .up_cfg_is_writeable(up_cfg_is_writeable),
+    .up_cfg_lmfc_offset(up_cfg_lmfc_offset),
+    .up_cfg_sysref_oneshot(up_cfg_sysref_oneshot),
+    .up_cfg_sysref_disable(up_cfg_sysref_disable));
 
-  .up_cfg_lmfc_offset(up_cfg_lmfc_offset),
-  .up_cfg_sysref_oneshot(up_cfg_sysref_oneshot),
-  .up_cfg_sysref_disable(up_cfg_sysref_disable)
-);
+  jesd204_up_rx #(
+    .NUM_LANES(NUM_LANES),
+    .DATA_PATH_WIDTH(DATA_PATH_WIDTH),
+    .DATA_PATH_WIDTH_LOG2(DATA_PATH_WIDTH_LOG2)
+  ) i_up_rx (
+    .up_clk(s_axi_aclk),
+    .up_reset(up_reset),
+    .up_reset_synchronizer(up_reset_synchronizer),
 
-jesd204_up_rx #(
-  .NUM_LANES(NUM_LANES),
-  .DATA_PATH_WIDTH(DATA_PATH_WIDTH),
-  .DATA_PATH_WIDTH_LOG2(DATA_PATH_WIDTH_LOG2)
-) i_up_rx (
-  .up_clk(s_axi_aclk),
-  .up_reset(up_reset),
-  .up_reset_synchronizer(up_reset_synchronizer),
+    .core_clk(core_clk),
+    .core_reset(core_reset),
 
-  .core_clk(core_clk),
-  .core_reset(core_reset),
+    .up_rreq(up_rreq),
+    .up_raddr(up_raddr),
+    .up_rdata(up_rdata_rx),
+    .up_wreq(up_wreq),
+    .up_waddr(up_waddr),
+    .up_wdata(up_wdata),
 
-  .up_rreq(up_rreq),
-  .up_raddr(up_raddr),
-  .up_rdata(up_rdata_rx),
-  .up_wreq(up_wreq),
-  .up_waddr(up_waddr),
-  .up_wdata(up_wdata),
+    .up_cfg_is_writeable(up_cfg_is_writeable),
 
-  .up_cfg_is_writeable(up_cfg_is_writeable),
+    .up_cfg_buffer_early_release(up_cfg_buffer_early_release),
+    .up_cfg_buffer_delay(up_cfg_buffer_delay),
 
-  .up_cfg_buffer_early_release(up_cfg_buffer_early_release),
-  .up_cfg_buffer_delay(up_cfg_buffer_delay),
+    .up_cfg_frame_align_err_threshold(up_cfg_frame_align_err_threshold),
 
-  .up_cfg_frame_align_err_threshold(up_cfg_frame_align_err_threshold),
+    .core_ctrl_err_statistics_reset(core_ctrl_err_statistics_reset),
+    .core_ctrl_err_statistics_mask(core_ctrl_err_statistics_mask),
 
-  .core_ctrl_err_statistics_reset(core_ctrl_err_statistics_reset),
-  .core_ctrl_err_statistics_mask(core_ctrl_err_statistics_mask),
+    .core_status_ctrl_state(core_status_ctrl_state),
+    .core_status_lane_cgs_state(core_status_lane_cgs_state),
+    .core_status_lane_emb_state(core_status_lane_emb_state),
+    .core_status_lane_ifs_ready(core_status_lane_ifs_ready),
+    .core_status_lane_latency(core_status_lane_latency),
+    .core_status_lane_frame_align_err_cnt(core_status_lane_frame_align_err_cnt),
 
-  .core_status_ctrl_state(core_status_ctrl_state),
-  .core_status_lane_cgs_state(core_status_lane_cgs_state),
-  .core_status_lane_emb_state(core_status_lane_emb_state),
-  .core_status_lane_ifs_ready(core_status_lane_ifs_ready),
-  .core_status_lane_latency(core_status_lane_latency),
-  .core_status_lane_frame_align_err_cnt(core_status_lane_frame_align_err_cnt),
+    .core_status_err_statistics_cnt(core_status_err_statistics_cnt),
 
-  .core_status_err_statistics_cnt(core_status_err_statistics_cnt),
+    .core_ilas_config_valid(core_ilas_config_valid),
+    .core_ilas_config_addr(core_ilas_config_addr),
+    .core_ilas_config_data(core_ilas_config_data));
 
-  .core_ilas_config_valid(core_ilas_config_valid),
-  .core_ilas_config_addr(core_ilas_config_addr),
-  .core_ilas_config_data(core_ilas_config_data)
-);
+  always @(posedge s_axi_aclk) begin
+    up_wack <= up_wreq;
 
-always @(posedge s_axi_aclk) begin
-  up_wack <= up_wreq;
-
-  // ILAS memory takes one clock cycle before the data is ready, hence the extra
-  // delay.
-  up_rreq_d1 <= up_rreq;
-  up_rack <= up_rreq_d1;
-  if (up_rreq_d1 == 1'b1) begin
-    up_rdata <= up_rdata_common | up_rdata_sysref | up_rdata_rx;
+    // ILAS memory takes one clock cycle before the data is ready, hence the extra
+    // delay.
+    up_rreq_d1 <= up_rreq;
+    up_rack <= up_rreq_d1;
+    if (up_rreq_d1 == 1'b1) begin
+      up_rdata <= up_rdata_common | up_rdata_sysref | up_rdata_rx;
+    end
   end
-end
 
 endmodule
diff --git a/library/jesd204/axi_jesd204_rx/jesd204_up_ilas_mem.v b/library/jesd204/axi_jesd204_rx/jesd204_up_ilas_mem.v
index 5eebff043..9663395b7 100755
--- a/library/jesd204/axi_jesd204_rx/jesd204_up_ilas_mem.v
+++ b/library/jesd204/axi_jesd204_rx/jesd204_up_ilas_mem.v
@@ -46,7 +46,7 @@
 
 module jesd204_up_ilas_mem #(
   parameter DATA_PATH_WIDTH = 4
-)(
+) (
   input up_clk,
 
   input up_rreq,
@@ -63,74 +63,73 @@ module jesd204_up_ilas_mem #(
   output up_ilas_ready
 );
 
-localparam ILAS_DATA_LENGTH = (DATA_PATH_WIDTH == 4) ? 4 : 2;
+  localparam ILAS_DATA_LENGTH = (DATA_PATH_WIDTH == 4) ? 4 : 2;
 
-reg [DATA_PATH_WIDTH*8-1:0] mem[0:ILAS_DATA_LENGTH-1];
-reg core_ilas_captured = 1'b0;
+  reg [DATA_PATH_WIDTH*8-1:0] mem[0:ILAS_DATA_LENGTH-1];
+  reg core_ilas_captured = 1'b0;
 
-sync_bits i_cdc_ilas_ready (
-  .in_bits(core_ilas_captured),
-  .out_resetn(1'b1),
-  .out_clk(up_clk),
-  .out_bits(up_ilas_ready)
-);
+  sync_bits i_cdc_ilas_ready (
+    .in_bits(core_ilas_captured),
+    .out_resetn(1'b1),
+    .out_clk(up_clk),
+    .out_bits(up_ilas_ready));
 
-always @(posedge core_clk) begin
-  if (core_reset == 1'b1) begin
-    core_ilas_captured <= 1'b0;
-  end else begin
-    if (core_ilas_config_valid == 1'b1 && core_ilas_config_addr == ILAS_DATA_LENGTH-1) begin
-      core_ilas_captured <= 1'b1;
+  always @(posedge core_clk) begin
+    if (core_reset == 1'b1) begin
+      core_ilas_captured <= 1'b0;
+    end else begin
+      if (core_ilas_config_valid == 1'b1 && core_ilas_config_addr == ILAS_DATA_LENGTH-1) begin
+        core_ilas_captured <= 1'b1;
+      end
     end
   end
-end
 
-generate
-if(DATA_PATH_WIDTH == 4)  begin : dp_4_gen
-always @(posedge up_clk) begin
-  if (up_rreq == 1'b1) begin
-    up_rdata <= mem[up_raddr];
+  generate
+  if(DATA_PATH_WIDTH == 4)  begin : dp_4_gen
+  always @(posedge up_clk) begin
+    if (up_rreq == 1'b1) begin
+      up_rdata <= mem[up_raddr];
+    end
   end
-end
-end else if(DATA_PATH_WIDTH == 8) begin : dp_8_gen
-always @(posedge up_clk) begin
-  if (up_rreq == 1'b1) begin
-    up_rdata <= mem[up_raddr[1]] >> (up_raddr[0]*32);
+  end else if(DATA_PATH_WIDTH == 8) begin : dp_8_gen
+  always @(posedge up_clk) begin
+    if (up_rreq == 1'b1) begin
+      up_rdata <= mem[up_raddr[1]] >> (up_raddr[0]*32);
+    end
   end
-end
-end
-endgenerate
-
-always @(posedge core_clk) begin
-  if (core_ilas_config_valid == 1'b1) begin
-    mem[core_ilas_config_addr] <= core_ilas_config_data;
   end
-end
-
-/*
- * Shift register with variable tap for accessing the stored data.
- *
- * This has slightly better utilization on Xilinx based platforms than the dual
- * port RAM approach, but there is no equivalent primitive on Intel resulting
- * in increased utilization since it needs to be implemented used registers and
- * muxes.
- *
- * We might make this a device dependent configuration option at some point.
-
-reg [3:0] mem[0:31];
-
-generate
-genvar i;
-for (i = 0; i < 32; i = i + 1) begin: gen_ilas_mem
-  assign up_rdata[i] = mem[i][~up_raddr];
+  endgenerate
 
   always @(posedge core_clk) begin
     if (core_ilas_config_valid == 1'b1) begin
-      mem[i] <= {mem[i][2:0],core_ilas_config_data[i]};
+      mem[core_ilas_config_addr] <= core_ilas_config_data;
     end
   end
-end
-endgenerate
-*/
+
+  /*
+   * Shift register with variable tap for accessing the stored data.
+   *
+   * This has slightly better utilization on Xilinx based platforms than the dual
+   * port RAM approach, but there is no equivalent primitive on Intel resulting
+   * in increased utilization since it needs to be implemented used registers and
+   * muxes.
+   *
+   * We might make this a device dependent configuration option at some point.
+
+  reg [3:0] mem[0:31];
+
+  generate
+  genvar i;
+  for (i = 0; i < 32; i = i + 1) begin: gen_ilas_mem
+    assign up_rdata[i] = mem[i][~up_raddr];
+
+    always @(posedge core_clk) begin
+      if (core_ilas_config_valid == 1'b1) begin
+        mem[i] <= {mem[i][2:0],core_ilas_config_data[i]};
+      end
+    end
+  end
+  endgenerate
+  */
 
 endmodule
diff --git a/library/jesd204/axi_jesd204_rx/jesd204_up_rx.v b/library/jesd204/axi_jesd204_rx/jesd204_up_rx.v
index fbdec0432..4a3935a1e 100755
--- a/library/jesd204/axi_jesd204_rx/jesd204_up_rx.v
+++ b/library/jesd204/axi_jesd204_rx/jesd204_up_rx.v
@@ -44,7 +44,7 @@
 
 `timescale 1ns/100ps
 
-module jesd204_up_rx # (
+module jesd204_up_rx #(
   parameter NUM_LANES = 1,
   parameter DATA_PATH_WIDTH = 4,
   parameter DATA_PATH_WIDTH_LOG2 = 2
@@ -85,156 +85,153 @@ module jesd204_up_rx # (
   output reg [7:0] up_cfg_frame_align_err_threshold
 );
 
-localparam ELASTIC_BUFFER_SIZE = 256;
+  localparam ELASTIC_BUFFER_SIZE = 256;
 
-wire [1:0] up_status_ctrl_state;
-wire [2*NUM_LANES-1:0] up_status_lane_cgs_state;
-wire [8*NUM_LANES-1:0] up_status_lane_frame_align_err_cnt;
-wire [3*NUM_LANES-1:0] up_status_lane_emb_state;
-wire [31:0] up_lane_rdata[0:NUM_LANES-1];
-wire [32*NUM_LANES-1:0] up_status_err_statistics_cnt;
+  wire [1:0] up_status_ctrl_state;
+  wire [2*NUM_LANES-1:0] up_status_lane_cgs_state;
+  wire [8*NUM_LANES-1:0] up_status_lane_frame_align_err_cnt;
+  wire [3*NUM_LANES-1:0] up_status_lane_emb_state;
+  wire [31:0] up_lane_rdata[0:NUM_LANES-1];
+  wire [32*NUM_LANES-1:0] up_status_err_statistics_cnt;
 
-reg up_ctrl_err_statistics_reset = 0;
-reg [6:0] up_ctrl_err_statistics_mask = 7'h0;
+  reg up_ctrl_err_statistics_reset = 0;
+  reg [6:0] up_ctrl_err_statistics_mask = 7'h0;
 
-sync_data #(
-  .NUM_OF_BITS(2+NUM_LANES*(3+2+32+8))
-) i_cdc_status (
-  .in_clk(core_clk),
-  .in_data({
-    core_status_err_statistics_cnt,
-    core_status_ctrl_state,
-    core_status_lane_cgs_state,
-    core_status_lane_emb_state,
-    core_status_lane_frame_align_err_cnt
-  }),
-  .out_clk(up_clk),
-  .out_data({
-    up_status_err_statistics_cnt,
-    up_status_ctrl_state,
-    up_status_lane_cgs_state,
-    up_status_lane_emb_state,
-    up_status_lane_frame_align_err_cnt
-  })
-);
+  sync_data #(
+    .NUM_OF_BITS(2+NUM_LANES*(3+2+32+8))
+  ) i_cdc_status (
+    .in_clk(core_clk),
+    .in_data({
+      core_status_err_statistics_cnt,
+      core_status_ctrl_state,
+      core_status_lane_cgs_state,
+      core_status_lane_emb_state,
+      core_status_lane_frame_align_err_cnt
+    }),
+    .out_clk(up_clk),
+    .out_data({
+      up_status_err_statistics_cnt,
+      up_status_ctrl_state,
+      up_status_lane_cgs_state,
+      up_status_lane_emb_state,
+      up_status_lane_frame_align_err_cnt
+    }));
 
-sync_data #(
-  .NUM_OF_BITS(8)
-) i_cdc_cfg (
-  .in_clk(up_clk),
-  .in_data({
-    up_ctrl_err_statistics_mask,
-    up_ctrl_err_statistics_reset
-  }),
-  .out_clk(core_clk),
-  .out_data({
-    core_ctrl_err_statistics_mask,
-    core_ctrl_err_statistics_reset
-  })
-);
+  sync_data #(
+    .NUM_OF_BITS(8)
+  ) i_cdc_cfg (
+    .in_clk(up_clk),
+    .in_data({
+      up_ctrl_err_statistics_mask,
+      up_ctrl_err_statistics_reset
+    }),
+    .out_clk(core_clk),
+    .out_data({
+      core_ctrl_err_statistics_mask,
+      core_ctrl_err_statistics_reset
+    }));
 
-localparam LANE_BASE_ADDR = 'h300 / 32;
+  localparam LANE_BASE_ADDR = 'h300 / 32;
 
-always @(*) begin
-  case (up_raddr)
-  /* Core configuration */
-  12'h010: up_rdata = ELASTIC_BUFFER_SIZE; /* Elastic buffer size in octets */
+  always @(*) begin
+    case (up_raddr)
+    /* Core configuration */
+    12'h010: up_rdata = ELASTIC_BUFFER_SIZE; /* Elastic buffer size in octets */
 
-  /* JESD RX configuraton */
-  12'h090: up_rdata = {
-    /* 17-31 */ 15'h00, /* Reserved for future additions */
-    /*    16 */ up_cfg_buffer_early_release, /* Release buffer as soon as all lanes are ready. */
-    /* 10-15 */ 6'b0000, /* Reserved for future extensions of buffer_delay */
-    /* 02-09 */ up_cfg_buffer_delay, /* Buffer release delay */
-    /* 00-01 */ 2'b00 /* Data path width alignment */
-  };
-  12'h91: up_rdata = {
-    /* 15-31 */ 17'h00, /* Reserved for future additions */
-    /* 08-14 */ up_ctrl_err_statistics_mask,
-    /* 01-07 */ 7'h0,
-    /*    00 */ up_ctrl_err_statistics_reset
-  };
-  12'h92: up_rdata = {
-    /* 08-31 */ 24'h0,
-    /* 00-07 */ up_cfg_frame_align_err_threshold
-  };
-
-  /* 0x93-0x9f reserved for future use */
-
-  /* JESD RX status */
-  12'ha0: up_rdata = {
-    /* 04-31 */ 28'h00, /* Reserved for future additions */
-    /* 02-03 */ 2'b00, /* Reserved for future extensions of ctrl_state */
-    /* 00-01 */ up_status_ctrl_state /* State of the internal state machine */
-  };
-  default: begin
-    if (up_raddr[11:3] >= LANE_BASE_ADDR &&
-        up_raddr[11:3] < LANE_BASE_ADDR + NUM_LANES) begin
-      up_rdata = up_lane_rdata[up_raddr[11:3] - LANE_BASE_ADDR];
-    end else begin
-      up_rdata = 'h00;
-    end
-  end
-  endcase
-end
-
-always @(posedge up_clk) begin
-  if (up_reset == 1'b1) begin
-    up_cfg_buffer_early_release <= 1'b0;
-    up_cfg_buffer_delay <= 'h00;
-    up_ctrl_err_statistics_mask <= 7'h0;
-    up_ctrl_err_statistics_reset <= 1'b0;
-    up_cfg_frame_align_err_threshold <= 8'd4;
-  end else if (up_wreq == 1'b1 && up_cfg_is_writeable == 1'b1) begin
-    case (up_waddr)
     /* JESD RX configuraton */
-    12'h090: begin
-      up_cfg_buffer_early_release <= up_wdata[16];
-      up_cfg_buffer_delay <= up_wdata[9:DATA_PATH_WIDTH_LOG2];
-    end
-    endcase
-  end else if (up_wreq == 1'b1) begin
-    case (up_waddr)
-    12'h91: begin
-      up_ctrl_err_statistics_mask <= up_wdata[14:8];
-      up_ctrl_err_statistics_reset <= up_wdata[0];
-    end
-    12'h92: begin
-      up_cfg_frame_align_err_threshold <= up_wdata[7:0];
+    12'h090: up_rdata = {
+      /* 17-31 */ 15'h00, /* Reserved for future additions */
+      /*    16 */ up_cfg_buffer_early_release, /* Release buffer as soon as all lanes are ready. */
+      /* 10-15 */ 6'b0000, /* Reserved for future extensions of buffer_delay */
+      /* 02-09 */ up_cfg_buffer_delay, /* Buffer release delay */
+      /* 00-01 */ 2'b00 /* Data path width alignment */
+    };
+    12'h91: up_rdata = {
+      /* 15-31 */ 17'h00, /* Reserved for future additions */
+      /* 08-14 */ up_ctrl_err_statistics_mask,
+      /* 01-07 */ 7'h0,
+      /*    00 */ up_ctrl_err_statistics_reset
+    };
+    12'h92: up_rdata = {
+      /* 08-31 */ 24'h0,
+      /* 00-07 */ up_cfg_frame_align_err_threshold
+    };
+
+    /* 0x93-0x9f reserved for future use */
+
+    /* JESD RX status */
+    12'ha0: up_rdata = {
+      /* 04-31 */ 28'h00, /* Reserved for future additions */
+      /* 02-03 */ 2'b00, /* Reserved for future extensions of ctrl_state */
+      /* 00-01 */ up_status_ctrl_state /* State of the internal state machine */
+    };
+    default: begin
+      if (up_raddr[11:3] >= LANE_BASE_ADDR &&
+          up_raddr[11:3] < LANE_BASE_ADDR + NUM_LANES) begin
+        up_rdata = up_lane_rdata[up_raddr[11:3] - LANE_BASE_ADDR];
+      end else begin
+        up_rdata = 'h00;
+      end
     end
     endcase
   end
-end
 
-genvar i;
-generate for (i = 0; i < NUM_LANES; i = i + 1) begin: gen_lane
-    jesd204_up_rx_lane #(
-      .DATA_PATH_WIDTH(DATA_PATH_WIDTH)
-    ) i_up_rx_lane (
-      .up_clk(up_clk),
-      .up_reset_synchronizer(up_reset_synchronizer),
-
-      .up_rreq(up_rreq),
-      .up_raddr(up_raddr[2:0]),
-      .up_rdata(up_lane_rdata[i]),
-
-      .up_status_cgs_state(up_status_lane_cgs_state[2*i+1:2*i]),
-      .up_status_err_statistics_cnt(up_status_err_statistics_cnt[32*i+31:32*i]),
-      .up_status_emb_state(up_status_lane_emb_state[3*i+2:3*i]),
-      .up_status_lane_frame_align_err_cnt(up_status_lane_frame_align_err_cnt[8*i+7:8*i]),
-
-      .core_clk(core_clk),
-      .core_reset(core_reset),
-
-      .core_ilas_config_valid(core_ilas_config_valid[i]),
-      .core_ilas_config_addr(core_ilas_config_addr[2*i+1:2*i]),
-      .core_ilas_config_data(core_ilas_config_data[(DATA_PATH_WIDTH*8*i)+(DATA_PATH_WIDTH*8)-1:DATA_PATH_WIDTH*8*i]),
-
-      .core_status_ifs_ready(core_status_lane_ifs_ready[i]),
-      .core_status_latency(core_status_lane_latency[14*i+13:14*i])
-    );
+  always @(posedge up_clk) begin
+    if (up_reset == 1'b1) begin
+      up_cfg_buffer_early_release <= 1'b0;
+      up_cfg_buffer_delay <= 'h00;
+      up_ctrl_err_statistics_mask <= 7'h0;
+      up_ctrl_err_statistics_reset <= 1'b0;
+      up_cfg_frame_align_err_threshold <= 8'd4;
+    end else if (up_wreq == 1'b1 && up_cfg_is_writeable == 1'b1) begin
+      case (up_waddr)
+      /* JESD RX configuraton */
+      12'h090: begin
+        up_cfg_buffer_early_release <= up_wdata[16];
+        up_cfg_buffer_delay <= up_wdata[9:DATA_PATH_WIDTH_LOG2];
+      end
+      endcase
+    end else if (up_wreq == 1'b1) begin
+      case (up_waddr)
+      12'h91: begin
+        up_ctrl_err_statistics_mask <= up_wdata[14:8];
+        up_ctrl_err_statistics_reset <= up_wdata[0];
+      end
+      12'h92: begin
+        up_cfg_frame_align_err_threshold <= up_wdata[7:0];
+      end
+      endcase
+    end
   end
 
-endgenerate
+  genvar i;
+  generate for (i = 0; i < NUM_LANES; i = i + 1) begin: gen_lane
+      jesd204_up_rx_lane #(
+        .DATA_PATH_WIDTH(DATA_PATH_WIDTH)
+      ) i_up_rx_lane (
+        .up_clk(up_clk),
+        .up_reset_synchronizer(up_reset_synchronizer),
+
+        .up_rreq(up_rreq),
+        .up_raddr(up_raddr[2:0]),
+        .up_rdata(up_lane_rdata[i]),
+
+        .up_status_cgs_state(up_status_lane_cgs_state[2*i+1:2*i]),
+        .up_status_err_statistics_cnt(up_status_err_statistics_cnt[32*i+31:32*i]),
+        .up_status_emb_state(up_status_lane_emb_state[3*i+2:3*i]),
+        .up_status_lane_frame_align_err_cnt(up_status_lane_frame_align_err_cnt[8*i+7:8*i]),
+
+        .core_clk(core_clk),
+        .core_reset(core_reset),
+
+        .core_ilas_config_valid(core_ilas_config_valid[i]),
+        .core_ilas_config_addr(core_ilas_config_addr[2*i+1:2*i]),
+        .core_ilas_config_data(core_ilas_config_data[(DATA_PATH_WIDTH*8*i)+(DATA_PATH_WIDTH*8)-1:DATA_PATH_WIDTH*8*i]),
+
+        .core_status_ifs_ready(core_status_lane_ifs_ready[i]),
+        .core_status_latency(core_status_lane_latency[14*i+13:14*i]));
+    end
+
+  endgenerate
 
 endmodule
diff --git a/library/jesd204/axi_jesd204_rx/jesd204_up_rx_lane.v b/library/jesd204/axi_jesd204_rx/jesd204_up_rx_lane.v
index 8cc0941bc..3663dc750 100755
--- a/library/jesd204/axi_jesd204_rx/jesd204_up_rx_lane.v
+++ b/library/jesd204/axi_jesd204_rx/jesd204_up_rx_lane.v
@@ -46,7 +46,7 @@
 
 module jesd204_up_rx_lane #(
   parameter DATA_PATH_WIDTH = 4
-)(
+) (
   input up_clk,
   input up_reset_synchronizer,
 
@@ -70,87 +70,85 @@ module jesd204_up_rx_lane #(
   input [13:0] core_status_latency
 );
 
-wire [1:0] up_status_ctrl_state;
+  wire [1:0] up_status_ctrl_state;
 
-wire up_status_ifs_ready;
-reg [13:0] up_status_latency = 'h00;
+  wire up_status_ifs_ready;
+  reg [13:0] up_status_latency = 'h00;
 
-wire [31:0] up_ilas_rdata;
-wire up_ilas_ready;
+  wire [31:0] up_ilas_rdata;
+  wire up_ilas_ready;
 
-sync_bits #(
-  .NUM_OF_BITS(1)
-) i_cdc_status_ready (
-  .in_bits({
-    core_status_ifs_ready
-  }),
-  .out_clk(up_clk),
-  .out_resetn(1'b1),
-  .out_bits({
-    up_status_ifs_ready
-  })
-);
+  sync_bits #(
+    .NUM_OF_BITS(1)
+  ) i_cdc_status_ready (
+    .in_bits({
+      core_status_ifs_ready
+    }),
+    .out_clk(up_clk),
+    .out_resetn(1'b1),
+    .out_bits({
+      up_status_ifs_ready
+    }));
 
-always @(posedge up_clk) begin
-  if (up_reset_synchronizer == 1'b1) begin
-    up_status_latency <= 'h00;
-  end else begin
-    if (up_status_ifs_ready == 1'b1) begin
-      up_status_latency <= core_status_latency;
-    end
-  end
-end
-
-always @(*) begin
-  if (up_raddr[2] == 1'b1) begin
-    if (up_ilas_ready == 1'b1) begin
-      up_rdata = up_ilas_rdata;
+  always @(posedge up_clk) begin
+    if (up_reset_synchronizer == 1'b1) begin
+      up_status_latency <= 'h00;
     end else begin
-      up_rdata = 'h00;
+      if (up_status_ifs_ready == 1'b1) begin
+        up_status_latency <= core_status_latency;
+      end
     end
-  end else begin
-    case (up_raddr[1:0])
-    2'b00: up_rdata = {
-      /* 11-31 */ 21'h0, /* Reserved for future use */
-      /* 08-10 */ up_status_emb_state,
-      /* 06-07 */ 2'h00,
-      /*    05 */ up_ilas_ready,
-      /*    04 */ up_status_ifs_ready,
-      /* 02-03 */ 2'b00, /* Reserved for future extensions of cgs_state */
-      /* 00-01 */ up_status_cgs_state
-    };
-    2'b01: up_rdata = {
-      /* 14-31 */ 18'h00, /* Reserved for future use */
-      /* 00-13 */ up_status_latency
-    };
-    2'b10: up_rdata = {
-      /* 00-31 */ up_status_err_statistics_cnt
-    };
-    2'b11: up_rdata = {
-      /* 08-31 */ 24'h0, /* Reserved for future use */
-      /* 00-07 */ up_status_lane_frame_align_err_cnt
-    };
-    default: up_rdata = 'h00;
-    endcase
   end
-end
 
-jesd204_up_ilas_mem #(
-  .DATA_PATH_WIDTH(DATA_PATH_WIDTH)
-) i_ilas_mem (
-  .up_clk(up_clk),
+  always @(*) begin
+    if (up_raddr[2] == 1'b1) begin
+      if (up_ilas_ready == 1'b1) begin
+        up_rdata = up_ilas_rdata;
+      end else begin
+        up_rdata = 'h00;
+      end
+    end else begin
+      case (up_raddr[1:0])
+      2'b00: up_rdata = {
+        /* 11-31 */ 21'h0, /* Reserved for future use */
+        /* 08-10 */ up_status_emb_state,
+        /* 06-07 */ 2'h00,
+        /*    05 */ up_ilas_ready,
+        /*    04 */ up_status_ifs_ready,
+        /* 02-03 */ 2'b00, /* Reserved for future extensions of cgs_state */
+        /* 00-01 */ up_status_cgs_state
+      };
+      2'b01: up_rdata = {
+        /* 14-31 */ 18'h00, /* Reserved for future use */
+        /* 00-13 */ up_status_latency
+      };
+      2'b10: up_rdata = {
+        /* 00-31 */ up_status_err_statistics_cnt
+      };
+      2'b11: up_rdata = {
+        /* 08-31 */ 24'h0, /* Reserved for future use */
+        /* 00-07 */ up_status_lane_frame_align_err_cnt
+      };
+      default: up_rdata = 'h00;
+      endcase
+    end
+  end
 
-  .up_rreq(up_rreq),
-  .up_raddr(up_raddr[1:0]),
-  .up_rdata(up_ilas_rdata),
-  .up_ilas_ready(up_ilas_ready),
+  jesd204_up_ilas_mem #(
+    .DATA_PATH_WIDTH(DATA_PATH_WIDTH)
+  ) i_ilas_mem (
+    .up_clk(up_clk),
 
-  .core_clk(core_clk),
-  .core_reset(core_reset),
+    .up_rreq(up_rreq),
+    .up_raddr(up_raddr[1:0]),
+    .up_rdata(up_ilas_rdata),
+    .up_ilas_ready(up_ilas_ready),
 
-  .core_ilas_config_valid(core_ilas_config_valid),
-  .core_ilas_config_addr(core_ilas_config_addr),
-  .core_ilas_config_data(core_ilas_config_data)
-);
+    .core_clk(core_clk),
+    .core_reset(core_reset),
+
+    .core_ilas_config_valid(core_ilas_config_valid),
+    .core_ilas_config_addr(core_ilas_config_addr),
+    .core_ilas_config_data(core_ilas_config_data));
 
 endmodule
diff --git a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx.v b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx.v
index d15327197..cff70b35a 100755
--- a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx.v
+++ b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx.v
@@ -119,212 +119,207 @@ module axi_jesd204_tx #(
   input [31:0] status_synth_params2
 );
 
-localparam PCORE_VERSION = 32'h00010661; // 1.06.a
-localparam PCORE_MAGIC = 32'h32303454; // 204T
+  localparam PCORE_VERSION = 32'h00010661; // 1.06.a
+  localparam PCORE_MAGIC = 32'h32303454; // 204T
 
-localparam DATA_PATH_WIDTH_LOG2 = (DATA_PATH_WIDTH == 8) ? 3 : 2;
+  localparam DATA_PATH_WIDTH_LOG2 = (DATA_PATH_WIDTH == 8) ? 3 : 2;
 
-wire up_reset;
+  wire up_reset;
 
-/* Register interface signals */
-reg [31:0] up_rdata = 'd0;
-reg up_wack = 1'b0;
-reg up_rack = 1'b0;
-wire up_wreq;
-wire up_rreq;
-wire [31:0] up_wdata;
-wire [11:0] up_waddr;
-wire [11:0] up_raddr;
-wire [31:0] up_rdata_common;
-wire [31:0] up_rdata_sysref;
-wire [31:0] up_rdata_tx;
+  /* Register interface signals */
+  reg [31:0] up_rdata = 'd0;
+  reg up_wack = 1'b0;
+  reg up_rack = 1'b0;
+  wire up_wreq;
+  wire up_rreq;
+  wire [31:0] up_wdata;
+  wire [11:0] up_waddr;
+  wire [11:0] up_raddr;
+  wire [31:0] up_rdata_common;
+  wire [31:0] up_rdata_sysref;
+  wire [31:0] up_rdata_tx;
 
-wire up_cfg_skip_ilas;
-wire up_cfg_continuous_ilas;
-wire up_cfg_continuous_cgs;
-wire [7:0] up_cfg_mframes_per_ilas;
-wire [7:0] up_cfg_lmfc_offset;
-wire up_cfg_sysref_oneshot;
-wire up_cfg_sysref_disable;
-wire up_cfg_is_writeable;
+  wire up_cfg_skip_ilas;
+  wire up_cfg_continuous_ilas;
+  wire up_cfg_continuous_cgs;
+  wire [7:0] up_cfg_mframes_per_ilas;
+  wire [7:0] up_cfg_lmfc_offset;
+  wire up_cfg_sysref_oneshot;
+  wire up_cfg_sysref_disable;
+  wire up_cfg_is_writeable;
 
-wire [4:0] up_irq_trigger;
+  wire [4:0] up_irq_trigger;
 
-assign up_irq_trigger[4:0] = 5'b00000;
+  assign up_irq_trigger[4:0] = 5'b00000;
 
-up_axi #(
-  .AXI_ADDRESS_WIDTH (14)
-) i_up_axi (
-  .up_rstn(~up_reset),
-  .up_clk(s_axi_aclk),
-  .up_axi_awvalid(s_axi_awvalid),
-  .up_axi_awaddr(s_axi_awaddr),
-  .up_axi_awready(s_axi_awready),
-  .up_axi_wvalid(s_axi_wvalid),
-  .up_axi_wdata(s_axi_wdata),
-  .up_axi_wstrb(s_axi_wstrb),
-  .up_axi_wready(s_axi_wready),
-  .up_axi_bvalid(s_axi_bvalid),
-  .up_axi_bresp(s_axi_bresp),
-  .up_axi_bready(s_axi_bready),
-  .up_axi_arvalid(s_axi_arvalid),
-  .up_axi_araddr(s_axi_araddr),
-  .up_axi_arready(s_axi_arready),
-  .up_axi_rvalid(s_axi_rvalid),
-  .up_axi_rresp(s_axi_rresp),
-  .up_axi_rdata(s_axi_rdata),
-  .up_axi_rready(s_axi_rready),
-  .up_wreq(up_wreq),
-  .up_waddr(up_waddr),
-  .up_wdata(up_wdata),
-  .up_wack(up_wack),
-  .up_rreq(up_rreq),
-  .up_raddr(up_raddr),
-  .up_rdata(up_rdata),
-  .up_rack(up_rack)
-);
+  up_axi #(
+    .AXI_ADDRESS_WIDTH (14)
+  ) i_up_axi (
+    .up_rstn(~up_reset),
+    .up_clk(s_axi_aclk),
+    .up_axi_awvalid(s_axi_awvalid),
+    .up_axi_awaddr(s_axi_awaddr),
+    .up_axi_awready(s_axi_awready),
+    .up_axi_wvalid(s_axi_wvalid),
+    .up_axi_wdata(s_axi_wdata),
+    .up_axi_wstrb(s_axi_wstrb),
+    .up_axi_wready(s_axi_wready),
+    .up_axi_bvalid(s_axi_bvalid),
+    .up_axi_bresp(s_axi_bresp),
+    .up_axi_bready(s_axi_bready),
+    .up_axi_arvalid(s_axi_arvalid),
+    .up_axi_araddr(s_axi_araddr),
+    .up_axi_arready(s_axi_arready),
+    .up_axi_rvalid(s_axi_rvalid),
+    .up_axi_rresp(s_axi_rresp),
+    .up_axi_rdata(s_axi_rdata),
+    .up_axi_rready(s_axi_rready),
+    .up_wreq(up_wreq),
+    .up_waddr(up_waddr),
+    .up_wdata(up_wdata),
+    .up_wack(up_wack),
+    .up_rreq(up_rreq),
+    .up_raddr(up_raddr),
+    .up_rdata(up_rdata),
+    .up_rack(up_rack));
 
-jesd204_up_common #(
-  .PCORE_VERSION(PCORE_VERSION),
-  .PCORE_MAGIC(PCORE_MAGIC),
-  .ID(ID),
-  .NUM_LANES(NUM_LANES),
-  .NUM_LINKS(NUM_LINKS),
-  .NUM_IRQS(5),
-  .EXTRA_CFG_WIDTH(11),
-  .DEV_EXTRA_CFG_WIDTH(10),
-  .ENABLE_LINK_STATS(ENABLE_LINK_STATS)
-) i_up_common (
-  .up_clk(s_axi_aclk),
-  .ext_resetn(s_axi_aresetn),
+  jesd204_up_common #(
+    .PCORE_VERSION(PCORE_VERSION),
+    .PCORE_MAGIC(PCORE_MAGIC),
+    .ID(ID),
+    .NUM_LANES(NUM_LANES),
+    .NUM_LINKS(NUM_LINKS),
+    .NUM_IRQS(5),
+    .EXTRA_CFG_WIDTH(11),
+    .DEV_EXTRA_CFG_WIDTH(10),
+    .ENABLE_LINK_STATS(ENABLE_LINK_STATS)
+  ) i_up_common (
+    .up_clk(s_axi_aclk),
+    .ext_resetn(s_axi_aresetn),
 
-  .up_reset(up_reset),
+    .up_reset(up_reset),
 
-  .up_reset_synchronizer(),
+    .up_reset_synchronizer(),
 
-  .core_clk(core_clk),
-  .core_reset_ext(core_reset_ext),
-  .core_reset(core_reset),
+    .core_clk(core_clk),
+    .core_reset_ext(core_reset_ext),
+    .core_reset(core_reset),
 
-  .device_clk(device_clk),
-  .device_reset(device_reset),
+    .device_clk(device_clk),
+    .device_reset(device_reset),
 
-  .up_raddr(up_raddr),
-  .up_rdata(up_rdata_common),
+    .up_raddr(up_raddr),
+    .up_rdata(up_rdata_common),
 
-  .up_wreq(up_wreq),
-  .up_waddr(up_waddr),
-  .up_wdata(up_wdata),
+    .up_wreq(up_wreq),
+    .up_waddr(up_waddr),
+    .up_wdata(up_wdata),
 
-  .up_cfg_is_writeable(up_cfg_is_writeable),
+    .up_cfg_is_writeable(up_cfg_is_writeable),
 
-  .up_irq_trigger(up_irq_trigger),
-  .irq(irq),
+    .up_irq_trigger(up_irq_trigger),
+    .irq(irq),
 
-  .core_cfg_octets_per_multiframe(core_cfg_octets_per_multiframe),
-  .core_cfg_octets_per_frame(core_cfg_octets_per_frame),
-  .core_cfg_lanes_disable(core_cfg_lanes_disable),
-  .core_cfg_links_disable(core_cfg_links_disable),
-  .core_cfg_disable_scrambler(core_cfg_disable_scrambler),
-  .core_cfg_disable_char_replacement(core_cfg_disable_char_replacement),
+    .core_cfg_octets_per_multiframe(core_cfg_octets_per_multiframe),
+    .core_cfg_octets_per_frame(core_cfg_octets_per_frame),
+    .core_cfg_lanes_disable(core_cfg_lanes_disable),
+    .core_cfg_links_disable(core_cfg_links_disable),
+    .core_cfg_disable_scrambler(core_cfg_disable_scrambler),
+    .core_cfg_disable_char_replacement(core_cfg_disable_char_replacement),
 
-  .up_extra_cfg({
-    /*    10 */ up_cfg_continuous_cgs,
-    /*    09 */ up_cfg_continuous_ilas,
-    /*    08 */ up_cfg_skip_ilas,
-    /* 00-07 */ up_cfg_mframes_per_ilas
-  }),
-  .core_extra_cfg({
-    /*    10 */ core_cfg_continuous_cgs,
-    /*    09 */ core_cfg_continuous_ilas,
-    /*    08 */ core_cfg_skip_ilas,
-    /* 00-07 */ core_cfg_mframes_per_ilas
-  }),
+    .up_extra_cfg({
+      /*    10 */ up_cfg_continuous_cgs,
+      /*    09 */ up_cfg_continuous_ilas,
+      /*    08 */ up_cfg_skip_ilas,
+      /* 00-07 */ up_cfg_mframes_per_ilas
+    }),
+    .core_extra_cfg({
+      /*    10 */ core_cfg_continuous_cgs,
+      /*    09 */ core_cfg_continuous_ilas,
+      /*    08 */ core_cfg_skip_ilas,
+      /* 00-07 */ core_cfg_mframes_per_ilas
+    }),
 
-  .device_cfg_octets_per_multiframe(device_cfg_octets_per_multiframe),
-  .device_cfg_octets_per_frame(device_cfg_octets_per_frame),
-  .device_cfg_beats_per_multiframe(device_cfg_beats_per_multiframe),
+    .device_cfg_octets_per_multiframe(device_cfg_octets_per_multiframe),
+    .device_cfg_octets_per_frame(device_cfg_octets_per_frame),
+    .device_cfg_beats_per_multiframe(device_cfg_beats_per_multiframe),
 
-  .up_dev_extra_cfg({
-    /*    09 */ up_cfg_sysref_disable,
-    /*    08 */ up_cfg_sysref_oneshot,
-    /* 00-07 */ up_cfg_lmfc_offset
-  }),
-  .device_extra_cfg({
-    /*    09 */ device_cfg_sysref_disable,
-    /*    08 */ device_cfg_sysref_oneshot,
-    /* 00-07 */ device_cfg_lmfc_offset
-  }),
+    .up_dev_extra_cfg({
+      /*    09 */ up_cfg_sysref_disable,
+      /*    08 */ up_cfg_sysref_oneshot,
+      /* 00-07 */ up_cfg_lmfc_offset
+    }),
+    .device_extra_cfg({
+      /*    09 */ device_cfg_sysref_disable,
+      /*    08 */ device_cfg_sysref_oneshot,
+      /* 00-07 */ device_cfg_lmfc_offset
+    }),
 
-  .status_synth_params0(status_synth_params0),
-  .status_synth_params1(status_synth_params1),
-  .status_synth_params2(status_synth_params2)
+    .status_synth_params0(status_synth_params0),
+    .status_synth_params1(status_synth_params1),
+    .status_synth_params2(status_synth_params2));
 
-);
+  jesd204_up_sysref #(
+    .DATA_PATH_WIDTH_LOG2(DATA_PATH_WIDTH_LOG2)
+  ) i_up_sysref (
+    .up_clk(s_axi_aclk),
+    .up_reset(up_reset),
 
-jesd204_up_sysref #(
-  .DATA_PATH_WIDTH_LOG2(DATA_PATH_WIDTH_LOG2)
-) i_up_sysref (
-  .up_clk(s_axi_aclk),
-  .up_reset(up_reset),
+    .core_clk(core_clk),
+    .device_clk(device_clk),
+    .device_event_sysref_alignment_error(device_event_sysref_alignment_error),
+    .device_event_sysref_edge(device_event_sysref_edge),
 
-  .core_clk(core_clk),
-  .device_clk(device_clk),
-  .device_event_sysref_alignment_error(device_event_sysref_alignment_error),
-  .device_event_sysref_edge(device_event_sysref_edge),
+    .up_cfg_lmfc_offset(up_cfg_lmfc_offset),
+    .up_cfg_sysref_oneshot(up_cfg_sysref_oneshot),
+    .up_cfg_sysref_disable(up_cfg_sysref_disable),
 
-  .up_cfg_lmfc_offset(up_cfg_lmfc_offset),
-  .up_cfg_sysref_oneshot(up_cfg_sysref_oneshot),
-  .up_cfg_sysref_disable(up_cfg_sysref_disable),
+    .up_raddr(up_raddr),
+    .up_rdata(up_rdata_sysref),
 
-  .up_raddr(up_raddr),
-  .up_rdata(up_rdata_sysref),
+    .up_wreq(up_wreq),
+    .up_waddr(up_waddr),
+    .up_wdata(up_wdata),
 
-  .up_wreq(up_wreq),
-  .up_waddr(up_waddr),
-  .up_wdata(up_wdata),
+    .up_cfg_is_writeable(up_cfg_is_writeable));
 
-  .up_cfg_is_writeable(up_cfg_is_writeable)
-);
+  jesd204_up_tx #(
+    .NUM_LANES(NUM_LANES),
+    .NUM_LINKS(NUM_LINKS),
+    .DATA_PATH_WIDTH(DATA_PATH_WIDTH)
+  ) i_up_tx (
+    .up_clk(s_axi_aclk),
+    .up_reset(up_reset),
 
-jesd204_up_tx #(
-  .NUM_LANES(NUM_LANES),
-  .NUM_LINKS(NUM_LINKS),
-  .DATA_PATH_WIDTH(DATA_PATH_WIDTH)
-) i_up_tx (
-  .up_clk(s_axi_aclk),
-  .up_reset(up_reset),
+    .core_clk(core_clk),
+    .core_ilas_config_rd(core_ilas_config_rd),
+    .core_ilas_config_addr(core_ilas_config_addr),
+    .core_ilas_config_data(core_ilas_config_data),
 
-  .core_clk(core_clk),
-  .core_ilas_config_rd(core_ilas_config_rd),
-  .core_ilas_config_addr(core_ilas_config_addr),
-  .core_ilas_config_data(core_ilas_config_data),
+    .core_ctrl_manual_sync_request(core_ctrl_manual_sync_request),
 
-  .core_ctrl_manual_sync_request(core_ctrl_manual_sync_request),
+    .core_status_state(core_status_state),
+    .core_status_sync(core_status_sync),
 
-  .core_status_state(core_status_state),
-  .core_status_sync(core_status_sync),
+    .up_raddr(up_raddr),
+    .up_rdata(up_rdata_tx),
+    .up_wreq(up_wreq),
+    .up_waddr(up_waddr),
+    .up_wdata(up_wdata),
 
-  .up_raddr(up_raddr),
-  .up_rdata(up_rdata_tx),
-  .up_wreq(up_wreq),
-  .up_waddr(up_waddr),
-  .up_wdata(up_wdata),
+    .up_cfg_is_writeable(up_cfg_is_writeable),
 
-  .up_cfg_is_writeable(up_cfg_is_writeable),
+    .up_cfg_continuous_cgs(up_cfg_continuous_cgs),
+    .up_cfg_continuous_ilas(up_cfg_continuous_ilas),
+    .up_cfg_skip_ilas(up_cfg_skip_ilas),
+    .up_cfg_mframes_per_ilas(up_cfg_mframes_per_ilas));
 
-  .up_cfg_continuous_cgs(up_cfg_continuous_cgs),
-  .up_cfg_continuous_ilas(up_cfg_continuous_ilas),
-  .up_cfg_skip_ilas(up_cfg_skip_ilas),
-  .up_cfg_mframes_per_ilas(up_cfg_mframes_per_ilas)
-);
-
-always @(posedge s_axi_aclk) begin
-  up_wack <= up_wreq;
-  up_rack <= up_rreq;
-  if (up_rreq == 1'b1) begin
-    up_rdata <= up_rdata_common | up_rdata_sysref | up_rdata_tx;
+  always @(posedge s_axi_aclk) begin
+    up_wack <= up_wreq;
+    up_rack <= up_rreq;
+    if (up_rreq == 1'b1) begin
+      up_rdata <= up_rdata_common | up_rdata_sysref | up_rdata_tx;
+    end
   end
-end
 
 endmodule
diff --git a/library/jesd204/axi_jesd204_tx/jesd204_up_tx.v b/library/jesd204/axi_jesd204_tx/jesd204_up_tx.v
index 178bb0819..1596f0cba 100755
--- a/library/jesd204/axi_jesd204_tx/jesd204_up_tx.v
+++ b/library/jesd204/axi_jesd204_tx/jesd204_up_tx.v
@@ -44,7 +44,7 @@
 
 `timescale 1ns/100ps
 
-module jesd204_up_tx # (
+module jesd204_up_tx #(
   parameter NUM_LANES = 1,
   parameter NUM_LINKS = 1,
   parameter DATA_PATH_WIDTH = 4
@@ -76,243 +76,240 @@ module jesd204_up_tx # (
   input [NUM_LINKS-1:0] core_status_sync
 );
 
-reg [31:0] up_cfg_ilas_data[0:NUM_LANES-1][0:3];
-reg up_ctrl_manual_sync_request = 1'b0;
+  reg [31:0] up_cfg_ilas_data[0:NUM_LANES-1][0:3];
+  reg up_ctrl_manual_sync_request = 1'b0;
 
-wire [1:0] up_status_state;
-wire [NUM_LINKS-1:0] up_status_sync;
+  wire [1:0] up_status_state;
+  wire [NUM_LINKS-1:0] up_status_sync;
 
-sync_bits #(
-  .NUM_OF_BITS (NUM_LINKS))
-i_cdc_sync (
-  .in_bits(core_status_sync),
-  .out_clk(up_clk),
-  .out_resetn(1'b1),
-  .out_bits(up_status_sync)
-);
+  sync_bits #(
+    .NUM_OF_BITS (NUM_LINKS)
+  ) i_cdc_sync (
+    .in_bits(core_status_sync),
+    .out_clk(up_clk),
+    .out_resetn(1'b1),
+    .out_bits(up_status_sync));
 
-sync_data #(
-  .NUM_OF_BITS(2)
-) i_cdc_status (
-  .in_clk(core_clk),
-  .in_data(core_status_state),
-  .out_clk(up_clk),
-  .out_data(up_status_state)
-);
+  sync_data #(
+    .NUM_OF_BITS(2)
+  ) i_cdc_status (
+    .in_clk(core_clk),
+    .in_data(core_status_state),
+    .out_clk(up_clk),
+    .out_data(up_status_state));
 
-sync_event #(
-  .NUM_OF_EVENTS(1),
-  .ASYNC_CLK(1)
-) i_cdc_manual_sync_request (
-  .in_clk(up_clk),
-  .in_event(up_ctrl_manual_sync_request),
-  .out_clk(core_clk),
-  .out_event(core_ctrl_manual_sync_request)
-);
+  sync_event #(
+    .NUM_OF_EVENTS(1),
+    .ASYNC_CLK(1)
+  ) i_cdc_manual_sync_request (
+    .in_clk(up_clk),
+    .in_event(up_ctrl_manual_sync_request),
+    .out_clk(core_clk),
+    .out_event(core_ctrl_manual_sync_request));
 
-integer i;
+  integer i;
 
-always @(*) begin
-  case (up_raddr)
-  /* JESD TX configuration */
-  12'h090: up_rdata = {
-    /* 03-31 */ 29'h00, /* Reserved for future additions */
-    /*    02 */ up_cfg_skip_ilas, /* Don't send ILAS, go directly from CGS to DATA */
-    /*    01 */ up_cfg_continuous_ilas, /* Continuously send ILAS sequence */
-    /*    00 */ up_cfg_continuous_cgs /* Continuously send CGS characters */
-  };
-  12'h091: up_rdata = {
-    /* 08-31 */ 24'h00, /* Reserved for future additions */
-    /* 00-07 */ up_cfg_mframes_per_ilas /* Number of multiframes send during the ILAS */
-  };
+  always @(*) begin
+    case (up_raddr)
+    /* JESD TX configuration */
+    12'h090: up_rdata = {
+      /* 03-31 */ 29'h00, /* Reserved for future additions */
+      /*    02 */ up_cfg_skip_ilas, /* Don't send ILAS, go directly from CGS to DATA */
+      /*    01 */ up_cfg_continuous_ilas, /* Continuously send ILAS sequence */
+      /*    00 */ up_cfg_continuous_cgs /* Continuously send CGS characters */
+    };
+    12'h091: up_rdata = {
+      /* 08-31 */ 24'h00, /* Reserved for future additions */
+      /* 00-07 */ up_cfg_mframes_per_ilas /* Number of multiframes send during the ILAS */
+    };
 
-  /* JESD TX status */
-  12'ha0: up_rdata = {
-    /* 12-31 */ 20'h00, /* Reserved for future additions */
-    /* 04-11 */ up_status_sync, /* Raw value of the SYNC pin */
-    /* 02-03 */ 2'b0, /* Reserved fo future extension of the status_state field */
-    /* 00-01 */ up_status_state /* State of the internal state machine (0=CGS, 1=ILAS, 2=DATA) */
-  };
-  default: begin
-    if (up_raddr[10:3] >= ('h300/32) &&
-        up_raddr[10:3] < (('h300/32) + NUM_LANES) &&
-      up_raddr[2] == 1'b1) begin
-      up_rdata = up_cfg_ilas_data[up_raddr[5:3]][up_raddr[1:0]];
-    end else begin
-       up_rdata = 32'h00000000;
-    end
-  end
-  endcase
-
-end
-
-always @(posedge up_clk) begin
-  if (up_reset == 1'b1) begin
-    up_cfg_skip_ilas <= 1'b0;
-    up_cfg_continuous_ilas <= 1'b0;
-    up_cfg_continuous_cgs <= 1'b0;
-    up_cfg_mframes_per_ilas <= 'h3;
-  end else if (up_wreq == 1'b1 && up_cfg_is_writeable == 1'b1) begin
-    case (up_waddr)
-    /* JESD TX configuraton */
-    12'h090: begin
-      up_cfg_skip_ilas <= up_wdata[2];
-      up_cfg_continuous_ilas <= up_wdata[1];
-      up_cfg_continuous_cgs <= up_wdata[0];
-    end
-    12'h091: begin
-//      We'll enable this if we ever have a usecase
-//      cfg_mframes_per_ilas <= up_wdata[7:0];
+    /* JESD TX status */
+    12'ha0: up_rdata = {
+      /* 12-31 */ 20'h00, /* Reserved for future additions */
+      /* 04-11 */ up_status_sync, /* Raw value of the SYNC pin */
+      /* 02-03 */ 2'b0, /* Reserved fo future extension of the status_state field */
+      /* 00-01 */ up_status_state /* State of the internal state machine (0=CGS, 1=ILAS, 2=DATA) */
+    };
+    default: begin
+      if (up_raddr[10:3] >= ('h300/32) &&
+          up_raddr[10:3] < (('h300/32) + NUM_LANES) &&
+        up_raddr[2] == 1'b1) begin
+        up_rdata = up_cfg_ilas_data[up_raddr[5:3]][up_raddr[1:0]];
+      end else begin
+         up_rdata = 32'h00000000;
+      end
     end
     endcase
+
   end
-end
 
-always @(posedge up_clk) begin
-  if (up_reset == 1'b1) begin
-    up_ctrl_manual_sync_request <= 1'b0;
-  end else if (up_wreq == 1'b1 && up_waddr == 12'h092) begin
-    up_ctrl_manual_sync_request <= up_wdata[0];
-  end else begin
-    up_ctrl_manual_sync_request <= 1'b0;
-  end
-end
-
-/* Shared ILAS data can be access through any lane register map window */
-
-/* Shared ILAS data */
-reg [7:0] up_cfg_ilas_data_did = 'h00;
-reg [3:0] up_cfg_ilas_data_bid = 'h00;
-reg [4:0] up_cfg_ilas_data_l = 'h00;
-reg up_cfg_ilas_data_scr = 'h00;
-reg [7:0] up_cfg_ilas_data_f = 'h00;
-reg [4:0] up_cfg_ilas_data_k = 'h00;
-reg [7:0] up_cfg_ilas_data_m = 'h00;
-reg [4:0] up_cfg_ilas_data_n = 'h00;
-reg [1:0] up_cfg_ilas_data_cs = 'h00;
-reg [4:0] up_cfg_ilas_data_np = 'h00;
-reg [2:0] up_cfg_ilas_data_subclassv = 'h00;
-reg [4:0] up_cfg_ilas_data_s = 'h00;
-reg [2:0] up_cfg_ilas_data_jesdv = 'h00;
-reg [4:0] up_cfg_ilas_data_cf = 'h00;
-reg up_cfg_ilas_data_hd = 'h00;
-
-/* Per lane ILAS data */
-reg [4:0] up_cfg_ilas_data_lid[0:NUM_LANES-1];
-reg [7:0] up_cfg_ilas_data_fchk[0:NUM_LANES-1];
-
-always @(*) begin
-  for (i = 0; i < NUM_LANES; i = i + 1) begin
-    up_cfg_ilas_data[i][0] = {
-      4'b0000,
-      up_cfg_ilas_data_bid,
-      up_cfg_ilas_data_did,
-      16'h00
-    };
-    up_cfg_ilas_data[i][1] = {
-      3'b000,
-      up_cfg_ilas_data_k,
-      up_cfg_ilas_data_f,
-      up_cfg_ilas_data_scr,
-      2'b00,
-      up_cfg_ilas_data_l,
-      3'b000,
-      up_cfg_ilas_data_lid[i]
-    };
-    up_cfg_ilas_data[i][2] = {
-      up_cfg_ilas_data_jesdv,
-      up_cfg_ilas_data_s,
-      up_cfg_ilas_data_subclassv,
-      up_cfg_ilas_data_np,
-      up_cfg_ilas_data_cs,
-      1'b0,
-      up_cfg_ilas_data_n,
-      up_cfg_ilas_data_m
-    };
-    up_cfg_ilas_data[i][3] = {
-      up_cfg_ilas_data_fchk[i],
-      16'h0000,
-      up_cfg_ilas_data_hd,
-      2'b00,
-      up_cfg_ilas_data_cf
-    };
-  end
-end
-
-always @(posedge up_clk) begin
-  if (up_reset == 1'b1) begin
-    up_cfg_ilas_data_did <= 'h00;
-    up_cfg_ilas_data_bid <= 'h00;
-    up_cfg_ilas_data_scr <= 'h00;
-    up_cfg_ilas_data_f <= 'h00;
-    up_cfg_ilas_data_k <= 'h00;
-    up_cfg_ilas_data_m <= 'h00;
-    up_cfg_ilas_data_n <= 'h00;
-    up_cfg_ilas_data_cs <= 'h00;
-    up_cfg_ilas_data_np <= 'h00;
-    up_cfg_ilas_data_subclassv <= 'h00;
-    up_cfg_ilas_data_s <= 'h00;
-    up_cfg_ilas_data_jesdv <= 'h00;
-    up_cfg_ilas_data_cf <= 'h00;
-    up_cfg_ilas_data_hd <= 'h00;
-    up_cfg_ilas_data_l <= 'h00;
-    for (i = 0; i < NUM_LANES; i = i + 1) begin
-      up_cfg_ilas_data_lid[i] <= 'h00;
-      up_cfg_ilas_data_fchk[i] <= 'h00;
+  always @(posedge up_clk) begin
+    if (up_reset == 1'b1) begin
+      up_cfg_skip_ilas <= 1'b0;
+      up_cfg_continuous_ilas <= 1'b0;
+      up_cfg_continuous_cgs <= 1'b0;
+      up_cfg_mframes_per_ilas <= 'h3;
+    end else if (up_wreq == 1'b1 && up_cfg_is_writeable == 1'b1) begin
+      case (up_waddr)
+      /* JESD TX configuraton */
+      12'h090: begin
+        up_cfg_skip_ilas <= up_wdata[2];
+        up_cfg_continuous_ilas <= up_wdata[1];
+        up_cfg_continuous_cgs <= up_wdata[0];
+      end
+      12'h091: begin
+  //      We'll enable this if we ever have a usecase
+  //      cfg_mframes_per_ilas <= up_wdata[7:0];
+      end
+      endcase
     end
-  end else if (up_wreq == 1'b1 && up_cfg_is_writeable == 1'b1) begin
+  end
+
+  always @(posedge up_clk) begin
+    if (up_reset == 1'b1) begin
+      up_ctrl_manual_sync_request <= 1'b0;
+    end else if (up_wreq == 1'b1 && up_waddr == 12'h092) begin
+      up_ctrl_manual_sync_request <= up_wdata[0];
+    end else begin
+      up_ctrl_manual_sync_request <= 1'b0;
+    end
+  end
+
+  /* Shared ILAS data can be access through any lane register map window */
+
+  /* Shared ILAS data */
+  reg [7:0] up_cfg_ilas_data_did = 'h00;
+  reg [3:0] up_cfg_ilas_data_bid = 'h00;
+  reg [4:0] up_cfg_ilas_data_l = 'h00;
+  reg up_cfg_ilas_data_scr = 'h00;
+  reg [7:0] up_cfg_ilas_data_f = 'h00;
+  reg [4:0] up_cfg_ilas_data_k = 'h00;
+  reg [7:0] up_cfg_ilas_data_m = 'h00;
+  reg [4:0] up_cfg_ilas_data_n = 'h00;
+  reg [1:0] up_cfg_ilas_data_cs = 'h00;
+  reg [4:0] up_cfg_ilas_data_np = 'h00;
+  reg [2:0] up_cfg_ilas_data_subclassv = 'h00;
+  reg [4:0] up_cfg_ilas_data_s = 'h00;
+  reg [2:0] up_cfg_ilas_data_jesdv = 'h00;
+  reg [4:0] up_cfg_ilas_data_cf = 'h00;
+  reg up_cfg_ilas_data_hd = 'h00;
+
+  /* Per lane ILAS data */
+  reg [4:0] up_cfg_ilas_data_lid[0:NUM_LANES-1];
+  reg [7:0] up_cfg_ilas_data_fchk[0:NUM_LANES-1];
+
+  always @(*) begin
     for (i = 0; i < NUM_LANES; i = i + 1) begin
-      if (up_waddr[10:2] == ('h310 / 16) + i*2) begin
-        case (up_waddr[1:0])
-          2'h0: begin
-            up_cfg_ilas_data_bid <= up_wdata[27:24];
-            up_cfg_ilas_data_did <= up_wdata[23:16];
-          end
-          2'h1: begin
-            up_cfg_ilas_data_k <= up_wdata[28:24];
-            up_cfg_ilas_data_f <= up_wdata[23:16];
-            up_cfg_ilas_data_scr <= up_wdata[15];
-            up_cfg_ilas_data_l <= up_wdata[12:8];
-            up_cfg_ilas_data_lid[i] <= up_wdata[4:0];
-          end
-          2'h2: begin
-            up_cfg_ilas_data_jesdv <= up_wdata[31:29];
-            up_cfg_ilas_data_s <= up_wdata[28:24];
-            up_cfg_ilas_data_subclassv <= up_wdata[23:21];
-            up_cfg_ilas_data_np <= up_wdata[20:16];
-            up_cfg_ilas_data_cs <= up_wdata[15:14];
-            up_cfg_ilas_data_n <= up_wdata[12:8];
-            up_cfg_ilas_data_m <= up_wdata[7:0];
-          end
-          2'h3: begin
-            up_cfg_ilas_data_fchk[i] <= up_wdata[31:24];
-            up_cfg_ilas_data_hd <= up_wdata[7];
-            up_cfg_ilas_data_cf <= up_wdata[4:0];
-          end
-        endcase
+      up_cfg_ilas_data[i][0] = {
+        4'b0000,
+        up_cfg_ilas_data_bid,
+        up_cfg_ilas_data_did,
+        16'h00
+      };
+      up_cfg_ilas_data[i][1] = {
+        3'b000,
+        up_cfg_ilas_data_k,
+        up_cfg_ilas_data_f,
+        up_cfg_ilas_data_scr,
+        2'b00,
+        up_cfg_ilas_data_l,
+        3'b000,
+        up_cfg_ilas_data_lid[i]
+      };
+      up_cfg_ilas_data[i][2] = {
+        up_cfg_ilas_data_jesdv,
+        up_cfg_ilas_data_s,
+        up_cfg_ilas_data_subclassv,
+        up_cfg_ilas_data_np,
+        up_cfg_ilas_data_cs,
+        1'b0,
+        up_cfg_ilas_data_n,
+        up_cfg_ilas_data_m
+      };
+      up_cfg_ilas_data[i][3] = {
+        up_cfg_ilas_data_fchk[i],
+        16'h0000,
+        up_cfg_ilas_data_hd,
+        2'b00,
+        up_cfg_ilas_data_cf
+      };
+    end
+  end
+
+  always @(posedge up_clk) begin
+    if (up_reset == 1'b1) begin
+      up_cfg_ilas_data_did <= 'h00;
+      up_cfg_ilas_data_bid <= 'h00;
+      up_cfg_ilas_data_scr <= 'h00;
+      up_cfg_ilas_data_f <= 'h00;
+      up_cfg_ilas_data_k <= 'h00;
+      up_cfg_ilas_data_m <= 'h00;
+      up_cfg_ilas_data_n <= 'h00;
+      up_cfg_ilas_data_cs <= 'h00;
+      up_cfg_ilas_data_np <= 'h00;
+      up_cfg_ilas_data_subclassv <= 'h00;
+      up_cfg_ilas_data_s <= 'h00;
+      up_cfg_ilas_data_jesdv <= 'h00;
+      up_cfg_ilas_data_cf <= 'h00;
+      up_cfg_ilas_data_hd <= 'h00;
+      up_cfg_ilas_data_l <= 'h00;
+      for (i = 0; i < NUM_LANES; i = i + 1) begin
+        up_cfg_ilas_data_lid[i] <= 'h00;
+        up_cfg_ilas_data_fchk[i] <= 'h00;
+      end
+    end else if (up_wreq == 1'b1 && up_cfg_is_writeable == 1'b1) begin
+      for (i = 0; i < NUM_LANES; i = i + 1) begin
+        if (up_waddr[10:2] == ('h310 / 16) + i*2) begin
+          case (up_waddr[1:0])
+            2'h0: begin
+              up_cfg_ilas_data_bid <= up_wdata[27:24];
+              up_cfg_ilas_data_did <= up_wdata[23:16];
+            end
+            2'h1: begin
+              up_cfg_ilas_data_k <= up_wdata[28:24];
+              up_cfg_ilas_data_f <= up_wdata[23:16];
+              up_cfg_ilas_data_scr <= up_wdata[15];
+              up_cfg_ilas_data_l <= up_wdata[12:8];
+              up_cfg_ilas_data_lid[i] <= up_wdata[4:0];
+            end
+            2'h2: begin
+              up_cfg_ilas_data_jesdv <= up_wdata[31:29];
+              up_cfg_ilas_data_s <= up_wdata[28:24];
+              up_cfg_ilas_data_subclassv <= up_wdata[23:21];
+              up_cfg_ilas_data_np <= up_wdata[20:16];
+              up_cfg_ilas_data_cs <= up_wdata[15:14];
+              up_cfg_ilas_data_n <= up_wdata[12:8];
+              up_cfg_ilas_data_m <= up_wdata[7:0];
+            end
+            2'h3: begin
+              up_cfg_ilas_data_fchk[i] <= up_wdata[31:24];
+              up_cfg_ilas_data_hd <= up_wdata[7];
+              up_cfg_ilas_data_cf <= up_wdata[4:0];
+            end
+          endcase
+        end
       end
     end
   end
-end
 
-generate
-if(DATA_PATH_WIDTH == 4) begin : gen_dp_4
-always @(posedge core_clk) begin
-  if (core_ilas_config_rd == 1'b1) begin
-    for (i = 0; i < NUM_LANES; i = i + 1) begin
-      core_ilas_config_data[i*32+:32] <= up_cfg_ilas_data[i][core_ilas_config_addr];
+  generate
+  if(DATA_PATH_WIDTH == 4) begin : gen_dp_4
+  always @(posedge core_clk) begin
+    if (core_ilas_config_rd == 1'b1) begin
+      for (i = 0; i < NUM_LANES; i = i + 1) begin
+        core_ilas_config_data[i*32+:32] <= up_cfg_ilas_data[i][core_ilas_config_addr];
+      end
     end
   end
-end
-end else if(DATA_PATH_WIDTH == 8) begin : gen_dp_8
-always @(posedge core_clk) begin
-  if (core_ilas_config_rd == 1'b1) begin
-    for (i = 0; i < NUM_LANES; i = i + 1) begin
-      core_ilas_config_data[i*64+:64] <= {up_cfg_ilas_data[i][{core_ilas_config_addr[0], 1'b1}],up_cfg_ilas_data[i][{core_ilas_config_addr[0], 1'b0}]};
+  end else if(DATA_PATH_WIDTH == 8) begin : gen_dp_8
+  always @(posedge core_clk) begin
+    if (core_ilas_config_rd == 1'b1) begin
+      for (i = 0; i < NUM_LANES; i = i + 1) begin
+        core_ilas_config_data[i*64+:64] <= {up_cfg_ilas_data[i][{core_ilas_config_addr[0], 1'b1}],up_cfg_ilas_data[i][{core_ilas_config_addr[0], 1'b0}]};
+      end
     end
   end
-end
-end
-endgenerate
+  end
+  endgenerate
 
 endmodule
diff --git a/library/jesd204/jesd204_common/jesd204_crc12.v b/library/jesd204/jesd204_common/jesd204_crc12.v
index 9d2155ebd..0cd320ec7 100644
--- a/library/jesd204/jesd204_common/jesd204_crc12.v
+++ b/library/jesd204/jesd204_common/jesd204_crc12.v
@@ -56,33 +56,33 @@ module jesd204_crc12 #(
   output [11:0] crc12
 );
 
-reg [11:0] state = 12'b0;
+  reg [11:0] state = 12'b0;
 
-wire [WIDTH-1:0] feedback;
-wire [WIDTH-1+12:0] full_state;
+  wire [WIDTH-1:0] feedback;
+  wire [WIDTH-1+12:0] full_state;
 
-assign full_state = {init ? 12'h0 : state, feedback};
-assign feedback = full_state[WIDTH-1+12:12] ^
-                  full_state[WIDTH-1:11] ^
-                  full_state[WIDTH-1:10] ^
-                  full_state[WIDTH-1:9] ^
-                  full_state[WIDTH-1:4] ^
-                  full_state[WIDTH-1:3] ^
-                  data_in;
+  assign full_state = {init ? 12'h0 : state, feedback};
+  assign feedback = full_state[WIDTH-1+12:12] ^
+                    full_state[WIDTH-1:11] ^
+                    full_state[WIDTH-1:10] ^
+                    full_state[WIDTH-1:9] ^
+                    full_state[WIDTH-1:4] ^
+                    full_state[WIDTH-1:3] ^
+                    data_in;
 
-always @(posedge clk) begin
-  if (reset == 1'b1) begin
-    state <= 12'b0;
-  end else begin
-    state <= full_state[11:0] ^
-            {full_state[10:0],1'b0} ^
-            {full_state[9:0],2'b0} ^
-            {full_state[8:0],3'b0} ^
-            {full_state[3:0],8'b0} ^
-            {full_state[2:0],9'b0};
+  always @(posedge clk) begin
+    if (reset == 1'b1) begin
+      state <= 12'b0;
+    end else begin
+      state <= full_state[11:0] ^
+              {full_state[10:0],1'b0} ^
+              {full_state[9:0],2'b0} ^
+              {full_state[8:0],3'b0} ^
+              {full_state[3:0],8'b0} ^
+              {full_state[2:0],9'b0};
+    end
   end
-end
 
-assign crc12 = state;
+  assign crc12 = state;
 
 endmodule
diff --git a/library/jesd204/jesd204_common/jesd204_eof_generator.v b/library/jesd204/jesd204_common/jesd204_eof_generator.v
index 73c001cd3..bd92ae2cb 100644
--- a/library/jesd204/jesd204_common/jesd204_eof_generator.v
+++ b/library/jesd204/jesd204_common/jesd204_eof_generator.v
@@ -61,94 +61,94 @@ module jesd204_eof_generator #(
   output reg eomf
 );
 
-localparam CW = MAX_OCTETS_PER_FRAME > 128 ? 8 :
-  MAX_OCTETS_PER_FRAME > 64 ? 7 :
-  MAX_OCTETS_PER_FRAME > 32 ? 6 :
-  MAX_OCTETS_PER_FRAME > 16 ? 5 :
-  MAX_OCTETS_PER_FRAME > 8 ? 4 :
-  MAX_OCTETS_PER_FRAME > 4 ? 3 :
-  MAX_OCTETS_PER_FRAME > 2 ? 2 : 1;
-localparam DPW_LOG2 = DATA_PATH_WIDTH == 8 ? 3 :
-  DATA_PATH_WIDTH == 4 ? 2 : 1;
+  localparam CW = MAX_OCTETS_PER_FRAME > 128 ? 8 :
+    MAX_OCTETS_PER_FRAME > 64 ? 7 :
+    MAX_OCTETS_PER_FRAME > 32 ? 6 :
+    MAX_OCTETS_PER_FRAME > 16 ? 5 :
+    MAX_OCTETS_PER_FRAME > 8 ? 4 :
+    MAX_OCTETS_PER_FRAME > 4 ? 3 :
+    MAX_OCTETS_PER_FRAME > 2 ? 2 : 1;
+  localparam DPW_LOG2 = DATA_PATH_WIDTH == 8 ? 3 :
+    DATA_PATH_WIDTH == 4 ? 2 : 1;
 
-reg lmfc_edge_d1 = 1'b0;
+  reg lmfc_edge_d1 = 1'b0;
 
-wire beat_counter_sof;
-wire beat_counter_eof;
-wire small_octets_per_frame;
-
-always @(posedge clk) begin
-  if (cfg_generate_eomf == 1'b1) begin
-    lmfc_edge_d1 <= lmfc_edge;
-  end else begin
-    lmfc_edge_d1 <= 1'b0;
-  end
-  eomf <= lmfc_edge_d1;
-end
-
-generate
-if (CW > DPW_LOG2) begin
-  reg [CW-DPW_LOG2-1:0] beat_counter = 'h00;
-  wire [CW-DPW_LOG2-1:0] cfg_beats_per_frame = cfg_octets_per_frame[CW-1:DPW_LOG2];
-
-  assign beat_counter_sof = beat_counter == 'h00;
-  assign beat_counter_eof = beat_counter == cfg_beats_per_frame;
-  assign small_octets_per_frame = cfg_beats_per_frame == 'h00;
+  wire beat_counter_sof;
+  wire beat_counter_eof;
+  wire small_octets_per_frame;
 
   always @(posedge clk) begin
-    if (reset == 1'b1) begin
-      beat_counter <= 'h00;
-    end else if (beat_counter_eof == 1'b1) begin
-      beat_counter <= 'h00;
+    if (cfg_generate_eomf == 1'b1) begin
+      lmfc_edge_d1 <= lmfc_edge;
     end else begin
-      beat_counter <= beat_counter + 1'b1;
+      lmfc_edge_d1 <= 1'b0;
     end
+    eomf <= lmfc_edge_d1;
   end
 
-end else begin
-  assign beat_counter_sof = 1'b1;
-  assign beat_counter_eof = 1'b1;
-  assign small_octets_per_frame = 1'b1;
-end
-endgenerate
+  generate
+  if (CW > DPW_LOG2) begin
+    reg [CW-DPW_LOG2-1:0] beat_counter = 'h00;
+    wire [CW-DPW_LOG2-1:0] cfg_beats_per_frame = cfg_octets_per_frame[CW-1:DPW_LOG2];
 
-function [1:0] ffs;
-input [2:0] x;
-begin
-  case (x)
-  1: ffs = 0;
-  2: ffs = 1;
-  3: ffs = 0;
-  4: ffs = 2;
-  5: ffs = 0;
-  6: ffs = 1;
-  7: ffs = 0;
-  default: ffs = 0;
-  endcase
-end
-endfunction
+    assign beat_counter_sof = beat_counter == 'h00;
+    assign beat_counter_eof = beat_counter == cfg_beats_per_frame;
+    assign small_octets_per_frame = cfg_beats_per_frame == 'h00;
 
-integer i;
-
-/* Only 1, 2 and multiples of 4 are supported atm */
-always @(posedge clk) begin
-  if (reset == 1'b1) begin
-    sof <= {DATA_PATH_WIDTH{1'b0}};
-    eof <= {DATA_PATH_WIDTH{1'b0}};
-  end else begin
-    sof <= {{DATA_PATH_WIDTH-1{1'b0}},beat_counter_sof};
-    eof <= {beat_counter_eof,{DATA_PATH_WIDTH-1{1'b0}}};
-
-    if (small_octets_per_frame == 1'b1) begin
-      for (i = 1; i < DATA_PATH_WIDTH; i = i + 1) begin
-        if (cfg_octets_per_frame[ffs(i)] != 1'b1) begin
-          sof[i] <= 1'b1;
-          eof[DATA_PATH_WIDTH-1-i] <= 1'b1;
-        end
+    always @(posedge clk) begin
+      if (reset == 1'b1) begin
+        beat_counter <= 'h00;
+      end else if (beat_counter_eof == 1'b1) begin
+        beat_counter <= 'h00;
+      end else begin
+        beat_counter <= beat_counter + 1'b1;
       end
+    end
+
+  end else begin
+    assign beat_counter_sof = 1'b1;
+    assign beat_counter_eof = 1'b1;
+    assign small_octets_per_frame = 1'b1;
+  end
+  endgenerate
+
+  function [1:0] ffs;
+  input [2:0] x;
+  begin
+    case (x)
+    1: ffs = 0;
+    2: ffs = 1;
+    3: ffs = 0;
+    4: ffs = 2;
+    5: ffs = 0;
+    6: ffs = 1;
+    7: ffs = 0;
+    default: ffs = 0;
+    endcase
+  end
+  endfunction
+
+  integer i;
+
+  /* Only 1, 2 and multiples of 4 are supported atm */
+  always @(posedge clk) begin
+    if (reset == 1'b1) begin
+      sof <= {DATA_PATH_WIDTH{1'b0}};
+      eof <= {DATA_PATH_WIDTH{1'b0}};
     end else begin
+      sof <= {{DATA_PATH_WIDTH-1{1'b0}},beat_counter_sof};
+      eof <= {beat_counter_eof,{DATA_PATH_WIDTH-1{1'b0}}};
+
+      if (small_octets_per_frame == 1'b1) begin
+        for (i = 1; i < DATA_PATH_WIDTH; i = i + 1) begin
+          if (cfg_octets_per_frame[ffs(i)] != 1'b1) begin
+            sof[i] <= 1'b1;
+            eof[DATA_PATH_WIDTH-1-i] <= 1'b1;
+          end
+        end
+      end else begin
+      end
     end
   end
-end
 
 endmodule
diff --git a/library/jesd204/jesd204_common/jesd204_frame_align_replace.v b/library/jesd204/jesd204_common/jesd204_frame_align_replace.v
index 3cbc24b00..152ab638b 100755
--- a/library/jesd204/jesd204_common/jesd204_frame_align_replace.v
+++ b/library/jesd204/jesd204_common/jesd204_frame_align_replace.v
@@ -70,177 +70,177 @@ module jesd204_frame_align_replace #(
   output [DATA_PATH_WIDTH-1:0]      charisk_out
 );
 
-localparam DPW_LOG2 = DATA_PATH_WIDTH == 8 ? 3 : DATA_PATH_WIDTH == 4 ? 2 : 1;
+  localparam DPW_LOG2 = DATA_PATH_WIDTH == 8 ? 3 : DATA_PATH_WIDTH == 4 ? 2 : 1;
 
-wire                                  single_eof = cfg_octets_per_frame >= (DATA_PATH_WIDTH-1);
-reg  [DATA_PATH_WIDTH*8-1:0]          data_d1;
-reg  [DATA_PATH_WIDTH*8-1:0]          data_d2;
-wire [DATA_PATH_WIDTH-1:0]            char_is_align;
-reg  [DATA_PATH_WIDTH-1:0]            char_is_align_d1;
-reg  [DATA_PATH_WIDTH-1:0]            char_is_align_d2;
-wire [((DATA_PATH_WIDTH*2)+4)*8-1:0]  saved_data;
-wire [((DATA_PATH_WIDTH*2)+4)-1:0]    saved_char_is_align;
-wire [DATA_PATH_WIDTH*8-1:0]          data_replaced;
-wire [DATA_PATH_WIDTH*8-1:0]          data_prev_eof;
-wire [DATA_PATH_WIDTH*8-1:0]          data_prev_prev_eof;
-reg  [7:0]                            data_prev_eof_single;
-reg  [7:0]                            data_prev_eof_single_int;
-reg                                   char_is_align_prev_single;
+  wire                                  single_eof = cfg_octets_per_frame >= (DATA_PATH_WIDTH-1);
+  reg  [DATA_PATH_WIDTH*8-1:0]          data_d1;
+  reg  [DATA_PATH_WIDTH*8-1:0]          data_d2;
+  wire [DATA_PATH_WIDTH-1:0]            char_is_align;
+  reg  [DATA_PATH_WIDTH-1:0]            char_is_align_d1;
+  reg  [DATA_PATH_WIDTH-1:0]            char_is_align_d2;
+  wire [((DATA_PATH_WIDTH*2)+4)*8-1:0]  saved_data;
+  wire [((DATA_PATH_WIDTH*2)+4)-1:0]    saved_char_is_align;
+  wire [DATA_PATH_WIDTH*8-1:0]          data_replaced;
+  wire [DATA_PATH_WIDTH*8-1:0]          data_prev_eof;
+  wire [DATA_PATH_WIDTH*8-1:0]          data_prev_prev_eof;
+  reg  [7:0]                            data_prev_eof_single;
+  reg  [7:0]                            data_prev_eof_single_int;
+  reg                                   char_is_align_prev_single;
 
-wire [DATA_PATH_WIDTH*8-1:0]          prev_data_1;
-wire [DATA_PATH_WIDTH*8-1:0]          prev_prev_data_1;
-wire [DATA_PATH_WIDTH-1:0]            prev_char_is_align_1;
-wire [DATA_PATH_WIDTH*8-1:0]          prev_data_2;
-wire [DATA_PATH_WIDTH*8-1:0]          prev_prev_data_2;
-wire [DATA_PATH_WIDTH-1:0]            prev_char_is_align_2;
-wire [DATA_PATH_WIDTH*8-1:0]          prev_data_3;
-wire [DATA_PATH_WIDTH*8-1:0]          prev_prev_data_3;
-wire [DATA_PATH_WIDTH-1:0]            prev_char_is_align_3;
-wire [DATA_PATH_WIDTH*8-1:0]          prev_data_4;
-wire [DATA_PATH_WIDTH*8-1:0]          prev_prev_data_4;
-wire [DATA_PATH_WIDTH-1:0]            prev_char_is_align_4;
-wire [DATA_PATH_WIDTH*8-1:0]          prev_data_6;
-wire [DATA_PATH_WIDTH*8-1:0]          prev_prev_data_6;
-wire [DATA_PATH_WIDTH-1:0]            prev_char_is_align_6;
-reg  [DATA_PATH_WIDTH*8-1:0]          prev_data;
-reg  [DATA_PATH_WIDTH*8-1:0]          prev_prev_data;
-reg  [DATA_PATH_WIDTH-1:0]            prev_char_is_align;
-reg  [DPW_LOG2:0]                     jj;
-reg  [DPW_LOG2:0]                     ll;
+  wire [DATA_PATH_WIDTH*8-1:0]          prev_data_1;
+  wire [DATA_PATH_WIDTH*8-1:0]          prev_prev_data_1;
+  wire [DATA_PATH_WIDTH-1:0]            prev_char_is_align_1;
+  wire [DATA_PATH_WIDTH*8-1:0]          prev_data_2;
+  wire [DATA_PATH_WIDTH*8-1:0]          prev_prev_data_2;
+  wire [DATA_PATH_WIDTH-1:0]            prev_char_is_align_2;
+  wire [DATA_PATH_WIDTH*8-1:0]          prev_data_3;
+  wire [DATA_PATH_WIDTH*8-1:0]          prev_prev_data_3;
+  wire [DATA_PATH_WIDTH-1:0]            prev_char_is_align_3;
+  wire [DATA_PATH_WIDTH*8-1:0]          prev_data_4;
+  wire [DATA_PATH_WIDTH*8-1:0]          prev_prev_data_4;
+  wire [DATA_PATH_WIDTH-1:0]            prev_char_is_align_4;
+  wire [DATA_PATH_WIDTH*8-1:0]          prev_data_6;
+  wire [DATA_PATH_WIDTH*8-1:0]          prev_prev_data_6;
+  wire [DATA_PATH_WIDTH-1:0]            prev_char_is_align_6;
+  reg  [DATA_PATH_WIDTH*8-1:0]          prev_data;
+  reg  [DATA_PATH_WIDTH*8-1:0]          prev_prev_data;
+  reg  [DATA_PATH_WIDTH-1:0]            prev_char_is_align;
+  reg  [DPW_LOG2:0]                     jj;
+  reg  [DPW_LOG2:0]                     ll;
 
-always @(posedge clk) begin
-  data_d1 <= data;
-  data_d2 <= data_d1;
-end
-
-always @(posedge clk) begin
-  if(reset) begin
-    char_is_align_d1 <= 'b0;
-    char_is_align_d2 <= 'b0;
-  end else begin
-    char_is_align_d1 <= char_is_align;
-    char_is_align_d2 <= char_is_align_d1;
+  always @(posedge clk) begin
+    data_d1 <= data;
+    data_d2 <= data_d1;
   end
-end
 
-// Capture single EOF in current cycle
-
-always @(eof, data) begin
-  data_prev_eof_single_int = 'b0;
-  for(ll = 0; ll < DATA_PATH_WIDTH; ll=ll+1) begin
-    data_prev_eof_single_int = data_prev_eof_single_int | (data[ll*8 +: 8] & {8{eof[ll]}});
-  end
-end
-
-always @(posedge clk) begin
-  if(reset) begin
-    data_prev_eof_single <= 'b0;
-  end else begin
-    if(|eof && (!IS_RX || !(|char_is_align))) begin
-      data_prev_eof_single <= data_prev_eof_single_int;
+  always @(posedge clk) begin
+    if(reset) begin
+      char_is_align_d1 <= 'b0;
+      char_is_align_d2 <= 'b0;
+    end else begin
+      char_is_align_d1 <= char_is_align;
+      char_is_align_d2 <= char_is_align_d1;
     end
   end
-end
 
-always @(posedge clk) begin
-  if(reset) begin
-    char_is_align_prev_single <= 'b0;
-  end else begin
-    if(|eof) begin
-      char_is_align_prev_single <= |char_is_align;
+  // Capture single EOF in current cycle
+
+  always @(eof, data) begin
+    data_prev_eof_single_int = 'b0;
+    for(ll = 0; ll < DATA_PATH_WIDTH; ll=ll+1) begin
+      data_prev_eof_single_int = data_prev_eof_single_int | (data[ll*8 +: 8] & {8{eof[ll]}});
     end
   end
-end
 
-assign saved_data = {data, data_d1, data_d2[(DATA_PATH_WIDTH*8)-1:(DATA_PATH_WIDTH-4)*8]};
-assign saved_char_is_align = {char_is_align, char_is_align_d1, char_is_align_d2[DATA_PATH_WIDTH-1:DATA_PATH_WIDTH-4]};
-
-genvar ii;
-generate
-for (ii = 0; ii < DATA_PATH_WIDTH; ii = ii + 1) begin: gen_replace_byte
-  assign prev_data_1[ii*8 +:8] = saved_data[(DATA_PATH_WIDTH+3+ii)*8 +: 8];
-  assign prev_data_2[ii*8 +:8] = saved_data[(DATA_PATH_WIDTH+2+ii)*8 +: 8];
-  assign prev_data_3[ii*8 +:8] = saved_data[(DATA_PATH_WIDTH+1+ii)*8 +: 8];
-  assign prev_prev_data_1[ii*8 +:8] = saved_data[(DATA_PATH_WIDTH+2+ii)*8 +: 8];
-  assign prev_prev_data_2[ii*8 +:8] = saved_data[(DATA_PATH_WIDTH+ii)*8 +: 8];
-  assign prev_prev_data_3[ii*8 +:8] = saved_data[(DATA_PATH_WIDTH-2+ii)*8 +: 8];
-  assign prev_char_is_align_1[ii] = saved_char_is_align[(DATA_PATH_WIDTH+3+ii)];
-  assign prev_char_is_align_2[ii] = saved_char_is_align[(DATA_PATH_WIDTH+2+ii)];
-  assign prev_char_is_align_3[ii] = saved_char_is_align[(DATA_PATH_WIDTH+1+ii)];
-
-  if(DATA_PATH_WIDTH == 8) begin : gen_dp_8
-    assign prev_data_4[ii*8 +:8] = saved_data[(DATA_PATH_WIDTH+ii)*8 +: 8];
-    assign prev_data_6[ii*8 +:8] = saved_data[(DATA_PATH_WIDTH-2+ii)*8 +: 8];
-    assign prev_prev_data_4[ii*8 +:8] = saved_data[(DATA_PATH_WIDTH-4+ii)*8 +: 8];
-    assign prev_prev_data_6[ii*8 +:8] = saved_data[(DATA_PATH_WIDTH-8+ii)*8 +: 8];
-    assign prev_char_is_align_4[ii] = saved_char_is_align[(DATA_PATH_WIDTH+ii)];
-    assign prev_char_is_align_6[ii] = saved_char_is_align[(DATA_PATH_WIDTH-2+ii)];
-  end else begin
-    assign prev_data_4[ii*8 +:8] = 'bX;
-    assign prev_data_6[ii*8 +:8] = 'bX;
-    assign prev_prev_data_4[ii*8 +:8] = 'bX;
-    assign prev_prev_data_6[ii*8 +:8] = 'bX;
-    assign prev_char_is_align_4[ii] = 'bX;
-    assign prev_char_is_align_6[ii] = 'bX;
+  always @(posedge clk) begin
+    if(reset) begin
+      data_prev_eof_single <= 'b0;
+    end else begin
+      if(|eof && (!IS_RX || !(|char_is_align))) begin
+        data_prev_eof_single <= data_prev_eof_single_int;
+      end
+    end
   end
 
-  always @(*) begin
-    case(cfg_octets_per_frame)
-      0:
-        begin
-          prev_data[ii*8 +:8] = prev_data_1[ii*8 +:8];
-          prev_prev_data[ii*8 +:8] = prev_prev_data_1[ii*8 +:8];
-          prev_char_is_align[ii] = prev_char_is_align_1[ii];
-        end
-      1:
-        begin
-          prev_data[ii*8 +:8] = prev_data_2[ii*8 +:8];
-          prev_prev_data[ii*8 +:8] = prev_prev_data_2[ii*8 +:8];
-          prev_char_is_align[ii] = prev_char_is_align_2[ii];
-        end
-      2:
-        begin
-          prev_data[ii*8 +:8] = prev_data_3[ii*8 +:8];
-          prev_prev_data[ii*8 +:8] = prev_prev_data_3[ii*8 +:8];
-          prev_char_is_align[ii] = prev_char_is_align_3[ii];
-        end
-      3:
-        begin
-          prev_data[ii*8 +:8] = prev_data_4[ii*8 +:8];
-          prev_prev_data[ii*8 +:8] = prev_prev_data_4[ii*8 +:8];
-          prev_char_is_align[ii] = prev_char_is_align_4[ii];
-        end
-      5:
-        begin
-          prev_data[ii*8 +:8] = prev_data_6[ii*8 +:8];
-          prev_prev_data[ii*8 +:8] = prev_prev_data_6[ii*8 +:8];
-          prev_char_is_align[ii] = prev_char_is_align_6[ii];
-        end
-      default:
-        begin
-          prev_data[ii*8 +:8] = 'bX;
-          prev_prev_data[ii*8 +:8] = 'bX;
-          prev_char_is_align[ii] = 1'bX;
-        end
-    endcase
+  always @(posedge clk) begin
+    if(reset) begin
+      char_is_align_prev_single <= 'b0;
+    end else begin
+      if(|eof) begin
+        char_is_align_prev_single <= |char_is_align;
+      end
+    end
   end
 
-  if(IS_RX) begin : gen_rx
-    // RX
-    assign char_is_align[ii] = !reset && (rx_char_is_a[ii] | rx_char_is_f[ii]);
-    assign data_replaced[ii*8 +: 8] = char_is_align[ii] ? data_prev_eof[ii*8 +: 8] : data[ii*8 +: 8];
-    assign data_prev_eof[ii*8 +: 8] = single_eof ? data_prev_eof_single : prev_char_is_align[ii] ? data_prev_prev_eof[ii*8 +: 8] : prev_data[ii*8 +: 8];
-    assign data_prev_prev_eof[ii*8 +: 8] = prev_prev_data[ii*8 +: 8];
-  end else begin : gen_tx
-    // TX
-    assign data_prev_eof[ii*8 +: 8] = single_eof ? data_prev_eof_single : prev_data[ii*8 +: 8];
-    assign char_is_align[ii] = !reset && (tx_eomf[ii] || (eof[ii] && !(single_eof ? char_is_align_prev_single : prev_char_is_align[ii]))) && (data[ii*8 +: 8] == data_prev_eof[ii*8 +: 8]);
-    assign data_replaced[ii*8 +: 8] = char_is_align[ii] ? (tx_eomf[ii] ? 8'h7c : 8'hfc) : data[ii*8 +: 8];
-  end
-end
-endgenerate
+  assign saved_data = {data, data_d1, data_d2[(DATA_PATH_WIDTH*8)-1:(DATA_PATH_WIDTH-4)*8]};
+  assign saved_char_is_align = {char_is_align, char_is_align_d1, char_is_align_d2[DATA_PATH_WIDTH-1:DATA_PATH_WIDTH-4]};
 
-assign data_out = (cfg_disable_char_replacement || !cfg_disable_scrambler || ENABLED==0) ? data : data_replaced;
-assign charisk_out = (IS_RX || !cfg_disable_scrambler || cfg_disable_char_replacement || ENABLED==0) ? 'b0 : char_is_align;
+  genvar ii;
+  generate
+  for (ii = 0; ii < DATA_PATH_WIDTH; ii = ii + 1) begin: gen_replace_byte
+    assign prev_data_1[ii*8 +:8] = saved_data[(DATA_PATH_WIDTH+3+ii)*8 +: 8];
+    assign prev_data_2[ii*8 +:8] = saved_data[(DATA_PATH_WIDTH+2+ii)*8 +: 8];
+    assign prev_data_3[ii*8 +:8] = saved_data[(DATA_PATH_WIDTH+1+ii)*8 +: 8];
+    assign prev_prev_data_1[ii*8 +:8] = saved_data[(DATA_PATH_WIDTH+2+ii)*8 +: 8];
+    assign prev_prev_data_2[ii*8 +:8] = saved_data[(DATA_PATH_WIDTH+ii)*8 +: 8];
+    assign prev_prev_data_3[ii*8 +:8] = saved_data[(DATA_PATH_WIDTH-2+ii)*8 +: 8];
+    assign prev_char_is_align_1[ii] = saved_char_is_align[(DATA_PATH_WIDTH+3+ii)];
+    assign prev_char_is_align_2[ii] = saved_char_is_align[(DATA_PATH_WIDTH+2+ii)];
+    assign prev_char_is_align_3[ii] = saved_char_is_align[(DATA_PATH_WIDTH+1+ii)];
+
+    if(DATA_PATH_WIDTH == 8) begin : gen_dp_8
+      assign prev_data_4[ii*8 +:8] = saved_data[(DATA_PATH_WIDTH+ii)*8 +: 8];
+      assign prev_data_6[ii*8 +:8] = saved_data[(DATA_PATH_WIDTH-2+ii)*8 +: 8];
+      assign prev_prev_data_4[ii*8 +:8] = saved_data[(DATA_PATH_WIDTH-4+ii)*8 +: 8];
+      assign prev_prev_data_6[ii*8 +:8] = saved_data[(DATA_PATH_WIDTH-8+ii)*8 +: 8];
+      assign prev_char_is_align_4[ii] = saved_char_is_align[(DATA_PATH_WIDTH+ii)];
+      assign prev_char_is_align_6[ii] = saved_char_is_align[(DATA_PATH_WIDTH-2+ii)];
+    end else begin
+      assign prev_data_4[ii*8 +:8] = 'bX;
+      assign prev_data_6[ii*8 +:8] = 'bX;
+      assign prev_prev_data_4[ii*8 +:8] = 'bX;
+      assign prev_prev_data_6[ii*8 +:8] = 'bX;
+      assign prev_char_is_align_4[ii] = 'bX;
+      assign prev_char_is_align_6[ii] = 'bX;
+    end
+
+    always @(*) begin
+      case(cfg_octets_per_frame)
+        0:
+          begin
+            prev_data[ii*8 +:8] = prev_data_1[ii*8 +:8];
+            prev_prev_data[ii*8 +:8] = prev_prev_data_1[ii*8 +:8];
+            prev_char_is_align[ii] = prev_char_is_align_1[ii];
+          end
+        1:
+          begin
+            prev_data[ii*8 +:8] = prev_data_2[ii*8 +:8];
+            prev_prev_data[ii*8 +:8] = prev_prev_data_2[ii*8 +:8];
+            prev_char_is_align[ii] = prev_char_is_align_2[ii];
+          end
+        2:
+          begin
+            prev_data[ii*8 +:8] = prev_data_3[ii*8 +:8];
+            prev_prev_data[ii*8 +:8] = prev_prev_data_3[ii*8 +:8];
+            prev_char_is_align[ii] = prev_char_is_align_3[ii];
+          end
+        3:
+          begin
+            prev_data[ii*8 +:8] = prev_data_4[ii*8 +:8];
+            prev_prev_data[ii*8 +:8] = prev_prev_data_4[ii*8 +:8];
+            prev_char_is_align[ii] = prev_char_is_align_4[ii];
+          end
+        5:
+          begin
+            prev_data[ii*8 +:8] = prev_data_6[ii*8 +:8];
+            prev_prev_data[ii*8 +:8] = prev_prev_data_6[ii*8 +:8];
+            prev_char_is_align[ii] = prev_char_is_align_6[ii];
+          end
+        default:
+          begin
+            prev_data[ii*8 +:8] = 'bX;
+            prev_prev_data[ii*8 +:8] = 'bX;
+            prev_char_is_align[ii] = 1'bX;
+          end
+      endcase
+    end
+
+    if(IS_RX) begin : gen_rx
+      // RX
+      assign char_is_align[ii] = !reset && (rx_char_is_a[ii] | rx_char_is_f[ii]);
+      assign data_replaced[ii*8 +: 8] = char_is_align[ii] ? data_prev_eof[ii*8 +: 8] : data[ii*8 +: 8];
+      assign data_prev_eof[ii*8 +: 8] = single_eof ? data_prev_eof_single : prev_char_is_align[ii] ? data_prev_prev_eof[ii*8 +: 8] : prev_data[ii*8 +: 8];
+      assign data_prev_prev_eof[ii*8 +: 8] = prev_prev_data[ii*8 +: 8];
+    end else begin : gen_tx
+      // TX
+      assign data_prev_eof[ii*8 +: 8] = single_eof ? data_prev_eof_single : prev_data[ii*8 +: 8];
+      assign char_is_align[ii] = !reset && (tx_eomf[ii] || (eof[ii] && !(single_eof ? char_is_align_prev_single : prev_char_is_align[ii]))) && (data[ii*8 +: 8] == data_prev_eof[ii*8 +: 8]);
+      assign data_replaced[ii*8 +: 8] = char_is_align[ii] ? (tx_eomf[ii] ? 8'h7c : 8'hfc) : data[ii*8 +: 8];
+    end
+  end
+  endgenerate
+
+  assign data_out = (cfg_disable_char_replacement || !cfg_disable_scrambler || ENABLED==0) ? data : data_replaced;
+  assign charisk_out = (IS_RX || !cfg_disable_scrambler || cfg_disable_char_replacement || ENABLED==0) ? 'b0 : char_is_align;
 
 endmodule
diff --git a/library/jesd204/jesd204_common/jesd204_frame_mark.v b/library/jesd204/jesd204_common/jesd204_frame_mark.v
index f1fc047b6..a92a880a4 100755
--- a/library/jesd204/jesd204_common/jesd204_frame_mark.v
+++ b/library/jesd204/jesd204_common/jesd204_frame_mark.v
@@ -68,227 +68,226 @@ module jesd204_frame_mark #(
   output reg [DATA_PATH_WIDTH-1:0]  eomf
 );
 
-localparam MAX_OCTETS_PER_FRAME = 32;
-localparam DPW_LOG2 = DATA_PATH_WIDTH == 8 ? 3 : DATA_PATH_WIDTH == 4 ? 2 : 1;
-localparam CW = MAX_OCTETS_PER_FRAME > 128 ? 8 :
-  MAX_OCTETS_PER_FRAME > 64 ? 7 :
-  MAX_OCTETS_PER_FRAME > 32 ? 6 :
-  MAX_OCTETS_PER_FRAME > 16 ? 5 :
-  MAX_OCTETS_PER_FRAME > 8 ? 4 :
-  MAX_OCTETS_PER_FRAME > 4 ? 3 :
-  MAX_OCTETS_PER_FRAME > 2 ? 2 : 1;
-localparam BEATS_PER_FRAME_WIDTH = CW-DPW_LOG2;
-localparam BEATS_PER_MF_WIDTH = 10-DPW_LOG2;
+  localparam MAX_OCTETS_PER_FRAME = 32;
+  localparam DPW_LOG2 = DATA_PATH_WIDTH == 8 ? 3 : DATA_PATH_WIDTH == 4 ? 2 : 1;
+  localparam CW = MAX_OCTETS_PER_FRAME > 128 ? 8 :
+    MAX_OCTETS_PER_FRAME > 64 ? 7 :
+    MAX_OCTETS_PER_FRAME > 32 ? 6 :
+    MAX_OCTETS_PER_FRAME > 16 ? 5 :
+    MAX_OCTETS_PER_FRAME > 8 ? 4 :
+    MAX_OCTETS_PER_FRAME > 4 ? 3 :
+    MAX_OCTETS_PER_FRAME > 2 ? 2 : 1;
+  localparam BEATS_PER_FRAME_WIDTH = CW-DPW_LOG2;
+  localparam BEATS_PER_MF_WIDTH = 10-DPW_LOG2;
 
-// For DATA_PATH_WIDTH = 8, special case if F*K%8=4
-wire                              octets_per_mf_4_mod_8 = (DATA_PATH_WIDTH == 8) && ~cfg_octets_per_multiframe[2];
-reg [BEATS_PER_MF_WIDTH-1:0]      cur_beats_per_multiframe;
-reg                               mf_phase;
-reg [1:0]                         beat_cnt_mod_3;
-reg [BEATS_PER_FRAME_WIDTH-1:0]   beat_cnt_frame;
-wire                              cur_sof;
-wire                              cur_eof;
-reg [BEATS_PER_MF_WIDTH-1:0]      beat_cnt_mf;
-wire                              cur_somf;
-wire                              cur_eomf;
-wire [DATA_PATH_WIDTH-1:0]        default_sof;
-wire [DATA_PATH_WIDTH-1:0]        default_eof;
+  // For DATA_PATH_WIDTH = 8, special case if F*K%8=4
+  wire                              octets_per_mf_4_mod_8 = (DATA_PATH_WIDTH == 8) && ~cfg_octets_per_multiframe[2];
+  reg [BEATS_PER_MF_WIDTH-1:0]      cur_beats_per_multiframe;
+  reg                               mf_phase;
+  reg [1:0]                         beat_cnt_mod_3;
+  reg [BEATS_PER_FRAME_WIDTH-1:0]   beat_cnt_frame;
+  wire                              cur_sof;
+  wire                              cur_eof;
+  reg [BEATS_PER_MF_WIDTH-1:0]      beat_cnt_mf;
+  wire                              cur_somf;
+  wire                              cur_eomf;
+  wire [DATA_PATH_WIDTH-1:0]        default_sof;
+  wire [DATA_PATH_WIDTH-1:0]        default_eof;
 
-wire [BEATS_PER_FRAME_WIDTH-1:0]  cfg_beats_per_frame = cfg_octets_per_frame[CW-1:DPW_LOG2];
-reg [DATA_PATH_WIDTH-1:0] sof_f_3[2:0];
-reg [DATA_PATH_WIDTH-1:0] eof_f_3[2:0];
-reg [DATA_PATH_WIDTH-1:0] sof_f_6[2:0];
-reg [DATA_PATH_WIDTH-1:0] eof_f_6[2:0];
-reg [DATA_PATH_WIDTH-1:0] sof_f_12[2:0];
-reg [DATA_PATH_WIDTH-1:0] eof_f_12[2:0];
+  wire [BEATS_PER_FRAME_WIDTH-1:0]  cfg_beats_per_frame = cfg_octets_per_frame[CW-1:DPW_LOG2];
+  reg [DATA_PATH_WIDTH-1:0] sof_f_3[2:0];
+  reg [DATA_PATH_WIDTH-1:0] eof_f_3[2:0];
+  reg [DATA_PATH_WIDTH-1:0] sof_f_6[2:0];
+  reg [DATA_PATH_WIDTH-1:0] eof_f_6[2:0];
+  reg [DATA_PATH_WIDTH-1:0] sof_f_12[2:0];
+  reg [DATA_PATH_WIDTH-1:0] eof_f_12[2:0];
 
-generate
-if(DATA_PATH_WIDTH == 4) begin : gen_dp_4
-initial begin
-  sof_f_3[0] = {4'b1001};
-  sof_f_3[1] = {4'b0100};
-  sof_f_3[2] = {4'b0010};
-  eof_f_3[0] = {4'b0100};
-  eof_f_3[1] = {4'b0010};
-  eof_f_3[2] = {4'b1001};
-  sof_f_6[0] = {4'b0001};
-  sof_f_6[1] = {4'b0100};
-  sof_f_6[2] = {4'b0000};
-  eof_f_6[0] = {4'b0000};
-  eof_f_6[1] = {4'b0010};
-  eof_f_6[2] = {4'b1000};
-end
-end else if(DATA_PATH_WIDTH == 6) begin : gen_dp_6
-initial begin
-  sof_f_3[0] = {6'b001001};
-  sof_f_3[1] = {6'b001001};
-  sof_f_3[2] = {6'b001001};
-  eof_f_3[0] = {6'b100100};
-  eof_f_3[1] = {6'b100100};
-  eof_f_3[2] = {6'b100100};
-  sof_f_6[0] = {6'b000001};
-  sof_f_6[1] = {6'b000001};
-  sof_f_6[2] = {6'b000001};
-  eof_f_6[0] = {6'b100000};
-  eof_f_6[1] = {6'b100000};
-  eof_f_6[2] = {6'b100000};
-end
-end else if(DATA_PATH_WIDTH == 8) begin : gen_dp_8
-initial begin
-  sof_f_3[0]  = {8'b01001001};
-  sof_f_3[1]  = {8'b10010010};
-  sof_f_3[2]  = {8'b00100100};
-  eof_f_3[0]  = {8'b00100100};
-  eof_f_3[1]  = {8'b01001001};
-  eof_f_3[2]  = {8'b10010010};
-  sof_f_6[0]  = {8'b01000001};
-  sof_f_6[1]  = {8'b00010000};
-  sof_f_6[2]  = {8'b00000100};
-  eof_f_6[0]  = {8'b00100000};
-  eof_f_6[1]  = {8'b00001000};
-  eof_f_6[2]  = {8'b10000010};
-  sof_f_12[0] = {8'b00000001};
-  sof_f_12[1] = {8'b00010000};
-  sof_f_12[2] = {8'b00000000};
-  eof_f_12[0] = {8'b00000000};
-  eof_f_12[1] = {8'b00001000};
-  eof_f_12[2] = {8'b10000000};
-end
-end
-// Beat count % 3, to support F=3, 6, 12
-always @(posedge clk) begin
-  if(reset) begin
-    beat_cnt_mod_3 <= 2'd0;
-  end else begin
-    if(beat_cnt_mod_3 == 2'd2) begin
+  generate
+  if(DATA_PATH_WIDTH == 4) begin : gen_dp_4
+  initial begin
+    sof_f_3[0] = {4'b1001};
+    sof_f_3[1] = {4'b0100};
+    sof_f_3[2] = {4'b0010};
+    eof_f_3[0] = {4'b0100};
+    eof_f_3[1] = {4'b0010};
+    eof_f_3[2] = {4'b1001};
+    sof_f_6[0] = {4'b0001};
+    sof_f_6[1] = {4'b0100};
+    sof_f_6[2] = {4'b0000};
+    eof_f_6[0] = {4'b0000};
+    eof_f_6[1] = {4'b0010};
+    eof_f_6[2] = {4'b1000};
+  end
+  end else if(DATA_PATH_WIDTH == 6) begin : gen_dp_6
+  initial begin
+    sof_f_3[0] = {6'b001001};
+    sof_f_3[1] = {6'b001001};
+    sof_f_3[2] = {6'b001001};
+    eof_f_3[0] = {6'b100100};
+    eof_f_3[1] = {6'b100100};
+    eof_f_3[2] = {6'b100100};
+    sof_f_6[0] = {6'b000001};
+    sof_f_6[1] = {6'b000001};
+    sof_f_6[2] = {6'b000001};
+    eof_f_6[0] = {6'b100000};
+    eof_f_6[1] = {6'b100000};
+    eof_f_6[2] = {6'b100000};
+  end
+  end else if(DATA_PATH_WIDTH == 8) begin : gen_dp_8
+  initial begin
+    sof_f_3[0]  = {8'b01001001};
+    sof_f_3[1]  = {8'b10010010};
+    sof_f_3[2]  = {8'b00100100};
+    eof_f_3[0]  = {8'b00100100};
+    eof_f_3[1]  = {8'b01001001};
+    eof_f_3[2]  = {8'b10010010};
+    sof_f_6[0]  = {8'b01000001};
+    sof_f_6[1]  = {8'b00010000};
+    sof_f_6[2]  = {8'b00000100};
+    eof_f_6[0]  = {8'b00100000};
+    eof_f_6[1]  = {8'b00001000};
+    eof_f_6[2]  = {8'b10000010};
+    sof_f_12[0] = {8'b00000001};
+    sof_f_12[1] = {8'b00010000};
+    sof_f_12[2] = {8'b00000000};
+    eof_f_12[0] = {8'b00000000};
+    eof_f_12[1] = {8'b00001000};
+    eof_f_12[2] = {8'b10000000};
+  end
+  end
+  // Beat count % 3, to support F=3, 6, 12
+  always @(posedge clk) begin
+    if(reset) begin
       beat_cnt_mod_3 <= 2'd0;
     end else begin
-      beat_cnt_mod_3 <= beat_cnt_mod_3 + 1'b1;
+      if(beat_cnt_mod_3 == 2'd2) begin
+        beat_cnt_mod_3 <= 2'd0;
+      end else begin
+        beat_cnt_mod_3 <= beat_cnt_mod_3 + 1'b1;
+      end
     end
   end
-end
 
-// Beat count per frame
-always @(posedge clk) begin
-  if(reset) begin
-    beat_cnt_frame <= {BEATS_PER_FRAME_WIDTH{1'b0}};
-  end else begin
-    if(beat_cnt_frame == cfg_beats_per_frame) begin
+  // Beat count per frame
+  always @(posedge clk) begin
+    if(reset) begin
       beat_cnt_frame <= {BEATS_PER_FRAME_WIDTH{1'b0}};
     end else begin
-      beat_cnt_frame <= beat_cnt_frame + 1'b1;
+      if(beat_cnt_frame == cfg_beats_per_frame) begin
+        beat_cnt_frame <= {BEATS_PER_FRAME_WIDTH{1'b0}};
+      end else begin
+        beat_cnt_frame <= beat_cnt_frame + 1'b1;
+      end
     end
   end
-end
 
-assign cur_sof = beat_cnt_frame == 0;
-assign cur_eof = beat_cnt_frame == cfg_beats_per_frame;
+  assign cur_sof = beat_cnt_frame == 0;
+  assign cur_eof = beat_cnt_frame == cfg_beats_per_frame;
 
-assign default_sof = {{DATA_PATH_WIDTH-1{1'b0}}, cur_sof};
-assign default_eof = {cur_eof, {DATA_PATH_WIDTH-1{1'b0}}};
+  assign default_sof = {{DATA_PATH_WIDTH-1{1'b0}}, cur_sof};
+  assign default_eof = {cur_eof, {DATA_PATH_WIDTH-1{1'b0}}};
 
-// cfg_octets_per_frame must be a multiple of DATA_PATH_WIDTH
-// except for the following supported special cases
-always @(*) begin
-  case(cfg_octets_per_frame)
-    8'd0:
-      begin
-        sof = {DATA_PATH_WIDTH{1'b1}};
-        eof = {DATA_PATH_WIDTH{1'b1}};
-      end
-    8'd1:
-      begin
-        sof = {DATA_PATH_WIDTH/2{2'b01}};
-        eof = {DATA_PATH_WIDTH/2{2'b10}};
-      end
-    8'd2:
-      begin
-        sof = sof_f_3[beat_cnt_mod_3];
-        eof = eof_f_3[beat_cnt_mod_3];
-      end
-    8'd3:
-      begin
-        sof = {DATA_PATH_WIDTH/4{4'b0001}};
-        eof = {DATA_PATH_WIDTH/4{4'b1000}};
-      end
-    8'd5:
-      begin
-        sof = sof_f_6[beat_cnt_mod_3];
-        eof = eof_f_6[beat_cnt_mod_3];
-      end
-    8'd11:
-      begin
-        sof = (DATA_PATH_WIDTH == 4) ? default_sof : sof_f_12[beat_cnt_mod_3];
-        eof = (DATA_PATH_WIDTH == 4) ? default_eof : eof_f_12[beat_cnt_mod_3];
-      end
-    default:
-      begin
-        sof = default_sof;
-        eof = default_eof;
-      end
-  endcase
-end
+  // cfg_octets_per_frame must be a multiple of DATA_PATH_WIDTH
+  // except for the following supported special cases
+  always @(*) begin
+    case(cfg_octets_per_frame)
+      8'd0:
+        begin
+          sof = {DATA_PATH_WIDTH{1'b1}};
+          eof = {DATA_PATH_WIDTH{1'b1}};
+        end
+      8'd1:
+        begin
+          sof = {DATA_PATH_WIDTH/2{2'b01}};
+          eof = {DATA_PATH_WIDTH/2{2'b10}};
+        end
+      8'd2:
+        begin
+          sof = sof_f_3[beat_cnt_mod_3];
+          eof = eof_f_3[beat_cnt_mod_3];
+        end
+      8'd3:
+        begin
+          sof = {DATA_PATH_WIDTH/4{4'b0001}};
+          eof = {DATA_PATH_WIDTH/4{4'b1000}};
+        end
+      8'd5:
+        begin
+          sof = sof_f_6[beat_cnt_mod_3];
+          eof = eof_f_6[beat_cnt_mod_3];
+        end
+      8'd11:
+        begin
+          sof = (DATA_PATH_WIDTH == 4) ? default_sof : sof_f_12[beat_cnt_mod_3];
+          eof = (DATA_PATH_WIDTH == 4) ? default_eof : eof_f_12[beat_cnt_mod_3];
+        end
+      default:
+        begin
+          sof = default_sof;
+          eof = default_eof;
+        end
+    endcase
+  end
 
-// Beat count per multiframe
-// Only support F*K%4=0
-// If DATA_PATH_WIDTH == 4, or if DATA_PATH_WIDTH == 8 and F*K%8=0,
-// then multiframes always start/end at the first/last octet in the data bus
-// Otherwise, start/end of multiframe have more complicated patterns
-always @(posedge clk) begin
-  if(reset) begin
-    beat_cnt_mf <= 8'b0;
-    mf_phase <= 1'b0;
-  end else begin
-    if(beat_cnt_mf == cur_beats_per_multiframe) begin
+  // Beat count per multiframe
+  // Only support F*K%4=0
+  // If DATA_PATH_WIDTH == 4, or if DATA_PATH_WIDTH == 8 and F*K%8=0,
+  // then multiframes always start/end at the first/last octet in the data bus
+  // Otherwise, start/end of multiframe have more complicated patterns
+  always @(posedge clk) begin
+    if(reset) begin
       beat_cnt_mf <= 8'b0;
-      mf_phase <= ~mf_phase;
+      mf_phase <= 1'b0;
     end else begin
-      beat_cnt_mf <= beat_cnt_mf + 1'b1;
+      if(beat_cnt_mf == cur_beats_per_multiframe) begin
+        beat_cnt_mf <= 8'b0;
+        mf_phase <= ~mf_phase;
+      end else begin
+        beat_cnt_mf <= beat_cnt_mf + 1'b1;
+      end
     end
   end
-end
 
-assign cur_somf = beat_cnt_mf == 0;
-assign cur_eomf = beat_cnt_mf == cur_beats_per_multiframe;
+  assign cur_somf = beat_cnt_mf == 0;
+  assign cur_eomf = beat_cnt_mf == cur_beats_per_multiframe;
 
-if(DATA_PATH_WIDTH == 4 || DATA_PATH_WIDTH == 6) begin : gen_mf_dp_4_6
-always @(*) begin
-  cur_beats_per_multiframe = cfg_beats_per_multiframe;
-  somf = {{DATA_PATH_WIDTH-1{1'b0}}, cur_somf};
-  eomf = {cur_eomf, {DATA_PATH_WIDTH-1{1'b0}}};
-end
-end else if(DATA_PATH_WIDTH == 8) begin : gen_mf_dp_8
-always @(*) begin
-   // cfg_octets_per_multiframe = 4
-   if(cfg_octets_per_multiframe[9:2] == 0) begin
-     cur_beats_per_multiframe = 8'hXX;
-     somf = 8'h11;
-     eomf = 8'h88;
-   end else if(~octets_per_mf_4_mod_8) begin
-     cur_beats_per_multiframe = cfg_beats_per_multiframe;
-     somf = {{DATA_PATH_WIDTH-1{1'b0}}, cur_somf};
-     eomf = {cur_eomf, {DATA_PATH_WIDTH-1{1'b0}}};
-   end else begin
-      cur_beats_per_multiframe = cfg_beats_per_multiframe - mf_phase;
-      if((mf_phase == 0) && (beat_cnt_mf == 0)) begin
-        somf = 8'h01;
-      end else if((mf_phase == 0) && (beat_cnt_mf == cur_beats_per_multiframe)) begin
-        somf = 8'h10;
-      end else begin
-        somf = 8'b0;
-      end
+  if(DATA_PATH_WIDTH == 4 || DATA_PATH_WIDTH == 6) begin : gen_mf_dp_4_6
+  always @(*) begin
+    cur_beats_per_multiframe = cfg_beats_per_multiframe;
+    somf = {{DATA_PATH_WIDTH-1{1'b0}}, cur_somf};
+    eomf = {cur_eomf, {DATA_PATH_WIDTH-1{1'b0}}};
+  end
+  end else if(DATA_PATH_WIDTH == 8) begin : gen_mf_dp_8
+  always @(*) begin
+     // cfg_octets_per_multiframe = 4
+     if(cfg_octets_per_multiframe[9:2] == 0) begin
+       cur_beats_per_multiframe = 8'hXX;
+       somf = 8'h11;
+       eomf = 8'h88;
+     end else if(~octets_per_mf_4_mod_8) begin
+       cur_beats_per_multiframe = cfg_beats_per_multiframe;
+       somf = {{DATA_PATH_WIDTH-1{1'b0}}, cur_somf};
+       eomf = {cur_eomf, {DATA_PATH_WIDTH-1{1'b0}}};
+     end else begin
+        cur_beats_per_multiframe = cfg_beats_per_multiframe - mf_phase;
+        if((mf_phase == 0) && (beat_cnt_mf == 0)) begin
+          somf = 8'h01;
+        end else if((mf_phase == 0) && (beat_cnt_mf == cur_beats_per_multiframe)) begin
+          somf = 8'h10;
+        end else begin
+          somf = 8'b0;
+        end
 
-      if((mf_phase == 0) && (beat_cnt_mf == cur_beats_per_multiframe)) begin
-        eomf = 8'h08;
-      end else if((mf_phase == 1) && (beat_cnt_mf == cur_beats_per_multiframe)) begin
-        eomf = 8'h80;
-      end else begin
-        eomf = 8'b0;
-      end
-   end
-end
-end
-endgenerate
+        if((mf_phase == 0) && (beat_cnt_mf == cur_beats_per_multiframe)) begin
+          eomf = 8'h08;
+        end else if((mf_phase == 1) && (beat_cnt_mf == cur_beats_per_multiframe)) begin
+          eomf = 8'h80;
+        end else begin
+          eomf = 8'b0;
+        end
+     end
+  end
+  end
+  endgenerate
 
 endmodule
-
diff --git a/library/jesd204/jesd204_common/jesd204_lmfc.v b/library/jesd204/jesd204_common/jesd204_lmfc.v
index af6f06525..9b3d9fe1e 100755
--- a/library/jesd204/jesd204_common/jesd204_lmfc.v
+++ b/library/jesd204/jesd204_common/jesd204_lmfc.v
@@ -73,167 +73,167 @@ module jesd204_lmfc #(
   output reg sysref_alignment_error
 );
 
-localparam DPW_LOG2 = DATA_PATH_WIDTH == 8 ? 3 : DATA_PATH_WIDTH == 4 ? 2 : 1;
-localparam BEATS_PER_MF_WIDTH = 10-DPW_LOG2;
+  localparam DPW_LOG2 = DATA_PATH_WIDTH == 8 ? 3 : DATA_PATH_WIDTH == 4 ? 2 : 1;
+  localparam BEATS_PER_MF_WIDTH = 10-DPW_LOG2;
 
-//wire [BEATS_PER_MF_WIDTH-1:0]     cfg_beats_per_multiframe = cfg_octets_per_multiframe[9:DPW_LOG2];
-reg  [BEATS_PER_MF_WIDTH:0]       cfg_whole_beats_per_multiframe;
+  //wire [BEATS_PER_MF_WIDTH-1:0]     cfg_beats_per_multiframe = cfg_octets_per_multiframe[9:DPW_LOG2];
+  reg  [BEATS_PER_MF_WIDTH:0]       cfg_whole_beats_per_multiframe;
 
-reg sysref_r = 1'b0;
-reg sysref_d1 = 1'b0;
-reg sysref_d2 = 1'b0;
-reg sysref_d3 = 1'b0;
+  reg sysref_r = 1'b0;
+  reg sysref_d1 = 1'b0;
+  reg sysref_d2 = 1'b0;
+  reg sysref_d3 = 1'b0;
 
-reg sysref_captured;
+  reg sysref_captured;
 
-/* lmfc_octet_counter = lmfc_counter * (char_clock_rate / device_clock_rate) */
-reg [7:0] lmfc_counter_next = 'h00;
+  /* lmfc_octet_counter = lmfc_counter * (char_clock_rate / device_clock_rate) */
+  reg [7:0] lmfc_counter_next = 'h00;
 
-reg lmfc_clk_p1 = 1'b1;
+  reg lmfc_clk_p1 = 1'b1;
 
-reg lmfc_active = 1'b0;
+  reg lmfc_active = 1'b0;
 
-always @(posedge clk) begin
-  sysref_r <= sysref;
-end
-
-/*
- * Unfortunately setup and hold are often ignored on the sysref signal relative
- * to the device clock. The device will often still work fine, just not
- * deterministic. Reduce the probability that the meta-stability creeps into the
- * reset of the system and causes non-reproducible issues.
- */
-always @(posedge clk) begin
-  sysref_d1 <= sysref_r;
-  sysref_d2 <= sysref_d1;
-  sysref_d3 <= sysref_d2;
-end
-
-always @(posedge clk) begin
-  if (sysref_d3 == 1'b0 && sysref_d2 == 1'b1 && cfg_sysref_disable == 1'b0) begin
-    sysref_edge <= 1'b1;
-  end else begin
-    sysref_edge <= 1'b0;
+  always @(posedge clk) begin
+    sysref_r <= sysref;
   end
-end
 
-always @(posedge clk) begin
-  if (reset == 1'b1) begin
-    sysref_captured <= 1'b0;
-  end else if (sysref_edge == 1'b1) begin
-    sysref_captured <= 1'b1;
+  /*
+   * Unfortunately setup and hold are often ignored on the sysref signal relative
+   * to the device clock. The device will often still work fine, just not
+   * deterministic. Reduce the probability that the meta-stability creeps into the
+   * reset of the system and causes non-reproducible issues.
+   */
+  always @(posedge clk) begin
+    sysref_d1 <= sysref_r;
+    sysref_d2 <= sysref_d1;
+    sysref_d3 <= sysref_d2;
   end
-end
 
-/*
- * The configuration must be static when the core is out of reset. Otherwise
- * undefined behaviour might occur.
- * E.g. lmfc_counter > beats_per_multiframe
- *
- * To change the configuration first assert reset, then update the configuration
- * setting, finally deassert reset.
- */
-
-/*
- * For DATA_PATH_WIDTH == 8, F*K%8=4, set
- * cfg_beats_per_multiframe = cfg_beats_per_multiframe*2
- * LMFC will be twice the actual length
- */
-always @(*) begin
-  if((LINK_MODE == 1) && (DATA_PATH_WIDTH == 8) && ~cfg_octets_per_multiframe[2]) begin
-    cfg_whole_beats_per_multiframe = cfg_beats_per_multiframe*2;
-  end else begin
-    cfg_whole_beats_per_multiframe = cfg_beats_per_multiframe;
-  end
-end
-
-always @(*) begin
-  if (lmfc_counter == cfg_whole_beats_per_multiframe) begin
-    lmfc_counter_next = 'h00;
-  end else begin
-    lmfc_counter_next = lmfc_counter + 1'b1;
-  end
-end
-
-always @(posedge clk) begin
-  if (reset == 1'b1) begin
-    lmfc_counter <= 'h01;
-    lmfc_active <= cfg_sysref_disable;
-  end else begin
-    /*
-     * In oneshot mode only the first occurence of the
-     * SYSREF signal is used for alignment.
-     */
-    if (sysref_edge == 1'b1 &&
-        (cfg_sysref_oneshot == 1'b0 || sysref_captured == 1'b0)) begin
-      lmfc_counter <= cfg_lmfc_offset;
-      lmfc_active <= 1'b1;
+  always @(posedge clk) begin
+    if (sysref_d3 == 1'b0 && sysref_d2 == 1'b1 && cfg_sysref_disable == 1'b0) begin
+      sysref_edge <= 1'b1;
     end else begin
-      lmfc_counter <= lmfc_counter_next;
+      sysref_edge <= 1'b0;
     end
   end
-end
 
-always @(posedge clk) begin
-  if (reset == 1'b1) begin
-    sysref_alignment_error <= 1'b0;
-  end else begin
-    /*
-     * Alignement error is reported regardless of oneshot mode
-     * setting.
-     */
-    sysref_alignment_error <= 1'b0;
-    if (sysref_edge == 1'b1 && lmfc_active == 1'b1 &&
-        lmfc_counter_next != cfg_lmfc_offset) begin
-      sysref_alignment_error <= 1'b1;
+  always @(posedge clk) begin
+    if (reset == 1'b1) begin
+      sysref_captured <= 1'b0;
+    end else if (sysref_edge == 1'b1) begin
+      sysref_captured <= 1'b1;
     end
   end
-end
 
-always @(posedge clk) begin
-  if (lmfc_counter == 'h00 && lmfc_active == 1'b1) begin
-    lmfc_edge <= 1'b1;
-  end else begin
-    lmfc_edge <= 1'b0;
-  end
-end
+  /*
+   * The configuration must be static when the core is out of reset. Otherwise
+   * undefined behaviour might occur.
+   * E.g. lmfc_counter > beats_per_multiframe
+   *
+   * To change the configuration first assert reset, then update the configuration
+   * setting, finally deassert reset.
+   */
 
-// 1 MultiBlock = 32 blocks
-always @(posedge clk) begin
-  if (lmfc_counter[4:0] == 'h00 && lmfc_active == 1'b1) begin
-    lmc_edge <= 1'b1;
-  end else begin
-    lmc_edge <= 1'b0;
+  /*
+   * For DATA_PATH_WIDTH == 8, F*K%8=4, set
+   * cfg_beats_per_multiframe = cfg_beats_per_multiframe*2
+   * LMFC will be twice the actual length
+   */
+  always @(*) begin
+    if((LINK_MODE == 1) && (DATA_PATH_WIDTH == 8) && ~cfg_octets_per_multiframe[2]) begin
+      cfg_whole_beats_per_multiframe = cfg_beats_per_multiframe*2;
+    end else begin
+      cfg_whole_beats_per_multiframe = cfg_beats_per_multiframe;
+    end
   end
-end
-always @(posedge clk) begin
-  if (lmfc_counter[2:0] == 'h00 && lmfc_active == 1'b1) begin
-    lmc_quarter_edge <= 1'b1;
-  end else begin
-    lmc_quarter_edge <= 1'b0;
-  end
-end
-// End of Extended MultiBlock
-always @(posedge clk) begin
-  if (lmfc_active == 1'b1) begin
-    eoemb <= lmfc_counter[7:5] == cfg_whole_beats_per_multiframe[7:5];
-  end else begin
-    eoemb <= 1'b0;
-  end
-end
 
-always @(posedge clk) begin
-  if (reset == 1'b1) begin
-    lmfc_clk_p1 <= 1'b0;
-  end else if (lmfc_active == 1'b1) begin
+  always @(*) begin
     if (lmfc_counter == cfg_whole_beats_per_multiframe) begin
-      lmfc_clk_p1 <= 1'b1;
-    end else if (lmfc_counter == cfg_whole_beats_per_multiframe[7:1]) begin
-      lmfc_clk_p1 <= 1'b0;
+      lmfc_counter_next = 'h00;
+    end else begin
+      lmfc_counter_next = lmfc_counter + 1'b1;
     end
   end
 
-  lmfc_clk <= lmfc_clk_p1;
-end
+  always @(posedge clk) begin
+    if (reset == 1'b1) begin
+      lmfc_counter <= 'h01;
+      lmfc_active <= cfg_sysref_disable;
+    end else begin
+      /*
+       * In oneshot mode only the first occurence of the
+       * SYSREF signal is used for alignment.
+       */
+      if (sysref_edge == 1'b1 &&
+          (cfg_sysref_oneshot == 1'b0 || sysref_captured == 1'b0)) begin
+        lmfc_counter <= cfg_lmfc_offset;
+        lmfc_active <= 1'b1;
+      end else begin
+        lmfc_counter <= lmfc_counter_next;
+      end
+    end
+  end
+
+  always @(posedge clk) begin
+    if (reset == 1'b1) begin
+      sysref_alignment_error <= 1'b0;
+    end else begin
+      /*
+       * Alignement error is reported regardless of oneshot mode
+       * setting.
+       */
+      sysref_alignment_error <= 1'b0;
+      if (sysref_edge == 1'b1 && lmfc_active == 1'b1 &&
+          lmfc_counter_next != cfg_lmfc_offset) begin
+        sysref_alignment_error <= 1'b1;
+      end
+    end
+  end
+
+  always @(posedge clk) begin
+    if (lmfc_counter == 'h00 && lmfc_active == 1'b1) begin
+      lmfc_edge <= 1'b1;
+    end else begin
+      lmfc_edge <= 1'b0;
+    end
+  end
+
+  // 1 MultiBlock = 32 blocks
+  always @(posedge clk) begin
+    if (lmfc_counter[4:0] == 'h00 && lmfc_active == 1'b1) begin
+      lmc_edge <= 1'b1;
+    end else begin
+      lmc_edge <= 1'b0;
+    end
+  end
+  always @(posedge clk) begin
+    if (lmfc_counter[2:0] == 'h00 && lmfc_active == 1'b1) begin
+      lmc_quarter_edge <= 1'b1;
+    end else begin
+      lmc_quarter_edge <= 1'b0;
+    end
+  end
+  // End of Extended MultiBlock
+  always @(posedge clk) begin
+    if (lmfc_active == 1'b1) begin
+      eoemb <= lmfc_counter[7:5] == cfg_whole_beats_per_multiframe[7:5];
+    end else begin
+      eoemb <= 1'b0;
+    end
+  end
+
+  always @(posedge clk) begin
+    if (reset == 1'b1) begin
+      lmfc_clk_p1 <= 1'b0;
+    end else if (lmfc_active == 1'b1) begin
+      if (lmfc_counter == cfg_whole_beats_per_multiframe) begin
+        lmfc_clk_p1 <= 1'b1;
+      end else if (lmfc_counter == cfg_whole_beats_per_multiframe[7:1]) begin
+        lmfc_clk_p1 <= 1'b0;
+      end
+    end
+
+    lmfc_clk <= lmfc_clk_p1;
+  end
 
 endmodule
diff --git a/library/jesd204/jesd204_common/jesd204_scrambler.v b/library/jesd204/jesd204_common/jesd204_scrambler.v
index 2dd86ddc7..91f5cc83a 100644
--- a/library/jesd204/jesd204_common/jesd204_scrambler.v
+++ b/library/jesd204/jesd204_common/jesd204_scrambler.v
@@ -57,37 +57,37 @@ module jesd204_scrambler #(
   output [WIDTH-1:0] data_out
 );
 
-reg [14:0] state = 'h7f80;
-reg [WIDTH-1:0] swizzle_out;
-wire [WIDTH-1:0] swizzle_in;
-wire [WIDTH-1:0] feedback;
-wire [WIDTH-1+15:0] full_state;
+  reg [14:0] state = 'h7f80;
+  reg [WIDTH-1:0] swizzle_out;
+  wire [WIDTH-1:0] swizzle_in;
+  wire [WIDTH-1:0] feedback;
+  wire [WIDTH-1+15:0] full_state;
 
-generate
-genvar i;
-for (i = 0; i < WIDTH / 8; i = i + 1) begin: gen_swizzle
-  assign swizzle_in[WIDTH-1-i*8:WIDTH-i*8-8] = data_in[i*8+7:i*8];
-  assign data_out[WIDTH-1-i*8:WIDTH-i*8-8] = swizzle_out[i*8+7:i*8];
-end
-endgenerate
-
-assign full_state = {state,DESCRAMBLE ? swizzle_in : feedback};
-assign feedback = full_state[WIDTH-1+15:15] ^ full_state[WIDTH-1+14:14] ^ swizzle_in;
-
-always @(*) begin
-  if (enable == 1'b0) begin
-    swizzle_out = swizzle_in;
-  end else begin
-    swizzle_out = feedback;
+  generate
+  genvar i;
+  for (i = 0; i < WIDTH / 8; i = i + 1) begin: gen_swizzle
+    assign swizzle_in[WIDTH-1-i*8:WIDTH-i*8-8] = data_in[i*8+7:i*8];
+    assign data_out[WIDTH-1-i*8:WIDTH-i*8-8] = swizzle_out[i*8+7:i*8];
   end
-end
+  endgenerate
 
-always @(posedge clk) begin
-  if (reset == 1'b1) begin
-    state <= 'h7f80;
-  end else begin
-    state <= full_state[14:0];
+  assign full_state = {state,DESCRAMBLE ? swizzle_in : feedback};
+  assign feedback = full_state[WIDTH-1+15:15] ^ full_state[WIDTH-1+14:14] ^ swizzle_in;
+
+  always @(*) begin
+    if (enable == 1'b0) begin
+      swizzle_out = swizzle_in;
+    end else begin
+      swizzle_out = feedback;
+    end
+  end
+
+  always @(posedge clk) begin
+    if (reset == 1'b1) begin
+      state <= 'h7f80;
+    end else begin
+      state <= full_state[14:0];
+    end
   end
-end
 
 endmodule
diff --git a/library/jesd204/jesd204_common/jesd204_scrambler_64b.v b/library/jesd204/jesd204_common/jesd204_scrambler_64b.v
index 83f43900f..6b8eaf312 100644
--- a/library/jesd204/jesd204_common/jesd204_scrambler_64b.v
+++ b/library/jesd204/jesd204_common/jesd204_scrambler_64b.v
@@ -57,27 +57,27 @@ module jesd204_scrambler_64b #(
   output reg [WIDTH-1:0] data_out
 );
 
-reg [57:0] state = {1'b1,57'b0};
-wire [WIDTH-1:0] feedback;
-wire [WIDTH-1+58:0] full_state;
+  reg [57:0] state = {1'b1,57'b0};
+  wire [WIDTH-1:0] feedback;
+  wire [WIDTH-1+58:0] full_state;
 
-assign full_state = {state,DESCRAMBLE ? data_in : feedback};
-assign feedback = full_state[WIDTH-1+58:58] ^ full_state[WIDTH-1:39] ^ data_in;
+  assign full_state = {state,DESCRAMBLE ? data_in : feedback};
+  assign feedback = full_state[WIDTH-1+58:58] ^ full_state[WIDTH-1:39] ^ data_in;
 
-always @(*) begin
-  if (enable == 1'b0) begin
-    data_out = data_in;
-  end else begin
-    data_out = feedback;
+  always @(*) begin
+    if (enable == 1'b0) begin
+      data_out = data_in;
+    end else begin
+      data_out = feedback;
+    end
   end
-end
 
-always @(posedge clk) begin
-  if (reset == 1'b1) begin
-    state <= {1'b1,57'b0};
-  end else begin
-    state <= full_state[57:0] ^ {full_state[38:0],19'b0};
+  always @(posedge clk) begin
+    if (reset == 1'b1) begin
+      state <= {1'b1,57'b0};
+    end else begin
+      state <= full_state[57:0] ^ {full_state[38:0],19'b0};
+    end
   end
-end
 
 endmodule
diff --git a/library/jesd204/jesd204_common/pipeline_stage.v b/library/jesd204/jesd204_common/pipeline_stage.v
index 02f33359f..325698d61 100644
--- a/library/jesd204/jesd204_common/pipeline_stage.v
+++ b/library/jesd204/jesd204_common/pipeline_stage.v
@@ -53,18 +53,12 @@ module pipeline_stage #(
   output [WIDTH-1:0] out
 );
 
-generate if (REGISTERED == 0) begin
-
-  assign out = in;
-
-end else begin
-
-  (* shreg_extract = "no" *)  reg [REGISTERED*WIDTH-1:0] in_dly = {REGISTERED*WIDTH{1'b0}};
-
-  always @(posedge clk) in_dly <= {in_dly,in};
-
-  assign out = in_dly[REGISTERED*WIDTH-1 -: WIDTH];
-
-end endgenerate
+  generate if (REGISTERED == 0) begin
+    assign out = in;
+  end else begin
+    (* shreg_extract = "no" *)  reg [REGISTERED*WIDTH-1:0] in_dly = {REGISTERED*WIDTH{1'b0}};
+    always @(posedge clk) in_dly <= {in_dly,in};
+    assign out = in_dly[REGISTERED*WIDTH-1 -: WIDTH];
+  end endgenerate
 
 endmodule
diff --git a/library/jesd204/jesd204_common/sync_header_align.v b/library/jesd204/jesd204_common/sync_header_align.v
index 47b42991e..e2af2958c 100644
--- a/library/jesd204/jesd204_common/sync_header_align.v
+++ b/library/jesd204/jesd204_common/sync_header_align.v
@@ -44,8 +44,7 @@
 
 `timescale 1ns/100ps
 
-module sync_header_align #(
-) (
+module sync_header_align (
   input clk,
   input reset,
 
@@ -58,80 +57,78 @@ module sync_header_align #(
   output o_block_sync
 );
 
-assign {o_header,o_data} = i_data;
+  assign {o_header,o_data} = i_data;
 
-// TODO : Add alignment FSM
-localparam STATE_SH_HUNT = 3'b001;
-localparam STATE_SH_SLIP = 3'b010;
-localparam STATE_SH_LOCK = 3'b100;
+  // TODO : Add alignment FSM
+  localparam STATE_SH_HUNT = 3'b001;
+  localparam STATE_SH_SLIP = 3'b010;
+  localparam STATE_SH_LOCK = 3'b100;
 
-localparam BIT_SH_HUNT = 0;
-localparam BIT_SH_SLIP = 1;
-localparam BIT_SH_LOCK = 2;
+  localparam BIT_SH_HUNT = 0;
+  localparam BIT_SH_SLIP = 1;
+  localparam BIT_SH_LOCK = 2;
 
-localparam RX_THRESH_SH_ERR = 16;
-localparam LOG2_RX_THRESH_SH_ERR = $clog2(RX_THRESH_SH_ERR);
+  localparam RX_THRESH_SH_ERR = 16;
+  localparam LOG2_RX_THRESH_SH_ERR = $clog2(RX_THRESH_SH_ERR);
 
-reg [2:0] state = STATE_SH_HUNT;
-reg [2:0] next_state;
+  reg [2:0] state = STATE_SH_HUNT;
+  reg [2:0] next_state;
 
-reg [7:0] header_vcnt = 8'h0;
-reg [LOG2_RX_THRESH_SH_ERR:0] header_icnt = 'h0;
+  reg [7:0] header_vcnt = 8'h0;
+  reg [LOG2_RX_THRESH_SH_ERR:0] header_icnt = 'h0;
 
-wire valid_header;
-assign valid_header = ^o_header;
+  wire valid_header;
+  assign valid_header = ^o_header;
 
-always @(posedge clk) begin
-  if (reset | ~valid_header) begin
-    header_vcnt <= 'b0;
-  end else if (state[BIT_SH_HUNT] & ~header_vcnt[7]) begin
-    header_vcnt <= header_vcnt + 'b1;
+  always @(posedge clk) begin
+    if (reset | ~valid_header) begin
+      header_vcnt <= 'b0;
+    end else if (state[BIT_SH_HUNT] & ~header_vcnt[7]) begin
+      header_vcnt <= header_vcnt + 'b1;
+    end
   end
-end
 
-always @(posedge clk) begin
-  if (reset | valid_header) begin
-    header_icnt <= 'b0;
-  end else if (state[BIT_SH_LOCK] & ~header_icnt[LOG2_RX_THRESH_SH_ERR]) begin
-    header_icnt <= header_icnt + 'b1;
+  always @(posedge clk) begin
+    if (reset | valid_header) begin
+      header_icnt <= 'b0;
+    end else if (state[BIT_SH_LOCK] & ~header_icnt[LOG2_RX_THRESH_SH_ERR]) begin
+      header_icnt <= header_icnt + 'b1;
+    end
   end
-end
 
-always @(*) begin
-  next_state = state;
-  case (state)
-    STATE_SH_HUNT:
-      if (valid_header) begin
-        if (header_vcnt[7]) begin
-          next_state = STATE_SH_LOCK;
+  always @(*) begin
+    next_state = state;
+    case (state)
+      STATE_SH_HUNT:
+        if (valid_header) begin
+          if (header_vcnt[7]) begin
+            next_state = STATE_SH_LOCK;
+          end
+        end else begin
+          next_state = STATE_SH_SLIP;
         end
-      end else begin
-        next_state = STATE_SH_SLIP;
-      end
-    STATE_SH_SLIP:
-      if (i_slip_done) begin
-        next_state = STATE_SH_HUNT;
-      end
-    STATE_SH_LOCK:
-      if (~valid_header) begin
-        if (header_icnt[LOG2_RX_THRESH_SH_ERR]) begin
+      STATE_SH_SLIP:
+        if (i_slip_done) begin
           next_state = STATE_SH_HUNT;
         end
-      end
-  endcase
-end
-
-always @(posedge clk) begin
-  if (reset == 1'b1) begin
-    state <= STATE_SH_HUNT;
-  end else begin
-    state <= next_state;
+      STATE_SH_LOCK:
+        if (~valid_header) begin
+          if (header_icnt[LOG2_RX_THRESH_SH_ERR]) begin
+            next_state = STATE_SH_HUNT;
+          end
+        end
+    endcase
   end
-end
 
-assign o_block_sync = state[BIT_SH_LOCK];
-assign i_slip = state[BIT_SH_SLIP];
+  always @(posedge clk) begin
+    if (reset == 1'b1) begin
+      state <= STATE_SH_HUNT;
+    end else begin
+      state <= next_state;
+    end
+  end
+
+  assign o_block_sync = state[BIT_SH_LOCK];
+  assign i_slip = state[BIT_SH_SLIP];
 
 endmodule
-
-
diff --git a/library/jesd204/jesd204_rx/align_mux.v b/library/jesd204/jesd204_rx/align_mux.v
index 22ccef688..b328a7a71 100755
--- a/library/jesd204/jesd204_rx/align_mux.v
+++ b/library/jesd204/jesd204_rx/align_mux.v
@@ -55,25 +55,25 @@ module align_mux #(
   output [DATA_PATH_WIDTH-1:0] out_charisk
 );
 
-localparam DPW_LOG2 = DATA_PATH_WIDTH == 8 ? 3 : DATA_PATH_WIDTH == 4 ? 2 : 1;
+  localparam DPW_LOG2 = DATA_PATH_WIDTH == 8 ? 3 : DATA_PATH_WIDTH == 4 ? 2 : 1;
 
-wire [DPW_LOG2-1:0]                align_int;
-reg  [DATA_PATH_WIDTH*8-1:0]       in_data_d1;
-reg  [DATA_PATH_WIDTH-1:0]         in_charisk_d1;
-wire [(DATA_PATH_WIDTH*8*2)-1:0]   data;
-wire [(DATA_PATH_WIDTH*2)-1:0]     charisk;
+  wire [DPW_LOG2-1:0]                align_int;
+  reg  [DATA_PATH_WIDTH*8-1:0]       in_data_d1;
+  reg  [DATA_PATH_WIDTH-1:0]         in_charisk_d1;
+  wire [(DATA_PATH_WIDTH*8*2)-1:0]   data;
+  wire [(DATA_PATH_WIDTH*2)-1:0]     charisk;
 
-always @(posedge clk) begin
-  in_data_d1 <= in_data;
-  in_charisk_d1 <= in_charisk;
-end
+  always @(posedge clk) begin
+    in_data_d1 <= in_data;
+    in_charisk_d1 <= in_charisk;
+  end
 
-assign data = {in_data, in_data_d1};
-assign charisk = {in_charisk, in_charisk_d1};
+  assign data = {in_data, in_data_d1};
+  assign charisk = {in_charisk, in_charisk_d1};
 
-assign align_int = align[DPW_LOG2-1:0];
+  assign align_int = align[DPW_LOG2-1:0];
 
-assign out_data = data[align_int*8 +: (DATA_PATH_WIDTH*8)];
-assign out_charisk = charisk[align_int +: DATA_PATH_WIDTH];
+  assign out_data = data[align_int*8 +: (DATA_PATH_WIDTH*8)];
+  assign out_charisk = charisk[align_int +: DATA_PATH_WIDTH];
 
 endmodule
diff --git a/library/jesd204/jesd204_rx/elastic_buffer.v b/library/jesd204/jesd204_rx/elastic_buffer.v
index 208821e0b..25da3c7a5 100644
--- a/library/jesd204/jesd204_rx/elastic_buffer.v
+++ b/library/jesd204/jesd204_rx/elastic_buffer.v
@@ -64,59 +64,58 @@ module elastic_buffer #(
   input do_release_n
 );
 
-localparam ADDR_WIDTH = SIZE > 128 ? 7 :
-  SIZE > 64 ? 6 :
-  SIZE > 32 ? 5 :
-  SIZE > 16 ? 4 :
-  SIZE > 8 ? 3 :
-  SIZE > 4 ? 2 :
-  SIZE > 2 ? 1 : 0;
+  localparam ADDR_WIDTH = SIZE > 128 ? 7 :
+    SIZE > 64 ? 6 :
+    SIZE > 32 ? 5 :
+    SIZE > 16 ? 4 :
+    SIZE > 8 ? 3 :
+    SIZE > 4 ? 2 :
+    SIZE > 2 ? 1 : 0;
 
-localparam WIDTH = OWIDTH >= IWIDTH ? OWIDTH : IWIDTH;
+  localparam WIDTH = OWIDTH >= IWIDTH ? OWIDTH : IWIDTH;
 
-reg [ADDR_WIDTH:0] wr_addr = 'h00;
-reg [ADDR_WIDTH:0] rd_addr = 'h00;
-(* ram_style = "distributed" *) reg [WIDTH-1:0] mem[0:SIZE - 1];
+  reg [ADDR_WIDTH:0] wr_addr = 'h00;
+  reg [ADDR_WIDTH:0] rd_addr = 'h00;
+  (* ram_style = "distributed" *) reg [WIDTH-1:0] mem[0:SIZE - 1];
 
-wire mem_wr;
-wire [WIDTH-1:0] mem_wr_data;
+  wire mem_wr;
+  wire [WIDTH-1:0] mem_wr_data;
 
-generate if ((OWIDTH > IWIDTH) && ASYNC_CLK) begin
-  ad_pack #(
-    .I_W(IWIDTH/8),
-    .O_W(OWIDTH/8),
-    .UNIT_W(8)
-  ) i_ad_pack (
-    .clk(clk),
-    .reset(ready_n),
-    .idata(wr_data),
-    .ivalid(1'b1),
+  generate if ((OWIDTH > IWIDTH) && ASYNC_CLK) begin
+    ad_pack #(
+      .I_W(IWIDTH/8),
+      .O_W(OWIDTH/8),
+      .UNIT_W(8)
+    ) i_ad_pack (
+      .clk(clk),
+      .reset(ready_n),
+      .idata(wr_data),
+      .ivalid(1'b1),
 
-    .odata(mem_wr_data),
-    .ovalid(mem_wr)
-  );
-end else begin
-  assign mem_wr = 1'b1;
-  assign mem_wr_data = wr_data;
-end
-endgenerate
-
-always @(posedge clk) begin
-  if (ready_n == 1'b1) begin
-    wr_addr <= 'h00;
-  end else if (mem_wr) begin
-    mem[wr_addr] <= mem_wr_data;
-    wr_addr <= wr_addr + 1'b1;
-  end
-end
-
-always @(posedge device_clk) begin
-  if (do_release_n == 1'b1) begin
-    rd_addr <= 'h00;
+      .odata(mem_wr_data),
+      .ovalid(mem_wr));
   end else begin
-    rd_addr <= rd_addr + 1'b1;
-    rd_data <= mem[rd_addr];
+    assign mem_wr = 1'b1;
+    assign mem_wr_data = wr_data;
+  end
+  endgenerate
+
+  always @(posedge clk) begin
+    if (ready_n == 1'b1) begin
+      wr_addr <= 'h00;
+    end else if (mem_wr) begin
+      mem[wr_addr] <= mem_wr_data;
+      wr_addr <= wr_addr + 1'b1;
+    end
+  end
+
+  always @(posedge device_clk) begin
+    if (do_release_n == 1'b1) begin
+      rd_addr <= 'h00;
+    end else begin
+      rd_addr <= rd_addr + 1'b1;
+      rd_data <= mem[rd_addr];
+    end
   end
-end
 
 endmodule
diff --git a/library/jesd204/jesd204_rx/error_monitor.v b/library/jesd204/jesd204_rx/error_monitor.v
index 0ddd0133d..4fec2b948 100644
--- a/library/jesd204/jesd204_rx/error_monitor.v
+++ b/library/jesd204/jesd204_rx/error_monitor.v
@@ -56,35 +56,35 @@ module error_monitor #(
   output reg [CNT_WIDTH-1:0] status_err_cnt = 'h0
 );
 
-localparam EVENT_WIDTH_LOG = $clog2(EVENT_WIDTH);
+  localparam EVENT_WIDTH_LOG = $clog2(EVENT_WIDTH);
 
-reg  [EVENT_WIDTH-1:0] err;
+  reg  [EVENT_WIDTH-1:0] err;
 
-function [EVENT_WIDTH_LOG-1:0] num_set_bits;
-input [EVENT_WIDTH-1:0] x;
-integer j;
-begin
-  num_set_bits = 0;
-  for (j = 0; j < EVENT_WIDTH; j = j + 1) begin
-    num_set_bits = num_set_bits + x[j];
+  function [EVENT_WIDTH_LOG-1:0] num_set_bits;
+  input [EVENT_WIDTH-1:0] x;
+  integer j;
+  begin
+    num_set_bits = 0;
+    for (j = 0; j < EVENT_WIDTH; j = j + 1) begin
+      num_set_bits = num_set_bits + x[j];
+    end
   end
-end
-endfunction
+  endfunction
 
-always @(posedge clk) begin
-  if (active == 1'b1) begin
-    err <= (~error_event_mask) & error_event;
-  end else begin
-    err <= {EVENT_WIDTH{1'b0}};
+  always @(posedge clk) begin
+    if (active == 1'b1) begin
+      err <= (~error_event_mask) & error_event;
+    end else begin
+      err <= {EVENT_WIDTH{1'b0}};
+    end
   end
-end
 
-always @(posedge clk) begin
-  if (reset == 1'b1) begin
-    status_err_cnt <= 'h0;
-  end else if (~&status_err_cnt[CNT_WIDTH-1:EVENT_WIDTH_LOG]) begin
-    status_err_cnt <= status_err_cnt + num_set_bits(err);
+  always @(posedge clk) begin
+    if (reset == 1'b1) begin
+      status_err_cnt <= 'h0;
+    end else if (~&status_err_cnt[CNT_WIDTH-1:EVENT_WIDTH_LOG]) begin
+      status_err_cnt <= status_err_cnt + num_set_bits(err);
+    end
   end
-end
 
 endmodule
diff --git a/library/jesd204/jesd204_rx/jesd204_ilas_monitor.v b/library/jesd204/jesd204_rx/jesd204_ilas_monitor.v
index b35fe0f0e..5629bdc1f 100755
--- a/library/jesd204/jesd204_rx/jesd204_ilas_monitor.v
+++ b/library/jesd204/jesd204_rx/jesd204_ilas_monitor.v
@@ -61,102 +61,100 @@ module jesd204_ilas_monitor #(
   output data_ready_n
 );
 
+  localparam STATE_ILAS = 1'b1;
+  localparam STATE_DATA = 1'b0;
+  localparam ILAS_DATA_LENGTH = (DATA_PATH_WIDTH == 4) ? 4 : 2;
 
-localparam STATE_ILAS = 1'b1;
-localparam STATE_DATA = 1'b0;
-localparam ILAS_DATA_LENGTH = (DATA_PATH_WIDTH == 4) ? 4 : 2;
+  wire octets_per_mf_4_mod_8 = (DATA_PATH_WIDTH == 8) && ~cfg_octets_per_multiframe[2];
+  reg state = STATE_ILAS;
+  reg next_state;
+  reg prev_was_last = 1'b0;
+  wire ilas_config_start;
+  reg ilas_config_valid_i;
+  reg [1:0] ilas_config_addr_i;
+  reg [DATA_PATH_WIDTH*8-1:0] ilas_config_data_i;
 
-wire octets_per_mf_4_mod_8 = (DATA_PATH_WIDTH == 8) && ~cfg_octets_per_multiframe[2];
-reg state = STATE_ILAS;
-reg next_state;
-reg prev_was_last = 1'b0;
-wire ilas_config_start;
-reg ilas_config_valid_i;
-reg [1:0] ilas_config_addr_i;
-reg [DATA_PATH_WIDTH*8-1:0] ilas_config_data_i;
+  assign data_ready_n = next_state;
 
-assign data_ready_n = next_state;
-
-always @(*) begin
-  next_state = state;
-  if (reset == 1'b0 && prev_was_last == 1'b1) begin
-    if (charisk28[0] != 1'b1 || data[7:5] != 3'h0) begin
-      next_state = STATE_DATA;
+  always @(*) begin
+    next_state = state;
+    if (reset == 1'b0 && prev_was_last == 1'b1) begin
+      if (charisk28[0] != 1'b1 || data[7:5] != 3'h0) begin
+        next_state = STATE_DATA;
+      end
     end
   end
-end
 
-always @(posedge clk) begin
-  if (reset == 1'b1) begin
-    state <= STATE_ILAS;
-  end else begin
-    state <= next_state;
+  always @(posedge clk) begin
+    if (reset == 1'b1) begin
+      state <= STATE_ILAS;
+    end else begin
+      state <= next_state;
+    end
   end
-end
 
-always @(posedge clk) begin
-  if (reset == 1'b1 || (charisk28[DATA_PATH_WIDTH-1] == 1'b1 && data[(DATA_PATH_WIDTH*8)-1:(DATA_PATH_WIDTH*8)-3] == 3'h3)) begin
-    prev_was_last <= 1'b1;
-  end else begin
-    prev_was_last <= 1'b0;
+  always @(posedge clk) begin
+    if (reset == 1'b1 || (charisk28[DATA_PATH_WIDTH-1] == 1'b1 && data[(DATA_PATH_WIDTH*8)-1:(DATA_PATH_WIDTH*8)-3] == 3'h3)) begin
+      prev_was_last <= 1'b1;
+    end else begin
+      prev_was_last <= 1'b0;
+    end
   end
-end
 
-always @(posedge clk) begin
-  if (reset == 1'b1) begin
-    ilas_config_valid_i <= 1'b0;
-  end else if (state == STATE_ILAS) begin
-    if (ilas_config_start) begin
-      ilas_config_valid_i <= 1'b1;
-    end else if (ilas_config_addr_i == (ILAS_DATA_LENGTH-1)) begin
+  always @(posedge clk) begin
+    if (reset == 1'b1) begin
       ilas_config_valid_i <= 1'b0;
+    end else if (state == STATE_ILAS) begin
+      if (ilas_config_start) begin
+        ilas_config_valid_i <= 1'b1;
+      end else if (ilas_config_addr_i == (ILAS_DATA_LENGTH-1)) begin
+        ilas_config_valid_i <= 1'b0;
+      end
     end
   end
-end
 
-always @(posedge clk) begin
-  if (ilas_config_valid_i == 1'b0) begin
-    ilas_config_addr_i <= 1'b0;
-  end else if (ilas_config_valid_i == 1'b1) begin
-    ilas_config_addr_i <= ilas_config_addr_i + 1'b1;
+  always @(posedge clk) begin
+    if (ilas_config_valid_i == 1'b0) begin
+      ilas_config_addr_i <= 1'b0;
+    end else if (ilas_config_valid_i == 1'b1) begin
+      ilas_config_addr_i <= ilas_config_addr_i + 1'b1;
+    end
   end
-end
 
-always @(posedge clk) begin
-  ilas_config_data_i <= data;
-end
-
-
-generate
-if(DATA_PATH_WIDTH == 4) begin : gen_dp_4
-
-assign ilas_config_start = charisk28[1] && (data[15:13] == 3'h4);
-
-always @(*) begin
-  ilas_config_valid = ilas_config_valid_i;
-  ilas_config_addr = ilas_config_addr_i;
-  ilas_config_data = ilas_config_data_i;
-end
-
-end else begin : gen_dp_8
-
-assign ilas_config_start = octets_per_mf_4_mod_8 ? 
-  (charisk28[5] && (data[47:45] == 3'h4)) :
-  (charisk28[1] && (data[15:13] == 3'h4));
-
-always @(posedge clk) begin
-  if (reset == 1'b1) begin
-    ilas_config_valid <= 1'b0;
-  end else begin
-    ilas_config_valid <= ilas_config_valid_i;
+  always @(posedge clk) begin
+    ilas_config_data_i <= data;
   end
-end
 
-always @(posedge clk) begin
-  ilas_config_addr <= ilas_config_addr_i;
-  ilas_config_data <= octets_per_mf_4_mod_8 ? {data[31:0], ilas_config_data_i[63:32]} : ilas_config_data_i;
-end
-end
-endgenerate
+  generate
+  if(DATA_PATH_WIDTH == 4) begin : gen_dp_4
+
+  assign ilas_config_start = charisk28[1] && (data[15:13] == 3'h4);
+
+  always @(*) begin
+    ilas_config_valid = ilas_config_valid_i;
+    ilas_config_addr = ilas_config_addr_i;
+    ilas_config_data = ilas_config_data_i;
+  end
+
+  end else begin : gen_dp_8
+
+  assign ilas_config_start = octets_per_mf_4_mod_8 ?
+    (charisk28[5] && (data[47:45] == 3'h4)) :
+    (charisk28[1] && (data[15:13] == 3'h4));
+
+  always @(posedge clk) begin
+    if (reset == 1'b1) begin
+      ilas_config_valid <= 1'b0;
+    end else begin
+      ilas_config_valid <= ilas_config_valid_i;
+    end
+  end
+
+  always @(posedge clk) begin
+    ilas_config_addr <= ilas_config_addr_i;
+    ilas_config_data <= octets_per_mf_4_mod_8 ? {data[31:0], ilas_config_data_i[63:32]} : ilas_config_data_i;
+  end
+  end
+  endgenerate
 
 endmodule
diff --git a/library/jesd204/jesd204_rx/jesd204_lane_latency_monitor.v b/library/jesd204/jesd204_rx/jesd204_lane_latency_monitor.v
index d533db84e..93db35b76 100755
--- a/library/jesd204/jesd204_rx/jesd204_lane_latency_monitor.v
+++ b/library/jesd204/jesd204_rx/jesd204_lane_latency_monitor.v
@@ -58,39 +58,39 @@ module jesd204_lane_latency_monitor #(
   output [NUM_LANES-1:0] lane_latency_ready
 );
 
-localparam DPW_LOG2 = DATA_PATH_WIDTH == 8 ? 3 : DATA_PATH_WIDTH == 4 ? 2 : 1;
-localparam BEAT_CNT_WIDTH = 14-DPW_LOG2;
+  localparam DPW_LOG2 = DATA_PATH_WIDTH == 8 ? 3 : DATA_PATH_WIDTH == 4 ? 2 : 1;
+  localparam BEAT_CNT_WIDTH = 14-DPW_LOG2;
 
-reg [BEAT_CNT_WIDTH-1:0] beat_counter;
+  reg [BEAT_CNT_WIDTH-1:0] beat_counter;
 
-reg [BEAT_CNT_WIDTH-1:0] lane_latency_mem[0:NUM_LANES-1];
-reg [NUM_LANES-1:0] lane_captured = 'h00;
+  reg [BEAT_CNT_WIDTH-1:0] lane_latency_mem[0:NUM_LANES-1];
+  reg [NUM_LANES-1:0] lane_captured = 'h00;
 
-always @(posedge clk) begin
-  if (reset == 1'b1) begin
-    beat_counter <= 'h0;
-  end else if (beat_counter != {BEAT_CNT_WIDTH{1'b1}}) begin
-    beat_counter <= beat_counter + 1'b1;
-  end
-end
-
-generate
-genvar i;
-
-for (i = 0; i < NUM_LANES; i = i + 1) begin: gen_lane
   always @(posedge clk) begin
     if (reset == 1'b1) begin
-      lane_latency_mem[i] <= 'h00;
-      lane_captured[i] <= 1'b0;
-    end else if (lane_ready[i] == 1'b1 && lane_captured[i] == 1'b0) begin
-      lane_latency_mem[i] <= beat_counter;
-      lane_captured[i] <= 1'b1;
+      beat_counter <= 'h0;
+    end else if (beat_counter != {BEAT_CNT_WIDTH{1'b1}}) begin
+      beat_counter <= beat_counter + 1'b1;
     end
   end
 
-  assign lane_latency[i*14+13:i*14] = {lane_latency_mem[i],lane_frame_align[(i*3)+DPW_LOG2-1:i*3]};
-  assign lane_latency_ready[i] = lane_captured[i];
-end
-endgenerate
+  generate
+  genvar i;
+
+  for (i = 0; i < NUM_LANES; i = i + 1) begin: gen_lane
+    always @(posedge clk) begin
+      if (reset == 1'b1) begin
+        lane_latency_mem[i] <= 'h00;
+        lane_captured[i] <= 1'b0;
+      end else if (lane_ready[i] == 1'b1 && lane_captured[i] == 1'b0) begin
+        lane_latency_mem[i] <= beat_counter;
+        lane_captured[i] <= 1'b1;
+      end
+    end
+
+    assign lane_latency[i*14+13:i*14] = {lane_latency_mem[i],lane_frame_align[(i*3)+DPW_LOG2-1:i*3]};
+    assign lane_latency_ready[i] = lane_captured[i];
+  end
+  endgenerate
 
 endmodule
diff --git a/library/jesd204/jesd204_rx/jesd204_rx.v b/library/jesd204/jesd204_rx/jesd204_rx.v
index 6dc961eec..37990979c 100755
--- a/library/jesd204/jesd204_rx/jesd204_rx.v
+++ b/library/jesd204/jesd204_rx/jesd204_rx.v
@@ -129,497 +129,483 @@ module jesd204_rx #(
   output [31:0] status_synth_params2
 );
 
-/*
- * Can be used to enable additional pipeline stages to ease timing. Usually not
- * necessary.
- */
-localparam CHAR_INFO_REGISTERED = 0;
-localparam ALIGN_MUX_REGISTERED = 1;
-localparam SCRAMBLER_REGISTERED = 0;
+  /*
+   * Can be used to enable additional pipeline stages to ease timing. Usually not
+   * necessary.
+   */
+  localparam CHAR_INFO_REGISTERED = 0;
+  localparam ALIGN_MUX_REGISTERED = 1;
+  localparam SCRAMBLER_REGISTERED = 0;
 
-/*
- * Maximum number of octets per multiframe for ADI JESD204 DACs is 256 (Adjust
- * as necessary). Divide by data path width.
- */
-localparam MAX_OCTETS_PER_FRAME = 32;
-localparam MAX_OCTETS_PER_MULTIFRAME =
-  (MAX_OCTETS_PER_FRAME * 32) > 1024 ? 1024 : (MAX_OCTETS_PER_FRAME * 32);
-localparam MAX_BEATS_PER_MULTIFRAME = MAX_OCTETS_PER_MULTIFRAME / DATA_PATH_WIDTH;
-localparam ELASTIC_BUFFER_SIZE = MAX_BEATS_PER_MULTIFRAME;
-localparam DPW_LOG2 = DATA_PATH_WIDTH == 8 ? 3 : DATA_PATH_WIDTH == 4 ? 2 : 1;
+  /*
+   * Maximum number of octets per multiframe for ADI JESD204 DACs is 256 (Adjust
+   * as necessary). Divide by data path width.
+   */
+  localparam MAX_OCTETS_PER_FRAME = 32;
+  localparam MAX_OCTETS_PER_MULTIFRAME =
+    (MAX_OCTETS_PER_FRAME * 32) > 1024 ? 1024 : (MAX_OCTETS_PER_FRAME * 32);
+  localparam MAX_BEATS_PER_MULTIFRAME = MAX_OCTETS_PER_MULTIFRAME / DATA_PATH_WIDTH;
+  localparam ELASTIC_BUFFER_SIZE = MAX_BEATS_PER_MULTIFRAME;
+  localparam DPW_LOG2 = DATA_PATH_WIDTH == 8 ? 3 : DATA_PATH_WIDTH == 4 ? 2 : 1;
 
-localparam LMFC_COUNTER_WIDTH = MAX_BEATS_PER_MULTIFRAME > 256 ? 9 :
-  MAX_BEATS_PER_MULTIFRAME > 128 ? 8 :
-  MAX_BEATS_PER_MULTIFRAME > 64 ? 7 :
-  MAX_BEATS_PER_MULTIFRAME > 32 ? 6 :
-  MAX_BEATS_PER_MULTIFRAME > 16 ? 5 :
-  MAX_BEATS_PER_MULTIFRAME > 8 ? 4 :
-  MAX_BEATS_PER_MULTIFRAME > 4 ? 3 :
-  MAX_BEATS_PER_MULTIFRAME > 2 ? 2 : 1;
+  localparam LMFC_COUNTER_WIDTH = MAX_BEATS_PER_MULTIFRAME > 256 ? 9 :
+    MAX_BEATS_PER_MULTIFRAME > 128 ? 8 :
+    MAX_BEATS_PER_MULTIFRAME > 64 ? 7 :
+    MAX_BEATS_PER_MULTIFRAME > 32 ? 6 :
+    MAX_BEATS_PER_MULTIFRAME > 16 ? 5 :
+    MAX_BEATS_PER_MULTIFRAME > 8 ? 4 :
+    MAX_BEATS_PER_MULTIFRAME > 4 ? 3 :
+    MAX_BEATS_PER_MULTIFRAME > 2 ? 2 : 1;
 
-/* Helper for common expressions */
-localparam DW = 8*DATA_PATH_WIDTH*NUM_LANES;
-localparam ODW = 8*TPL_DATA_PATH_WIDTH*NUM_LANES;
-localparam CW = DATA_PATH_WIDTH*NUM_LANES;
-localparam HW = 2*NUM_LANES;
+  /* Helper for common expressions */
+  localparam DW = 8*DATA_PATH_WIDTH*NUM_LANES;
+  localparam ODW = 8*TPL_DATA_PATH_WIDTH*NUM_LANES;
+  localparam CW = DATA_PATH_WIDTH*NUM_LANES;
+  localparam HW = 2*NUM_LANES;
 
-wire [7:0] cfg_beats_per_multiframe = cfg_octets_per_multiframe >> DPW_LOG2;
-wire [7:0] device_cfg_beats_per_multiframe_s;
+  wire [7:0] cfg_beats_per_multiframe = cfg_octets_per_multiframe >> DPW_LOG2;
+  wire [7:0] device_cfg_beats_per_multiframe_s;
 
-wire [NUM_LANES-1:0] cgs_reset;
-wire [NUM_LANES-1:0] cgs_ready;
-wire [NUM_LANES-1:0] ifs_reset;
+  wire [NUM_LANES-1:0] cgs_reset;
+  wire [NUM_LANES-1:0] cgs_ready;
+  wire [NUM_LANES-1:0] ifs_reset;
 
-reg buffer_release_n = 1'b1;
-reg buffer_release_d1 = 1'b0;
-wire [NUM_LANES-1:0] buffer_ready_n;
-wire all_buffer_ready_n;
-wire dev_all_buffer_ready_n;
+  reg buffer_release_n = 1'b1;
+  reg buffer_release_d1 = 1'b0;
+  wire [NUM_LANES-1:0] buffer_ready_n;
+  wire all_buffer_ready_n;
+  wire dev_all_buffer_ready_n;
 
-reg eof_reset = 1'b1;
+  reg eof_reset = 1'b1;
 
-wire [DW-1:0] phy_data_r;
-wire [HW-1:0] phy_header_r;
-wire [CW-1:0] phy_charisk_r;
-wire [CW-1:0] phy_notintable_r;
-wire [CW-1:0] phy_disperr_r;
-wire [NUM_LANES-1:0] phy_block_sync_r;
+  wire [DW-1:0] phy_data_r;
+  wire [HW-1:0] phy_header_r;
+  wire [CW-1:0] phy_charisk_r;
+  wire [CW-1:0] phy_notintable_r;
+  wire [CW-1:0] phy_disperr_r;
+  wire [NUM_LANES-1:0] phy_block_sync_r;
 
-wire [ODW-1:0] rx_data_s;
+  wire [ODW-1:0] rx_data_s;
 
-wire rx_valid_s = buffer_release_d1;
+  wire rx_valid_s = buffer_release_d1;
 
-wire [7:0] lmfc_counter;
-wire latency_monitor_reset;
+  wire [7:0] lmfc_counter;
+  wire latency_monitor_reset;
 
-wire [3*NUM_LANES-1:0] frame_align;
-wire [NUM_LANES-1:0] ifs_ready;
+  wire [3*NUM_LANES-1:0] frame_align;
+  wire [NUM_LANES-1:0] ifs_ready;
 
-wire event_data_phase;
-wire err_statistics_reset;
+  wire event_data_phase;
+  wire err_statistics_reset;
 
-wire lmfc_edge_synced;
+  wire lmfc_edge_synced;
 
-reg [NUM_LANES-1:0] frame_align_err_thresh_met = {NUM_LANES{1'b0}};
-reg [NUM_LANES-1:0] event_frame_alignment_error_per_lane = {NUM_LANES{1'b0}};
+  reg [NUM_LANES-1:0] frame_align_err_thresh_met = {NUM_LANES{1'b0}};
+  reg [NUM_LANES-1:0] event_frame_alignment_error_per_lane = {NUM_LANES{1'b0}};
 
-reg buffer_release_opportunity = 1'b0;
+  reg buffer_release_opportunity = 1'b0;
 
-always @(posedge device_clk) begin
-  if (lmfc_counter == device_cfg_buffer_delay ||
-      device_cfg_buffer_early_release == 1'b1) begin
-    buffer_release_opportunity <= 1'b1;
-  end else begin
-    buffer_release_opportunity <= 1'b0;
-  end
-end
-
-assign all_buffer_ready_n = |(buffer_ready_n & ~cfg_lanes_disable);
-
-sync_bits #(
-  .NUM_OF_BITS (1),
-  .ASYNC_CLK(ASYNC_CLK)
-) i_all_buffer_ready_cdc (
-  .in_bits(all_buffer_ready_n),
-  .out_clk(device_clk),
-  .out_resetn(1'b1),
-  .out_bits(dev_all_buffer_ready_n)
-);
-
-always @(posedge device_clk) begin
-  if (device_reset == 1'b1) begin
-    buffer_release_n <= 1'b1;
-  end else begin
-    if (buffer_release_opportunity == 1'b1) begin
-      buffer_release_n <= dev_all_buffer_ready_n;
+  always @(posedge device_clk) begin
+    if (lmfc_counter == device_cfg_buffer_delay ||
+        device_cfg_buffer_early_release == 1'b1) begin
+      buffer_release_opportunity <= 1'b1;
+    end else begin
+      buffer_release_opportunity <= 1'b0;
     end
   end
-  buffer_release_d1 <= ~buffer_release_n;
-  eof_reset <= buffer_release_n;
-end
 
-pipeline_stage #(
-  .WIDTH(NUM_LANES + (3 * CW) + HW + DW),
-  .REGISTERED(NUM_INPUT_PIPELINE)
-) i_input_pipeline_stage (
-  .clk(clk),
-  .in({
-    phy_data,
-    phy_header,
-    phy_charisk,
-    phy_notintable,
-    phy_disperr,
-    phy_block_sync
-  }),
-  .out({
-    phy_data_r,
-    phy_header_r,
-    phy_charisk_r,
-    phy_notintable_r,
-    phy_disperr_r,
-    phy_block_sync_r
-  })
-);
+  assign all_buffer_ready_n = |(buffer_ready_n & ~cfg_lanes_disable);
 
-pipeline_stage #(
-  .WIDTH(ODW+2),
-  .REGISTERED(NUM_OUTPUT_PIPELINE)
-) i_output_pipeline_stage (
-  .clk(device_clk),
-  .in({
-    eof_reset,
-    rx_data_s,
-    rx_valid_s
-  }),
-  .out({
-    eof_reset_d,
-    rx_data,
-    rx_valid
-  })
-);
-
-// If input and output widths are symmetric keep the calculation for backwards
-// compatibility of the software.
-assign device_cfg_beats_per_multiframe_s = (TPL_DATA_PATH_WIDTH == DATA_PATH_WIDTH) ?
-                                   device_cfg_octets_per_multiframe >> DPW_LOG2 :
-                                   device_cfg_beats_per_multiframe;
-
-jesd204_lmfc #(
-  .LINK_MODE(LINK_MODE),
-  .DATA_PATH_WIDTH(TPL_DATA_PATH_WIDTH)
-) i_lmfc (
-  .clk(device_clk),
-  .reset(device_reset),
-
-  .cfg_octets_per_multiframe(device_cfg_octets_per_multiframe),
-  .cfg_beats_per_multiframe(device_cfg_beats_per_multiframe_s),
-  .cfg_lmfc_offset(device_cfg_lmfc_offset),
-  .cfg_sysref_oneshot(device_cfg_sysref_oneshot),
-  .cfg_sysref_disable(device_cfg_sysref_disable),
-
-  .sysref(sysref),
-  .lmfc_edge(lmfc_edge),
-  .lmfc_clk(lmfc_clk),
-  .lmfc_counter(lmfc_counter),
-  .lmc_edge(),
-  .lmc_quarter_edge(),
-  .eoemb(),
-
-  .sysref_edge(device_event_sysref_edge),
-  .sysref_alignment_error(device_event_sysref_alignment_error)
-);
-
-jesd204_frame_mark #(
-  .DATA_PATH_WIDTH            (TPL_DATA_PATH_WIDTH)
-) i_frame_mark (
-  .clk                        (device_clk),
-  .reset                      (eof_reset_d),
-  .cfg_beats_per_multiframe   (device_cfg_beats_per_multiframe_s),
-  .cfg_octets_per_multiframe  (device_cfg_octets_per_multiframe),
-  .cfg_octets_per_frame       (device_cfg_octets_per_frame),
-  .sof                        (rx_sof),
-  .eof                        (rx_eof),
-  .somf                       (rx_somf),
-  .eomf                       (rx_eomf)
-);
-
-generate
-genvar i;
-
-sync_event #(
-  .NUM_OF_EVENTS (1),
-  .ASYNC_CLK(ASYNC_CLK)
-) i_sync_lmfc (
-  .in_clk(device_clk),
-  .in_event(lmfc_edge),
-  .out_clk(clk),
-  .out_event(lmfc_edge_synced)
-);
-
-if (LINK_MODE[0] == 1) begin : mode_8b10b
-
-wire unexpected_lane_state_error;
-reg unexpected_lane_state_error_d = 1'b0;
-
-jesd204_rx_ctrl #(
-  .NUM_LANES(NUM_LANES),
-  .NUM_LINKS(NUM_LINKS),
-  .ENABLE_FRAME_ALIGN_ERR_RESET(ENABLE_FRAME_ALIGN_ERR_RESET)
-) i_rx_ctrl (
-  .clk(clk),
-  .reset(reset),
-
-  .cfg_lanes_disable(cfg_lanes_disable),
-  .cfg_links_disable(cfg_links_disable),
-
-  .phy_ready(1'b1),
-  .phy_en_char_align(phy_en_char_align),
-
-  .lmfc_edge(lmfc_edge_synced),
-  .frame_align_err_thresh_met(frame_align_err_thresh_met),
-  .sync(sync),
-
-  .latency_monitor_reset(latency_monitor_reset),
-
-  .cgs_reset(cgs_reset),
-  .cgs_ready(cgs_ready),
-
-  .ifs_reset(ifs_reset),
-
-  .status_state(status_ctrl_state),
-
-  .event_data_phase(event_data_phase)
-);
-
-assign err_statistics_reset = ctrl_err_statistics_reset ||
-                              event_data_phase;
-
-for (i = 0; i < NUM_LANES; i = i + 1) begin: gen_lane
-
-  localparam D_START = i * DATA_PATH_WIDTH*8;
-  localparam D_STOP = D_START + DATA_PATH_WIDTH*8-1;
-  localparam OD_START = i * TPL_DATA_PATH_WIDTH*8;
-  localparam OD_STOP = OD_START + TPL_DATA_PATH_WIDTH*8-1;
-  localparam C_START = i * DATA_PATH_WIDTH;
-  localparam C_STOP = C_START + DATA_PATH_WIDTH-1;
-
-  jesd204_rx_lane #(
-    .DATA_PATH_WIDTH(DATA_PATH_WIDTH),
-    .TPL_DATA_PATH_WIDTH(TPL_DATA_PATH_WIDTH),
-    .CHAR_INFO_REGISTERED(CHAR_INFO_REGISTERED),
-    .ALIGN_MUX_REGISTERED(ALIGN_MUX_REGISTERED),
-    .SCRAMBLER_REGISTERED(SCRAMBLER_REGISTERED),
-    .ELASTIC_BUFFER_SIZE(ELASTIC_BUFFER_SIZE),
-    .ENABLE_FRAME_ALIGN_CHECK(ENABLE_FRAME_ALIGN_CHECK),
-    .ENABLE_CHAR_REPLACE(ENABLE_CHAR_REPLACE),
+  sync_bits #(
+    .NUM_OF_BITS (1),
     .ASYNC_CLK(ASYNC_CLK)
-  ) i_lane (
-    .clk(clk),
-    .reset(reset),
+  ) i_all_buffer_ready_cdc (
+    .in_bits(all_buffer_ready_n),
+    .out_clk(device_clk),
+    .out_resetn(1'b1),
+    .out_bits(dev_all_buffer_ready_n));
 
-    .device_clk(device_clk),
-    .device_reset(device_reset),
-
-    .phy_data(phy_data_r[D_STOP:D_START]),
-    .phy_charisk(phy_charisk_r[C_STOP:C_START]),
-    .phy_notintable(phy_notintable_r[C_STOP:C_START]),
-    .phy_disperr(phy_disperr_r[C_STOP:C_START]),
-
-    .cgs_reset(cgs_reset[i]),
-    .cgs_ready(cgs_ready[i]),
-
-    .ifs_reset(ifs_reset[i]),
-
-    .rx_data(rx_data_s[OD_STOP:OD_START]),
-
-    .buffer_release_n(buffer_release_n),
-    .buffer_ready_n(buffer_ready_n[i]),
-
-    .cfg_octets_per_multiframe(cfg_octets_per_multiframe),
-    .cfg_octets_per_frame(cfg_octets_per_frame),
-    .cfg_disable_char_replacement(cfg_disable_char_replacement),
-    .cfg_disable_scrambler(cfg_disable_scrambler),
-
-    .err_statistics_reset(err_statistics_reset),
-    .ctrl_err_statistics_mask(ctrl_err_statistics_mask[2:0]),
-    .status_err_statistics_cnt(status_err_statistics_cnt[32*i+31:32*i]),
-
-    .ilas_config_valid(ilas_config_valid[i]),
-    .ilas_config_addr(ilas_config_addr[2*i+1:2*i]),
-    .ilas_config_data(ilas_config_data[D_STOP:D_START]),
-
-    .status_cgs_state(status_lane_cgs_state[2*i+1:2*i]),
-    .status_ifs_ready(ifs_ready[i]),
-    .status_frame_align(frame_align[3*i+2:3*i]),
-
-    .status_frame_align_err_cnt(status_lane_frame_align_err_cnt[8*i+7:8*i])
-  );
-
-  if(ENABLE_FRAME_ALIGN_CHECK) begin : gen_frame_align_err_thresh
-    always @(posedge clk) begin
-      if (reset) begin
-        frame_align_err_thresh_met[i] <= 1'b0;
-        event_frame_alignment_error_per_lane[i] <= 1'b0;
-      end else begin
-        if (status_lane_frame_align_err_cnt[8*i+7:8*i] >= cfg_frame_align_err_threshold) begin
-          frame_align_err_thresh_met[i] <= cgs_ready[i];
-          event_frame_alignment_error_per_lane[i] <= ~frame_align_err_thresh_met[i];
-        end else begin
-          frame_align_err_thresh_met[i] <= 1'b0;
-          event_frame_alignment_error_per_lane[i] <= 1'b0;
-        end
+  always @(posedge device_clk) begin
+    if (device_reset == 1'b1) begin
+      buffer_release_n <= 1'b1;
+    end else begin
+      if (buffer_release_opportunity == 1'b1) begin
+        buffer_release_n <= dev_all_buffer_ready_n;
       end
     end
-  end else begin : gen_no_frame_align_err_thresh
-    always @(*) begin
-      frame_align_err_thresh_met[i] <= 1'b0;
-      event_frame_alignment_error_per_lane[i] <= 1'b0;
+    buffer_release_d1 <= ~buffer_release_n;
+    eof_reset <= buffer_release_n;
+  end
+
+  pipeline_stage #(
+    .WIDTH(NUM_LANES + (3 * CW) + HW + DW),
+    .REGISTERED(NUM_INPUT_PIPELINE)
+  ) i_input_pipeline_stage (
+    .clk(clk),
+    .in({
+      phy_data,
+      phy_header,
+      phy_charisk,
+      phy_notintable,
+      phy_disperr,
+      phy_block_sync
+    }),
+    .out({
+      phy_data_r,
+      phy_header_r,
+      phy_charisk_r,
+      phy_notintable_r,
+      phy_disperr_r,
+      phy_block_sync_r
+    }));
+
+  pipeline_stage #(
+    .WIDTH(ODW+2),
+    .REGISTERED(NUM_OUTPUT_PIPELINE)
+  ) i_output_pipeline_stage (
+    .clk(device_clk),
+    .in({
+      eof_reset,
+      rx_data_s,
+      rx_valid_s
+    }),
+    .out({
+      eof_reset_d,
+      rx_data,
+      rx_valid
+    }));
+
+  // If input and output widths are symmetric keep the calculation for backwards
+  // compatibility of the software.
+  assign device_cfg_beats_per_multiframe_s = (TPL_DATA_PATH_WIDTH == DATA_PATH_WIDTH) ?
+                                     device_cfg_octets_per_multiframe >> DPW_LOG2 :
+                                     device_cfg_beats_per_multiframe;
+
+  jesd204_lmfc #(
+    .LINK_MODE (LINK_MODE),
+    .DATA_PATH_WIDTH (TPL_DATA_PATH_WIDTH)
+  ) i_lmfc (
+    .clk (device_clk),
+    .reset (device_reset),
+
+    .cfg_octets_per_multiframe (device_cfg_octets_per_multiframe),
+    .cfg_beats_per_multiframe (device_cfg_beats_per_multiframe_s),
+    .cfg_lmfc_offset (device_cfg_lmfc_offset),
+    .cfg_sysref_oneshot (device_cfg_sysref_oneshot),
+    .cfg_sysref_disable (device_cfg_sysref_disable),
+
+    .sysref (sysref),
+    .lmfc_edge (lmfc_edge),
+    .lmfc_clk (lmfc_clk),
+    .lmfc_counter (lmfc_counter),
+    .lmc_edge (),
+    .lmc_quarter_edge (),
+    .eoemb (),
+
+    .sysref_edge (device_event_sysref_edge),
+    .sysref_alignment_error (device_event_sysref_alignment_error));
+
+  jesd204_frame_mark #(
+    .DATA_PATH_WIDTH (TPL_DATA_PATH_WIDTH)
+  ) i_frame_mark (
+    .clk (device_clk),
+    .reset (eof_reset_d),
+    .cfg_beats_per_multiframe (device_cfg_beats_per_multiframe_s),
+    .cfg_octets_per_multiframe (device_cfg_octets_per_multiframe),
+    .cfg_octets_per_frame (device_cfg_octets_per_frame),
+    .sof (rx_sof),
+    .eof (rx_eof),
+    .somf (rx_somf),
+    .eomf (rx_eomf));
+
+  generate
+  genvar i;
+
+  sync_event #(
+    .NUM_OF_EVENTS (1),
+    .ASYNC_CLK(ASYNC_CLK)
+  ) i_sync_lmfc (
+    .in_clk(device_clk),
+    .in_event(lmfc_edge),
+    .out_clk(clk),
+    .out_event(lmfc_edge_synced));
+
+  if (LINK_MODE[0] == 1) begin : mode_8b10b
+
+  wire unexpected_lane_state_error;
+  reg unexpected_lane_state_error_d = 1'b0;
+
+  jesd204_rx_ctrl #(
+    .NUM_LANES (NUM_LANES),
+    .NUM_LINKS (NUM_LINKS),
+    .ENABLE_FRAME_ALIGN_ERR_RESET (ENABLE_FRAME_ALIGN_ERR_RESET)
+  ) i_rx_ctrl (
+    .clk (clk),
+    .reset (reset),
+
+    .cfg_lanes_disable (cfg_lanes_disable),
+    .cfg_links_disable (cfg_links_disable),
+
+    .phy_ready (1'b1),
+    .phy_en_char_align (phy_en_char_align),
+
+    .lmfc_edge (lmfc_edge_synced),
+    .frame_align_err_thresh_met (frame_align_err_thresh_met),
+    .sync (sync),
+
+    .latency_monitor_reset (latency_monitor_reset),
+
+    .cgs_reset (cgs_reset),
+    .cgs_ready (cgs_ready),
+
+    .ifs_reset (ifs_reset),
+
+    .status_state (status_ctrl_state),
+
+    .event_data_phase (event_data_phase));
+
+  assign err_statistics_reset = ctrl_err_statistics_reset ||
+                                event_data_phase;
+
+  for (i = 0; i < NUM_LANES; i = i + 1) begin: gen_lane
+
+    localparam D_START = i * DATA_PATH_WIDTH*8;
+    localparam D_STOP = D_START + DATA_PATH_WIDTH*8-1;
+    localparam OD_START = i * TPL_DATA_PATH_WIDTH*8;
+    localparam OD_STOP = OD_START + TPL_DATA_PATH_WIDTH*8-1;
+    localparam C_START = i * DATA_PATH_WIDTH;
+    localparam C_STOP = C_START + DATA_PATH_WIDTH-1;
+
+    jesd204_rx_lane #(
+      .DATA_PATH_WIDTH(DATA_PATH_WIDTH),
+      .TPL_DATA_PATH_WIDTH(TPL_DATA_PATH_WIDTH),
+      .CHAR_INFO_REGISTERED(CHAR_INFO_REGISTERED),
+      .ALIGN_MUX_REGISTERED(ALIGN_MUX_REGISTERED),
+      .SCRAMBLER_REGISTERED(SCRAMBLER_REGISTERED),
+      .ELASTIC_BUFFER_SIZE(ELASTIC_BUFFER_SIZE),
+      .ENABLE_FRAME_ALIGN_CHECK(ENABLE_FRAME_ALIGN_CHECK),
+      .ENABLE_CHAR_REPLACE(ENABLE_CHAR_REPLACE),
+      .ASYNC_CLK(ASYNC_CLK)
+    ) i_lane (
+      .clk(clk),
+      .reset(reset),
+
+      .device_clk(device_clk),
+      .device_reset(device_reset),
+
+      .phy_data(phy_data_r[D_STOP:D_START]),
+      .phy_charisk(phy_charisk_r[C_STOP:C_START]),
+      .phy_notintable(phy_notintable_r[C_STOP:C_START]),
+      .phy_disperr(phy_disperr_r[C_STOP:C_START]),
+
+      .cgs_reset(cgs_reset[i]),
+      .cgs_ready(cgs_ready[i]),
+
+      .ifs_reset(ifs_reset[i]),
+
+      .rx_data(rx_data_s[OD_STOP:OD_START]),
+
+      .buffer_release_n(buffer_release_n),
+      .buffer_ready_n(buffer_ready_n[i]),
+
+      .cfg_octets_per_multiframe(cfg_octets_per_multiframe),
+      .cfg_octets_per_frame(cfg_octets_per_frame),
+      .cfg_disable_char_replacement(cfg_disable_char_replacement),
+      .cfg_disable_scrambler(cfg_disable_scrambler),
+
+      .err_statistics_reset(err_statistics_reset),
+      .ctrl_err_statistics_mask(ctrl_err_statistics_mask[2:0]),
+      .status_err_statistics_cnt(status_err_statistics_cnt[32*i+31:32*i]),
+
+      .ilas_config_valid(ilas_config_valid[i]),
+      .ilas_config_addr(ilas_config_addr[2*i+1:2*i]),
+      .ilas_config_data(ilas_config_data[D_STOP:D_START]),
+
+      .status_cgs_state(status_lane_cgs_state[2*i+1:2*i]),
+      .status_ifs_ready(ifs_ready[i]),
+      .status_frame_align(frame_align[3*i+2:3*i]),
+
+      .status_frame_align_err_cnt(status_lane_frame_align_err_cnt[8*i+7:8*i]));
+
+    if(ENABLE_FRAME_ALIGN_CHECK) begin : gen_frame_align_err_thresh
+      always @(posedge clk) begin
+        if (reset) begin
+          frame_align_err_thresh_met[i] <= 1'b0;
+          event_frame_alignment_error_per_lane[i] <= 1'b0;
+        end else begin
+          if (status_lane_frame_align_err_cnt[8*i+7:8*i] >= cfg_frame_align_err_threshold) begin
+            frame_align_err_thresh_met[i] <= cgs_ready[i];
+            event_frame_alignment_error_per_lane[i] <= ~frame_align_err_thresh_met[i];
+          end else begin
+            frame_align_err_thresh_met[i] <= 1'b0;
+            event_frame_alignment_error_per_lane[i] <= 1'b0;
+          end
+        end
+      end
+    end else begin : gen_no_frame_align_err_thresh
+      always @(*) begin
+        frame_align_err_thresh_met[i] <= 1'b0;
+        event_frame_alignment_error_per_lane[i] <= 1'b0;
+      end
     end
   end
-end
 
-assign event_frame_alignment_error = |event_frame_alignment_error_per_lane;
+  assign event_frame_alignment_error = |event_frame_alignment_error_per_lane;
 
-/* If one of the enabled lanes falls out of DATA phase while the link is in DATA phase
- * report an error event */
-assign unexpected_lane_state_error = |(~(cgs_ready|cfg_lanes_disable)) & &status_ctrl_state;
-always @(posedge clk) begin
-  unexpected_lane_state_error_d <= unexpected_lane_state_error;
-end
-assign event_unexpected_lane_state_error = unexpected_lane_state_error & ~unexpected_lane_state_error_d;
+  /* If one of the enabled lanes falls out of DATA phase while the link is in DATA phase
+   * report an error event */
+  assign unexpected_lane_state_error = |(~(cgs_ready|cfg_lanes_disable)) & &status_ctrl_state;
+  always @(posedge clk) begin
+    unexpected_lane_state_error_d <= unexpected_lane_state_error;
+  end
+  assign event_unexpected_lane_state_error = unexpected_lane_state_error & ~unexpected_lane_state_error_d;
 
+  /* Delay matching based on the number of pipeline stages */
+  reg [NUM_LANES-1:0] ifs_ready_d1 = 1'b0;
+  reg [NUM_LANES-1:0] ifs_ready_d2 = 1'b0;
+  reg [NUM_LANES-1:0] ifs_ready_mux;
 
-/* Delay matching based on the number of pipeline stages */
-reg [NUM_LANES-1:0] ifs_ready_d1 = 1'b0;
-reg [NUM_LANES-1:0] ifs_ready_d2 = 1'b0;
-reg [NUM_LANES-1:0] ifs_ready_mux;
+  always @(posedge clk) begin
+    ifs_ready_d1 <= ifs_ready;
+    ifs_ready_d2 <= ifs_ready_d1;
+  end
 
-always @(posedge clk) begin
-  ifs_ready_d1 <= ifs_ready;
-  ifs_ready_d2 <= ifs_ready_d1;
-end
+  always @(*) begin
+    case (SCRAMBLER_REGISTERED + ALIGN_MUX_REGISTERED)
+    1: ifs_ready_mux = ifs_ready_d1;
+    2: ifs_ready_mux = ifs_ready_d2;
+    default: ifs_ready_mux = ifs_ready;
+    endcase
+  end
 
-always @(*) begin
-  case (SCRAMBLER_REGISTERED + ALIGN_MUX_REGISTERED)
-  1: ifs_ready_mux = ifs_ready_d1;
-  2: ifs_ready_mux = ifs_ready_d2;
-  default: ifs_ready_mux = ifs_ready;
-  endcase
-end
+  jesd204_lane_latency_monitor #(
+    .NUM_LANES(NUM_LANES),
+    .DATA_PATH_WIDTH(DATA_PATH_WIDTH)
+  ) i_lane_latency_monitor (
+    .clk(clk),
+    .reset(latency_monitor_reset),
 
-jesd204_lane_latency_monitor #(
-  .NUM_LANES(NUM_LANES),
-  .DATA_PATH_WIDTH(DATA_PATH_WIDTH)
-) i_lane_latency_monitor (
-  .clk(clk),
-  .reset(latency_monitor_reset),
+    .lane_ready(ifs_ready_mux),
+    .lane_frame_align(frame_align),
+    .lane_latency_ready(status_lane_ifs_ready),
+    .lane_latency(status_lane_latency));
 
-  .lane_ready(ifs_ready_mux),
-  .lane_frame_align(frame_align),
-  .lane_latency_ready(status_lane_ifs_ready),
-  .lane_latency(status_lane_latency)
-);
+  assign status_lane_emb_state = 'b0;
 
-assign status_lane_emb_state = 'b0;
+  end
 
-end
+  if (LINK_MODE[1] == 1) begin : mode_64b66b
 
-if (LINK_MODE[1] == 1) begin : mode_64b66b
+  wire [NUM_LANES-1:0] emb_lock;
+  wire link_buffer_release_n;
 
-wire [NUM_LANES-1:0] emb_lock;
-wire link_buffer_release_n;
-
-sync_bits #(
-  .NUM_OF_BITS (1),
-  .ASYNC_CLK(ASYNC_CLK)
-) i_buffer_release_cdc (
-  .in_bits(buffer_release_n),
-  .out_clk(clk),
-  .out_resetn(1'b1),
-  .out_bits(link_buffer_release_n)
-);
-
-jesd204_rx_ctrl_64b  #(
-  .NUM_LANES(NUM_LANES)
-) i_jesd204_rx_ctrl_64b (
-  .clk(clk),
-  .reset(reset),
-
-  .cfg_lanes_disable(cfg_lanes_disable),
-
-  .phy_block_sync(phy_block_sync_r),
-  .emb_lock(emb_lock),
-
-  .all_emb_lock(all_emb_lock),
-  .buffer_release_n(link_buffer_release_n),
-
-  .status_state(status_ctrl_state),
-  .event_unexpected_lane_state_error(event_unexpected_lane_state_error)
-);
-
-for (i = 0; i < NUM_LANES; i = i + 1) begin: gen_lane
-
-  localparam D_START = i * DATA_PATH_WIDTH*8;
-  localparam D_STOP = D_START + DATA_PATH_WIDTH*8-1;
-  localparam TPL_D_START = i * TPL_DATA_PATH_WIDTH*8;
-  localparam TPL_D_STOP = TPL_D_START + TPL_DATA_PATH_WIDTH*8-1;
-  localparam H_START = i * 2;
-  localparam H_STOP = H_START + 2-1;
-
-  wire [7:0] status_lane_skew;
-
-  jesd204_rx_lane_64b #(
-    .ELASTIC_BUFFER_SIZE(ELASTIC_BUFFER_SIZE),
-    .TPL_DATA_PATH_WIDTH(TPL_DATA_PATH_WIDTH),
+  sync_bits #(
+    .NUM_OF_BITS (1),
     .ASYNC_CLK(ASYNC_CLK)
-  ) i_lane (
+  ) i_buffer_release_cdc (
+    .in_bits(buffer_release_n),
+    .out_clk(clk),
+    .out_resetn(1'b1),
+    .out_bits(link_buffer_release_n));
+
+  jesd204_rx_ctrl_64b  #(
+    .NUM_LANES(NUM_LANES)
+  ) i_jesd204_rx_ctrl_64b (
     .clk(clk),
     .reset(reset),
 
-    .device_clk(device_clk),
-    .device_reset(device_reset),
+    .cfg_lanes_disable(cfg_lanes_disable),
 
-    .phy_data(phy_data_r[D_STOP:D_START]),
-    .phy_header(phy_header_r[H_STOP:H_START]),
-    .phy_block_sync(phy_block_sync_r[i]),
+    .phy_block_sync(phy_block_sync_r),
+    .emb_lock(emb_lock),
 
-    .cfg_disable_scrambler(cfg_disable_scrambler),
-    .cfg_header_mode(2'b0),
-    .cfg_rx_thresh_emb_err(5'd8),
-    .cfg_beats_per_multiframe(cfg_beats_per_multiframe),
+    .all_emb_lock(all_emb_lock),
+    .buffer_release_n(link_buffer_release_n),
 
-    .rx_data(rx_data_s[TPL_D_STOP:TPL_D_START]),
+    .status_state(status_ctrl_state),
+    .event_unexpected_lane_state_error(event_unexpected_lane_state_error));
 
-    .buffer_release_n(buffer_release_n),
-    .buffer_ready_n(buffer_ready_n[i]),
-    .all_buffer_ready_n(all_buffer_ready_n),
+  for (i = 0; i < NUM_LANES; i = i + 1) begin: gen_lane
 
-    .lmfc_edge(lmfc_edge_synced),
-    .emb_lock(emb_lock[i]),
+    localparam D_START = i * DATA_PATH_WIDTH*8;
+    localparam D_STOP = D_START + DATA_PATH_WIDTH*8-1;
+    localparam TPL_D_START = i * TPL_DATA_PATH_WIDTH*8;
+    localparam TPL_D_STOP = TPL_D_START + TPL_DATA_PATH_WIDTH*8-1;
+    localparam H_START = i * 2;
+    localparam H_STOP = H_START + 2-1;
 
-    .ctrl_err_statistics_reset(ctrl_err_statistics_reset),
-    .ctrl_err_statistics_mask(ctrl_err_statistics_mask[6:3]),
-    .status_err_statistics_cnt(status_err_statistics_cnt[32*i+31:32*i]),
+    wire [7:0] status_lane_skew;
 
-    .status_lane_emb_state(status_lane_emb_state[3*i+2:3*i]),
-    .status_lane_skew(status_lane_skew)
-  );
+    jesd204_rx_lane_64b #(
+      .ELASTIC_BUFFER_SIZE(ELASTIC_BUFFER_SIZE),
+      .TPL_DATA_PATH_WIDTH(TPL_DATA_PATH_WIDTH),
+      .ASYNC_CLK(ASYNC_CLK)
+    ) i_lane (
+      .clk(clk),
+      .reset(reset),
 
-assign status_lane_latency[14*(i+1)-1:14*i] = {3'b0,status_lane_skew,3'b0};
+      .device_clk(device_clk),
+      .device_reset(device_reset),
 
-end
+      .phy_data(phy_data_r[D_STOP:D_START]),
+      .phy_header(phy_header_r[H_STOP:H_START]),
+      .phy_block_sync(phy_block_sync_r[i]),
 
-// Assign unused outputs
-assign sync = 'b0;
-assign phy_en_char_align = 1'b0;
+      .cfg_disable_scrambler(cfg_disable_scrambler),
+      .cfg_header_mode(2'b0),
+      .cfg_rx_thresh_emb_err(5'd8),
+      .cfg_beats_per_multiframe(cfg_beats_per_multiframe),
 
-assign ilas_config_valid ='b0;
-assign ilas_config_addr = 'b0;
-assign ilas_config_data = 'b0;
-assign status_lane_cgs_state = 'b0;
-assign status_lane_ifs_ready = {NUM_LANES{1'b1}};
-assign event_frame_alignment_error = 1'b0;
+      .rx_data(rx_data_s[TPL_D_STOP:TPL_D_START]),
 
-end
+      .buffer_release_n(buffer_release_n),
+      .buffer_ready_n(buffer_ready_n[i]),
+      .all_buffer_ready_n(all_buffer_ready_n),
 
+      .lmfc_edge(lmfc_edge_synced),
+      .emb_lock(emb_lock[i]),
 
-endgenerate
+      .ctrl_err_statistics_reset(ctrl_err_statistics_reset),
+      .ctrl_err_statistics_mask(ctrl_err_statistics_mask[6:3]),
+      .status_err_statistics_cnt(status_err_statistics_cnt[32*i+31:32*i]),
 
-// Core static parameters
-assign status_synth_params0 = {NUM_LANES};
-assign status_synth_params1 = {
-                 /*31:16 */  16'b0,
-                 /*15: 8 */  1'b0,TPL_DATA_PATH_WIDTH[6:0],
-                 /* 7: 0 */  4'b0,DPW_LOG2[3:0]};
-assign status_synth_params2 = {
-                 /*31:19 */  13'b0,
-                 /*   18 */  ENABLE_CHAR_REPLACE[0],
-                 /*   17 */  ENABLE_FRAME_ALIGN_ERR_RESET[0],
-                 /*   16 */  ENABLE_FRAME_ALIGN_CHECK[0],
-                 /*15:13 */  3'b0,
-                 /*   12 */  ASYNC_CLK[0],
-                 /*11:10 */  2'b0,
-                 /* 9: 8 */  LINK_MODE[1:0],
-                 /* 7: 0 */  NUM_LINKS[7:0]};
+      .status_lane_emb_state(status_lane_emb_state[3*i+2:3*i]),
+      .status_lane_skew(status_lane_skew));
+
+  assign status_lane_latency[14*(i+1)-1:14*i] = {3'b0,status_lane_skew,3'b0};
+
+  end
+
+  // Assign unused outputs
+  assign sync = 'b0;
+  assign phy_en_char_align = 1'b0;
+
+  assign ilas_config_valid ='b0;
+  assign ilas_config_addr = 'b0;
+  assign ilas_config_data = 'b0;
+  assign status_lane_cgs_state = 'b0;
+  assign status_lane_ifs_ready = {NUM_LANES{1'b1}};
+  assign event_frame_alignment_error = 1'b0;
+
+  end
+
+  endgenerate
+
+  // Core static parameters
+  assign status_synth_params0 = {NUM_LANES};
+  assign status_synth_params1 = {
+                   /*31:16 */  16'b0,
+                   /*15: 8 */  1'b0,TPL_DATA_PATH_WIDTH[6:0],
+                   /* 7: 0 */  4'b0,DPW_LOG2[3:0]};
+  assign status_synth_params2 = {
+                   /*31:19 */  13'b0,
+                   /*   18 */  ENABLE_CHAR_REPLACE[0],
+                   /*   17 */  ENABLE_FRAME_ALIGN_ERR_RESET[0],
+                   /*   16 */  ENABLE_FRAME_ALIGN_CHECK[0],
+                   /*15:13 */  3'b0,
+                   /*   12 */  ASYNC_CLK[0],
+                   /*11:10 */  2'b0,
+                   /* 9: 8 */  LINK_MODE[1:0],
+                   /* 7: 0 */  NUM_LINKS[7:0]};
 
 endmodule
diff --git a/library/jesd204/jesd204_rx/jesd204_rx_cgs.v b/library/jesd204/jesd204_rx/jesd204_rx_cgs.v
index 2eeb036bc..9753d5590 100644
--- a/library/jesd204/jesd204_rx/jesd204_rx_cgs.v
+++ b/library/jesd204/jesd204_rx/jesd204_rx_cgs.v
@@ -58,68 +58,68 @@ module jesd204_rx_cgs #(
   output [1:0] status_state
 );
 
-localparam CGS_STATE_INIT = 2'b00;
-localparam CGS_STATE_CHECK = 2'b01;
-localparam CGS_STATE_DATA = 2'b10;
+  localparam CGS_STATE_INIT = 2'b00;
+  localparam CGS_STATE_CHECK = 2'b01;
+  localparam CGS_STATE_DATA = 2'b10;
 
-reg [1:0] state = CGS_STATE_INIT;
-reg rdy = 1'b0;
-reg [1:0] beat_error_count = 'h00;
+  reg [1:0] state = CGS_STATE_INIT;
+  reg rdy = 1'b0;
+  reg [1:0] beat_error_count = 'h00;
 
-wire beat_is_cgs = &char_is_cgs;
-wire beat_has_error = |char_is_error;
-wire beat_is_all_error = &char_is_error;
+  wire beat_is_cgs = &char_is_cgs;
+  wire beat_has_error = |char_is_error;
+  wire beat_is_all_error = &char_is_error;
 
-assign ready = rdy;
-assign status_state = state;
+  assign ready = rdy;
+  assign status_state = state;
 
-always @(posedge clk) begin
-  if (state == CGS_STATE_INIT) begin
-    beat_error_count <= 'h00;
-  end else begin
-    if (beat_has_error == 1'b1) begin
-      beat_error_count <= beat_error_count + 1'b1;
-    end else begin
+  always @(posedge clk) begin
+    if (state == CGS_STATE_INIT) begin
       beat_error_count <= 'h00;
+    end else begin
+      if (beat_has_error == 1'b1) begin
+        beat_error_count <= beat_error_count + 1'b1;
+      end else begin
+        beat_error_count <= 'h00;
+      end
     end
   end
-end
 
-always @(posedge clk) begin
-  if (reset == 1'b1) begin
-    state <= CGS_STATE_INIT;
-  end else begin
-    case (state)
-    CGS_STATE_INIT: begin
-      if (beat_is_cgs == 1'b1) begin
-        state <= CGS_STATE_CHECK;
-      end
-    end
-    CGS_STATE_CHECK: begin
-      if (beat_has_error == 1'b1) begin
-        if (beat_error_count == 'h3 ||
-            beat_is_all_error == 1'b1) begin
-          state <= CGS_STATE_INIT;
+  always @(posedge clk) begin
+    if (reset == 1'b1) begin
+      state <= CGS_STATE_INIT;
+    end else begin
+      case (state)
+      CGS_STATE_INIT: begin
+        if (beat_is_cgs == 1'b1) begin
+          state <= CGS_STATE_CHECK;
         end
-      end else begin
-        state <= CGS_STATE_DATA;
       end
-    end
-    CGS_STATE_DATA: begin
-      if (beat_has_error == 1'b1) begin
-        state <= CGS_STATE_CHECK;
+      CGS_STATE_CHECK: begin
+        if (beat_has_error == 1'b1) begin
+          if (beat_error_count == 'h3 ||
+              beat_is_all_error == 1'b1) begin
+            state <= CGS_STATE_INIT;
+          end
+        end else begin
+          state <= CGS_STATE_DATA;
+        end
       end
+      CGS_STATE_DATA: begin
+        if (beat_has_error == 1'b1) begin
+          state <= CGS_STATE_CHECK;
+        end
+      end
+      endcase
     end
+  end
+
+  always @(posedge clk) begin
+    case (state)
+    CGS_STATE_INIT: rdy <= 1'b0;
+    CGS_STATE_DATA: rdy <= 1'b1;
+    default: rdy <= rdy;
     endcase
   end
-end
-
-always @(posedge clk) begin
-  case (state)
-  CGS_STATE_INIT: rdy <= 1'b0;
-  CGS_STATE_DATA: rdy <= 1'b1;
-  default: rdy <= rdy;
-  endcase
-end
 
 endmodule
diff --git a/library/jesd204/jesd204_rx/jesd204_rx_ctrl.v b/library/jesd204/jesd204_rx/jesd204_rx_ctrl.v
index b8326f635..e04085fd1 100755
--- a/library/jesd204/jesd204_rx/jesd204_rx_ctrl.v
+++ b/library/jesd204/jesd204_rx/jesd204_rx_ctrl.v
@@ -58,7 +58,6 @@ module jesd204_rx_ctrl #(
   input phy_ready,
   output phy_en_char_align,
 
-
   output [NUM_LANES-1:0] cgs_reset,
   input [NUM_LANES-1:0] cgs_ready,
 
@@ -74,114 +73,114 @@ module jesd204_rx_ctrl #(
   output event_data_phase
 );
 
-localparam STATE_RESET = 0;
-localparam STATE_WAIT_FOR_PHY = 1;
-localparam STATE_CGS = 2;
-localparam STATE_SYNCHRONIZED = 3;
+  localparam STATE_RESET = 0;
+  localparam STATE_WAIT_FOR_PHY = 1;
+  localparam STATE_CGS = 2;
+  localparam STATE_SYNCHRONIZED = 3;
 
-reg [2:0] state = STATE_RESET;
-reg [2:0] next_state = STATE_RESET;
+  reg [2:0] state = STATE_RESET;
+  reg [2:0] next_state = STATE_RESET;
 
-reg [NUM_LANES-1:0] cgs_rst = {NUM_LANES{1'b1}};
-reg [NUM_LANES-1:0] ifs_rst = {NUM_LANES{1'b1}};
-reg [NUM_LINKS-1:0] sync_n = {NUM_LINKS{1'b1}};
-reg en_align = 1'b0;
-reg state_good = 1'b0;
+  reg [NUM_LANES-1:0] cgs_rst = {NUM_LANES{1'b1}};
+  reg [NUM_LANES-1:0] ifs_rst = {NUM_LANES{1'b1}};
+  reg [NUM_LINKS-1:0] sync_n = {NUM_LINKS{1'b1}};
+  reg en_align = 1'b0;
+  reg state_good = 1'b0;
 
-reg [7:0] good_counter = 'h00;
+  reg [7:0] good_counter = 'h00;
 
-wire [7:0] good_cnt_limit_s;
-wire       good_cnt_limit_reached_s;
-wire       goto_next_state_s;
+  wire [7:0] good_cnt_limit_s;
+  wire       good_cnt_limit_reached_s;
+  wire       goto_next_state_s;
 
-assign cgs_reset = cgs_rst;
-assign ifs_reset = ifs_rst;
-assign sync = sync_n;
-assign phy_en_char_align = en_align;
+  assign cgs_reset = cgs_rst;
+  assign ifs_reset = ifs_rst;
+  assign sync = sync_n;
+  assign phy_en_char_align = en_align;
 
-assign status_state = state;
+  assign status_state = state;
 
-always @(posedge clk) begin
-  case (state)
-  STATE_RESET: begin
-    cgs_rst <= {NUM_LANES{1'b1}};
-    ifs_rst <= {NUM_LANES{1'b1}};
-    sync_n <= {NUM_LINKS{1'b1}};
-    latency_monitor_reset <= 1'b1;
-  end
-  STATE_CGS: begin
-    sync_n <= cfg_links_disable;
-    cgs_rst <= cfg_lanes_disable;
-  end
-  STATE_SYNCHRONIZED: begin
-    if (lmfc_edge == 1'b1) begin
+  always @(posedge clk) begin
+    case (state)
+    STATE_RESET: begin
+      cgs_rst <= {NUM_LANES{1'b1}};
+      ifs_rst <= {NUM_LANES{1'b1}};
       sync_n <= {NUM_LINKS{1'b1}};
-      ifs_rst <= cfg_lanes_disable;
-      latency_monitor_reset <= 1'b0;
+      latency_monitor_reset <= 1'b1;
     end
+    STATE_CGS: begin
+      sync_n <= cfg_links_disable;
+      cgs_rst <= cfg_lanes_disable;
+    end
+    STATE_SYNCHRONIZED: begin
+      if (lmfc_edge == 1'b1) begin
+        sync_n <= {NUM_LINKS{1'b1}};
+        ifs_rst <= cfg_lanes_disable;
+        latency_monitor_reset <= 1'b0;
+      end
+    end
+    endcase
   end
-  endcase
-end
 
-always @(*) begin
-  case (state)
-  STATE_RESET: state_good = 1'b1;
-  STATE_WAIT_FOR_PHY: state_good = phy_ready;
-  STATE_CGS: state_good = &(cgs_ready | cfg_lanes_disable);
-  STATE_SYNCHRONIZED: state_good = ENABLE_FRAME_ALIGN_ERR_RESET ?
-                                   &(~frame_align_err_thresh_met | cfg_lanes_disable) :
-                                   1'b1;
-  default: state_good = 1'b0;
-  endcase
-end
+  always @(*) begin
+    case (state)
+    STATE_RESET: state_good = 1'b1;
+    STATE_WAIT_FOR_PHY: state_good = phy_ready;
+    STATE_CGS: state_good = &(cgs_ready | cfg_lanes_disable);
+    STATE_SYNCHRONIZED: state_good = ENABLE_FRAME_ALIGN_ERR_RESET ?
+                                     &(~frame_align_err_thresh_met | cfg_lanes_disable) :
+                                     1'b1;
+    default: state_good = 1'b0;
+    endcase
+  end
 
-assign good_cnt_limit_s = (state == STATE_CGS) ? 'hff : 'h7;
-assign good_cnt_limit_reached_s = good_counter == good_cnt_limit_s;
+  assign good_cnt_limit_s = (state == STATE_CGS) ? 'hff : 'h7;
+  assign good_cnt_limit_reached_s = good_counter == good_cnt_limit_s;
 
-assign goto_next_state_s = good_cnt_limit_reached_s || (state == STATE_SYNCHRONIZED);
+  assign goto_next_state_s = good_cnt_limit_reached_s || (state == STATE_SYNCHRONIZED);
 
-always @(posedge clk) begin
-  if (reset) begin
-    good_counter <= 'h00;
-  end else if (state_good == 1'b1) begin
-    if (good_cnt_limit_reached_s) begin
+  always @(posedge clk) begin
+    if (reset) begin
       good_counter <= 'h00;
+    end else if (state_good == 1'b1) begin
+      if (good_cnt_limit_reached_s) begin
+        good_counter <= 'h00;
+      end else begin
+        good_counter <= good_counter + 1'b1;
+      end
     end else begin
-      good_counter <= good_counter + 1'b1;
-    end
-  end else begin
-    good_counter <= 'h00;
-  end
-end
-
-always @(posedge clk) begin
-  case (state)
-  STATE_CGS: en_align <= 1'b1;
-  default: en_align <= 1'b0;
-  endcase
-end
-
-always @(*) begin
-  case (state)
-  STATE_RESET: next_state = STATE_WAIT_FOR_PHY;
-  STATE_WAIT_FOR_PHY: next_state = STATE_CGS;
-  STATE_CGS: next_state = STATE_SYNCHRONIZED;
-  default: next_state = state_good ? state : STATE_RESET;
-  endcase
-end
-
-always @(posedge clk) begin
-  if (reset == 1'b1) begin
-    state <= STATE_RESET;
-  end else begin
-    if (goto_next_state_s) begin
-      state <= next_state;
+      good_counter <= 'h00;
     end
   end
-end
 
-assign event_data_phase = state == STATE_CGS &&
-                          next_state == STATE_SYNCHRONIZED &&
-                          good_cnt_limit_reached_s;
+  always @(posedge clk) begin
+    case (state)
+    STATE_CGS: en_align <= 1'b1;
+    default: en_align <= 1'b0;
+    endcase
+  end
+
+  always @(*) begin
+    case (state)
+    STATE_RESET: next_state = STATE_WAIT_FOR_PHY;
+    STATE_WAIT_FOR_PHY: next_state = STATE_CGS;
+    STATE_CGS: next_state = STATE_SYNCHRONIZED;
+    default: next_state = state_good ? state : STATE_RESET;
+    endcase
+  end
+
+  always @(posedge clk) begin
+    if (reset == 1'b1) begin
+      state <= STATE_RESET;
+    end else begin
+      if (goto_next_state_s) begin
+        state <= next_state;
+      end
+    end
+  end
+
+  assign event_data_phase = state == STATE_CGS &&
+                            next_state == STATE_SYNCHRONIZED &&
+                            good_cnt_limit_reached_s;
 
 endmodule
diff --git a/library/jesd204/jesd204_rx/jesd204_rx_ctrl_64b.v b/library/jesd204/jesd204_rx/jesd204_rx_ctrl_64b.v
index 1e3d952fe..0e5f89738 100644
--- a/library/jesd204/jesd204_rx/jesd204_rx_ctrl_64b.v
+++ b/library/jesd204/jesd204_rx/jesd204_rx_ctrl_64b.v
@@ -63,95 +63,94 @@ module jesd204_rx_ctrl_64b #(
   output reg event_unexpected_lane_state_error
 );
 
+  localparam STATE_RESET = 2'b00;
+  localparam STATE_WAIT_BS = 2'b01;
+  localparam STATE_BLOCK_SYNC = 2'b10;
+  localparam STATE_DATA = 2'b11;
 
-localparam STATE_RESET = 2'b00;
-localparam STATE_WAIT_BS = 2'b01;
-localparam STATE_BLOCK_SYNC = 2'b10;
-localparam STATE_DATA = 2'b11;
+  reg [1:0] state = STATE_RESET;
+  reg [1:0] next_state;
+  reg [5:0] good_cnt;
+  reg rst_good_cnt;
+  reg event_unexpected_lane_state_error_nx;
 
-reg [1:0] state = STATE_RESET;
-reg [1:0] next_state;
-reg [5:0] good_cnt;
-reg rst_good_cnt;
-reg event_unexpected_lane_state_error_nx;
+  wire [NUM_LANES-1:0] phy_block_sync_masked;
+  wire [NUM_LANES-1:0] emb_lock_masked;
+  wire all_block_sync;
 
-wire [NUM_LANES-1:0] phy_block_sync_masked;
-wire [NUM_LANES-1:0] emb_lock_masked;
-wire all_block_sync;
+  reg [NUM_LANES-1:0] emb_lock_d = {NUM_LANES{1'b0}};
+  reg buffer_release_d_n = 1'b1;
 
-reg [NUM_LANES-1:0] emb_lock_d = {NUM_LANES{1'b0}};
-reg buffer_release_d_n = 1'b1;
+  always @(posedge clk) begin
+    emb_lock_d <= emb_lock;
+    buffer_release_d_n <= buffer_release_n;
+  end
 
-always @(posedge clk) begin
-  emb_lock_d <= emb_lock;
-  buffer_release_d_n <= buffer_release_n;
-end
+  assign phy_block_sync_masked = phy_block_sync | cfg_lanes_disable;
+  assign emb_lock_masked = emb_lock_d | cfg_lanes_disable;
 
-assign phy_block_sync_masked = phy_block_sync | cfg_lanes_disable;
-assign emb_lock_masked = emb_lock_d | cfg_lanes_disable;
+  assign all_block_sync = &phy_block_sync_masked;
+  assign all_emb_lock = &emb_lock_masked;
 
-assign all_block_sync = &phy_block_sync_masked;
-assign all_emb_lock = &emb_lock_masked;
-
-always @(*) begin
-  next_state = state;
-  rst_good_cnt = 1'b1;
-  event_unexpected_lane_state_error_nx = 1'b0;
-  case (state)
-    STATE_RESET:
-      next_state = STATE_WAIT_BS;
-    STATE_WAIT_BS:
-      if (all_block_sync) begin
-        rst_good_cnt = 1'b0;
-        if (&good_cnt) begin
+  always @(*) begin
+    next_state = state;
+    rst_good_cnt = 1'b1;
+    event_unexpected_lane_state_error_nx = 1'b0;
+    case (state)
+      STATE_RESET:
+        next_state = STATE_WAIT_BS;
+      STATE_WAIT_BS:
+        if (all_block_sync) begin
+          rst_good_cnt = 1'b0;
+          if (&good_cnt) begin
+            next_state = STATE_BLOCK_SYNC;
+          end
+        end
+      STATE_BLOCK_SYNC:
+        if (~all_block_sync) begin
+          next_state = STATE_WAIT_BS;
+        end else if (all_emb_lock & ~buffer_release_d_n) begin
+          rst_good_cnt = 1'b0;
+          if (&good_cnt) begin
+            next_state = STATE_DATA;
+          end
+        end
+      STATE_DATA:
+        if (~all_block_sync) begin
+          next_state = STATE_WAIT_BS;
+          event_unexpected_lane_state_error_nx = 1'b1;
+        end else if (~all_emb_lock | buffer_release_d_n) begin
           next_state = STATE_BLOCK_SYNC;
+          event_unexpected_lane_state_error_nx = 1'b1;
         end
-      end
-    STATE_BLOCK_SYNC:
-      if (~all_block_sync) begin
-        next_state = STATE_WAIT_BS;
-      end else if (all_emb_lock & ~buffer_release_d_n) begin
-        rst_good_cnt = 1'b0;
-        if (&good_cnt) begin
-          next_state = STATE_DATA;
-        end
-      end
-    STATE_DATA:
-      if (~all_block_sync) begin
-        next_state = STATE_WAIT_BS;
-        event_unexpected_lane_state_error_nx = 1'b1;
-      end else if (~all_emb_lock | buffer_release_d_n) begin
-        next_state = STATE_BLOCK_SYNC;
-        event_unexpected_lane_state_error_nx = 1'b1;
-      end
-  endcase
-end
-
-// Wait n consecutive valid cycles before jumping into next state
-always @(posedge clk) begin
-  if (reset || rst_good_cnt) begin
-    good_cnt <= 'h0;
-  end else begin
-    good_cnt <= good_cnt + 1;
+    endcase
   end
-end
 
-always @(posedge clk) begin
-  if (reset == 1'b1) begin
-    state <= STATE_RESET;
-  end else begin
-    state <= next_state;
+  // Wait n consecutive valid cycles before jumping into next state
+  always @(posedge clk) begin
+    if (reset || rst_good_cnt) begin
+      good_cnt <= 'h0;
+    end else begin
+      good_cnt <= good_cnt + 1;
+    end
   end
-end
 
-always @(posedge clk) begin
-  if (reset == 1'b1) begin
-    event_unexpected_lane_state_error <= 1'b0;
-  end else begin
-    event_unexpected_lane_state_error <= event_unexpected_lane_state_error_nx;
+  always @(posedge clk) begin
+    if (reset == 1'b1) begin
+      state <= STATE_RESET;
+    end else begin
+      state <= next_state;
+    end
   end
-end
 
-assign status_state = state;
+  always @(posedge clk) begin
+    if (reset == 1'b1) begin
+      event_unexpected_lane_state_error <= 1'b0;
+    end else begin
+      event_unexpected_lane_state_error <= event_unexpected_lane_state_error_nx;
+    end
+  end
+
+  assign status_state = state;
 
 endmodule
diff --git a/library/jesd204/jesd204_rx/jesd204_rx_frame_align.v b/library/jesd204/jesd204_rx/jesd204_rx_frame_align.v
index 09c755780..6dbf943da 100755
--- a/library/jesd204/jesd204_rx/jesd204_rx_frame_align.v
+++ b/library/jesd204/jesd204_rx/jesd204_rx_frame_align.v
@@ -61,141 +61,139 @@ module jesd204_rx_frame_align #(
   output reg [7:0]                  align_err_cnt
 );
 
-// Reset alignment error count on good multiframe alignment,
-// or on good frame or multiframe alignment
-// If disabled, misalignments could me masked if
-// due to cfg_octets_per_multiframe mismatch or due to
-// a slip of a multiple of cfg_octets_per_frame octets
-localparam RESET_COUNT_ON_MF_ONLY = 1'b1;
+  // Reset alignment error count on good multiframe alignment,
+  // or on good frame or multiframe alignment
+  // If disabled, misalignments could me masked if
+  // due to cfg_octets_per_multiframe mismatch or due to
+  // a slip of a multiple of cfg_octets_per_frame octets
+  localparam RESET_COUNT_ON_MF_ONLY = 1'b1;
 
-localparam DPW_LOG2 = DATA_PATH_WIDTH == 8 ? 3 :
-  DATA_PATH_WIDTH == 4 ? 2 : 1;
+  localparam DPW_LOG2 = DATA_PATH_WIDTH == 8 ? 3 :
+    DATA_PATH_WIDTH == 4 ? 2 : 1;
 
-function automatic [DPW_LOG2*2:0] count_ones(input [DATA_PATH_WIDTH*2-1:0] val);
-  reg [DPW_LOG2*2-1:0] ii;
-  begin
-    count_ones = 0;
-    for(ii = 0; ii != (DATA_PATH_WIDTH*2-1); ii=ii+1) begin
-      count_ones = count_ones + val[ii];
-    end
-  end
-endfunction
-
-reg  [DATA_PATH_WIDTH-1:0]        char_is_a;
-reg  [DATA_PATH_WIDTH-1:0]        char_is_f;
-wire [DATA_PATH_WIDTH-1:0]        eof;
-wire [DATA_PATH_WIDTH-1:0]        eomf;
-reg  [DATA_PATH_WIDTH-1:0]        eof_err;
-reg  [DATA_PATH_WIDTH-1:0]        eof_good;
-reg  [DATA_PATH_WIDTH-1:0]        eomf_err;
-reg  [DATA_PATH_WIDTH-1:0]        eomf_good;
-reg                               align_good;
-reg                               align_err;
-reg  [DPW_LOG2*2:0]               cur_align_err_cnt;
-wire [8:0]                        align_err_cnt_next;
-
-wire [7:0] cfg_beats_per_multiframe = cfg_octets_per_multiframe>>DPW_LOG2;
-
-jesd204_frame_mark #(
-  .DATA_PATH_WIDTH            (DATA_PATH_WIDTH)
-) i_frame_mark (
-  .clk                        (clk),
-  .reset                      (reset),
-  .cfg_octets_per_multiframe  (cfg_octets_per_multiframe),
-  .cfg_beats_per_multiframe   (cfg_beats_per_multiframe),
-  .cfg_octets_per_frame       (cfg_octets_per_frame),
-  .sof                        (),
-  .eof                        (eof),
-  .somf                       (),
-  .eomf                       (eomf)
-);
-
-genvar ii;
-generate
-for (ii = 0; ii < DATA_PATH_WIDTH; ii = ii + 1) begin: gen_k_char
-  always @(*) begin
-    char_is_a[ii] = 1'b0;
-    char_is_f[ii] = 1'b0;
-
-    if(charisk28[ii]) begin
-      if(data[ii*8+7:ii*8+5] == 3'd3) begin
-        char_is_a[ii] = 1'b1;
+  function automatic [DPW_LOG2*2:0] count_ones(input [DATA_PATH_WIDTH*2-1:0] val);
+    reg [DPW_LOG2*2-1:0] ii;
+    begin
+      count_ones = 0;
+      for(ii = 0; ii != (DATA_PATH_WIDTH*2-1); ii=ii+1) begin
+        count_ones = count_ones + val[ii];
       end
-      if(data[ii*8+7:ii*8+5] == 3'd7) begin
-        char_is_f[ii] = 1'b1;
+    end
+  endfunction
+
+  reg  [DATA_PATH_WIDTH-1:0]        char_is_a;
+  reg  [DATA_PATH_WIDTH-1:0]        char_is_f;
+  wire [DATA_PATH_WIDTH-1:0]        eof;
+  wire [DATA_PATH_WIDTH-1:0]        eomf;
+  reg  [DATA_PATH_WIDTH-1:0]        eof_err;
+  reg  [DATA_PATH_WIDTH-1:0]        eof_good;
+  reg  [DATA_PATH_WIDTH-1:0]        eomf_err;
+  reg  [DATA_PATH_WIDTH-1:0]        eomf_good;
+  reg                               align_good;
+  reg                               align_err;
+  reg  [DPW_LOG2*2:0]               cur_align_err_cnt;
+  wire [8:0]                        align_err_cnt_next;
+
+  wire [7:0] cfg_beats_per_multiframe = cfg_octets_per_multiframe>>DPW_LOG2;
+
+  jesd204_frame_mark #(
+    .DATA_PATH_WIDTH (DATA_PATH_WIDTH)
+  ) i_frame_mark (
+    .clk (clk),
+    .reset (reset),
+    .cfg_octets_per_multiframe (cfg_octets_per_multiframe),
+    .cfg_beats_per_multiframe (cfg_beats_per_multiframe),
+    .cfg_octets_per_frame (cfg_octets_per_frame),
+    .sof (),
+    .eof (eof),
+    .somf (),
+    .eomf (eomf));
+
+  genvar ii;
+  generate
+  for (ii = 0; ii < DATA_PATH_WIDTH; ii = ii + 1) begin: gen_k_char
+    always @(*) begin
+      char_is_a[ii] = 1'b0;
+      char_is_f[ii] = 1'b0;
+
+      if(charisk28[ii]) begin
+        if(data[ii*8+7:ii*8+5] == 3'd3) begin
+          char_is_a[ii] = 1'b1;
+        end
+        if(data[ii*8+7:ii*8+5] == 3'd7) begin
+          char_is_f[ii] = 1'b1;
+        end
+      end
+    end
+
+    always @(posedge clk) begin
+      if(reset) begin
+        eomf_err[ii] <= 1'b0;
+        eomf_good[ii] <= 1'b0;
+        eof_err[ii] <= 1'b0;
+        eof_good[ii] <= 1'b0;
+      end else begin
+        eomf_err[ii]  <= char_is_a[ii] && !eomf[ii];
+        eomf_good[ii] <= char_is_a[ii] && eomf[ii];
+        eof_err[ii]   <= char_is_f[ii] && !eof[ii];
+        eof_good[ii]  <= char_is_f[ii] && eof[ii];
       end
     end
   end
+  endgenerate
 
   always @(posedge clk) begin
     if(reset) begin
-      eomf_err[ii] <= 1'b0;
-      eomf_good[ii] <= 1'b0;
-      eof_err[ii] <= 1'b0;
-      eof_good[ii] <= 1'b0;
+      align_good <= 1'b0;
+      align_err <= 1'b0;
     end else begin
-      eomf_err[ii]  <= char_is_a[ii] && !eomf[ii];
-      eomf_good[ii] <= char_is_a[ii] && eomf[ii];
-      eof_err[ii]   <= char_is_f[ii] && !eof[ii];
-      eof_good[ii]  <= char_is_f[ii] && eof[ii];
+      if(RESET_COUNT_ON_MF_ONLY) begin
+        align_good <= |eomf_good;
+      end else begin
+        align_good <= |({eomf_good, eof_good});
+      end
+
+      align_err <= |({eomf_err, eof_err});
     end
   end
-end
-endgenerate
 
-always @(posedge clk) begin
-  if(reset) begin
-    align_good <= 1'b0;
-    align_err <= 1'b0;
-  end else begin
-    if(RESET_COUNT_ON_MF_ONLY) begin
-      align_good <= |eomf_good;
-    end else begin
-      align_good <= |({eomf_good, eof_good});
-    end
+  assign align_err_cnt_next = {1'b0, align_err_cnt} + cur_align_err_cnt;
 
-    align_err <= |({eomf_err, eof_err});
-  end
-end
-
-assign align_err_cnt_next = {1'b0, align_err_cnt} + cur_align_err_cnt;
-
-// Alignment error counter
-// Resets upon good alignment
-always @(posedge clk) begin
-  if(reset) begin
-    align_err_cnt <= 8'd0;
-    cur_align_err_cnt <= 'd0;
-  end else begin
-    cur_align_err_cnt <= count_ones({eomf_err, eof_err});
-
-    if(align_good && !align_err) begin
+  // Alignment error counter
+  // Resets upon good alignment
+  always @(posedge clk) begin
+    if(reset) begin
       align_err_cnt <= 8'd0;
-    end else if(align_err_cnt_next[8]) begin
-      align_err_cnt <= 8'hFF;
+      cur_align_err_cnt <= 'd0;
     end else begin
-      align_err_cnt <= align_err_cnt_next[7:0];
+      cur_align_err_cnt <= count_ones({eomf_err, eof_err});
+
+      if(align_good && !align_err) begin
+        align_err_cnt <= 8'd0;
+      end else if(align_err_cnt_next[8]) begin
+        align_err_cnt <= 8'hFF;
+      end else begin
+        align_err_cnt <= align_err_cnt_next[7:0];
+      end
     end
   end
-end
 
-jesd204_frame_align_replace #(
-  .DATA_PATH_WIDTH              (DATA_PATH_WIDTH),
-  .IS_RX                        (1'b1),
-  .ENABLED                      (ENABLE_CHAR_REPLACE)
-) i_align_replace (
-  .clk                          (clk),
-  .reset                        (reset),
-  .cfg_octets_per_frame         (cfg_octets_per_frame),
-  .cfg_disable_char_replacement (cfg_disable_char_replacement),
-  .cfg_disable_scrambler        (cfg_disable_scrambler),
-  .data                         (data),
-  .eof                          (eof),
-  .rx_char_is_a                 (char_is_a),
-  .rx_char_is_f                 (char_is_f),
-  .tx_eomf                      ({DATA_PATH_WIDTH{1'b0}}),
-  .data_out                     (data_replaced),
-  .charisk_out                  ()
-);
+  jesd204_frame_align_replace #(
+    .DATA_PATH_WIDTH (DATA_PATH_WIDTH),
+    .IS_RX (1'b1),
+    .ENABLED (ENABLE_CHAR_REPLACE)
+  ) i_align_replace (
+    .clk (clk),
+    .reset (reset),
+    .cfg_octets_per_frame (cfg_octets_per_frame),
+    .cfg_disable_char_replacement (cfg_disable_char_replacement),
+    .cfg_disable_scrambler (cfg_disable_scrambler),
+    .data (data),
+    .eof (eof),
+    .rx_char_is_a (char_is_a),
+    .rx_char_is_f (char_is_f),
+    .tx_eomf ({DATA_PATH_WIDTH{1'b0}}),
+    .data_out (data_replaced),
+    .charisk_out ());
 
 endmodule
diff --git a/library/jesd204/jesd204_rx/jesd204_rx_header.v b/library/jesd204/jesd204_rx/jesd204_rx_header.v
index 539272544..3fd1e6d9f 100644
--- a/library/jesd204/jesd204_rx/jesd204_rx_header.v
+++ b/library/jesd204/jesd204_rx/jesd204_rx_header.v
@@ -70,138 +70,134 @@ module jesd204_rx_header (
   output reg event_invalid_header,
   output reg event_unexpected_eomb,
   output reg event_unexpected_eoemb
-
 );
 
-localparam STATE_EMB_INIT = 3'b001;
-localparam STATE_EMB_HUNT = 3'b010;
-localparam STATE_EMB_LOCK = 3'b100;
+  localparam STATE_EMB_INIT = 3'b001;
+  localparam STATE_EMB_HUNT = 3'b010;
+  localparam STATE_EMB_LOCK = 3'b100;
 
-localparam BIT_EMB_INIT = 0;
-localparam BIT_EMB_HUNT = 1;
-localparam BIT_EMB_LOCK = 2;
+  localparam BIT_EMB_INIT = 0;
+  localparam BIT_EMB_HUNT = 1;
+  localparam BIT_EMB_LOCK = 2;
 
-reg [2:0] state = STATE_EMB_INIT;
-reg [2:0] next_state;
+  reg [2:0] state = STATE_EMB_INIT;
+  reg [2:0] next_state;
 
-reg [31:0] sync_word = 'h0;
+  reg [31:0] sync_word = 'h0;
 
-wire header_bit;
-wire invalid_sequence;
-wire invalid_eoemb;
-wire invalid_eomb;
-wire [6:0] cmd0;
-wire [6:0] cmd1;
-wire [18:0] cmd3;
-wire eoemb;
-wire eomb;
+  wire header_bit;
+  wire invalid_sequence;
+  wire invalid_eoemb;
+  wire invalid_eomb;
+  wire [6:0] cmd0;
+  wire [6:0] cmd1;
+  wire [18:0] cmd3;
+  wire eoemb;
+  wire eomb;
 
-assign header_bit = header == 2'b01;
+  assign header_bit = header == 2'b01;
 
-always @(posedge clk) begin
-  sync_word <= {sync_word[30:0],header_bit};
-end
-
-assign crc12 = {sync_word[31:29],sync_word[27:25],
-                sync_word[23:21],sync_word[19:17]};
-assign crc3 = {sync_word[31:29]};
-assign cmd0 = {sync_word[15:13],sync_word[11],
-               sync_word[7:5]};
-assign cmd1 = {sync_word[27:25],
-               sync_word[19:17],
-               sync_word[11]};
-assign cmd3 = {sync_word[31:29],sync_word[27:25],
-               sync_word[23:21],sync_word[19:17],
-               sync_word[15:13],sync_word[11],
-               sync_word[7:5]};
-
-assign cmd = cfg_header_mode == 0 ? {12'b0,cmd0} :
-             cfg_header_mode == 1 ? {12'b0,cmd1} :
-             cfg_header_mode == 3 ? cmd3 : 'b0;
-
-assign fec = {sync_word[31:10],sync_word[8:5]};
-
-
-assign eomb  = sync_word[4:0] == 5'b00001;
-assign eoemb = sync_word[9] & eomb;
-
-
-always @(posedge clk) begin
-  if (next_state[BIT_EMB_INIT] || sh_count == cfg_beats_per_multiframe) begin
-    sh_count <= 'h0;
-  end else begin
-    sh_count <= sh_count + 8'b1;
+  always @(posedge clk) begin
+    sync_word <= {sync_word[30:0],header_bit};
   end
-end
 
-reg [1:0] emb_vcount = 'b0;
-always @(posedge clk) begin
-  if (state[BIT_EMB_INIT]) begin
-    emb_vcount <= 'b0;
-  end else if (state[BIT_EMB_HUNT] && (sh_count == 0 && eoemb)) begin
-    emb_vcount <= emb_vcount + 'b1;
-  end
-end
+  assign crc12 = {sync_word[31:29],sync_word[27:25],
+                  sync_word[23:21],sync_word[19:17]};
+  assign crc3 = {sync_word[31:29]};
+  assign cmd0 = {sync_word[15:13],sync_word[11],
+                 sync_word[7:5]};
+  assign cmd1 = {sync_word[27:25],
+                 sync_word[19:17],
+                 sync_word[11]};
+  assign cmd3 = {sync_word[31:29],sync_word[27:25],
+                 sync_word[23:21],sync_word[19:17],
+                 sync_word[15:13],sync_word[11],
+                 sync_word[7:5]};
 
-reg [4:0] emb_icount = 'b0;
-always @(posedge clk) begin
-  if (state[BIT_EMB_INIT]) begin
-    emb_icount <= 'b0;
-  end else if (state[BIT_EMB_LOCK]) begin
-    if (sh_count == 0 && eoemb) begin
-      emb_icount <= 'b0;
-    end else if (invalid_eoemb || invalid_eomb) begin
-      emb_icount <= emb_icount + 5'b1;
+  assign cmd = cfg_header_mode == 0 ? {12'b0,cmd0} :
+               cfg_header_mode == 1 ? {12'b0,cmd1} :
+               cfg_header_mode == 3 ? cmd3 : 'b0;
+
+  assign fec = {sync_word[31:10],sync_word[8:5]};
+
+  assign eomb  = sync_word[4:0] == 5'b00001;
+  assign eoemb = sync_word[9] & eomb;
+
+  always @(posedge clk) begin
+    if (next_state[BIT_EMB_INIT] || sh_count == cfg_beats_per_multiframe) begin
+      sh_count <= 'h0;
+    end else begin
+      sh_count <= sh_count + 8'b1;
     end
   end
-end
 
-
-always @(*) begin
-  next_state = state;
-  case (state)
-    STATE_EMB_INIT:
-      if (eoemb) begin
-        next_state = STATE_EMB_HUNT;
-      end
-    STATE_EMB_HUNT:
-      if (invalid_sequence) begin
-        next_state = STATE_EMB_INIT;
-      end else if (eoemb && emb_vcount == 2'd3) begin
-        next_state = STATE_EMB_LOCK;
-      end
-    STATE_EMB_LOCK:
-      if (emb_icount == cfg_rx_thresh_emb_err) begin
-        next_state = STATE_EMB_INIT;
-      end
-  endcase
-  if (sh_lock == 1'b0) next_state = STATE_EMB_INIT;
-end
-
-assign invalid_eoemb = (sh_count == 0 && ~eoemb);
-assign invalid_eomb = (sh_count[4:0] == 0 && ~eomb);
-assign valid_eomb = next_state[BIT_EMB_LOCK] && eomb;
-assign valid_eoemb = next_state[BIT_EMB_LOCK] && eoemb;
-
-assign invalid_sequence = (invalid_eoemb || invalid_eomb);
-
-always @(posedge clk) begin
-  if (reset == 1'b1) begin
-    state <= STATE_EMB_INIT;
-  end else begin
-    state <= next_state;
+  reg [1:0] emb_vcount = 'b0;
+  always @(posedge clk) begin
+    if (state[BIT_EMB_INIT]) begin
+      emb_vcount <= 'b0;
+    end else if (state[BIT_EMB_HUNT] && (sh_count == 0 && eoemb)) begin
+      emb_vcount <= emb_vcount + 'b1;
+    end
   end
-end
 
-assign emb_lock = next_state[BIT_EMB_LOCK];
+  reg [4:0] emb_icount = 'b0;
+  always @(posedge clk) begin
+    if (state[BIT_EMB_INIT]) begin
+      emb_icount <= 'b0;
+    end else if (state[BIT_EMB_LOCK]) begin
+      if (sh_count == 0 && eoemb) begin
+        emb_icount <= 'b0;
+      end else if (invalid_eoemb || invalid_eomb) begin
+        emb_icount <= emb_icount + 5'b1;
+      end
+    end
+  end
 
-// Status & error events
-assign status_lane_emb_state = state;
+  always @(*) begin
+    next_state = state;
+    case (state)
+      STATE_EMB_INIT:
+        if (eoemb) begin
+          next_state = STATE_EMB_HUNT;
+        end
+      STATE_EMB_HUNT:
+        if (invalid_sequence) begin
+          next_state = STATE_EMB_INIT;
+        end else if (eoemb && emb_vcount == 2'd3) begin
+          next_state = STATE_EMB_LOCK;
+        end
+      STATE_EMB_LOCK:
+        if (emb_icount == cfg_rx_thresh_emb_err) begin
+          next_state = STATE_EMB_INIT;
+        end
+    endcase
+    if (sh_lock == 1'b0) next_state = STATE_EMB_INIT;
+  end
 
-always @(posedge clk) begin
-  event_invalid_header <= (~state[BIT_EMB_INIT]) && (header[0] == header[1]);
-  event_unexpected_eomb <= (~state[BIT_EMB_INIT]) && (sh_count[4:0] != 0 && eomb);
-  event_unexpected_eoemb <= (~state[BIT_EMB_INIT]) && invalid_eoemb;
-end
+  assign invalid_eoemb = (sh_count == 0 && ~eoemb);
+  assign invalid_eomb = (sh_count[4:0] == 0 && ~eomb);
+  assign valid_eomb = next_state[BIT_EMB_LOCK] && eomb;
+  assign valid_eoemb = next_state[BIT_EMB_LOCK] && eoemb;
+
+  assign invalid_sequence = (invalid_eoemb || invalid_eomb);
+
+  always @(posedge clk) begin
+    if (reset == 1'b1) begin
+      state <= STATE_EMB_INIT;
+    end else begin
+      state <= next_state;
+    end
+  end
+
+  assign emb_lock = next_state[BIT_EMB_LOCK];
+
+  // Status & error events
+  assign status_lane_emb_state = state;
+
+  always @(posedge clk) begin
+    event_invalid_header <= (~state[BIT_EMB_INIT]) && (header[0] == header[1]);
+    event_unexpected_eomb <= (~state[BIT_EMB_INIT]) && (sh_count[4:0] != 0 && eomb);
+    event_unexpected_eoemb <= (~state[BIT_EMB_INIT]) && invalid_eoemb;
+  end
 
 endmodule
diff --git a/library/jesd204/jesd204_rx/jesd204_rx_lane.v b/library/jesd204/jesd204_rx/jesd204_rx_lane.v
index dbaf73b44..048304c99 100755
--- a/library/jesd204/jesd204_rx/jesd204_rx_lane.v
+++ b/library/jesd204/jesd204_rx/jesd204_rx_lane.v
@@ -86,7 +86,7 @@ module jesd204_rx_lane #(
   output [DATA_PATH_WIDTH*8-1:0] ilas_config_data,
 
   input err_statistics_reset,
-  input [2:0]ctrl_err_statistics_mask,
+  input [2:0] ctrl_err_statistics_mask,
   output reg [31:0] status_err_statistics_cnt,
 
   output [1:0] status_cgs_state,
@@ -95,266 +95,257 @@ module jesd204_rx_lane #(
   output [7:0] status_frame_align_err_cnt
 );
 
-localparam MAX_DATA_PATH_WIDTH = 8;
-localparam DPW_LOG2 = DATA_PATH_WIDTH == 8 ? 3 : DATA_PATH_WIDTH == 4 ? 2 : 1;
+  localparam MAX_DATA_PATH_WIDTH = 8;
+  localparam DPW_LOG2 = DATA_PATH_WIDTH == 8 ? 3 : DATA_PATH_WIDTH == 4 ? 2 : 1;
 
-wire [7:0] char[0:DATA_PATH_WIDTH-1];
-wire [DATA_PATH_WIDTH-1:0] char_is_valid;
-reg [DATA_PATH_WIDTH-1:0] char_is_cgs = 1'b0;        // K28.5 /K/
+  wire [7:0] char[0:DATA_PATH_WIDTH-1];
+  wire [DATA_PATH_WIDTH-1:0] char_is_valid;
+  reg [DATA_PATH_WIDTH-1:0] char_is_cgs = 1'b0;        // K28.5 /K/
 
-reg [DATA_PATH_WIDTH-1:0] char_is_error = 1'b0;
-reg [DATA_PATH_WIDTH-1:0] charisk28 = 4'b0000;
+  reg [DATA_PATH_WIDTH-1:0] char_is_error = 1'b0;
+  reg [DATA_PATH_WIDTH-1:0] charisk28 = 4'b0000;
 
-wire cgs_beat_is_cgs = &char_is_cgs;
-wire cgs_beat_has_error = |char_is_error;
+  wire cgs_beat_is_cgs = &char_is_cgs;
+  wire cgs_beat_has_error = |char_is_error;
 
-reg ifs_ready = 1'b0;
-reg [2:0] frame_align = 'h00;
-reg [2:0] frame_align_int;
+  reg ifs_ready = 1'b0;
+  reg [2:0] frame_align = 'h00;
+  reg [2:0] frame_align_int;
 
-wire [DATA_PATH_WIDTH*8-1:0] phy_data_s;
-wire [DATA_PATH_WIDTH-1:0] charisk28_aligned_s;
-wire [DATA_PATH_WIDTH*8-1:0] data_aligned_s;
-wire [DATA_PATH_WIDTH-1:0] charisk28_aligned;
-wire [DATA_PATH_WIDTH*8-1:0] data_aligned;
-wire [DATA_PATH_WIDTH*8-1:0] data_replaced;
-wire [DATA_PATH_WIDTH*8-1:0] data_scrambled_s;
-wire [DATA_PATH_WIDTH*8-1:0] data_scrambled;
+  wire [DATA_PATH_WIDTH*8-1:0] phy_data_s;
+  wire [DATA_PATH_WIDTH-1:0] charisk28_aligned_s;
+  wire [DATA_PATH_WIDTH*8-1:0] data_aligned_s;
+  wire [DATA_PATH_WIDTH-1:0] charisk28_aligned;
+  wire [DATA_PATH_WIDTH*8-1:0] data_aligned;
+  wire [DATA_PATH_WIDTH*8-1:0] data_replaced;
+  wire [DATA_PATH_WIDTH*8-1:0] data_scrambled_s;
+  wire [DATA_PATH_WIDTH*8-1:0] data_scrambled;
 
-reg  [DATA_PATH_WIDTH-1:0] unexpected_char;
-reg  [DATA_PATH_WIDTH-1:0] phy_char_err;
+  reg  [DATA_PATH_WIDTH-1:0] unexpected_char;
+  reg  [DATA_PATH_WIDTH-1:0] phy_char_err;
 
-wire ilas_monitor_reset_s;
-wire ilas_monitor_reset;
-wire buffer_ready_n_s;
-reg  [DPW_LOG2:0] jj;
-reg  align_found;
+  wire ilas_monitor_reset_s;
+  wire ilas_monitor_reset;
+  wire buffer_ready_n_s;
+  reg  [DPW_LOG2:0] jj;
+  reg  align_found;
 
-assign status_ifs_ready = ifs_ready;
-assign status_frame_align = frame_align;
+  assign status_ifs_ready = ifs_ready;
+  assign status_frame_align = frame_align;
 
-genvar i;
-generate
+  genvar i;
+  generate
 
-for (i = 0; i < DATA_PATH_WIDTH; i = i + 1) begin: gen_char
-  assign char[i] = phy_data[i*8+7:i*8];
-  assign char_is_valid[i] = ~(phy_notintable[i] | phy_disperr[i]);
+  for (i = 0; i < DATA_PATH_WIDTH; i = i + 1) begin: gen_char
+    assign char[i] = phy_data[i*8+7:i*8];
+    assign char_is_valid[i] = ~(phy_notintable[i] | phy_disperr[i]);
 
-  always @(*) begin
-    char_is_error[i] = ~char_is_valid[i];
+    always @(*) begin
+      char_is_error[i] = ~char_is_valid[i];
 
-    char_is_cgs[i] = 1'b0;
-    charisk28[i] = 1'b0;
-    unexpected_char[i] = 1'b0;
+      char_is_cgs[i] = 1'b0;
+      charisk28[i] = 1'b0;
+      unexpected_char[i] = 1'b0;
 
-    if (phy_charisk[i] == 1'b1 && char_is_valid[i] == 1'b1) begin
-      if (char[i][4:0] == 'd28) begin
-        charisk28[i] = 1'b1;
-        if (char[i][7:5] == 'd5) begin
-          char_is_cgs[i] = 1'b1;
+      if (phy_charisk[i] == 1'b1 && char_is_valid[i] == 1'b1) begin
+        if (char[i][4:0] == 'd28) begin
+          charisk28[i] = 1'b1;
+          if (char[i][7:5] == 'd5) begin
+            char_is_cgs[i] = 1'b1;
+          end
+        end else begin
+          unexpected_char[i] = 1'b1;
         end
-      end else begin
-        unexpected_char[i] = 1'b1;
       end
     end
   end
-end
-endgenerate
+  endgenerate
 
-always @(posedge clk) begin
-  if (cgs_ready == 1'b1) begin
-    /*
-     * Set the bit in phy_char_err if at least one of the monitored error
-     * conditions has occured.
-     */
-    phy_char_err <= (~{DATA_PATH_WIDTH{ctrl_err_statistics_mask[0]}} & phy_disperr) |
-                    (~{DATA_PATH_WIDTH{ctrl_err_statistics_mask[1]}} & phy_notintable) |
-                    (~{DATA_PATH_WIDTH{ctrl_err_statistics_mask[2]}} & unexpected_char);
-  end else begin
-    phy_char_err <= {DATA_PATH_WIDTH{1'b0}};
-  end
-end
-
-function [7:0] num_set_bits;
-input [DATA_PATH_WIDTH-1:0] x;
-integer j;
-begin
-  num_set_bits = 0;
-  for (j = 0; j < DATA_PATH_WIDTH; j = j + 1) begin
-    num_set_bits = num_set_bits + x[j];
-  end
-end
-endfunction
-
-always @(posedge clk) begin
-  if (reset == 1'b1 || err_statistics_reset == 1'b1) begin
-    status_err_statistics_cnt <= 32'h0;
-  end else if (status_err_statistics_cnt[31:5] != 27'h7ffffff) begin
-    status_err_statistics_cnt <= status_err_statistics_cnt + num_set_bits(phy_char_err);
-  end
-end
-
-always @(posedge clk) begin
-  if (ifs_reset == 1'b1) begin
-    ifs_ready <= 1'b0;
-  end else if (cgs_beat_is_cgs == 1'b0 && cgs_beat_has_error == 1'b0) begin
-    ifs_ready <= 1'b1;
-  end
-end
-
-always @(*) begin
-  align_found = 1'b0;
-  frame_align_int = 0;
-  for(jj = 0; jj < DATA_PATH_WIDTH; jj=jj+1) begin
-    if (!align_found && (char_is_cgs[jj] == 1'b0)) begin
-      align_found = 1'b1;
-      frame_align_int = jj;
+  always @(posedge clk) begin
+    if (cgs_ready == 1'b1) begin
+      /*
+       * Set the bit in phy_char_err if at least one of the monitored error
+       * conditions has occured.
+       */
+      phy_char_err <= (~{DATA_PATH_WIDTH{ctrl_err_statistics_mask[0]}} & phy_disperr) |
+                      (~{DATA_PATH_WIDTH{ctrl_err_statistics_mask[1]}} & phy_notintable) |
+                      (~{DATA_PATH_WIDTH{ctrl_err_statistics_mask[2]}} & unexpected_char);
+    end else begin
+      phy_char_err <= {DATA_PATH_WIDTH{1'b0}};
     end
   end
-end
 
-always @(posedge clk) begin
-  if (ifs_ready == 1'b0) begin
-    frame_align <= frame_align_int;
+  function [7:0] num_set_bits;
+  input [DATA_PATH_WIDTH-1:0] x;
+  integer j;
+  begin
+    num_set_bits = 0;
+    for (j = 0; j < DATA_PATH_WIDTH; j = j + 1) begin
+      num_set_bits = num_set_bits + x[j];
+    end
   end
-end
+  endfunction
 
-pipeline_stage #(
-  .WIDTH(DATA_PATH_WIDTH*8),
-  .REGISTERED(CHAR_INFO_REGISTERED)
-) i_pipeline_stage0 (
-  .clk(clk),
-  .in(phy_data),
-  .out(phy_data_s)
-);
+  always @(posedge clk) begin
+    if (reset == 1'b1 || err_statistics_reset == 1'b1) begin
+      status_err_statistics_cnt <= 32'h0;
+    end else if (status_err_statistics_cnt[31:5] != 27'h7ffffff) begin
+      status_err_statistics_cnt <= status_err_statistics_cnt + num_set_bits(phy_char_err);
+    end
+  end
 
-align_mux #(
-  .DATA_PATH_WIDTH(DATA_PATH_WIDTH)
-) i_align_mux (
-  .clk(clk),
-  .align(frame_align),
-  .in_data(phy_data_s),
-  .out_data(data_aligned_s),
-  .in_charisk(charisk28),
-  .out_charisk(charisk28_aligned_s)
-);
+  always @(posedge clk) begin
+    if (ifs_reset == 1'b1) begin
+      ifs_ready <= 1'b0;
+    end else if (cgs_beat_is_cgs == 1'b0 && cgs_beat_has_error == 1'b0) begin
+      ifs_ready <= 1'b1;
+    end
+  end
 
-assign ilas_monitor_reset_s = ~ifs_ready;
+  always @(*) begin
+    align_found = 1'b0;
+    frame_align_int = 0;
+    for(jj = 0; jj < DATA_PATH_WIDTH; jj=jj+1) begin
+      if (!align_found && (char_is_cgs[jj] == 1'b0)) begin
+        align_found = 1'b1;
+        frame_align_int = jj;
+      end
+    end
+  end
 
-pipeline_stage #(
-  .WIDTH(1 + DATA_PATH_WIDTH * (8 + 1)),
-  .REGISTERED(ALIGN_MUX_REGISTERED)
-) i_pipeline_stage1 (
-  .clk(clk),
-  .in({
-      ilas_monitor_reset_s,
-      data_aligned_s,
-      charisk28_aligned_s
-    }),
-  .out({
-      ilas_monitor_reset,
-      data_aligned,
-      charisk28_aligned
-    })
-);
+  always @(posedge clk) begin
+    if (ifs_ready == 1'b0) begin
+      frame_align <= frame_align_int;
+    end
+  end
 
-generate
-if(ENABLE_FRAME_ALIGN_CHECK) begin : gen_frame_align
-jesd204_rx_frame_align #(
-  .DATA_PATH_WIDTH  (DATA_PATH_WIDTH),
-  .ENABLE_CHAR_REPLACE (ENABLE_CHAR_REPLACE)
-) i_frame_align (
-  .clk                          (clk),
-  .reset                        (buffer_ready_n_s),
-  .cfg_octets_per_multiframe    (cfg_octets_per_multiframe),
-  .cfg_octets_per_frame         (cfg_octets_per_frame),
-  .cfg_disable_char_replacement (cfg_disable_char_replacement),
-  .cfg_disable_scrambler        (cfg_disable_scrambler),
-  .charisk28                    (charisk28_aligned),
-  .data                         (data_aligned),
-  .data_replaced                (data_replaced),
-  .align_err_cnt                (status_frame_align_err_cnt)
-);
+  pipeline_stage #(
+    .WIDTH(DATA_PATH_WIDTH*8),
+    .REGISTERED(CHAR_INFO_REGISTERED)
+  ) i_pipeline_stage0 (
+    .clk(clk),
+    .in(phy_data),
+    .out(phy_data_s));
 
-end else begin : gen_no_frame_align_monitor
-  assign status_frame_align_err_cnt = 32'd0;
-  assign data_replaced = data_aligned;
-end
-endgenerate
+  align_mux #(
+    .DATA_PATH_WIDTH(DATA_PATH_WIDTH)
+  ) i_align_mux (
+    .clk(clk),
+    .align(frame_align),
+    .in_data(phy_data_s),
+    .out_data(data_aligned_s),
+    .in_charisk(charisk28),
+    .out_charisk(charisk28_aligned_s));
 
-jesd204_scrambler #(
-  .WIDTH(DATA_PATH_WIDTH*8),
-  .DESCRAMBLE(1)
-) i_descrambler (
-  .clk(clk),
-  .reset(buffer_ready_n_s),
-  .enable(~cfg_disable_scrambler),
-  .data_in(data_replaced),
-  .data_out(data_scrambled_s)
-);
+  assign ilas_monitor_reset_s = ~ifs_ready;
 
-pipeline_stage #(
-  .WIDTH(1 + DATA_PATH_WIDTH * 8),
-  .REGISTERED(SCRAMBLER_REGISTERED)
-) i_pipeline_stage2 (
-  .clk(clk),
-  .in({
-      buffer_ready_n_s,
-      data_scrambled_s
-    }),
-  .out({
-      buffer_ready_n,
-      data_scrambled
-    })
-);
+  pipeline_stage #(
+    .WIDTH(1 + DATA_PATH_WIDTH * (8 + 1)),
+    .REGISTERED(ALIGN_MUX_REGISTERED)
+  ) i_pipeline_stage1 (
+    .clk(clk),
+    .in({
+        ilas_monitor_reset_s,
+        data_aligned_s,
+        charisk28_aligned_s
+      }),
+    .out({
+        ilas_monitor_reset,
+        data_aligned,
+        charisk28_aligned
+      }));
 
-elastic_buffer #(
-  .IWIDTH(DATA_PATH_WIDTH*8),
-  .OWIDTH(TPL_DATA_PATH_WIDTH*8),
-  .SIZE(ELASTIC_BUFFER_SIZE),
-  .ASYNC_CLK(ASYNC_CLK)
-) i_elastic_buffer (
-  .clk(clk),
-  .reset(reset),
+  generate
+  if (ENABLE_FRAME_ALIGN_CHECK) begin : gen_frame_align
+  jesd204_rx_frame_align #(
+    .DATA_PATH_WIDTH (DATA_PATH_WIDTH),
+    .ENABLE_CHAR_REPLACE (ENABLE_CHAR_REPLACE)
+  ) i_frame_align (
+    .clk                          (clk),
+    .reset                        (buffer_ready_n_s),
+    .cfg_octets_per_multiframe    (cfg_octets_per_multiframe),
+    .cfg_octets_per_frame         (cfg_octets_per_frame),
+    .cfg_disable_char_replacement (cfg_disable_char_replacement),
+    .cfg_disable_scrambler        (cfg_disable_scrambler),
+    .charisk28                    (charisk28_aligned),
+    .data                         (data_aligned),
+    .data_replaced                (data_replaced),
+    .align_err_cnt                (status_frame_align_err_cnt));
 
-  .device_clk(device_clk),
-  .device_reset(device_reset),
+  end else begin : gen_no_frame_align_monitor
+    assign status_frame_align_err_cnt = 32'd0;
+    assign data_replaced = data_aligned;
+  end
+  endgenerate
 
-  .wr_data(data_scrambled),
-  .rd_data(rx_data),
+  jesd204_scrambler #(
+    .WIDTH(DATA_PATH_WIDTH*8),
+    .DESCRAMBLE(1)
+  ) i_descrambler (
+    .clk(clk),
+    .reset(buffer_ready_n_s),
+    .enable(~cfg_disable_scrambler),
+    .data_in(data_replaced),
+    .data_out(data_scrambled_s));
 
-  .ready_n(buffer_ready_n),
-  .do_release_n(buffer_release_n)
-);
+  pipeline_stage #(
+    .WIDTH(1 + DATA_PATH_WIDTH * 8),
+    .REGISTERED(SCRAMBLER_REGISTERED)
+  ) i_pipeline_stage2 (
+    .clk(clk),
+    .in({
+        buffer_ready_n_s,
+        data_scrambled_s
+      }),
+    .out({
+        buffer_ready_n,
+        data_scrambled
+      }));
 
-jesd204_ilas_monitor #(
-  .DATA_PATH_WIDTH(DATA_PATH_WIDTH)
-) i_ilas_monitor (
-  .clk(clk),
-  .reset(ilas_monitor_reset),
-  .cfg_octets_per_multiframe(cfg_octets_per_multiframe),
-  .data(data_aligned),
-  .charisk28(charisk28_aligned),
+  elastic_buffer #(
+    .IWIDTH(DATA_PATH_WIDTH*8),
+    .OWIDTH(TPL_DATA_PATH_WIDTH*8),
+    .SIZE(ELASTIC_BUFFER_SIZE),
+    .ASYNC_CLK(ASYNC_CLK)
+  ) i_elastic_buffer (
+    .clk(clk),
+    .reset(reset),
 
-  .data_ready_n(buffer_ready_n_s),
+    .device_clk(device_clk),
+    .device_reset(device_reset),
 
-  .ilas_config_valid(ilas_config_valid),
-  .ilas_config_addr(ilas_config_addr),
-  .ilas_config_data(ilas_config_data)
-);
+    .wr_data(data_scrambled),
+    .rd_data(rx_data),
 
-jesd204_rx_cgs #(
-  .DATA_PATH_WIDTH(DATA_PATH_WIDTH)
-) i_cgs (
-  .clk(clk),
-  .reset(cgs_reset),
+    .ready_n(buffer_ready_n),
+    .do_release_n(buffer_release_n));
 
-  .char_is_cgs(char_is_cgs),
-  .char_is_error(char_is_error),
+  jesd204_ilas_monitor #(
+    .DATA_PATH_WIDTH(DATA_PATH_WIDTH)
+  ) i_ilas_monitor (
+    .clk(clk),
+    .reset(ilas_monitor_reset),
+    .cfg_octets_per_multiframe(cfg_octets_per_multiframe),
+    .data(data_aligned),
+    .charisk28(charisk28_aligned),
 
-  .ready(cgs_ready),
+    .data_ready_n(buffer_ready_n_s),
 
-  .status_state(status_cgs_state)
-);
+    .ilas_config_valid(ilas_config_valid),
+    .ilas_config_addr(ilas_config_addr),
+    .ilas_config_data(ilas_config_data));
+
+  jesd204_rx_cgs #(
+    .DATA_PATH_WIDTH(DATA_PATH_WIDTH)
+  ) i_cgs (
+    .clk(clk),
+    .reset(cgs_reset),
+
+    .char_is_cgs(char_is_cgs),
+    .char_is_error(char_is_error),
+
+    .ready(cgs_ready),
+
+    .status_state(status_cgs_state));
 
 endmodule
diff --git a/library/jesd204/jesd204_rx/jesd204_rx_lane_64b.v b/library/jesd204/jesd204_rx/jesd204_rx_lane_64b.v
index 4ac205a49..17736d940 100644
--- a/library/jesd204/jesd204_rx/jesd204_rx_lane_64b.v
+++ b/library/jesd204/jesd204_rx/jesd204_rx_lane_64b.v
@@ -81,181 +81,172 @@ module jesd204_rx_lane_64b #(
   output reg [7:0] status_lane_skew
 );
 
-reg [11:0] crc12_calculated_prev;
+  reg [11:0] crc12_calculated_prev;
 
-wire [63:0] data_descrambled_s;
-wire [63:0] data_descrambled;
-wire [63:0] data_descrambled_reordered;
-wire [11:0] crc12_received;
-wire [11:0] crc12_calculated;
+  wire [63:0] data_descrambled_s;
+  wire [63:0] data_descrambled;
+  wire [63:0] data_descrambled_reordered;
+  wire [11:0] crc12_received;
+  wire [11:0] crc12_calculated;
 
-wire event_invalid_header;
-wire event_unexpected_eomb;
-wire event_unexpected_eoemb;
-wire event_crc12_mismatch;
-wire err_cnt_rst;
+  wire event_invalid_header;
+  wire event_unexpected_eomb;
+  wire event_unexpected_eoemb;
+  wire event_crc12_mismatch;
+  wire err_cnt_rst;
 
-wire [63:0] rx_data_msb_s;
+  wire [63:0] rx_data_msb_s;
 
-wire eomb;
-wire eoemb;
+  wire eomb;
+  wire eoemb;
 
-wire [7:0] sh_count;
+  wire [7:0] sh_count;
 
-jesd204_rx_header i_rx_header (
-  .clk(clk),
-  .reset(reset),
+  jesd204_rx_header i_rx_header (
+    .clk(clk),
+    .reset(reset),
 
-  .sh_lock(phy_block_sync),
-  .header(phy_header),
+    .sh_lock(phy_block_sync),
+    .header(phy_header),
 
-  .cfg_header_mode(cfg_header_mode),
-  .cfg_rx_thresh_emb_err(cfg_rx_thresh_emb_err),
-  .cfg_beats_per_multiframe(cfg_beats_per_multiframe),
+    .cfg_header_mode(cfg_header_mode),
+    .cfg_rx_thresh_emb_err(cfg_rx_thresh_emb_err),
+    .cfg_beats_per_multiframe(cfg_beats_per_multiframe),
 
-  .emb_lock(emb_lock),
+    .emb_lock(emb_lock),
 
-  .valid_eomb(eomb),
-  .valid_eoemb(eoemb),
-  .crc12(crc12_received),
-  .crc3(),
-  .fec(),
-  .cmd(),
-  .sh_count(sh_count),
+    .valid_eomb(eomb),
+    .valid_eoemb(eoemb),
+    .crc12(crc12_received),
+    .crc3(),
+    .fec(),
+    .cmd(),
+    .sh_count(sh_count),
 
-  .status_lane_emb_state(status_lane_emb_state),
-  .event_invalid_header(event_invalid_header),
-  .event_unexpected_eomb(event_unexpected_eomb),
-  .event_unexpected_eoemb(event_unexpected_eoemb)
-);
+    .status_lane_emb_state(status_lane_emb_state),
+    .event_invalid_header(event_invalid_header),
+    .event_unexpected_eomb(event_unexpected_eomb),
+    .event_unexpected_eoemb(event_unexpected_eoemb));
 
-jesd204_crc12 i_crc12 (
-  .clk(clk),
-  .reset(1'b0),
-  .init(eomb),
-  .data_in(phy_data),
-  .crc12(crc12_calculated)
-);
+  jesd204_crc12 i_crc12 (
+    .clk(clk),
+    .reset(1'b0),
+    .init(eomb),
+    .data_in(phy_data),
+    .crc12(crc12_calculated));
 
-reg crc12_on = 'b0;
-always @(posedge clk) begin
-  if (reset == 1'b1) begin
-    crc12_on <= 1'b0;
-  end else if (eomb) begin
-    crc12_on <= 1'b1;
+  reg crc12_on = 'b0;
+  always @(posedge clk) begin
+    if (reset == 1'b1) begin
+      crc12_on <= 1'b0;
+    end else if (eomb) begin
+      crc12_on <= 1'b1;
+    end
   end
-end
 
-reg crc12_rdy = 'b0;
-always @(posedge clk) begin
-  if (reset == 1'b1) begin
-    crc12_rdy <= 1'b0;
-  end else if (crc12_on && eomb) begin
-    crc12_rdy <= 1'b1;
+  reg crc12_rdy = 'b0;
+  always @(posedge clk) begin
+    if (reset == 1'b1) begin
+      crc12_rdy <= 1'b0;
+    end else if (crc12_on && eomb) begin
+      crc12_rdy <= 1'b1;
+    end
   end
-end
 
-always @(posedge clk) begin
-  if (eomb) begin
-    crc12_calculated_prev <= crc12_calculated;
+  always @(posedge clk) begin
+    if (eomb) begin
+      crc12_calculated_prev <= crc12_calculated;
+    end
   end
-end
 
-assign event_crc12_mismatch = crc12_rdy && eomb && (crc12_calculated_prev != crc12_received);
+  assign event_crc12_mismatch = crc12_rdy && eomb && (crc12_calculated_prev != crc12_received);
 
-assign err_cnt_rst = reset || ctrl_err_statistics_reset;
+  assign err_cnt_rst = reset || ctrl_err_statistics_reset;
 
-error_monitor #(
-  .EVENT_WIDTH(4),
-  .CNT_WIDTH(32)
-) i_error_monitor (
-  .clk(clk),
-  .reset(err_cnt_rst),
-  .active(1'b1),
-  .error_event({
-    event_invalid_header,
-    event_unexpected_eomb,
-    event_unexpected_eoemb,
-    event_crc12_mismatch
-  }),
-  .error_event_mask(ctrl_err_statistics_mask),
-  .status_err_cnt(status_err_statistics_cnt)
-);
-
-jesd204_scrambler_64b #(
-  .WIDTH(64),
-  .DESCRAMBLE(1)
-) i_descrambler (
-  .clk(clk),
-  .reset(1'b0),
-  .enable(~cfg_disable_scrambler),
-  .data_in(phy_data),
-  .data_out(data_descrambled_s)
-);
-
-pipeline_stage #(
-  .WIDTH(64),
-  .REGISTERED(1)
-) i_pipeline_stage2 (
-  .clk(clk),
-  .in({
-      data_descrambled_s
+  error_monitor #(
+    .EVENT_WIDTH(4),
+    .CNT_WIDTH(32)
+  ) i_error_monitor (
+    .clk(clk),
+    .reset(err_cnt_rst),
+    .active(1'b1),
+    .error_event({
+      event_invalid_header,
+      event_unexpected_eomb,
+      event_unexpected_eoemb,
+      event_crc12_mismatch
     }),
-  .out({
-      data_descrambled
-    })
-);
+    .error_event_mask(ctrl_err_statistics_mask),
+    .status_err_cnt(status_err_statistics_cnt));
 
-// Control when data is written to the elastic buffer
-// Start writing to the buffer when current lane is multiblock locked, but if
-// other lanes are not writing in the next half multiblock period stop
-// writing.
-// This limits the supported lane skew to half of the multiframe
-always @(posedge clk) begin
-  if (reset | ~emb_lock) begin
-    buffer_ready_n <= 1'b1;
-  end else if (sh_count == {1'b0,cfg_beats_per_multiframe[7:1]} && all_buffer_ready_n) begin
-    buffer_ready_n <= 1'b1;
-  end else if (eoemb) begin
-    buffer_ready_n <= 1'b0;
+  jesd204_scrambler_64b #(
+    .WIDTH(64),
+    .DESCRAMBLE(1)
+  ) i_descrambler (
+    .clk(clk),
+    .reset(1'b0),
+    .enable(~cfg_disable_scrambler),
+    .data_in(phy_data),
+    .data_out(data_descrambled_s));
+
+  pipeline_stage #(
+    .WIDTH(64),
+    .REGISTERED(1)
+  ) i_pipeline_stage2 (
+    .clk(clk),
+    .in({
+        data_descrambled_s
+      }),
+    .out({
+        data_descrambled
+      }));
+
+  // Control when data is written to the elastic buffer
+  // Start writing to the buffer when current lane is multiblock locked, but if
+  // other lanes are not writing in the next half multiblock period stop
+  // writing.
+  // This limits the supported lane skew to half of the multiframe
+  always @(posedge clk) begin
+    if (reset | ~emb_lock) begin
+      buffer_ready_n <= 1'b1;
+    end else if (sh_count == {1'b0,cfg_beats_per_multiframe[7:1]} && all_buffer_ready_n) begin
+      buffer_ready_n <= 1'b1;
+    end else if (eoemb) begin
+      buffer_ready_n <= 1'b0;
+    end
   end
-end
 
+  elastic_buffer #(
+    .IWIDTH(64),
+    .OWIDTH(TPL_DATA_PATH_WIDTH*8),
+    .SIZE(ELASTIC_BUFFER_SIZE),
+    .ASYNC_CLK(ASYNC_CLK)
+  ) i_elastic_buffer (
+    .clk(clk),
+    .reset(reset),
 
-elastic_buffer #(
-  .IWIDTH(64),
-  .OWIDTH(TPL_DATA_PATH_WIDTH*8),
-  .SIZE(ELASTIC_BUFFER_SIZE),
-  .ASYNC_CLK(ASYNC_CLK)
-) i_elastic_buffer (
-  .clk(clk),
-  .reset(reset),
+    .device_clk(device_clk),
+    .device_reset(device_reset),
 
-  .device_clk(device_clk),
-  .device_reset(device_reset),
+    .wr_data(data_descrambled_reordered),
+    .rd_data(rx_data),
 
-  .wr_data(data_descrambled_reordered),
-  .rd_data(rx_data),
+    .ready_n(buffer_ready_n),
+    .do_release_n(buffer_release_n));
 
-  .ready_n(buffer_ready_n),
-  .do_release_n(buffer_release_n)
-);
-
-// Measure the delay from the eoemb to the next LMFC edge.
-always @(posedge clk) begin
-  if (lmfc_edge) begin
-    status_lane_skew <= sh_count;
+  // Measure the delay from the eoemb to the next LMFC edge.
+  always @(posedge clk) begin
+    if (lmfc_edge) begin
+      status_lane_skew <= sh_count;
+    end
   end
-end
-
-
-/* Reorder octets LSB first */
-genvar i;
-generate
-  for (i = 0; i < 64; i = i + 8) begin: g_link_data
-    assign data_descrambled_reordered[i+:8] = data_descrambled[64-1-i-:8];
-  end
-endgenerate
 
+  /* Reorder octets LSB first */
+  genvar i;
+  generate
+    for (i = 0; i < 64; i = i + 8) begin: g_link_data
+      assign data_descrambled_reordered[i+:8] = data_descrambled[64-1-i-:8];
+    end
+  endgenerate
 
 endmodule
diff --git a/library/jesd204/jesd204_rx_static_config/jesd204_rx_static_config.v b/library/jesd204/jesd204_rx_static_config/jesd204_rx_static_config.v
index 34a479c3d..26e9256c5 100755
--- a/library/jesd204/jesd204_rx_static_config/jesd204_rx_static_config.v
+++ b/library/jesd204/jesd204_rx_static_config/jesd204_rx_static_config.v
@@ -78,21 +78,21 @@ module jesd204_rx_static_config #(
   output [7:0] device_cfg_buffer_delay
 );
 
-assign cfg_octets_per_multiframe = (FRAMES_PER_MULTIFRAME * OCTETS_PER_FRAME) - 1;
-assign cfg_octets_per_frame = OCTETS_PER_FRAME - 1;
-assign device_cfg_octets_per_multiframe = (FRAMES_PER_MULTIFRAME * OCTETS_PER_FRAME) - 1;
-assign device_cfg_octets_per_frame = OCTETS_PER_FRAME - 1;
-assign device_cfg_beats_per_multiframe = ((FRAMES_PER_MULTIFRAME * OCTETS_PER_FRAME) /
-                                          TPL_DATA_PATH_WIDTH) - 1;
-assign device_cfg_lmfc_offset = 1;
-assign device_cfg_sysref_oneshot = SYSREF_ONE_SHOT;
-assign device_cfg_sysref_disable = SYSREF_DISABLE;
-assign device_cfg_buffer_delay = 'h0;
-assign device_cfg_buffer_early_release = BUFFER_EARLY_RELEASE;
-assign cfg_lanes_disable = {NUM_LANES{1'b0}};
-assign cfg_links_disable = {NUM_LINKS{1'b0}};
-assign cfg_disable_scrambler = SCR ? 1'b0 : 1'b1;
-assign cfg_disable_char_replacement = 1'b0;
-assign cfg_frame_align_err_threshold = 8'd4;
+  assign cfg_octets_per_multiframe = (FRAMES_PER_MULTIFRAME * OCTETS_PER_FRAME) - 1;
+  assign cfg_octets_per_frame = OCTETS_PER_FRAME - 1;
+  assign device_cfg_octets_per_multiframe = (FRAMES_PER_MULTIFRAME * OCTETS_PER_FRAME) - 1;
+  assign device_cfg_octets_per_frame = OCTETS_PER_FRAME - 1;
+  assign device_cfg_beats_per_multiframe = ((FRAMES_PER_MULTIFRAME * OCTETS_PER_FRAME) /
+                                            TPL_DATA_PATH_WIDTH) - 1;
+  assign device_cfg_lmfc_offset = 1;
+  assign device_cfg_sysref_oneshot = SYSREF_ONE_SHOT;
+  assign device_cfg_sysref_disable = SYSREF_DISABLE;
+  assign device_cfg_buffer_delay = 'h0;
+  assign device_cfg_buffer_early_release = BUFFER_EARLY_RELEASE;
+  assign cfg_lanes_disable = {NUM_LANES{1'b0}};
+  assign cfg_links_disable = {NUM_LINKS{1'b0}};
+  assign cfg_disable_scrambler = SCR ? 1'b0 : 1'b1;
+  assign cfg_disable_char_replacement = 1'b0;
+  assign cfg_frame_align_err_threshold = 8'd4;
 
 endmodule
diff --git a/library/jesd204/jesd204_soft_pcs_rx/jesd204_8b10b_decoder.v b/library/jesd204/jesd204_soft_pcs_rx/jesd204_8b10b_decoder.v
index 2be7e40e5..745eab54d 100644
--- a/library/jesd204/jesd204_soft_pcs_rx/jesd204_8b10b_decoder.v
+++ b/library/jesd204/jesd204_soft_pcs_rx/jesd204_8b10b_decoder.v
@@ -55,362 +55,362 @@ module jesd204_8b10b_decoder (
   output reg out_disparity
 );
 
-/*
- * Only supports the subset of 8b10b that is used by JESD204.
- * If non-supported control characters are supplied the output is undefined.
- */
+  /*
+   * Only supports the subset of 8b10b that is used by JESD204.
+   * If non-supported control characters are supplied the output is undefined.
+   */
 
-reg [4:0] data5b;
-reg notintable5b;
-reg [1:0] disparity5b;
-reg ignore5b;
-reg [2:0] data3b;
-reg notintable3b;
-reg [1:0] disparity3b;
-reg ignore3b;
-reg [1:0] total_disparity;
-reg notintable_disparity;
+  reg [4:0] data5b;
+  reg notintable5b;
+  reg [1:0] disparity5b;
+  reg ignore5b;
+  reg [2:0] data3b;
+  reg notintable3b;
+  reg [1:0] disparity3b;
+  reg ignore3b;
+  reg [1:0] total_disparity;
+  reg notintable_disparity;
 
-// Only detect K28.X
-wire charisk = in_char[5:0] == 6'b000011 || in_char[5:0] == 6'b111100;
+  // Only detect K28.X
+  wire charisk = in_char[5:0] == 6'b000011 || in_char[5:0] == 6'b111100;
 
-always @(*) begin
-  notintable5b = 1'b0;
-  disparity5b = 2'b00;
-  ignore5b = 1'b0;
+  always @(*) begin
+    notintable5b = 1'b0;
+    disparity5b = 2'b00;
+    ignore5b = 1'b0;
 
-  case (in_char[5:0])
-  6'b000011: begin
-    data5b = 5'd28;
-    disparity5b = 2'b11;
-  end
-  6'b111100: begin
-    data5b = 5'd28;
-    disparity5b = 2'b01;
-  end
-  6'b000110: begin
-    data5b = 5'd00;
-    disparity5b = 2'b11;
-  end
-  6'b111001: begin
-    data5b = 5'd00;
-    disparity5b = 2'b01;
-  end
-  6'b010001: begin
-    data5b = 5'd01;
-    disparity5b = 2'b11;
-  end
-  6'b101110: begin
-    data5b = 5'd01;
-    disparity5b = 2'b01;
-  end
-  6'b010010: begin
-    data5b = 5'd02;
-    disparity5b = 2'b11;
-  end
-  6'b101101: begin
-    data5b = 5'd02;
-    disparity5b = 2'b01;
-  end
-  6'b100011: begin
-    data5b = 5'd03;
-  end
-  6'b010100: begin
-    data5b = 5'd04;
-    disparity5b = 2'b11;
-  end
-  6'b101011: begin
-    data5b = 5'd04;
-    disparity5b = 2'b01;
-  end
-  6'b100101: begin
-    data5b = 5'd05;
-  end
-  6'b100110: begin
-    data5b = 5'd06;
-  end
-  6'b000111: begin
-    data5b = 5'd7;
-    disparity5b = 2'b11;
-    ignore5b = 1'b1;
-  end
-  6'b111000: begin
-    data5b = 5'd7;
-    disparity5b = 2'b01;
-    ignore5b = 1'b1;
-  end
-  6'b011000: begin
-    data5b = 5'd8;
-    disparity5b = 2'b11;
-  end
-  6'b100111: begin
-    data5b = 5'd8;
-    disparity5b = 2'b01;
-  end
-  6'b101001: begin
-    data5b = 5'd9;
-  end
-  6'b101010: begin
-    data5b = 5'd10;
-  end
-  6'b001011: begin
-    data5b = 5'd11;
-  end
-  6'b101100: begin
-    data5b = 5'd12;
-  end
-  6'b001101: begin
-    data5b = 5'd13;
-  end
-  6'b001110: begin
-    data5b = 5'd14;
-  end
-  6'b000101: begin
-    data5b = 5'd15;
-    disparity5b = 2'b11;
-  end
-  6'b111010: begin
-    data5b = 5'd15;
-    disparity5b = 2'b01;
-  end
-  6'b001001: begin
-    data5b = 5'd16;
-    disparity5b = 2'b11;
-  end
-  6'b110110: begin
-    data5b = 5'd16;
-    disparity5b = 2'b01;
-  end
-  6'b110001: begin
-    data5b = 5'd17;
-  end
-  6'b110010: begin
-    data5b = 5'd18;
-  end
-  6'b010011: begin
-    data5b = 5'd19;
-  end
-  6'b110100: begin
-    data5b = 5'd20;
-  end
-  6'b010101: begin
-    data5b = 5'd21;
-  end
-  6'b010110: begin
-    data5b = 5'd22;
-  end
-  6'b101000: begin
-    data5b = 5'd23;
-    disparity5b = 2'b11;
-  end
-  6'b010111: begin
-    data5b = 5'd23;
-    disparity5b = 2'b01;
-  end
-  6'b001100: begin
-    data5b = 5'd24;
-    disparity5b = 2'b11;
-  end
-  6'b110011: begin
-    data5b = 5'd24;
-    disparity5b = 2'b01;
-  end
-  6'b011001: begin
-    data5b = 5'd25;
-  end
-  6'b011010: begin
-    data5b = 5'd26;
-  end
-  6'b100100: begin
-    data5b = 5'd27;
-    disparity5b = 2'b11;
-  end
-  6'b011011: begin
-    data5b = 5'd27;
-    disparity5b = 2'b01;
-  end
-  6'b011100: begin
-    data5b = 5'd28;
-  end
-  6'b100010: begin
-    data5b = 5'd29;
-    disparity5b = 2'b11;
-  end
-  6'b011101: begin
-    data5b = 5'd29;
-    disparity5b = 2'b01;
-  end
-  6'b100001: begin
-    data5b = 5'd30;
-    disparity5b = 2'b11;
-  end
-  6'b011110: begin
-    data5b = 5'd30;
-    disparity5b = 2'b01;
-  end
-  6'b001010: begin
-    data5b = 5'd31;
-    disparity5b = 2'b11;
-  end
-  6'b110101: begin
-    data5b = 5'd31;
-    disparity5b = 2'b01;
-  end
-  default: begin
-    data5b = 5'd00;
-    notintable5b = 1'b1;
-  end
-  endcase
-end
-
-always @(*) begin
-  ignore3b = 1'b0;
-
-  case (in_char[9:6])
-  4'b0010: begin
-    disparity3b = 2'b11;
-  end
-  4'b1101: begin
-    disparity3b = 2'b01;
-  end
-  4'b1100: begin
-    disparity3b = 2'b11;
-    ignore3b = 1'b1;
-  end
-  4'b0011: begin
-    disparity3b = 2'b01;
-    ignore3b = 1'b1;
-  end
-  4'b0100: begin
-    disparity3b = 2'b11;
-  end
-  4'b1011: begin
-    disparity3b = 2'b01;
-  end
-  4'b1000: begin
-    disparity3b = 2'b11;
-  end
-  4'b0111: begin
-    disparity3b = 2'b01;
-  end
-  4'b0001: begin
-    disparity3b = 2'b11;
-  end
-  4'b1110: begin
-    disparity3b = 2'b01;
-  end
-  default: begin
-    disparity3b = 2'b00;
-  end
-  endcase
-end
-
-always @(*) begin
-  notintable3b = 1'b0;
-
-  if (charisk == 1'b1) begin
-    case (in_char[9:6] ^ {4{in_char[5]}})
-    4'b1101: begin
-      data3b = 3'd0;
+    case (in_char[5:0])
+    6'b000011: begin
+      data5b = 5'd28;
+      disparity5b = 2'b11;
     end
-    4'b0011: begin
-      data3b = 3'd3;
+    6'b111100: begin
+      data5b = 5'd28;
+      disparity5b = 2'b01;
     end
-    4'b1011: begin
-      data3b = 3'd4;
+    6'b000110: begin
+      data5b = 5'd00;
+      disparity5b = 2'b11;
     end
-    4'b1010: begin
-      data3b = 3'd5;
+    6'b111001: begin
+      data5b = 5'd00;
+      disparity5b = 2'b01;
     end
-    4'b1110: begin
-      data3b = 3'd7;
+    6'b010001: begin
+      data5b = 5'd01;
+      disparity5b = 2'b11;
+    end
+    6'b101110: begin
+      data5b = 5'd01;
+      disparity5b = 2'b01;
+    end
+    6'b010010: begin
+      data5b = 5'd02;
+      disparity5b = 2'b11;
+    end
+    6'b101101: begin
+      data5b = 5'd02;
+      disparity5b = 2'b01;
+    end
+    6'b100011: begin
+      data5b = 5'd03;
+    end
+    6'b010100: begin
+      data5b = 5'd04;
+      disparity5b = 2'b11;
+    end
+    6'b101011: begin
+      data5b = 5'd04;
+      disparity5b = 2'b01;
+    end
+    6'b100101: begin
+      data5b = 5'd05;
+    end
+    6'b100110: begin
+      data5b = 5'd06;
+    end
+    6'b000111: begin
+      data5b = 5'd7;
+      disparity5b = 2'b11;
+      ignore5b = 1'b1;
+    end
+    6'b111000: begin
+      data5b = 5'd7;
+      disparity5b = 2'b01;
+      ignore5b = 1'b1;
+    end
+    6'b011000: begin
+      data5b = 5'd8;
+      disparity5b = 2'b11;
+    end
+    6'b100111: begin
+      data5b = 5'd8;
+      disparity5b = 2'b01;
+    end
+    6'b101001: begin
+      data5b = 5'd9;
+    end
+    6'b101010: begin
+      data5b = 5'd10;
+    end
+    6'b001011: begin
+      data5b = 5'd11;
+    end
+    6'b101100: begin
+      data5b = 5'd12;
+    end
+    6'b001101: begin
+      data5b = 5'd13;
+    end
+    6'b001110: begin
+      data5b = 5'd14;
+    end
+    6'b000101: begin
+      data5b = 5'd15;
+      disparity5b = 2'b11;
+    end
+    6'b111010: begin
+      data5b = 5'd15;
+      disparity5b = 2'b01;
+    end
+    6'b001001: begin
+      data5b = 5'd16;
+      disparity5b = 2'b11;
+    end
+    6'b110110: begin
+      data5b = 5'd16;
+      disparity5b = 2'b01;
+    end
+    6'b110001: begin
+      data5b = 5'd17;
+    end
+    6'b110010: begin
+      data5b = 5'd18;
+    end
+    6'b010011: begin
+      data5b = 5'd19;
+    end
+    6'b110100: begin
+      data5b = 5'd20;
+    end
+    6'b010101: begin
+      data5b = 5'd21;
+    end
+    6'b010110: begin
+      data5b = 5'd22;
+    end
+    6'b101000: begin
+      data5b = 5'd23;
+      disparity5b = 2'b11;
+    end
+    6'b010111: begin
+      data5b = 5'd23;
+      disparity5b = 2'b01;
+    end
+    6'b001100: begin
+      data5b = 5'd24;
+      disparity5b = 2'b11;
+    end
+    6'b110011: begin
+      data5b = 5'd24;
+      disparity5b = 2'b01;
+    end
+    6'b011001: begin
+      data5b = 5'd25;
+    end
+    6'b011010: begin
+      data5b = 5'd26;
+    end
+    6'b100100: begin
+      data5b = 5'd27;
+      disparity5b = 2'b11;
+    end
+    6'b011011: begin
+      data5b = 5'd27;
+      disparity5b = 2'b01;
+    end
+    6'b011100: begin
+      data5b = 5'd28;
+    end
+    6'b100010: begin
+      data5b = 5'd29;
+      disparity5b = 2'b11;
+    end
+    6'b011101: begin
+      data5b = 5'd29;
+      disparity5b = 2'b01;
+    end
+    6'b100001: begin
+      data5b = 5'd30;
+      disparity5b = 2'b11;
+    end
+    6'b011110: begin
+      data5b = 5'd30;
+      disparity5b = 2'b01;
+    end
+    6'b001010: begin
+      data5b = 5'd31;
+      disparity5b = 2'b11;
+    end
+    6'b110101: begin
+      data5b = 5'd31;
+      disparity5b = 2'b01;
     end
     default: begin
-      data3b = 3'd0;
-      notintable3b = 1'b1;
+      data5b = 5'd00;
+      notintable5b = 1'b1;
     end
     endcase
-  end else begin
+  end
+
+  always @(*) begin
+    ignore3b = 1'b0;
+
     case (in_char[9:6])
     4'b0010: begin
-      data3b = 3'd0;
+      disparity3b = 2'b11;
     end
     4'b1101: begin
-      data3b = 3'd0;
-    end
-    4'b1001: begin
-      data3b = 3'd1;
-    end
-    4'b1010: begin
-      data3b = 3'd2;
+      disparity3b = 2'b01;
     end
     4'b1100: begin
-      data3b = 3'd3;
+      disparity3b = 2'b11;
+      ignore3b = 1'b1;
     end
     4'b0011: begin
-      data3b = 3'd3;
+      disparity3b = 2'b01;
+      ignore3b = 1'b1;
     end
     4'b0100: begin
-      data3b = 3'd4;
+      disparity3b = 2'b11;
     end
     4'b1011: begin
-      data3b = 3'd4;
-    end
-    4'b0101: begin
-      data3b = 3'd5;
-    end
-    4'b0110: begin
-      data3b = 3'd6;
+      disparity3b = 2'b01;
     end
     4'b1000: begin
-      data3b = 3'd7;
-      notintable3b = in_char[5:4] == 2'b00;
+      disparity3b = 2'b11;
     end
     4'b0111: begin
-      data3b = 3'd7;
-      notintable3b = in_char[5:4] == 2'b11;
+      disparity3b = 2'b01;
     end
     4'b0001: begin
-      data3b = 3'd7;
-      notintable3b = in_char[5:4] != 2'b00;
+      disparity3b = 2'b11;
     end
     4'b1110: begin
-      data3b = 3'd7;
-      notintable3b = in_char[5:4] != 2'b11;
+      disparity3b = 2'b01;
     end
     default: begin
-      data3b = 3'd0;
-      notintable3b = 1'b1;
+      disparity3b = 2'b00;
     end
     endcase
   end
-end
 
-always @(*) begin
-  if (disparity3b == disparity5b && disparity3b != 2'b00) begin
-    notintable_disparity = 1'b1;
-  end else begin
-    notintable_disparity = 1'b0;
+  always @(*) begin
+    notintable3b = 1'b0;
+
+    if (charisk == 1'b1) begin
+      case (in_char[9:6] ^ {4{in_char[5]}})
+      4'b1101: begin
+        data3b = 3'd0;
+      end
+      4'b0011: begin
+        data3b = 3'd3;
+      end
+      4'b1011: begin
+        data3b = 3'd4;
+      end
+      4'b1010: begin
+        data3b = 3'd5;
+      end
+      4'b1110: begin
+        data3b = 3'd7;
+      end
+      default: begin
+        data3b = 3'd0;
+        notintable3b = 1'b1;
+      end
+      endcase
+    end else begin
+      case (in_char[9:6])
+      4'b0010: begin
+        data3b = 3'd0;
+      end
+      4'b1101: begin
+        data3b = 3'd0;
+      end
+      4'b1001: begin
+        data3b = 3'd1;
+      end
+      4'b1010: begin
+        data3b = 3'd2;
+      end
+      4'b1100: begin
+        data3b = 3'd3;
+      end
+      4'b0011: begin
+        data3b = 3'd3;
+      end
+      4'b0100: begin
+        data3b = 3'd4;
+      end
+      4'b1011: begin
+        data3b = 3'd4;
+      end
+      4'b0101: begin
+        data3b = 3'd5;
+      end
+      4'b0110: begin
+        data3b = 3'd6;
+      end
+      4'b1000: begin
+        data3b = 3'd7;
+        notintable3b = in_char[5:4] == 2'b00;
+      end
+      4'b0111: begin
+        data3b = 3'd7;
+        notintable3b = in_char[5:4] == 2'b11;
+      end
+      4'b0001: begin
+        data3b = 3'd7;
+        notintable3b = in_char[5:4] != 2'b00;
+      end
+      4'b1110: begin
+        data3b = 3'd7;
+        notintable3b = in_char[5:4] != 2'b11;
+      end
+      default: begin
+        data3b = 3'd0;
+        notintable3b = 1'b1;
+      end
+      endcase
+    end
   end
-end
 
-always @(*) begin
-  total_disparity = (ignore3b ? 2'b00 : disparity3b) ^ (ignore5b ? 2'b00 : disparity5b);
-
-  if (total_disparity[0] == 1'b0 || out_notintable == 1'b1) begin
-    out_disparity = in_disparity;
-    out_disperr = 1'b0;
-  end else if (total_disparity[1] == 1'b1) begin
-    out_disparity = 1'b0;
-    out_disperr = ~in_disparity;
-  end else begin
-    out_disparity = 1'b1;
-    out_disperr = in_disparity;
+  always @(*) begin
+    if (disparity3b == disparity5b && disparity3b != 2'b00) begin
+      notintable_disparity = 1'b1;
+    end else begin
+      notintable_disparity = 1'b0;
+    end
   end
-end
 
-assign out_char = {data3b,data5b};
-assign out_charisk = charisk;
-assign out_notintable = notintable5b | notintable3b | notintable_disparity;
+  always @(*) begin
+    total_disparity = (ignore3b ? 2'b00 : disparity3b) ^ (ignore5b ? 2'b00 : disparity5b);
+
+    if (total_disparity[0] == 1'b0 || out_notintable == 1'b1) begin
+      out_disparity = in_disparity;
+      out_disperr = 1'b0;
+    end else if (total_disparity[1] == 1'b1) begin
+      out_disparity = 1'b0;
+      out_disperr = ~in_disparity;
+    end else begin
+      out_disparity = 1'b1;
+      out_disperr = in_disparity;
+    end
+  end
+
+  assign out_char = {data3b,data5b};
+  assign out_charisk = charisk;
+  assign out_notintable = notintable5b | notintable3b | notintable_disparity;
 
 endmodule
diff --git a/library/jesd204/jesd204_soft_pcs_rx/jesd204_pattern_align.v b/library/jesd204/jesd204_soft_pcs_rx/jesd204_pattern_align.v
index d2d77cedc..48ea174d1 100644
--- a/library/jesd204/jesd204_soft_pcs_rx/jesd204_pattern_align.v
+++ b/library/jesd204/jesd204_soft_pcs_rx/jesd204_pattern_align.v
@@ -56,100 +56,100 @@ module jesd204_pattern_align #(
   output [DATA_PATH_WIDTH*10-1:0] out_data
 );
 
-localparam [9:0] PATTERN_P = 10'b1010000011;
-localparam [9:0] PATTERN_N = 10'b0101111100;
+  localparam [9:0] PATTERN_P = 10'b1010000011;
+  localparam [9:0] PATTERN_N = 10'b0101111100;
 
-reg [1:0] match_counter = 2'h0;
-reg pattern_sync = 1'b0;
-reg pattern_match = 1'b0;
+  reg [1:0] match_counter = 2'h0;
+  reg pattern_sync = 1'b0;
+  reg pattern_match = 1'b0;
 
-reg [3:0] align = 4'h0;
-reg [1:0] cooldown = 2'h3;
+  reg [3:0] align = 4'h0;
+  reg [1:0] cooldown = 2'h3;
 
-reg [8:0] data_d1 = 9'h00;
-reg [DATA_PATH_WIDTH*10+2:0] aligned_data_stage1;
-reg [DATA_PATH_WIDTH*10-1:0] aligned_data_stage2;
-wire [(DATA_PATH_WIDTH+1)*10-2:0] full_data;
+  reg [8:0] data_d1 = 9'h00;
+  reg [DATA_PATH_WIDTH*10+2:0] aligned_data_stage1;
+  reg [DATA_PATH_WIDTH*10-1:0] aligned_data_stage2;
+  wire [(DATA_PATH_WIDTH+1)*10-2:0] full_data;
 
-assign full_data = {in_data,data_d1};
-assign out_data = aligned_data_stage2;
+  assign full_data = {in_data,data_d1};
+  assign out_data = aligned_data_stage2;
 
-/* 2-stage cascade of 3:1 and 4:1 muxes */
+  /* 2-stage cascade of 3:1 and 4:1 muxes */
 
-integer i;
+  integer i;
 
-always @(*) begin
-  for (i = 0; i < DATA_PATH_WIDTH*10+3; i = i + 1) begin
-    if (i < DATA_PATH_WIDTH*10+1) begin
-      case (align[3:2])
-      2'b00: aligned_data_stage1[i] = full_data[i];
-      2'b01: aligned_data_stage1[i] = full_data[i+4];
-      2'b10: aligned_data_stage1[i] = full_data[i+8];
-      default: aligned_data_stage1[i] = 1'b0;
-      endcase
-    end else begin
-      case (align[2])
-      1'b0: aligned_data_stage1[i] = full_data[i];
-      default: aligned_data_stage1[i] = full_data[i+4];
-      endcase
-    end
-  end
-
-  aligned_data_stage2 = aligned_data_stage1[align[1:0]+:DATA_PATH_WIDTH*10];
-end
-
-always @(posedge clk) begin
-  data_d1 <= in_data[DATA_PATH_WIDTH*10-9+:9];
-end
-
-always @(posedge clk) begin
-  if (out_data[9:0] == PATTERN_P || out_data[9:0] == PATTERN_N) begin
-    pattern_match <= 1'b1;
-  end else begin
-    pattern_match <= 1'b0;
-  end
-end
-
-always @(posedge clk) begin
-  if (reset == 1'b1) begin
-    cooldown <= 2'h3;
-    align <= 4'h0;
-  end else begin
-    if (cooldown != 2'h0) begin
-      cooldown <= cooldown - 1'b1;
-    end else if (patternalign_en == 1'b1 && pattern_sync == 1'b0 &&
-                 pattern_match == 1'b0) begin
-      cooldown <= 2'h3;
-      if (align == 'h9) begin
-        align <= 4'h0;
+  always @(*) begin
+    for (i = 0; i < DATA_PATH_WIDTH*10+3; i = i + 1) begin
+      if (i < DATA_PATH_WIDTH*10+1) begin
+        case (align[3:2])
+        2'b00: aligned_data_stage1[i] = full_data[i];
+        2'b01: aligned_data_stage1[i] = full_data[i+4];
+        2'b10: aligned_data_stage1[i] = full_data[i+8];
+        default: aligned_data_stage1[i] = 1'b0;
+        endcase
       end else begin
-        align <= align + 1'b1;
+        case (align[2])
+        1'b0: aligned_data_stage1[i] = full_data[i];
+        default: aligned_data_stage1[i] = full_data[i+4];
+        endcase
       end
     end
+
+    aligned_data_stage2 = aligned_data_stage1[align[1:0]+:DATA_PATH_WIDTH*10];
   end
-end
 
-always @(posedge clk) begin
-  if (reset == 1'b1) begin
-    pattern_sync <= 1'b0;
-    match_counter <= 2'h0;
-  end else begin
-    if (match_counter == 2'h0) begin
-      pattern_sync <= 1'b0;
-    end else if (match_counter == 2'h3) begin
-      pattern_sync <= 1'b1;
-    end
+  always @(posedge clk) begin
+    data_d1 <= in_data[DATA_PATH_WIDTH*10-9+:9];
+  end
 
-    if (pattern_match == 1'b1) begin
-      if (match_counter != 2'h3) begin
-        match_counter <= match_counter + 1'b1;
-      end
+  always @(posedge clk) begin
+    if (out_data[9:0] == PATTERN_P || out_data[9:0] == PATTERN_N) begin
+      pattern_match <= 1'b1;
     end else begin
-      if (match_counter != 2'h0) begin
-        match_counter <= match_counter - 1'b1;
+      pattern_match <= 1'b0;
+    end
+  end
+
+  always @(posedge clk) begin
+    if (reset == 1'b1) begin
+      cooldown <= 2'h3;
+      align <= 4'h0;
+    end else begin
+      if (cooldown != 2'h0) begin
+        cooldown <= cooldown - 1'b1;
+      end else if (patternalign_en == 1'b1 && pattern_sync == 1'b0 &&
+                   pattern_match == 1'b0) begin
+        cooldown <= 2'h3;
+        if (align == 'h9) begin
+          align <= 4'h0;
+        end else begin
+          align <= align + 1'b1;
+        end
+      end
+    end
+  end
+
+  always @(posedge clk) begin
+    if (reset == 1'b1) begin
+      pattern_sync <= 1'b0;
+      match_counter <= 2'h0;
+    end else begin
+      if (match_counter == 2'h0) begin
+        pattern_sync <= 1'b0;
+      end else if (match_counter == 2'h3) begin
+        pattern_sync <= 1'b1;
+      end
+
+      if (pattern_match == 1'b1) begin
+        if (match_counter != 2'h3) begin
+          match_counter <= match_counter + 1'b1;
+        end
+      end else begin
+        if (match_counter != 2'h0) begin
+          match_counter <= match_counter - 1'b1;
+        end
       end
     end
   end
-end
 
 endmodule
diff --git a/library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx.v b/library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx.v
index 4fff3477f..b803904c9 100644
--- a/library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx.v
+++ b/library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx.v
@@ -50,108 +50,106 @@ module jesd204_soft_pcs_rx #(
   parameter REGISTER_INPUTS = 0,
   parameter INVERT_INPUTS = 0
 ) (
-   input clk,
-   input reset,
+  input clk,
+  input reset,
 
-   input patternalign_en,
+  input patternalign_en,
 
-   input [NUM_LANES*DATA_PATH_WIDTH*10-1:0] data,
+  input [NUM_LANES*DATA_PATH_WIDTH*10-1:0] data,
 
-   output reg [NUM_LANES*DATA_PATH_WIDTH*8-1:0] char,
-   output reg [NUM_LANES*DATA_PATH_WIDTH-1:0] charisk,
-   output reg [NUM_LANES*DATA_PATH_WIDTH-1:0] notintable,
-   output reg [NUM_LANES*DATA_PATH_WIDTH-1:0] disperr
+  output reg [NUM_LANES*DATA_PATH_WIDTH*8-1:0] char,
+  output reg [NUM_LANES*DATA_PATH_WIDTH-1:0] charisk,
+  output reg [NUM_LANES*DATA_PATH_WIDTH-1:0] notintable,
+  output reg [NUM_LANES*DATA_PATH_WIDTH-1:0] disperr
 );
 
-localparam LANE_DATA_WIDTH = DATA_PATH_WIDTH * 10;
+  localparam LANE_DATA_WIDTH = DATA_PATH_WIDTH * 10;
 
-wire [NUM_LANES*LANE_DATA_WIDTH-1:0] data_aligned;
+  wire [NUM_LANES*LANE_DATA_WIDTH-1:0] data_aligned;
 
-wire [NUM_LANES*DATA_PATH_WIDTH*8-1:0] char_s;
-wire [NUM_LANES*DATA_PATH_WIDTH-1:0] charisk_s;
-wire [NUM_LANES*DATA_PATH_WIDTH-1:0] notintable_s;
-wire [NUM_LANES*DATA_PATH_WIDTH-1:0] disperr_s;
+  wire [NUM_LANES*DATA_PATH_WIDTH*8-1:0] char_s;
+  wire [NUM_LANES*DATA_PATH_WIDTH-1:0] charisk_s;
+  wire [NUM_LANES*DATA_PATH_WIDTH-1:0] notintable_s;
+  wire [NUM_LANES*DATA_PATH_WIDTH-1:0] disperr_s;
 
-reg [NUM_LANES-1:0] disparity = {NUM_LANES{1'b0}};
-wire [DATA_PATH_WIDTH:0] disparity_chain[0:NUM_LANES-1];
+  reg [NUM_LANES-1:0] disparity = {NUM_LANES{1'b0}};
+  wire [DATA_PATH_WIDTH:0] disparity_chain[0:NUM_LANES-1];
 
-wire [NUM_LANES*DATA_PATH_WIDTH*10-1:0] data_s;
-wire patternalign_en_s;
+  wire [NUM_LANES*DATA_PATH_WIDTH*10-1:0] data_s;
+  wire patternalign_en_s;
 
-always @(posedge clk) begin
-  char <= char_s;
-  charisk <= charisk_s;
-  notintable <= notintable_s;
-  disperr <= disperr_s;
-end
-
-generate
-genvar lane;
-genvar i;
-if (REGISTER_INPUTS > 0) begin
-  reg                                     patternalign_en_r;
-  reg [NUM_LANES*DATA_PATH_WIDTH*10-1:0]  data_r;
   always @(posedge clk) begin
-    patternalign_en_r <= patternalign_en;
-    data_r  <= data;
+    char <= char_s;
+    charisk <= charisk_s;
+    notintable <= notintable_s;
+    disperr <= disperr_s;
   end
-  assign patternalign_en_s = patternalign_en_r;
-  assign data_s = data_r;
-end else begin
-  assign patternalign_en_s = patternalign_en;
-  assign data_s = data;
-end
 
-for (lane = 0; lane < NUM_LANES; lane = lane + 1) begin: gen_lane
-
-  jesd204_pattern_align #(
-    .DATA_PATH_WIDTH(DATA_PATH_WIDTH)
-  ) i_pattern_align (
-    .clk(clk),
-    .reset(reset),
-
-    .patternalign_en(patternalign_en_s),
-    .in_data(data_s[LANE_DATA_WIDTH*lane+:LANE_DATA_WIDTH]),
-    .out_data(data_aligned[LANE_DATA_WIDTH*lane+:LANE_DATA_WIDTH])
-  );
-
-  assign disparity_chain[lane][0] = disparity[lane];
-
-  always @(posedge clk) begin
-    if (reset == 1'b1) begin
-      disparity[lane] <= 1'b0;
-    end else begin
-      disparity[lane] <= disparity_chain[lane][DATA_PATH_WIDTH];
+  generate
+  genvar lane;
+  genvar i;
+  if (REGISTER_INPUTS > 0) begin
+    reg                                     patternalign_en_r;
+    reg [NUM_LANES*DATA_PATH_WIDTH*10-1:0]  data_r;
+    always @(posedge clk) begin
+      patternalign_en_r <= patternalign_en;
+      data_r  <= data;
     end
+    assign patternalign_en_s = patternalign_en_r;
+    assign data_s = data_r;
+  end else begin
+    assign patternalign_en_s = patternalign_en;
+    assign data_s = data;
   end
 
-  for (i = 0; i < DATA_PATH_WIDTH; i = i + 1) begin: gen_dpw
-    localparam j = DATA_PATH_WIDTH * lane + i;
-    wire [9:0] in_char;
-    if (REGISTER_INPUTS > 1) begin
-      reg [9:0] in_char_r = 10'b0;
-      always @(posedge clk) begin
-        in_char_r <= INVERT_INPUTS ? ~data_aligned[j*10+:10] :
-                                      data_aligned[j*10+:10];
+  for (lane = 0; lane < NUM_LANES; lane = lane + 1) begin: gen_lane
+
+    jesd204_pattern_align #(
+      .DATA_PATH_WIDTH(DATA_PATH_WIDTH)
+    ) i_pattern_align (
+      .clk(clk),
+      .reset(reset),
+
+      .patternalign_en(patternalign_en_s),
+      .in_data(data_s[LANE_DATA_WIDTH*lane+:LANE_DATA_WIDTH]),
+      .out_data(data_aligned[LANE_DATA_WIDTH*lane+:LANE_DATA_WIDTH]));
+
+    assign disparity_chain[lane][0] = disparity[lane];
+
+    always @(posedge clk) begin
+      if (reset == 1'b1) begin
+        disparity[lane] <= 1'b0;
+      end else begin
+        disparity[lane] <= disparity_chain[lane][DATA_PATH_WIDTH];
       end
-      assign in_char = in_char_r;
-    end else begin
-      assign in_char = INVERT_INPUTS ? ~data_aligned[j*10+:10] :
-                                        data_aligned[j*10+:10];
     end
 
-    jesd204_8b10b_decoder i_dec (
-      .in_char(in_char),
-      .out_char(char_s[j*8+:8]),
-      .out_charisk(charisk_s[j]),
-      .out_notintable(notintable_s[j]),
-      .out_disperr(disperr_s[j]),
+    for (i = 0; i < DATA_PATH_WIDTH; i = i + 1) begin: gen_dpw
+      localparam j = DATA_PATH_WIDTH * lane + i;
+      wire [9:0] in_char;
+      if (REGISTER_INPUTS > 1) begin
+        reg [9:0] in_char_r = 10'b0;
+        always @(posedge clk) begin
+          in_char_r <= INVERT_INPUTS ? ~data_aligned[j*10+:10] :
+                                        data_aligned[j*10+:10];
+        end
+        assign in_char = in_char_r;
+      end else begin
+        assign in_char = INVERT_INPUTS ? ~data_aligned[j*10+:10] :
+                                          data_aligned[j*10+:10];
+      end
 
-      .in_disparity(disparity_chain[lane][i]),
-      .out_disparity(disparity_chain[lane][i+1])
-    );
+      jesd204_8b10b_decoder i_dec (
+        .in_char(in_char),
+        .out_char(char_s[j*8+:8]),
+        .out_charisk(charisk_s[j]),
+        .out_notintable(notintable_s[j]),
+        .out_disperr(disperr_s[j]),
+
+        .in_disparity(disparity_chain[lane][i]),
+        .out_disparity(disparity_chain[lane][i+1]));
+    end
   end
-end
-endgenerate
+  endgenerate
 
 endmodule
diff --git a/library/jesd204/jesd204_soft_pcs_tx/jesd204_8b10b_encoder.v b/library/jesd204/jesd204_soft_pcs_tx/jesd204_8b10b_encoder.v
index e52bef321..eb0e9e707 100644
--- a/library/jesd204/jesd204_soft_pcs_tx/jesd204_8b10b_encoder.v
+++ b/library/jesd204/jesd204_soft_pcs_tx/jesd204_8b10b_encoder.v
@@ -53,278 +53,278 @@ module jesd204_8b10b_encoder (
   output out_disparity
 );
 
-/*
- * Only supports the subset of 8b10b that is used by JESD204.
- * If non-supported control characters are supplied the output is undefined.
- */
+  /*
+   * Only supports the subset of 8b10b that is used by JESD204.
+   * If non-supported control characters are supplied the output is undefined.
+   */
 
-reg [5:0] data6b;
-reg [5:0] out6b;
-reg may_invert6b;
-reg disparity6b;
-reg [3:0] data4b;
-reg [3:0] out4b;
-reg may_invert4b;
-reg disparity4b;
-wire disparity4b_in;
-reg alt7;
+  reg [5:0] data6b;
+  reg [5:0] out6b;
+  reg may_invert6b;
+  reg disparity6b;
+  reg [3:0] data4b;
+  reg [3:0] out4b;
+  reg may_invert4b;
+  reg disparity4b;
+  wire disparity4b_in;
+  reg alt7;
 
-always @(*) begin
-  if (in_charisk == 1'b1) begin
-    // Assume K28.x
-    data6b = 6'b000011;
-    may_invert6b = 1'b1;
-    disparity6b = 1'b1;
-  end else begin
-    case (in_char[4:0])
-    5'd00: begin
-      data6b = 6'b000110;
+  always @(*) begin
+    if (in_charisk == 1'b1) begin
+      // Assume K28.x
+      data6b = 6'b000011;
       may_invert6b = 1'b1;
       disparity6b = 1'b1;
+    end else begin
+      case (in_char[4:0])
+      5'd00: begin
+        data6b = 6'b000110;
+        may_invert6b = 1'b1;
+        disparity6b = 1'b1;
+      end
+      5'd01: begin
+        data6b = 6'b010001;
+        may_invert6b = 1'b1;
+        disparity6b = 1'b1;
+      end
+      5'd02: begin
+        data6b = 6'b010010;
+        may_invert6b = 1'b1;
+        disparity6b = 1'b1;
+      end
+      5'd03: begin
+        data6b = 6'b100011;
+        may_invert6b = 1'b0;
+        disparity6b = 1'b0;
+      end
+      5'd04: begin
+        data6b = 6'b010100;
+        may_invert6b = 1'b1;
+        disparity6b = 1'b1;
+      end
+      5'd05: begin
+        data6b = 6'b100101;
+        may_invert6b = 1'b0;
+        disparity6b = 1'b0;
+      end
+      5'd06: begin
+        data6b = 6'b100110;
+        may_invert6b = 1'b0;
+        disparity6b = 1'b0;
+      end
+      5'd07: begin
+        data6b = 6'b111000;
+        may_invert6b = 1'b1;
+        disparity6b = 1'b0;
+      end
+      5'd08: begin
+        data6b = 6'b011000;
+        may_invert6b = 1'b1;
+        disparity6b = 1'b1;
+      end
+      5'd09: begin
+        data6b = 6'b101001;
+        may_invert6b = 1'b0;
+        disparity6b = 1'b0;
+      end
+      5'd10: begin
+        data6b = 6'b101010;
+        may_invert6b = 1'b0;
+        disparity6b = 1'b0;
+      end
+      5'd11: begin
+        data6b = 6'b001011;
+        may_invert6b = 1'b0;
+        disparity6b = 1'b0;
+      end
+      5'd12: begin
+        data6b = 6'b101100;
+        may_invert6b = 1'b0;
+        disparity6b = 1'b0;
+      end
+      5'd13: begin
+        data6b = 6'b001101;
+        may_invert6b = 1'b0;
+        disparity6b = 1'b0;
+      end
+      5'd14: begin
+        data6b = 6'b001110;
+        may_invert6b = 1'b0;
+        disparity6b = 1'b0;
+      end
+      5'd15: begin
+        data6b = 6'b000101;
+        may_invert6b = 1'b1;
+        disparity6b = 1'b1;
+      end
+      5'd16: begin
+        data6b = 6'b001001;
+        may_invert6b = 1'b1;
+        disparity6b = 1'b1;
+      end
+      5'd17: begin
+        data6b = 6'b110001;
+        may_invert6b = 1'b0;
+        disparity6b = 1'b0;
+      end
+      5'd18: begin
+        data6b = 6'b110010;
+        may_invert6b = 1'b0;
+        disparity6b = 1'b0;
+      end
+      5'd19: begin
+        data6b = 6'b010011;
+        may_invert6b = 1'b0;
+        disparity6b = 1'b0;
+      end
+      5'd20: begin
+        data6b = 6'b110100;
+        may_invert6b = 1'b0;
+        disparity6b = 1'b0;
+      end
+      5'd21: begin
+        data6b = 6'b010101;
+        may_invert6b = 1'b0;
+        disparity6b = 1'b0;
+      end
+      5'd22: begin
+        data6b = 6'b010110;
+        may_invert6b = 1'b0;
+        disparity6b = 1'b0;
+      end
+      5'd23: begin
+        data6b = 6'b101000;
+        may_invert6b = 1'b1;
+        disparity6b = 1'b1;
+      end
+      5'd24: begin
+        data6b = 6'b001100;
+        may_invert6b = 1'b1;
+        disparity6b = 1'b1;
+      end
+      5'd25: begin
+        data6b = 6'b011001;
+        may_invert6b = 1'b0;
+        disparity6b = 1'b0;
+      end
+      5'd26: begin
+        data6b = 6'b011010;
+        may_invert6b = 1'b0;
+        disparity6b = 1'b0;
+      end
+      5'd27: begin
+        data6b = 6'b100100;
+        may_invert6b = 1'b1;
+        disparity6b = 1'b1;
+      end
+      5'd28: begin
+        data6b = 6'b011100;
+        may_invert6b = 1'b0;
+        disparity6b = 1'b0;
+      end
+      5'd29: begin
+        data6b = 6'b100010;
+        may_invert6b = 1'b1;
+        disparity6b = 1'b1;
+      end
+      5'd30: begin
+        data6b = 6'b100001;
+        may_invert6b = 1'b1;
+        disparity6b = 1'b1;
+      end
+      default: begin
+        data6b = 6'b001010;
+        may_invert6b = 1'b1;
+        disparity6b = 1'b1;
+      end
+      endcase
     end
-    5'd01: begin
-      data6b = 6'b010001;
-      may_invert6b = 1'b1;
-      disparity6b = 1'b1;
+  end
+
+  always @(*) begin
+    if (in_charisk == 1'b1) begin
+      alt7 = 1'b1;
+    end else begin
+  //    case (in_char[4:0])
+  //    5'd11, 5'd13, 5'd14: alt7 = in_disparity;
+  //    5'd17, 5'd18, 5'd20: alt7 = ~in_disparity;
+  //    default: alt7 = 1'b0;
+  //    endcase
+
+        // Slightly better packing
+        case ({may_invert6b,data6b[5:4]})
+        3'b000: alt7 = in_disparity;
+        3'b011: alt7 = ~in_disparity;
+        default: alt7 = 1'b0;
+        endcase
     end
-    5'd02: begin
-      data6b = 6'b010010;
-      may_invert6b = 1'b1;
-      disparity6b = 1'b1;
+  end
+
+  always @(*) begin
+    case (in_char[7:5])
+    3'd0: begin
+      data4b = 4'b0010;
+      may_invert4b = 1'b1;
+      disparity4b = 1'b1;
     end
-    5'd03: begin
-      data6b = 6'b100011;
-      may_invert6b = 1'b0;
-      disparity6b = 1'b0;
+    3'd1: begin
+      data4b = 4'b1001;
+      may_invert4b = in_charisk;
+      disparity4b = 1'b0;
     end
-    5'd04: begin
-      data6b = 6'b010100;
-      may_invert6b = 1'b1;
-      disparity6b = 1'b1;
+    3'd2: begin
+      data4b = 4'b1010;
+      may_invert4b = in_charisk;
+      disparity4b = 1'b0;
     end
-    5'd05: begin
-      data6b = 6'b100101;
-      may_invert6b = 1'b0;
-      disparity6b = 1'b0;
+    3'd3: begin
+      data4b = 4'b1100;
+      may_invert4b = 1'b1;
+      disparity4b = 1'b0;
     end
-    5'd06: begin
-      data6b = 6'b100110;
-      may_invert6b = 1'b0;
-      disparity6b = 1'b0;
+    3'd4: begin
+      data4b = 4'b0100;
+      may_invert4b = 1'b1;
+      disparity4b = 1'b1;
     end
-    5'd07: begin
-      data6b = 6'b111000;
-      may_invert6b = 1'b1;
-      disparity6b = 1'b0;
+    3'd5: begin
+      data4b = 4'b0101;
+      may_invert4b = in_charisk;
+      disparity4b = 1'b0;
     end
-    5'd08: begin
-      data6b = 6'b011000;
-      may_invert6b = 1'b1;
-      disparity6b = 1'b1;
-    end
-    5'd09: begin
-      data6b = 6'b101001;
-      may_invert6b = 1'b0;
-      disparity6b = 1'b0;
-    end
-    5'd10: begin
-      data6b = 6'b101010;
-      may_invert6b = 1'b0;
-      disparity6b = 1'b0;
-    end
-    5'd11: begin
-      data6b = 6'b001011;
-      may_invert6b = 1'b0;
-      disparity6b = 1'b0;
-    end
-    5'd12: begin
-      data6b = 6'b101100;
-      may_invert6b = 1'b0;
-      disparity6b = 1'b0;
-    end
-    5'd13: begin
-      data6b = 6'b001101;
-      may_invert6b = 1'b0;
-      disparity6b = 1'b0;
-    end
-    5'd14: begin
-      data6b = 6'b001110;
-      may_invert6b = 1'b0;
-      disparity6b = 1'b0;
-    end
-    5'd15: begin
-      data6b = 6'b000101;
-      may_invert6b = 1'b1;
-      disparity6b = 1'b1;
-    end
-    5'd16: begin
-      data6b = 6'b001001;
-      may_invert6b = 1'b1;
-      disparity6b = 1'b1;
-    end
-    5'd17: begin
-      data6b = 6'b110001;
-      may_invert6b = 1'b0;
-      disparity6b = 1'b0;
-    end
-    5'd18: begin
-      data6b = 6'b110010;
-      may_invert6b = 1'b0;
-      disparity6b = 1'b0;
-    end
-    5'd19: begin
-      data6b = 6'b010011;
-      may_invert6b = 1'b0;
-      disparity6b = 1'b0;
-    end
-    5'd20: begin
-      data6b = 6'b110100;
-      may_invert6b = 1'b0;
-      disparity6b = 1'b0;
-    end
-    5'd21: begin
-      data6b = 6'b010101;
-      may_invert6b = 1'b0;
-      disparity6b = 1'b0;
-    end
-    5'd22: begin
-      data6b = 6'b010110;
-      may_invert6b = 1'b0;
-      disparity6b = 1'b0;
-    end
-    5'd23: begin
-      data6b = 6'b101000;
-      may_invert6b = 1'b1;
-      disparity6b = 1'b1;
-    end
-    5'd24: begin
-      data6b = 6'b001100;
-      may_invert6b = 1'b1;
-      disparity6b = 1'b1;
-    end
-    5'd25: begin
-      data6b = 6'b011001;
-      may_invert6b = 1'b0;
-      disparity6b = 1'b0;
-    end
-    5'd26: begin
-      data6b = 6'b011010;
-      may_invert6b = 1'b0;
-      disparity6b = 1'b0;
-    end
-    5'd27: begin
-      data6b = 6'b100100;
-      may_invert6b = 1'b1;
-      disparity6b = 1'b1;
-    end
-    5'd28: begin
-      data6b = 6'b011100;
-      may_invert6b = 1'b0;
-      disparity6b = 1'b0;
-    end
-    5'd29: begin
-      data6b = 6'b100010;
-      may_invert6b = 1'b1;
-      disparity6b = 1'b1;
-    end
-    5'd30: begin
-      data6b = 6'b100001;
-      may_invert6b = 1'b1;
-      disparity6b = 1'b1;
+    3'd6: begin
+      data4b = 4'b0110;
+      may_invert4b = in_charisk;
+      disparity4b = 1'b0;
     end
     default: begin
-      data6b = 6'b001010;
-      may_invert6b = 1'b1;
-      disparity6b = 1'b1;
+      if (alt7 == 1'b1) begin
+        data4b = 4'b0001;
+      end else begin
+        data4b = 4'b1000;
+      end
+      may_invert4b = 1'b1;
+      disparity4b = 1'b1;
     end
     endcase
   end
-end
 
-always @(*) begin
-  if (in_charisk == 1'b1) begin
-    alt7 = 1'b1;
-  end else begin
-//    case (in_char[4:0])
-//    5'd11, 5'd13, 5'd14: alt7 = in_disparity;
-//    5'd17, 5'd18, 5'd20: alt7 = ~in_disparity;
-//    default: alt7 = 1'b0;
-//    endcase
+  assign disparity4b_in = in_disparity ^ disparity6b;
+  assign out_disparity = disparity4b_in ^ disparity4b;
 
-      // Slightly better packing
-      case ({may_invert6b,data6b[5:4]})
-      3'b000: alt7 = in_disparity;
-      3'b011: alt7 = ~in_disparity;
-      default: alt7 = 1'b0;
-      endcase
-  end
-end
-
-always @(*) begin
-  case (in_char[7:5])
-  3'd0: begin
-    data4b = 4'b0010;
-    may_invert4b = 1'b1;
-    disparity4b = 1'b1;
-  end
-  3'd1: begin
-    data4b = 4'b1001;
-    may_invert4b = in_charisk;
-    disparity4b = 1'b0;
-  end
-  3'd2: begin
-    data4b = 4'b1010;
-    may_invert4b = in_charisk;
-    disparity4b = 1'b0;
-  end
-  3'd3: begin
-    data4b = 4'b1100;
-    may_invert4b = 1'b1;
-    disparity4b = 1'b0;
-  end
-  3'd4: begin
-    data4b = 4'b0100;
-    may_invert4b = 1'b1;
-    disparity4b = 1'b1;
-  end
-  3'd5: begin
-    data4b = 4'b0101;
-    may_invert4b = in_charisk;
-    disparity4b = 1'b0;
-  end
-  3'd6: begin
-    data4b = 4'b0110;
-    may_invert4b = in_charisk;
-    disparity4b = 1'b0;
-  end
-  default: begin
-    if (alt7 == 1'b1) begin
-      data4b = 4'b0001;
+  always @(*) begin
+    if (in_disparity == 1'b0 && may_invert6b == 1'b1) begin
+      out6b = ~data6b;
     end else begin
-      data4b = 4'b1000;
+      out6b = data6b;
+    end
+    if (disparity4b_in == 1'b0 && may_invert4b == 1'b1) begin
+      out4b = ~data4b;
+    end else begin
+      out4b = data4b;
     end
-    may_invert4b = 1'b1;
-    disparity4b = 1'b1;
   end
-  endcase
-end
 
-assign disparity4b_in = in_disparity ^ disparity6b;
-assign out_disparity = disparity4b_in ^ disparity4b;
-
-always @(*) begin
-  if (in_disparity == 1'b0 && may_invert6b == 1'b1) begin
-    out6b = ~data6b;
-  end else begin
-    out6b = data6b;
-  end
-  if (disparity4b_in == 1'b0 && may_invert4b == 1'b1) begin
-    out4b = ~data4b;
-  end else begin
-    out4b = data4b;
-  end
-end
-
-assign out_char = {out4b,out6b};
+  assign out_char = {out4b,out6b};
 
 endmodule
diff --git a/library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx.v b/library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx.v
index 6cb29ed94..d22a1ae72 100644
--- a/library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx.v
+++ b/library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx.v
@@ -49,51 +49,50 @@ module jesd204_soft_pcs_tx #(
   parameter DATA_PATH_WIDTH = 4,
   parameter INVERT_OUTPUTS = 0
 ) (
-   input clk,
-   input reset,
+  input clk,
+  input reset,
 
-   input [NUM_LANES*DATA_PATH_WIDTH*8-1:0] char,
-   input [NUM_LANES*DATA_PATH_WIDTH-1:0] charisk,
+  input [NUM_LANES*DATA_PATH_WIDTH*8-1:0] char,
+  input [NUM_LANES*DATA_PATH_WIDTH-1:0] charisk,
 
-   output reg [NUM_LANES*DATA_PATH_WIDTH*10-1:0] data
+  output reg [NUM_LANES*DATA_PATH_WIDTH*10-1:0] data
 );
 
-reg [NUM_LANES-1:0] disparity = 'h00;
+  reg [NUM_LANES-1:0] disparity = 'h00;
 
-wire [DATA_PATH_WIDTH:0] disparity_chain[0:NUM_LANES-1];
-wire [NUM_LANES*DATA_PATH_WIDTH*10-1:0] data_s;
-
-always @(posedge clk) begin
-  data <= INVERT_OUTPUTS ? ~data_s : data_s;
-end
-
-generate
-genvar lane;
-genvar i;
-for (lane = 0; lane < NUM_LANES; lane = lane + 1) begin: gen_lane
-  assign disparity_chain[lane][0] = disparity[lane];
+  wire [DATA_PATH_WIDTH:0] disparity_chain[0:NUM_LANES-1];
+  wire [NUM_LANES*DATA_PATH_WIDTH*10-1:0] data_s;
 
   always @(posedge clk) begin
-    if (reset == 1'b1) begin
-      disparity[lane] <= 1'b0;
-    end else begin
-      disparity[lane] <= disparity_chain[lane][DATA_PATH_WIDTH];
+    data <= INVERT_OUTPUTS ? ~data_s : data_s;
+  end
+
+  generate
+  genvar lane;
+  genvar i;
+  for (lane = 0; lane < NUM_LANES; lane = lane + 1) begin: gen_lane
+    assign disparity_chain[lane][0] = disparity[lane];
+
+    always @(posedge clk) begin
+      if (reset == 1'b1) begin
+        disparity[lane] <= 1'b0;
+      end else begin
+        disparity[lane] <= disparity_chain[lane][DATA_PATH_WIDTH];
+      end
+    end
+
+    for (i = 0; i < DATA_PATH_WIDTH; i = i + 1) begin: gen_dpw
+      localparam j = DATA_PATH_WIDTH * lane + i;
+
+      jesd204_8b10b_encoder i_enc (
+        .in_char(char[j*8+:8]),
+        .in_charisk(charisk[j]),
+        .out_char(data_s[j*10+:10]),
+
+        .in_disparity(disparity_chain[lane][i]),
+        .out_disparity(disparity_chain[lane][i+1]));
     end
   end
-
-  for (i = 0; i < DATA_PATH_WIDTH; i = i + 1) begin: gen_dpw
-    localparam j = DATA_PATH_WIDTH * lane + i;
-
-    jesd204_8b10b_encoder i_enc (
-      .in_char(char[j*8+:8]),
-      .in_charisk(charisk[j]),
-      .out_char(data_s[j*10+:10]),
-
-      .in_disparity(disparity_chain[lane][i]),
-      .out_disparity(disparity_chain[lane][i+1])
-    );
-  end
-end
-endgenerate
+  endgenerate
 
 endmodule
diff --git a/library/jesd204/jesd204_tx/jesd204_tx.v b/library/jesd204/jesd204_tx/jesd204_tx.v
index 0af1217bf..d71b1313e 100755
--- a/library/jesd204/jesd204_tx/jesd204_tx.v
+++ b/library/jesd204/jesd204_tx/jesd204_tx.v
@@ -114,440 +114,426 @@ module jesd204_tx #(
   output [31:0] status_synth_params2
 );
 
+  localparam MAX_OCTETS_PER_FRAME = 32;
+  localparam MAX_OCTETS_PER_MULTIFRAME =
+    (MAX_OCTETS_PER_FRAME * 32) > 1024 ? 1024 : (MAX_OCTETS_PER_FRAME * 32);
+  localparam MAX_BEATS_PER_MULTIFRAME = MAX_OCTETS_PER_MULTIFRAME / DATA_PATH_WIDTH;
 
-localparam MAX_OCTETS_PER_FRAME = 32;
-localparam MAX_OCTETS_PER_MULTIFRAME =
-  (MAX_OCTETS_PER_FRAME * 32) > 1024 ? 1024 : (MAX_OCTETS_PER_FRAME * 32);
-localparam MAX_BEATS_PER_MULTIFRAME = MAX_OCTETS_PER_MULTIFRAME / DATA_PATH_WIDTH;
+  localparam DPW_LOG2 = DATA_PATH_WIDTH == 8 ? 3 : DATA_PATH_WIDTH == 4 ? 2 : 1;
 
-localparam DPW_LOG2 = DATA_PATH_WIDTH == 8 ? 3 : DATA_PATH_WIDTH == 4 ? 2 : 1;
+  localparam LMFC_COUNTER_WIDTH = MAX_BEATS_PER_MULTIFRAME > 256 ? 9 :
+    MAX_BEATS_PER_MULTIFRAME > 128 ? 8 :
+    MAX_BEATS_PER_MULTIFRAME > 64 ? 7 :
+    MAX_BEATS_PER_MULTIFRAME > 32 ? 6 :
+    MAX_BEATS_PER_MULTIFRAME > 16 ? 5 :
+    MAX_BEATS_PER_MULTIFRAME > 8 ? 4 :
+    MAX_BEATS_PER_MULTIFRAME > 4 ? 3 :
+    MAX_BEATS_PER_MULTIFRAME > 2 ? 2 : 1;
 
-localparam LMFC_COUNTER_WIDTH = MAX_BEATS_PER_MULTIFRAME > 256 ? 9 :
-  MAX_BEATS_PER_MULTIFRAME > 128 ? 8 :
-  MAX_BEATS_PER_MULTIFRAME > 64 ? 7 :
-  MAX_BEATS_PER_MULTIFRAME > 32 ? 6 :
-  MAX_BEATS_PER_MULTIFRAME > 16 ? 5 :
-  MAX_BEATS_PER_MULTIFRAME > 8 ? 4 :
-  MAX_BEATS_PER_MULTIFRAME > 4 ? 3 :
-  MAX_BEATS_PER_MULTIFRAME > 2 ? 2 : 1;
+  localparam DW = DATA_PATH_WIDTH * 8 * NUM_LANES;
+  localparam CW = DATA_PATH_WIDTH * NUM_LANES;
+  localparam HW = 2 * NUM_LANES;
 
-localparam DW = DATA_PATH_WIDTH * 8 * NUM_LANES;
-localparam CW = DATA_PATH_WIDTH * NUM_LANES;
-localparam HW = 2 * NUM_LANES;
+  wire [DW-1:0] phy_data_r;
+  wire [CW-1:0] phy_charisk_r;
+  wire [HW-1:0] phy_header_r;
 
-wire [DW-1:0] phy_data_r;
-wire [CW-1:0] phy_charisk_r;
-wire [HW-1:0] phy_header_r;
+  wire eof_gen_reset;
+  wire tx_ready_64b_next;
+  reg tx_ready_64b = 1'b0;
+  wire frame_mark_reset;
+  wire [DATA_PATH_WIDTH-1:0] tx_sof_fm;
+  wire [DATA_PATH_WIDTH-1:0] tx_eof_fm;
+  wire [DATA_PATH_WIDTH-1:0] tx_somf_fm;
+  wire [DATA_PATH_WIDTH-1:0] tx_eomf_fm;
+  reg [DATA_PATH_WIDTH-1:0] tx_sof_fm_d1;
+  reg [DATA_PATH_WIDTH-1:0] tx_eof_fm_d1;
+  reg [DATA_PATH_WIDTH-1:0] tx_somf_fm_d1;
+  reg [DATA_PATH_WIDTH-1:0] tx_eomf_fm_d1;
+  reg [DATA_PATH_WIDTH-1:0] tx_sof_fm_d2;
+  reg [DATA_PATH_WIDTH-1:0] tx_eof_fm_d2;
+  reg [DATA_PATH_WIDTH-1:0] tx_somf_fm_d2;
+  reg [DATA_PATH_WIDTH-1:0] tx_eomf_fm_d2;
+  wire lmfc_edge_synced;
+  wire lmc_edge;
+  wire lmc_quarter_edge;
+  wire eoemb;
+  wire [DATA_PATH_WIDTH*8*NUM_LANES-1:0] gearbox_data;
+  wire tx_ready_nx;
+  wire link_lmfc_edge;
+  wire link_lmfc_clk;
+  wire device_lmfc_edge;
+  wire device_lmfc_clk;
+  wire device_lmc_edge;
+  wire device_lmc_quarter_edge;
+  wire device_eoemb;
+  wire tx_next_mf_ready;
+  wire link_tx_ready;
 
-wire eof_gen_reset;
-wire tx_ready_64b_next;
-reg tx_ready_64b = 1'b0;
-wire frame_mark_reset;
-wire [DATA_PATH_WIDTH-1:0] tx_sof_fm;
-wire [DATA_PATH_WIDTH-1:0] tx_eof_fm;
-wire [DATA_PATH_WIDTH-1:0] tx_somf_fm;
-wire [DATA_PATH_WIDTH-1:0] tx_eomf_fm;
-reg [DATA_PATH_WIDTH-1:0] tx_sof_fm_d1;
-reg [DATA_PATH_WIDTH-1:0] tx_eof_fm_d1;
-reg [DATA_PATH_WIDTH-1:0] tx_somf_fm_d1;
-reg [DATA_PATH_WIDTH-1:0] tx_eomf_fm_d1;
-reg [DATA_PATH_WIDTH-1:0] tx_sof_fm_d2;
-reg [DATA_PATH_WIDTH-1:0] tx_eof_fm_d2;
-reg [DATA_PATH_WIDTH-1:0] tx_somf_fm_d2;
-reg [DATA_PATH_WIDTH-1:0] tx_eomf_fm_d2;
-wire lmfc_edge_synced;
-wire lmc_edge;
-wire lmc_quarter_edge;
-wire eoemb;
-wire [DATA_PATH_WIDTH*8*NUM_LANES-1:0] gearbox_data;
-wire tx_ready_nx;
-wire link_lmfc_edge;
-wire link_lmfc_clk;
-wire device_lmfc_edge;
-wire device_lmfc_clk;
-wire device_lmc_edge;
-wire device_lmc_quarter_edge;
-wire device_eoemb;
-wire tx_next_mf_ready;
-wire link_tx_ready;
+  wire [7:0] cfg_beats_per_multiframe = cfg_octets_per_multiframe >> DPW_LOG2;
+  wire [7:0] device_cfg_beats_per_multiframe_s;
 
-wire [7:0] cfg_beats_per_multiframe = cfg_octets_per_multiframe >> DPW_LOG2;
-wire [7:0] device_cfg_beats_per_multiframe_s;
-
-// If input and output widths are symmetric keep the calculation for backwards
-// compatibility of the software.
-assign device_cfg_beats_per_multiframe_s = (TPL_DATA_PATH_WIDTH == DATA_PATH_WIDTH) ?
-                                   device_cfg_octets_per_multiframe >> DPW_LOG2 :
-                                   device_cfg_beats_per_multiframe;
-
-jesd204_lmfc #(
-  .LINK_MODE(LINK_MODE),
-  .DATA_PATH_WIDTH(TPL_DATA_PATH_WIDTH)
-) i_lmfc (
-  .clk(device_clk),
-  .reset(device_reset),
-
-  .cfg_octets_per_multiframe(device_cfg_octets_per_multiframe),
-  .cfg_lmfc_offset(device_cfg_lmfc_offset),
-  .cfg_beats_per_multiframe(device_cfg_beats_per_multiframe_s),
-  .cfg_sysref_oneshot(device_cfg_sysref_oneshot),
-  .cfg_sysref_disable(device_cfg_sysref_disable),
-
-  .sysref(sysref),
-
-  .sysref_edge(device_event_sysref_edge),
-  .sysref_alignment_error(device_event_sysref_alignment_error),
-
-  .lmfc_edge(device_lmfc_edge),
-  .lmfc_clk(device_lmfc_clk),
-  .lmfc_counter(),
-  .lmc_edge(device_lmc_edge),
-  .lmc_quarter_edge(device_lmc_quarter_edge),
-  .eoemb(device_eoemb)
-);
-
-generate
-if (ASYNC_CLK) begin : dual_lmfc_mode
-
-  reg link_lmfc_reset = 1'b1;
-  reg device_lmfc_edge_d1 = 1'b0;
-  reg device_tx_ready = 1'b0;
+  // If input and output widths are symmetric keep the calculation for backwards
+  // compatibility of the software.
+  assign device_cfg_beats_per_multiframe_s = (TPL_DATA_PATH_WIDTH == DATA_PATH_WIDTH) ?
+                                     device_cfg_octets_per_multiframe >> DPW_LOG2 :
+                                     device_cfg_beats_per_multiframe;
 
   jesd204_lmfc #(
     .LINK_MODE(LINK_MODE),
-    .DATA_PATH_WIDTH(DATA_PATH_WIDTH)
-  ) i_link_lmfc (
-    .clk(clk),
-    .reset(link_lmfc_reset),
+    .DATA_PATH_WIDTH(TPL_DATA_PATH_WIDTH)
+  ) i_lmfc (
+    .clk(device_clk),
+    .reset(device_reset),
 
-    .cfg_octets_per_multiframe(cfg_octets_per_multiframe),
-    .cfg_lmfc_offset('h0),
-    .cfg_beats_per_multiframe(cfg_beats_per_multiframe),
-    .cfg_sysref_oneshot(1'b0),
-    .cfg_sysref_disable(1'b1),
+    .cfg_octets_per_multiframe(device_cfg_octets_per_multiframe),
+    .cfg_lmfc_offset(device_cfg_lmfc_offset),
+    .cfg_beats_per_multiframe(device_cfg_beats_per_multiframe_s),
+    .cfg_sysref_oneshot(device_cfg_sysref_oneshot),
+    .cfg_sysref_disable(device_cfg_sysref_disable),
 
     .sysref(sysref),
 
-    .sysref_edge(),
-    .sysref_alignment_error(),
+    .sysref_edge(device_event_sysref_edge),
+    .sysref_alignment_error(device_event_sysref_alignment_error),
 
-    .lmfc_edge(link_lmfc_edge),
-    .lmfc_clk(link_lmfc_clk),
+    .lmfc_edge(device_lmfc_edge),
+    .lmfc_clk(device_lmfc_clk),
     .lmfc_counter(),
-    .lmc_edge(lmc_edge),
-    .lmc_quarter_edge(lmc_quarter_edge),
-    .eoemb(eoemb)
-  );
+    .lmc_edge(device_lmc_edge),
+    .lmc_quarter_edge(device_lmc_quarter_edge),
+    .eoemb(device_eoemb));
 
-  sync_bits #(
-    .NUM_OF_BITS (1),
-    .ASYNC_CLK(ASYNC_CLK)
-  ) i_link_reset_done_cdc (
-    .in_bits(~reset),
-    .out_clk(device_clk),
-    .out_resetn(~device_reset),
-    .out_bits(link_reset_n)
-  );
+  generate
+  if (ASYNC_CLK) begin : dual_lmfc_mode
 
-  sync_event #(
-    .NUM_OF_EVENTS (1)
-  ) i_sync_lmfc (
-    .in_clk(device_clk),
-    .in_event(device_lmfc_edge & link_reset_n),
-    .out_clk(clk),
-    .out_event(lmfc_edge_synced)
-  );
+    reg link_lmfc_reset = 1'b1;
+    reg device_lmfc_edge_d1 = 1'b0;
+    reg device_tx_ready = 1'b0;
 
-  always @(posedge clk) begin
-    if (reset) begin
-      link_lmfc_reset <= 1'b1;
-    end else if (lmfc_edge_synced) begin
-      link_lmfc_reset <= 1'b0;
-    end
-  end
-
-  jesd204_tx_gearbox #(
-    .IN_DATA_PATH_WIDTH(TPL_DATA_PATH_WIDTH),
-    .OUT_DATA_PATH_WIDTH(DATA_PATH_WIDTH),
-    .NUM_LANES(NUM_LANES),
-    .DEPTH(8)
-  ) i_tx_gearbox(
-    .link_clk(clk),
-    .reset(reset),
-    .device_clk(device_clk),
-    .device_reset(device_reset),
-    .device_data(tx_data),
-    .device_lmfc_edge(device_lmfc_edge_d1),
-    .link_data(gearbox_data),
-    .output_ready(tx_ready_nx)
-  );
-
-  always @(posedge device_clk) begin
-    device_lmfc_edge_d1 <= device_lmfc_edge;
-  end
-
-  sync_bits #(
-    .NUM_OF_BITS (1),
-    .ASYNC_CLK(ASYNC_CLK)
-  ) i_next_mf_ready_cdc (
-    .in_bits(tx_next_mf_ready),
-    .out_clk(device_clk),
-    .out_resetn(1'b1),
-    .out_bits(device_tx_next_mf_ready)
-  );
-
-  always @(posedge device_clk) begin
-    if (device_reset) begin
-      device_tx_ready <= 1'b0;
-    end else if (device_lmfc_edge & device_tx_next_mf_ready) begin
-      device_tx_ready <= 1'b1;
-    end
-  end
-
-  jesd204_frame_mark #(
-    .DATA_PATH_WIDTH(TPL_DATA_PATH_WIDTH)
-  ) i_device_frame_mark (
-    .clk(device_clk),
-    .reset(~device_tx_ready),
-    .cfg_octets_per_multiframe(device_cfg_octets_per_multiframe),
-    .cfg_beats_per_multiframe(device_cfg_beats_per_multiframe_s),
-    .cfg_octets_per_frame(device_cfg_octets_per_frame),
-    .sof(tx_sof),
-    .eof(tx_eof),
-    .somf(tx_somf),
-    .eomf(tx_eomf)
-  );
-
-  assign tx_ready = device_tx_ready;
-
-end else begin
-  assign link_lmfc_edge = device_lmfc_edge;
-  assign link_lmfc_clk = device_lmfc_clk;
-  assign lmc_edge = device_lmc_edge;
-  assign lmc_quarter_edge = device_lmc_quarter_edge;
-  assign eoemb = device_eoemb;
-  assign gearbox_data = tx_data;
-
-  assign tx_sof = (LINK_MODE == 1) ? tx_sof_fm_d2 : tx_sof_fm;
-  assign tx_eof = (LINK_MODE == 1) ? tx_eof_fm_d2 : tx_eof_fm;
-  assign tx_somf = (LINK_MODE == 1) ? tx_somf_fm_d2 : tx_somf_fm;
-  assign tx_eomf = (LINK_MODE == 1) ? tx_eomf_fm_d2 : tx_eomf_fm;
-  assign tx_ready = link_tx_ready;
-
-end
-endgenerate
-
-assign lmfc_edge = device_lmfc_edge;
-assign lmfc_clk = device_lmfc_clk;
-
-assign frame_mark_reset = (LINK_MODE == 1) ? eof_gen_reset : ~tx_ready_64b_next;
-
-jesd204_frame_mark #(
-  .DATA_PATH_WIDTH            (DATA_PATH_WIDTH)
-) i_frame_mark (
-  .clk                        (clk),
-  .reset                      (frame_mark_reset),
-  .cfg_octets_per_multiframe  (cfg_octets_per_multiframe),
-  .cfg_beats_per_multiframe   (cfg_beats_per_multiframe),
-  .cfg_octets_per_frame       (cfg_octets_per_frame),
-  .sof                        (tx_sof_fm),
-  .eof                        (tx_eof_fm),
-  .somf                       (tx_somf_fm),
-  .eomf                       (tx_eomf_fm)
-);
-
-always @(posedge clk) begin
-  tx_sof_fm_d1  <= tx_sof_fm;
-  tx_eof_fm_d1  <= tx_eof_fm;
-  tx_somf_fm_d1 <= tx_somf_fm;
-  tx_eomf_fm_d1 <= tx_eomf_fm;
-  tx_sof_fm_d2  <= tx_sof_fm_d1;
-  tx_eof_fm_d2  <= tx_eof_fm_d1;
-  tx_somf_fm_d2 <= tx_somf_fm_d1;
-  tx_eomf_fm_d2 <= tx_eomf_fm_d1;
-end
-
-generate
-genvar i;
-
-if (LINK_MODE[0] == 1) begin : mode_8b10b
-
-reg [DATA_PATH_WIDTH-1:0] tx_eof_fm_d3;
-reg [DATA_PATH_WIDTH-1:0] tx_eomf_fm_d3;
-wire [NUM_LANES-1:0] lane_cgs_enable;
-wire [DW-1:0] ilas_data;
-wire [DATA_PATH_WIDTH*NUM_LANES-1:0] ilas_charisk;
-
-wire cfg_generate_eomf = 1'b1;
-
-always @(posedge clk) begin
-  tx_eof_fm_d3 <= tx_eof_fm_d2;
-  tx_eomf_fm_d3 <= tx_eomf_fm_d2;
-end
-
-jesd204_tx_ctrl #(
-  .NUM_LANES(NUM_LANES),
-  .NUM_LINKS(NUM_LINKS),
-  .DATA_PATH_WIDTH(DATA_PATH_WIDTH)
-) i_tx_ctrl (
-  .clk(clk),
-  .reset(reset),
-
-  .sync(sync),
-  .lmfc_edge(link_lmfc_edge),
-  .somf(tx_somf_fm_d2),
-  .somf_early2(tx_somf_fm),
-  .eomf(tx_eomf_fm_d2),
-
-  .lane_cgs_enable(lane_cgs_enable),
-  .eof_reset(eof_gen_reset),
-
-  .tx_ready(link_tx_ready),
-  .tx_ready_nx(tx_ready_nx),
-  .tx_next_mf_ready(tx_next_mf_ready),
-
-  .ilas_data(ilas_data),
-  .ilas_charisk(ilas_charisk),
-
-  .ilas_config_addr(ilas_config_addr),
-  .ilas_config_rd(ilas_config_rd),
-  .ilas_config_data(ilas_config_data),
-
-  .cfg_lanes_disable(cfg_lanes_disable),
-  .cfg_links_disable(cfg_links_disable),
-  .cfg_continuous_cgs(cfg_continuous_cgs),
-  .cfg_continuous_ilas(cfg_continuous_ilas),
-  .cfg_skip_ilas(cfg_skip_ilas),
-  .cfg_mframes_per_ilas(cfg_mframes_per_ilas),
-  .cfg_octets_per_multiframe(cfg_octets_per_multiframe),
-  .ctrl_manual_sync_request(ctrl_manual_sync_request),
-
-  .status_sync(status_sync),
-  .status_state(status_state)
-);
-
-for (i = 0; i < NUM_LANES; i = i + 1) begin: gen_lane
-
-  localparam D_START = i * DATA_PATH_WIDTH*8;
-  localparam D_STOP = D_START + DATA_PATH_WIDTH*8-1;
-  localparam C_START = i * DATA_PATH_WIDTH;
-  localparam C_STOP = C_START + DATA_PATH_WIDTH-1;
-
-  jesd204_tx_lane #(
-    .DATA_PATH_WIDTH(DATA_PATH_WIDTH),
-    .ENABLE_CHAR_REPLACE(ENABLE_CHAR_REPLACE)
-  ) i_lane (
-    .clk(clk),
-
-    .eof(tx_eof_fm_d3),
-    .eomf(tx_eomf_fm_d3),
-
-    .cgs_enable(lane_cgs_enable[i]),
-
-    .ilas_data(ilas_data[D_STOP:D_START]),
-    .ilas_charisk(ilas_charisk[C_STOP:C_START]),
-
-    .tx_data(gearbox_data[D_STOP:D_START]),
-    .tx_ready(link_tx_ready),
-
-    .phy_data(phy_data_r[D_STOP:D_START]),
-    .phy_charisk(phy_charisk_r[C_STOP:C_START]),
-
-    .cfg_octets_per_frame(cfg_octets_per_frame),
-    .cfg_disable_char_replacement(cfg_disable_char_replacement),
-    .cfg_disable_scrambler(cfg_disable_scrambler)
-  );
-end
-
-assign phy_header_r = 'h0;
-
-end
-
-if (LINK_MODE[1] == 1) begin : mode_64b66b
-
-  for (i = 0; i < NUM_LANES; i = i + 1) begin: gen_lane
-    localparam D_START = i * DATA_PATH_WIDTH*8;
-    localparam D_STOP = D_START + DATA_PATH_WIDTH*8-1;
-    localparam H_START = i * 2;
-    localparam H_STOP = H_START + 2 -1;
-    jesd204_tx_lane_64b i_lane(
+    jesd204_lmfc #(
+      .LINK_MODE(LINK_MODE),
+      .DATA_PATH_WIDTH(DATA_PATH_WIDTH)
+    ) i_link_lmfc (
       .clk(clk),
-      .reset(reset),
+      .reset(link_lmfc_reset),
 
-      .tx_data(gearbox_data[D_STOP:D_START]),
-      .tx_ready(tx_ready_64b),
+      .cfg_octets_per_multiframe(cfg_octets_per_multiframe),
+      .cfg_lmfc_offset('h0),
+      .cfg_beats_per_multiframe(cfg_beats_per_multiframe),
+      .cfg_sysref_oneshot(1'b0),
+      .cfg_sysref_disable(1'b1),
 
-      .phy_data(phy_data_r[D_STOP:D_START]),
-      .phy_header(phy_header_r[H_STOP:H_START]),
+      .sysref(sysref),
 
+      .sysref_edge(),
+      .sysref_alignment_error(),
+
+      .lmfc_edge(link_lmfc_edge),
+      .lmfc_clk(link_lmfc_clk),
+      .lmfc_counter(),
       .lmc_edge(lmc_edge),
       .lmc_quarter_edge(lmc_quarter_edge),
-      .eoemb(eoemb),
+      .eoemb(eoemb));
+
+    sync_bits #(
+      .NUM_OF_BITS (1),
+      .ASYNC_CLK(ASYNC_CLK)
+    ) i_link_reset_done_cdc (
+      .in_bits(~reset),
+      .out_clk(device_clk),
+      .out_resetn(~device_reset),
+      .out_bits(link_reset_n));
+
+    sync_event #(
+      .NUM_OF_EVENTS (1)
+    ) i_sync_lmfc (
+      .in_clk(device_clk),
+      .in_event(device_lmfc_edge & link_reset_n),
+      .out_clk(clk),
+      .out_event(lmfc_edge_synced));
+
+    always @(posedge clk) begin
+      if (reset) begin
+        link_lmfc_reset <= 1'b1;
+      end else if (lmfc_edge_synced) begin
+        link_lmfc_reset <= 1'b0;
+      end
+    end
+
+    jesd204_tx_gearbox #(
+      .IN_DATA_PATH_WIDTH(TPL_DATA_PATH_WIDTH),
+      .OUT_DATA_PATH_WIDTH(DATA_PATH_WIDTH),
+      .NUM_LANES(NUM_LANES),
+      .DEPTH(8)
+    ) i_tx_gearbox (
+      .link_clk(clk),
+      .reset(reset),
+      .device_clk(device_clk),
+      .device_reset(device_reset),
+      .device_data(tx_data),
+      .device_lmfc_edge(device_lmfc_edge_d1),
+      .link_data(gearbox_data),
+      .output_ready(tx_ready_nx));
+
+    always @(posedge device_clk) begin
+      device_lmfc_edge_d1 <= device_lmfc_edge;
+    end
+
+    sync_bits #(
+      .NUM_OF_BITS (1),
+      .ASYNC_CLK(ASYNC_CLK)
+    ) i_next_mf_ready_cdc (
+      .in_bits(tx_next_mf_ready),
+      .out_clk(device_clk),
+      .out_resetn(1'b1),
+      .out_bits(device_tx_next_mf_ready));
+
+    always @(posedge device_clk) begin
+      if (device_reset) begin
+        device_tx_ready <= 1'b0;
+      end else if (device_lmfc_edge & device_tx_next_mf_ready) begin
+        device_tx_ready <= 1'b1;
+      end
+    end
+
+    jesd204_frame_mark #(
+      .DATA_PATH_WIDTH(TPL_DATA_PATH_WIDTH)
+    ) i_device_frame_mark (
+      .clk(device_clk),
+      .reset(~device_tx_ready),
+      .cfg_octets_per_multiframe(device_cfg_octets_per_multiframe),
+      .cfg_beats_per_multiframe(device_cfg_beats_per_multiframe_s),
+      .cfg_octets_per_frame(device_cfg_octets_per_frame),
+      .sof(tx_sof),
+      .eof(tx_eof),
+      .somf(tx_somf),
+      .eomf(tx_eomf));
+
+    assign tx_ready = device_tx_ready;
+
+  end else begin
+    assign link_lmfc_edge = device_lmfc_edge;
+    assign link_lmfc_clk = device_lmfc_clk;
+    assign lmc_edge = device_lmc_edge;
+    assign lmc_quarter_edge = device_lmc_quarter_edge;
+    assign eoemb = device_eoemb;
+    assign gearbox_data = tx_data;
+
+    assign tx_sof = (LINK_MODE == 1) ? tx_sof_fm_d2 : tx_sof_fm;
+    assign tx_eof = (LINK_MODE == 1) ? tx_eof_fm_d2 : tx_eof_fm;
+    assign tx_somf = (LINK_MODE == 1) ? tx_somf_fm_d2 : tx_somf_fm;
+    assign tx_eomf = (LINK_MODE == 1) ? tx_eomf_fm_d2 : tx_eomf_fm;
+    assign tx_ready = link_tx_ready;
 
-      .cfg_disable_scrambler(cfg_disable_scrambler),
-      .cfg_header_mode(2'b0),
-      .cfg_lane_disable(cfg_lanes_disable[i])
-    );
   end
+  endgenerate
 
-  assign tx_ready_64b_next = reset ? 1'b0 : (link_lmfc_edge || tx_ready_64b);
+  assign lmfc_edge = device_lmfc_edge;
+  assign lmfc_clk = device_lmfc_clk;
+
+  assign frame_mark_reset = (LINK_MODE == 1) ? eof_gen_reset : ~tx_ready_64b_next;
+
+  jesd204_frame_mark #(
+    .DATA_PATH_WIDTH            (DATA_PATH_WIDTH)
+  ) i_frame_mark (
+    .clk                        (clk),
+    .reset                      (frame_mark_reset),
+    .cfg_octets_per_multiframe  (cfg_octets_per_multiframe),
+    .cfg_beats_per_multiframe   (cfg_beats_per_multiframe),
+    .cfg_octets_per_frame       (cfg_octets_per_frame),
+    .sof                        (tx_sof_fm),
+    .eof                        (tx_eof_fm),
+    .somf                       (tx_somf_fm),
+    .eomf                       (tx_eomf_fm));
 
   always @(posedge clk) begin
-    if (reset) begin
-      tx_ready_64b <= 1'b0;
-    end else begin
-      tx_ready_64b <= tx_ready_64b_next;
-    end
+    tx_sof_fm_d1  <= tx_sof_fm;
+    tx_eof_fm_d1  <= tx_eof_fm;
+    tx_somf_fm_d1 <= tx_somf_fm;
+    tx_eomf_fm_d1 <= tx_eomf_fm;
+    tx_sof_fm_d2  <= tx_sof_fm_d1;
+    tx_eof_fm_d2  <= tx_eof_fm_d1;
+    tx_somf_fm_d2 <= tx_somf_fm_d1;
+    tx_eomf_fm_d2 <= tx_eomf_fm_d1;
   end
 
-  assign tx_ready_nx = tx_ready_64b_next;
-  assign tx_next_mf_ready = 1'b1;
+  generate
+  genvar i;
 
-  assign link_tx_ready = tx_ready_64b;
-  // Link considered in DATA phase when SYSREF received and LEMC clock started
-  // running
-  assign status_state = {2{tx_ready_64b}};
+  if (LINK_MODE[0] == 1) begin : mode_8b10b
 
+  reg [DATA_PATH_WIDTH-1:0] tx_eof_fm_d3;
+  reg [DATA_PATH_WIDTH-1:0] tx_eomf_fm_d3;
+  wire [NUM_LANES-1:0] lane_cgs_enable;
+  wire [DW-1:0] ilas_data;
+  wire [DATA_PATH_WIDTH*NUM_LANES-1:0] ilas_charisk;
 
-  assign phy_charisk_r = 'h0;
-  assign ilas_config_rd = 'h0;
-  assign ilas_config_addr = 'h0;
-  assign status_sync = 'h0;
+  wire cfg_generate_eomf = 1'b1;
 
-end
+  always @(posedge clk) begin
+    tx_eof_fm_d3 <= tx_eof_fm_d2;
+    tx_eomf_fm_d3 <= tx_eomf_fm_d2;
+  end
 
-endgenerate
+  jesd204_tx_ctrl #(
+    .NUM_LANES(NUM_LANES),
+    .NUM_LINKS(NUM_LINKS),
+    .DATA_PATH_WIDTH(DATA_PATH_WIDTH)
+  ) i_tx_ctrl (
+    .clk(clk),
+    .reset(reset),
 
-pipeline_stage #(
-  .WIDTH(CW + DW + HW),
-  .REGISTERED(NUM_OUTPUT_PIPELINE)
-) i_output_pipeline_stage (
-  .clk(clk),
-  .in({
-    phy_data_r,
-    phy_charisk_r,
-    phy_header_r
-  }),
-  .out({
-    phy_data,
-    phy_charisk,
-    phy_header
-  })
-);
+    .sync(sync),
+    .lmfc_edge(link_lmfc_edge),
+    .somf(tx_somf_fm_d2),
+    .somf_early2(tx_somf_fm),
+    .eomf(tx_eomf_fm_d2),
 
-// Core static parameters
-assign status_synth_params0 = {NUM_LANES};
-assign status_synth_params1 = {
-                 /*31:16 */  16'b0,
-                 /*15: 8 */  1'b0,TPL_DATA_PATH_WIDTH[6:0],
-                 /* 7: 0 */  4'b0,DPW_LOG2[3:0]};
-assign status_synth_params2 = {
-                 /*31:19 */  13'b0,
-                 /*   18 */  ENABLE_CHAR_REPLACE[0],
-                 /*17:13 */  5'b0,
-                 /*   12 */  ASYNC_CLK[0],
-                 /*11:10 */  2'b0,
-                 /* 9: 8 */  LINK_MODE[1:0],
-                 /* 7: 0 */  NUM_LINKS[7:0]};
+    .lane_cgs_enable(lane_cgs_enable),
+    .eof_reset(eof_gen_reset),
+
+    .tx_ready(link_tx_ready),
+    .tx_ready_nx(tx_ready_nx),
+    .tx_next_mf_ready(tx_next_mf_ready),
+
+    .ilas_data(ilas_data),
+    .ilas_charisk(ilas_charisk),
+
+    .ilas_config_addr(ilas_config_addr),
+    .ilas_config_rd(ilas_config_rd),
+    .ilas_config_data(ilas_config_data),
+
+    .cfg_lanes_disable(cfg_lanes_disable),
+    .cfg_links_disable(cfg_links_disable),
+    .cfg_continuous_cgs(cfg_continuous_cgs),
+    .cfg_continuous_ilas(cfg_continuous_ilas),
+    .cfg_skip_ilas(cfg_skip_ilas),
+    .cfg_mframes_per_ilas(cfg_mframes_per_ilas),
+    .cfg_octets_per_multiframe(cfg_octets_per_multiframe),
+    .ctrl_manual_sync_request(ctrl_manual_sync_request),
+
+    .status_sync(status_sync),
+    .status_state(status_state));
+
+  for (i = 0; i < NUM_LANES; i = i + 1) begin: gen_lane
+
+    localparam D_START = i * DATA_PATH_WIDTH*8;
+    localparam D_STOP = D_START + DATA_PATH_WIDTH*8-1;
+    localparam C_START = i * DATA_PATH_WIDTH;
+    localparam C_STOP = C_START + DATA_PATH_WIDTH-1;
+
+    jesd204_tx_lane #(
+      .DATA_PATH_WIDTH(DATA_PATH_WIDTH),
+      .ENABLE_CHAR_REPLACE(ENABLE_CHAR_REPLACE)
+    ) i_lane (
+      .clk(clk),
+
+      .eof(tx_eof_fm_d3),
+      .eomf(tx_eomf_fm_d3),
+
+      .cgs_enable(lane_cgs_enable[i]),
+
+      .ilas_data(ilas_data[D_STOP:D_START]),
+      .ilas_charisk(ilas_charisk[C_STOP:C_START]),
+
+      .tx_data(gearbox_data[D_STOP:D_START]),
+      .tx_ready(link_tx_ready),
+
+      .phy_data(phy_data_r[D_STOP:D_START]),
+      .phy_charisk(phy_charisk_r[C_STOP:C_START]),
+
+      .cfg_octets_per_frame(cfg_octets_per_frame),
+      .cfg_disable_char_replacement(cfg_disable_char_replacement),
+      .cfg_disable_scrambler(cfg_disable_scrambler));
+  end
+
+  assign phy_header_r = 'h0;
+
+  end
+
+  if (LINK_MODE[1] == 1) begin : mode_64b66b
+
+    for (i = 0; i < NUM_LANES; i = i + 1) begin: gen_lane
+      localparam D_START = i * DATA_PATH_WIDTH*8;
+      localparam D_STOP = D_START + DATA_PATH_WIDTH*8-1;
+      localparam H_START = i * 2;
+      localparam H_STOP = H_START + 2 -1;
+      jesd204_tx_lane_64b i_lane(
+        .clk(clk),
+        .reset(reset),
+
+        .tx_data(gearbox_data[D_STOP:D_START]),
+        .tx_ready(tx_ready_64b),
+
+        .phy_data(phy_data_r[D_STOP:D_START]),
+        .phy_header(phy_header_r[H_STOP:H_START]),
+
+        .lmc_edge(lmc_edge),
+        .lmc_quarter_edge(lmc_quarter_edge),
+        .eoemb(eoemb),
+
+        .cfg_disable_scrambler(cfg_disable_scrambler),
+        .cfg_header_mode(2'b0),
+        .cfg_lane_disable(cfg_lanes_disable[i]));
+    end
+
+    assign tx_ready_64b_next = reset ? 1'b0 : (link_lmfc_edge || tx_ready_64b);
+
+    always @(posedge clk) begin
+      if (reset) begin
+        tx_ready_64b <= 1'b0;
+      end else begin
+        tx_ready_64b <= tx_ready_64b_next;
+      end
+    end
+
+    assign tx_ready_nx = tx_ready_64b_next;
+    assign tx_next_mf_ready = 1'b1;
+
+    assign link_tx_ready = tx_ready_64b;
+    // Link considered in DATA phase when SYSREF received and LEMC clock started
+    // running
+    assign status_state = {2{tx_ready_64b}};
+
+    assign phy_charisk_r = 'h0;
+    assign ilas_config_rd = 'h0;
+    assign ilas_config_addr = 'h0;
+    assign status_sync = 'h0;
+
+  end
+
+  endgenerate
+
+  pipeline_stage #(
+    .WIDTH(CW + DW + HW),
+    .REGISTERED(NUM_OUTPUT_PIPELINE)
+  ) i_output_pipeline_stage (
+    .clk(clk),
+    .in({
+      phy_data_r,
+      phy_charisk_r,
+      phy_header_r
+    }),
+    .out({
+      phy_data,
+      phy_charisk,
+      phy_header
+    }));
+
+  // Core static parameters
+  assign status_synth_params0 = {NUM_LANES};
+  assign status_synth_params1 = {
+                   /*31:16 */  16'b0,
+                   /*15: 8 */  1'b0,TPL_DATA_PATH_WIDTH[6:0],
+                   /* 7: 0 */  4'b0,DPW_LOG2[3:0]};
+  assign status_synth_params2 = {
+                   /*31:19 */  13'b0,
+                   /*   18 */  ENABLE_CHAR_REPLACE[0],
+                   /*17:13 */  5'b0,
+                   /*   12 */  ASYNC_CLK[0],
+                   /*11:10 */  2'b0,
+                   /* 9: 8 */  LINK_MODE[1:0],
+                   /* 7: 0 */  NUM_LINKS[7:0]};
 
 endmodule
diff --git a/library/jesd204/jesd204_tx/jesd204_tx_ctrl.v b/library/jesd204/jesd204_tx/jesd204_tx_ctrl.v
index c566403ad..3fe5800dc 100755
--- a/library/jesd204/jesd204_tx/jesd204_tx_ctrl.v
+++ b/library/jesd204/jesd204_tx/jesd204_tx_ctrl.v
@@ -85,294 +85,293 @@ module jesd204_tx_ctrl #(
   output reg [1:0] status_state
 );
 
-localparam ILAS_DATA_LENGTH = (DATA_PATH_WIDTH == 4) ? 4 : 2;
-localparam ILAS_COUNTER_WIDTH = (DATA_PATH_WIDTH == 4) ? 6 : 5;
-localparam DPW_LOG2 = DATA_PATH_WIDTH == 8 ? 3 : DATA_PATH_WIDTH == 4 ? 2 : 1;
-localparam BEATS_PER_MF_WIDTH = 10-DPW_LOG2;
+  localparam ILAS_DATA_LENGTH = (DATA_PATH_WIDTH == 4) ? 4 : 2;
+  localparam ILAS_COUNTER_WIDTH = (DATA_PATH_WIDTH == 4) ? 6 : 5;
+  localparam DPW_LOG2 = DATA_PATH_WIDTH == 8 ? 3 : DATA_PATH_WIDTH == 4 ? 2 : 1;
+  localparam BEATS_PER_MF_WIDTH = 10-DPW_LOG2;
 
-// For DATA_PATH_WIDTH = 8, special case if F*K%8=4
-//   Multiframe boundaries can occur in the middle of a beat
-//   jesd204_lmfc will assert lmfc_edge once per two LMFC periods
-//   cfg_mframes_per_ilas must be even
-wire [BEATS_PER_MF_WIDTH-1:0] cfg_beats_per_multiframe = cfg_octets_per_multiframe[9:DPW_LOG2];
-wire octets_per_mf_4_mod_8 = (DATA_PATH_WIDTH == 8) && ~cfg_octets_per_multiframe[2];
-wire [7:0] cfg_lmfc_per_ilas = octets_per_mf_4_mod_8 ? cfg_mframes_per_ilas/2 : cfg_mframes_per_ilas;
-reg lmfc_edge_d1 = 1'b0;
-reg lmfc_edge_d2 = 1'b0;
-reg eof_reset_d;
-reg ilas_reset = 1'b1;
-reg ilas_data_reset = 1'b1;
-reg sync_request = 1'b0;
-reg sync_request_received = 1'b0;
-reg last_ilas_mframe = 1'b0;
-reg [7:0] mframe_counter = 'h00;
-reg [ILAS_COUNTER_WIDTH-1:0] ilas_counter = 'h00;
-wire ilas_config_rd_start;
-reg ilas_config_rd_d1 = 1'b1;
-reg cgs_enable = 1'b1;
-wire [DATA_PATH_WIDTH*8-1:0] ilas_default_data;
+  // For DATA_PATH_WIDTH = 8, special case if F*K%8=4
+  //   Multiframe boundaries can occur in the middle of a beat
+  //   jesd204_lmfc will assert lmfc_edge once per two LMFC periods
+  //   cfg_mframes_per_ilas must be even
+  wire [BEATS_PER_MF_WIDTH-1:0] cfg_beats_per_multiframe = cfg_octets_per_multiframe[9:DPW_LOG2];
+  wire octets_per_mf_4_mod_8 = (DATA_PATH_WIDTH == 8) && ~cfg_octets_per_multiframe[2];
+  wire [7:0] cfg_lmfc_per_ilas = octets_per_mf_4_mod_8 ? cfg_mframes_per_ilas/2 : cfg_mframes_per_ilas;
+  reg lmfc_edge_d1 = 1'b0;
+  reg lmfc_edge_d2 = 1'b0;
+  reg eof_reset_d;
+  reg ilas_reset = 1'b1;
+  reg ilas_data_reset = 1'b1;
+  reg sync_request = 1'b0;
+  reg sync_request_received = 1'b0;
+  reg last_ilas_mframe = 1'b0;
+  reg [7:0] mframe_counter = 'h00;
+  reg [ILAS_COUNTER_WIDTH-1:0] ilas_counter = 'h00;
+  wire ilas_config_rd_start;
+  reg ilas_config_rd_d1 = 1'b1;
+  reg cgs_enable = 1'b1;
+  wire [DATA_PATH_WIDTH*8-1:0] ilas_default_data;
 
-wire [NUM_LINKS-1:0] status_sync_masked;
+  wire [NUM_LINKS-1:0] status_sync_masked;
 
-genvar ii;
-genvar jj;
+  genvar ii;
+  genvar jj;
 
-sync_bits #(
-  .NUM_OF_BITS (NUM_LINKS))
-i_cdc_sync (
-  .in_bits(sync),
-  .out_clk(clk),
-  .out_resetn(1'b1),
-  .out_bits(status_sync)
-);
+  sync_bits #(
+    .NUM_OF_BITS (NUM_LINKS)
+  ) i_cdc_sync (
+    .in_bits(sync),
+    .out_clk(clk),
+    .out_resetn(1'b1),
+    .out_bits(status_sync));
 
-assign status_sync_masked = status_sync | cfg_links_disable;
+  assign status_sync_masked = status_sync | cfg_links_disable;
 
-always @(posedge clk) begin
-  if (reset == 1'b1) begin
-    sync_request <= {NUM_LINKS{1'b0}};
-  end else begin
-    /* TODO: SYNC must be asserted at least 4 frames before interpreted as a
-     * sync request and the /K28.5/ symbol generation has lasted for at
-     * least 1 frame + 9 octets */
-    if (cfg_continuous_cgs == 1'b1) begin
-      sync_request <= 1'b1;
+  always @(posedge clk) begin
+    if (reset == 1'b1) begin
+      sync_request <= {NUM_LINKS{1'b0}};
     end else begin
-      sync_request <= ~(&status_sync_masked) | ctrl_manual_sync_request;
+      /* TODO: SYNC must be asserted at least 4 frames before interpreted as a
+       * sync request and the /K28.5/ symbol generation has lasted for at
+       * least 1 frame + 9 octets */
+      if (cfg_continuous_cgs == 1'b1) begin
+        sync_request <= 1'b1;
+      end else begin
+        sync_request <= ~(&status_sync_masked) | ctrl_manual_sync_request;
+      end
     end
   end
-end
 
-always @(posedge clk) begin
-  if (sync_request == 1'b0 && sync_request_received == 1'b1) begin
-    lmfc_edge_d1 <= lmfc_edge;
-    lmfc_edge_d2 <= lmfc_edge_d1;
-  end else begin
-    lmfc_edge_d1 <= 1'b0;
-    lmfc_edge_d2 <= 1'b0;
-  end
-end
-
-always @(posedge clk) begin
-  if (reset == 1'b1) begin
-    sync_request_received <= 1'b0;
-  end else if (sync_request == 1'b1) begin
-    sync_request_received <= 1'b1;
-  end
-end
-
-always @(posedge clk) begin
-  if (cfg_skip_ilas == 1'b1 ||
-    mframe_counter == cfg_lmfc_per_ilas) begin
-    last_ilas_mframe <= 1'b1;
-  end else begin
-    last_ilas_mframe <= 1'b0;
-  end
-end
-
-always @(*) begin
-  if (sync_request == 1'b1 || reset == 1'b1) begin
-    eof_reset = 1'b1;
-  end else if (lmfc_edge == 1'b1 && sync_request_received == 1'b1) begin
-    eof_reset = 1'b0;
-  end else begin
-    eof_reset = eof_reset_d;
-  end
-end
-
-always @(posedge clk) begin
-  eof_reset_d <= eof_reset;
-end
-
-localparam STATE_WAIT = 2'b00;
-localparam STATE_CGS = 2'b01;
-localparam STATE_ILAS = 2'b10;
-localparam STATE_DATA = 2'b11;
-
-/* Timeline
- *
- * #1 lmfc_edge == 1, ilas_reset update
- * #3 {lane_,}cgs_enable, tx_ready update
- *
- * One multi-frame should at least be 3 clock cycles (TBD 64-bit data path)
- */
-
-always @(posedge clk) begin
-  if (sync_request == 1'b1 || reset == 1'b1) begin
-    cgs_enable <= 1'b1;
-    lane_cgs_enable <= {NUM_LANES{1'b1}};
-    tx_ready <= 1'b0;
-    ilas_reset <= 1'b1;
-    ilas_data_reset <= 1'b1;
-
-    if (sync_request_received == 1'b0) begin
-      status_state <= STATE_WAIT;
+  always @(posedge clk) begin
+    if (sync_request == 1'b0 && sync_request_received == 1'b1) begin
+      lmfc_edge_d1 <= lmfc_edge;
+      lmfc_edge_d2 <= lmfc_edge_d1;
     end else begin
-      status_state <= STATE_CGS;
+      lmfc_edge_d1 <= 1'b0;
+      lmfc_edge_d2 <= 1'b0;
     end
-  end else if (sync_request_received == 1'b1) begin
-    if (lmfc_edge == 1'b1 && last_ilas_mframe == 1'b1) begin
+  end
+
+  always @(posedge clk) begin
+    if (reset == 1'b1) begin
+      sync_request_received <= 1'b0;
+    end else if (sync_request == 1'b1) begin
+      sync_request_received <= 1'b1;
+    end
+  end
+
+  always @(posedge clk) begin
+    if (cfg_skip_ilas == 1'b1 ||
+      mframe_counter == cfg_lmfc_per_ilas) begin
+      last_ilas_mframe <= 1'b1;
+    end else begin
+      last_ilas_mframe <= 1'b0;
+    end
+  end
+
+  always @(*) begin
+    if (sync_request == 1'b1 || reset == 1'b1) begin
+      eof_reset = 1'b1;
+    end else if (lmfc_edge == 1'b1 && sync_request_received == 1'b1) begin
+      eof_reset = 1'b0;
+    end else begin
+      eof_reset = eof_reset_d;
+    end
+  end
+
+  always @(posedge clk) begin
+    eof_reset_d <= eof_reset;
+  end
+
+  localparam STATE_WAIT = 2'b00;
+  localparam STATE_CGS = 2'b01;
+  localparam STATE_ILAS = 2'b10;
+  localparam STATE_DATA = 2'b11;
+
+  /* Timeline
+   *
+   * #1 lmfc_edge == 1, ilas_reset update
+   * #3 {lane_,}cgs_enable, tx_ready update
+   *
+   * One multi-frame should at least be 3 clock cycles (TBD 64-bit data path)
+   */
+
+  always @(posedge clk) begin
+    if (sync_request == 1'b1 || reset == 1'b1) begin
+      cgs_enable <= 1'b1;
+      lane_cgs_enable <= {NUM_LANES{1'b1}};
+      tx_ready <= 1'b0;
       ilas_reset <= 1'b1;
-      status_state <= STATE_DATA;
-    end else if (lmfc_edge_d1 == 1'b1 && (cfg_continuous_ilas == 1'b1 ||
-      cgs_enable == 1'b1)) begin
-      ilas_reset <= 1'b0;
-      status_state <= STATE_ILAS;
-    end
+      ilas_data_reset <= 1'b1;
 
-    if (lmfc_edge_d1 == 1'b1) begin
-      if (last_ilas_mframe == 1'b1 && cfg_continuous_ilas == 1'b0) begin
-        ilas_data_reset <= 1'b1;
-      end else if (cgs_enable == 1'b1) begin
-        ilas_data_reset <= 1'b0;
+      if (sync_request_received == 1'b0) begin
+        status_state <= STATE_WAIT;
+      end else begin
+        status_state <= STATE_CGS;
+      end
+    end else if (sync_request_received == 1'b1) begin
+      if (lmfc_edge == 1'b1 && last_ilas_mframe == 1'b1) begin
+        ilas_reset <= 1'b1;
+        status_state <= STATE_DATA;
+      end else if (lmfc_edge_d1 == 1'b1 && (cfg_continuous_ilas == 1'b1 ||
+        cgs_enable == 1'b1)) begin
+        ilas_reset <= 1'b0;
+        status_state <= STATE_ILAS;
       end
-    end
 
-    if (lmfc_edge_d2 == 1'b1) begin
-      lane_cgs_enable <= cfg_lanes_disable;
-      cgs_enable <= 1'b0;
-      if (last_ilas_mframe == 1'b1 && cfg_continuous_ilas == 1'b0) begin
-        tx_ready <= 1'b1;
+      if (lmfc_edge_d1 == 1'b1) begin
+        if (last_ilas_mframe == 1'b1 && cfg_continuous_ilas == 1'b0) begin
+          ilas_data_reset <= 1'b1;
+        end else if (cgs_enable == 1'b1) begin
+          ilas_data_reset <= 1'b0;
+        end
+      end
+
+      if (lmfc_edge_d2 == 1'b1) begin
+        lane_cgs_enable <= cfg_lanes_disable;
+        cgs_enable <= 1'b0;
+        if (last_ilas_mframe == 1'b1 && cfg_continuous_ilas == 1'b0) begin
+          tx_ready <= 1'b1;
+        end
       end
     end
   end
-end
 
-assign tx_next_mf_ready = sync_request_received & last_ilas_mframe & ~cfg_continuous_ilas;
-assign tx_ready_nx = tx_ready | (tx_next_mf_ready & lmfc_edge_d2);
+  assign tx_next_mf_ready = sync_request_received & last_ilas_mframe & ~cfg_continuous_ilas;
+  assign tx_ready_nx = tx_ready | (tx_next_mf_ready & lmfc_edge_d2);
 
-always @(posedge clk) begin
-  if (ilas_reset == 1'b1) begin
-    mframe_counter <= 'h00;
-  end else if (lmfc_edge_d1 == 1'b1) begin
-    mframe_counter <= mframe_counter + 1'b1;
+  always @(posedge clk) begin
+    if (ilas_reset == 1'b1) begin
+      mframe_counter <= 'h00;
+    end else if (lmfc_edge_d1 == 1'b1) begin
+      mframe_counter <= mframe_counter + 1'b1;
+    end
   end
-end
 
-always @(posedge clk) begin
-  if (ilas_reset == 1'b1) begin
-    ilas_config_rd <= 1'b0;
-  end else if (ilas_config_rd_start == 1'b1) begin
-    ilas_config_rd <= 1'b1;
-  end else if (ilas_config_addr == (ILAS_DATA_LENGTH-1)) begin
-    ilas_config_rd <= 1'b0;
+  always @(posedge clk) begin
+    if (ilas_reset == 1'b1) begin
+      ilas_config_rd <= 1'b0;
+    end else if (ilas_config_rd_start == 1'b1) begin
+      ilas_config_rd <= 1'b1;
+    end else if (ilas_config_addr == (ILAS_DATA_LENGTH-1)) begin
+      ilas_config_rd <= 1'b0;
+    end
+    ilas_config_rd_d1 <= ilas_config_rd;
   end
-  ilas_config_rd_d1 <= ilas_config_rd;
-end
 
-always @(posedge clk) begin
-  if (ilas_config_rd == 1'b0) begin
-    ilas_config_addr <= 'h00;
-  end else begin
-    ilas_config_addr <= ilas_config_addr + 1'b1;
+  always @(posedge clk) begin
+    if (ilas_config_rd == 1'b0) begin
+      ilas_config_addr <= 'h00;
+    end else begin
+      ilas_config_addr <= ilas_config_addr + 1'b1;
+    end
   end
-end
 
-always @(posedge clk) begin
-  if (ilas_reset == 1'b1) begin
-    ilas_counter <= 'h00;
-  end else begin
-    ilas_counter <= ilas_counter + 1'b1;
+  always @(posedge clk) begin
+    if (ilas_reset == 1'b1) begin
+      ilas_counter <= 'h00;
+    end else begin
+      ilas_counter <= ilas_counter + 1'b1;
+    end
   end
-end
 
-generate
-for(ii = 0; ii < DATA_PATH_WIDTH; ii=ii+1) begin : gen_default_data
-wire [(8-ILAS_COUNTER_WIDTH)-1:0] ii_sig = ii;
-assign ilas_default_data[(ii*8)+7:ii*8] = {ilas_counter, ii_sig};
-end
-endgenerate
+  generate
+  for(ii = 0; ii < DATA_PATH_WIDTH; ii=ii+1) begin : gen_default_data
+  wire [(8-ILAS_COUNTER_WIDTH)-1:0] ii_sig = ii;
+  assign ilas_default_data[(ii*8)+7:ii*8] = {ilas_counter, ii_sig};
+  end
+  endgenerate
 
-generate
-if(DATA_PATH_WIDTH == 4) begin : gen_dp4
+  generate
+  if(DATA_PATH_WIDTH == 4) begin : gen_dp4
 
-assign ilas_config_rd_start = mframe_counter == 'h00 && somf_early2[0];
+  assign ilas_config_rd_start = mframe_counter == 'h00 && somf_early2[0];
 
-always @(posedge clk) begin
-  if (ilas_data_reset == 1'b1) begin
-    ilas_data <= {NUM_LANES{32'h00}};
-    ilas_charisk <= {NUM_LANES{4'b0000}};
-  end else begin
-    if (ilas_config_rd_d1 == 1'b1) begin
-      case (ilas_config_addr)
-      2'h1: begin
-        ilas_data <= (ilas_config_data & {NUM_LANES{32'hffff0000}}) |
-          {NUM_LANES{16'h00,8'h9c,8'h1c}}; // /Q/ /R/
-        ilas_charisk <= {NUM_LANES{4'b0011}};
-      end
-      default: begin
-        ilas_data <= ilas_config_data;
+  always @(posedge clk) begin
+    if (ilas_data_reset == 1'b1) begin
+      ilas_data <= {NUM_LANES{32'h00}};
+      ilas_charisk <= {NUM_LANES{4'b0000}};
+    end else begin
+      if (ilas_config_rd_d1 == 1'b1) begin
+        case (ilas_config_addr)
+        2'h1: begin
+          ilas_data <= (ilas_config_data & {NUM_LANES{32'hffff0000}}) |
+            {NUM_LANES{16'h00,8'h9c,8'h1c}}; // /Q/ /R/
+          ilas_charisk <= {NUM_LANES{4'b0011}};
+        end
+        default: begin
+          ilas_data <= ilas_config_data;
+          ilas_charisk <= {NUM_LANES{4'b0000}};
+        end
+        endcase
+      end else if (lmfc_edge_d2 == 1'b1) begin
+        ilas_data <= {NUM_LANES{ilas_default_data[31:8],8'h1c}}; // /R/
+        ilas_charisk <= {NUM_LANES{4'b0001}};
+      end else if (lmfc_edge_d1 == 1'b1) begin
+        ilas_data <= {NUM_LANES{8'h7c,ilas_default_data[23:0]}}; // /A/
+        ilas_charisk <= {NUM_LANES{4'b1000}};
+      end else begin
+        ilas_data <= {NUM_LANES{ilas_default_data}};
         ilas_charisk <= {NUM_LANES{4'b0000}};
       end
-      endcase
-    end else if (lmfc_edge_d2 == 1'b1) begin
-      ilas_data <= {NUM_LANES{ilas_default_data[31:8],8'h1c}}; // /R/
-      ilas_charisk <= {NUM_LANES{4'b0001}};
-    end else if (lmfc_edge_d1 == 1'b1) begin
-      ilas_data <= {NUM_LANES{8'h7c,ilas_default_data[23:0]}}; // /A/
-      ilas_charisk <= {NUM_LANES{4'b1000}};
-    end else begin
-      ilas_data <= {NUM_LANES{ilas_default_data}};
-      ilas_charisk <= {NUM_LANES{4'b0000}};
     end
   end
-end
 
-end else if(DATA_PATH_WIDTH == 8) begin : gen_dp8
+  end else if(DATA_PATH_WIDTH == 8) begin : gen_dp8
 
-reg [63:0] ilas_config_data_d[NUM_LANES-1:0];
-reg ilas_config_rd_d2 = 1'b0;
+  reg [63:0] ilas_config_data_d[NUM_LANES-1:0];
+  reg ilas_config_rd_d2 = 1'b0;
 
-always @(posedge clk) begin
-  ilas_config_rd_d2 <= ilas_config_rd_d1;
-end
+  always @(posedge clk) begin
+    ilas_config_rd_d2 <= ilas_config_rd_d1;
+  end
 
-for(jj = 0; jj < NUM_LANES; jj = jj + 1) begin : gen_dp8_lane
+  for(jj = 0; jj < NUM_LANES; jj = jj + 1) begin : gen_dp8_lane
 
-assign ilas_config_rd_start = (mframe_counter == 'h00) && (octets_per_mf_4_mod_8 ? somf_early2[4] : somf_early2[0]);
+  assign ilas_config_rd_start = (mframe_counter == 'h00) && (octets_per_mf_4_mod_8 ? somf_early2[4] : somf_early2[0]);
 
-always @(posedge clk) begin
-  ilas_config_data_d[jj] <= {32'b0, ilas_config_data[(jj*64)+32+:32]};
-end
+  always @(posedge clk) begin
+    ilas_config_data_d[jj] <= {32'b0, ilas_config_data[(jj*64)+32+:32]};
+  end
 
-for(ii = 0; ii < DATA_PATH_WIDTH; ii=ii+1) begin : gen_ilas_data
+  for(ii = 0; ii < DATA_PATH_WIDTH; ii=ii+1) begin : gen_ilas_data
 
-always @(posedge clk) begin
-  if (ilas_data_reset) begin
-    ilas_data[(jj*64)+(ii*8)+:8] <= 8'h00;
-    ilas_charisk[(jj*8)+ii] <= 1'b0;
-  end else begin
-    if(somf[ii]) begin
-      ilas_data[(jj*64)+(ii*8)+:8] <= 8'h1c; // /R/
-      ilas_charisk[(jj*8)+ii] <= 1'b1;
-    end else if(eomf[ii]) begin
-      ilas_data[(jj*64)+(ii*8)+:8] <= 8'h7c; // /A/
-      ilas_charisk[(jj*8)+ii] <= 1'b1;
-    end else if (ilas_config_rd_d1 &&
-                 (ilas_config_addr == 2'h1) && 
-                 ((octets_per_mf_4_mod_8 && (ii == 5)) ||
-                   (!octets_per_mf_4_mod_8 && (ii == 1)))) begin
-        ilas_data[(jj*64)+(ii*8)+:8] <= 8'h9c; // /Q/
+  always @(posedge clk) begin
+    if (ilas_data_reset) begin
+      ilas_data[(jj*64)+(ii*8)+:8] <= 8'h00;
+      ilas_charisk[(jj*8)+ii] <= 1'b0;
+    end else begin
+      if(somf[ii]) begin
+        ilas_data[(jj*64)+(ii*8)+:8] <= 8'h1c; // /R/
         ilas_charisk[(jj*8)+ii] <= 1'b1;
-    end else if (octets_per_mf_4_mod_8 && ilas_config_rd_d2 && (ii < 4)) begin
-      ilas_data[(jj*64)+(ii*8)+:8] <= ilas_config_data_d[jj][ii*8+:8];
-      ilas_charisk[(jj*8)+ii] <= 1'b0;
-    end else if (octets_per_mf_4_mod_8 && ilas_config_rd_d1 && (ii >= 4)) begin
-      ilas_data[(jj*64)+(ii*8)+:8] <= ilas_config_data[(jj*64)+((ii-4)*8)+:8];
-      ilas_charisk[(jj*8)+ii] <= 1'b0;
-    end else if (!octets_per_mf_4_mod_8 && ilas_config_rd_d1) begin
-      ilas_data[(jj*64)+(ii*8)+:8] <= ilas_config_data[(jj*64)+(ii*8)+:8];
-      ilas_charisk[(jj*8)+ii] <= 1'b0;
-    end else begin
-      ilas_data[(jj*64)+(ii*8)+:8] <= ilas_default_data[ii*8+:8];
-      ilas_charisk[(jj*8)+ii] <= 1'b0;
+      end else if(eomf[ii]) begin
+        ilas_data[(jj*64)+(ii*8)+:8] <= 8'h7c; // /A/
+        ilas_charisk[(jj*8)+ii] <= 1'b1;
+      end else if (ilas_config_rd_d1 &&
+                   (ilas_config_addr == 2'h1) &&
+                   ((octets_per_mf_4_mod_8 && (ii == 5)) ||
+                     (!octets_per_mf_4_mod_8 && (ii == 1)))) begin
+          ilas_data[(jj*64)+(ii*8)+:8] <= 8'h9c; // /Q/
+          ilas_charisk[(jj*8)+ii] <= 1'b1;
+      end else if (octets_per_mf_4_mod_8 && ilas_config_rd_d2 && (ii < 4)) begin
+        ilas_data[(jj*64)+(ii*8)+:8] <= ilas_config_data_d[jj][ii*8+:8];
+        ilas_charisk[(jj*8)+ii] <= 1'b0;
+      end else if (octets_per_mf_4_mod_8 && ilas_config_rd_d1 && (ii >= 4)) begin
+        ilas_data[(jj*64)+(ii*8)+:8] <= ilas_config_data[(jj*64)+((ii-4)*8)+:8];
+        ilas_charisk[(jj*8)+ii] <= 1'b0;
+      end else if (!octets_per_mf_4_mod_8 && ilas_config_rd_d1) begin
+        ilas_data[(jj*64)+(ii*8)+:8] <= ilas_config_data[(jj*64)+(ii*8)+:8];
+        ilas_charisk[(jj*8)+ii] <= 1'b0;
+      end else begin
+        ilas_data[(jj*64)+(ii*8)+:8] <= ilas_default_data[ii*8+:8];
+        ilas_charisk[(jj*8)+ii] <= 1'b0;
+      end
     end
   end
-end
 
-end
-end
-end
-endgenerate
+  end
+  end
+  end
+  endgenerate
 
 endmodule
diff --git a/library/jesd204/jesd204_tx/jesd204_tx_gearbox.v b/library/jesd204/jesd204_tx/jesd204_tx_gearbox.v
index cfe02f58b..85669e9fe 100644
--- a/library/jesd204/jesd204_tx/jesd204_tx_gearbox.v
+++ b/library/jesd204/jesd204_tx/jesd204_tx_gearbox.v
@@ -64,81 +64,78 @@ module jesd204_tx_gearbox #(
   input output_ready
 );
 
-localparam MEM_W = IN_DATA_PATH_WIDTH*8*NUM_LANES;
-localparam D_LOG2 = $clog2(DEPTH);
+  localparam MEM_W = IN_DATA_PATH_WIDTH*8*NUM_LANES;
+  localparam D_LOG2 = $clog2(DEPTH);
 
-reg [MEM_W-1:0] mem [0:DEPTH-1];
-reg [D_LOG2-1:0]  in_addr ='h00;
-reg [D_LOG2-1:0]  out_addr = 'b0;
-reg               mem_rd_valid = 'b0;
-reg [MEM_W-1:0]  mem_rd_data;
+  reg [MEM_W-1:0] mem [0:DEPTH-1];
+  reg [D_LOG2-1:0]  in_addr ='h00;
+  reg [D_LOG2-1:0]  out_addr = 'b0;
+  reg               mem_rd_valid = 'b0;
+  reg [MEM_W-1:0]  mem_rd_data;
 
-wire                mem_wr_en = 1'b1;
-wire                mem_rd_en;
-wire [D_LOG2-1:0]  in_out_addr;
-wire [D_LOG2-1:0]  out_in_addr;
-wire [NUM_LANES-1:0] unpacker_ready;
-wire output_ready_sync;
+  wire                mem_wr_en = 1'b1;
+  wire                mem_rd_en;
+  wire [D_LOG2-1:0]  in_out_addr;
+  wire [D_LOG2-1:0]  out_in_addr;
+  wire [NUM_LANES-1:0] unpacker_ready;
+  wire output_ready_sync;
 
-sync_bits i_sync_ready (
-  .in_bits(output_ready),
-  .out_resetn(~device_reset),
-  .out_clk(device_clk),
-  .out_bits(output_ready_sync)
-);
+  sync_bits i_sync_ready (
+    .in_bits(output_ready),
+    .out_resetn(~device_reset),
+    .out_clk(device_clk),
+    .out_bits(output_ready_sync));
 
-always @(posedge device_clk) begin
-  if (device_lmfc_edge & ~output_ready_sync) begin
-    in_addr <= 'h01;
-  end else if (mem_wr_en) begin
-    in_addr <= in_addr + 1;
+  always @(posedge device_clk) begin
+    if (device_lmfc_edge & ~output_ready_sync) begin
+      in_addr <= 'h01;
+    end else if (mem_wr_en) begin
+      in_addr <= in_addr + 1;
+    end
   end
-end
 
-always @(posedge device_clk) begin
-  if (mem_wr_en) begin
-    mem[in_addr] <= device_data;
+  always @(posedge device_clk) begin
+    if (mem_wr_en) begin
+      mem[in_addr] <= device_data;
+    end
   end
-end
 
-assign mem_rd_en = output_ready&unpacker_ready[0];
+  assign mem_rd_en = output_ready&unpacker_ready[0];
 
-always @(posedge link_clk) begin
-  if (mem_rd_en) begin
-    mem_rd_data <= mem[out_addr];
+  always @(posedge link_clk) begin
+    if (mem_rd_en) begin
+      mem_rd_data <= mem[out_addr];
+    end
+    mem_rd_valid <= mem_rd_en;
   end
-  mem_rd_valid <= mem_rd_en;
-end
 
-always @(posedge link_clk) begin
-  if (reset) begin
-    out_addr <= 'b0;
-  end else if (mem_rd_en) begin
-    out_addr <= out_addr + 1;
+  always @(posedge link_clk) begin
+    if (reset) begin
+      out_addr <= 'b0;
+    end else if (mem_rd_en) begin
+      out_addr <= out_addr + 1;
+    end
   end
-end
 
-genvar i;
-generate for (i = 0; i < NUM_LANES; i=i+1) begin: unpacker
+  genvar i;
+  generate for (i = 0; i < NUM_LANES; i=i+1) begin: unpacker
 
-ad_upack #(
-  .I_W(IN_DATA_PATH_WIDTH),
-  .O_W(OUT_DATA_PATH_WIDTH),
-  .UNIT_W(8),
-  .O_REG(0)
-) i_ad_upack (
-  .clk(link_clk),
-  .reset(reset),
-  .idata(mem_rd_data[i*IN_DATA_PATH_WIDTH*8+:IN_DATA_PATH_WIDTH*8]),
-  .ivalid(mem_rd_valid),
-  .iready(unpacker_ready[i]),
+  ad_upack #(
+    .I_W(IN_DATA_PATH_WIDTH),
+    .O_W(OUT_DATA_PATH_WIDTH),
+    .UNIT_W(8),
+    .O_REG(0)
+  ) i_ad_upack (
+    .clk(link_clk),
+    .reset(reset),
+    .idata(mem_rd_data[i*IN_DATA_PATH_WIDTH*8+:IN_DATA_PATH_WIDTH*8]),
+    .ivalid(mem_rd_valid),
+    .iready(unpacker_ready[i]),
 
-  .odata(link_data[i*OUT_DATA_PATH_WIDTH*8+:OUT_DATA_PATH_WIDTH*8]),
-  .ovalid()
-);
+    .odata(link_data[i*OUT_DATA_PATH_WIDTH*8+:OUT_DATA_PATH_WIDTH*8]),
+    .ovalid());
 
-end
-endgenerate
+  end
+  endgenerate
 
 endmodule
-
diff --git a/library/jesd204/jesd204_tx/jesd204_tx_header.v b/library/jesd204/jesd204_tx/jesd204_tx_header.v
index 347247343..c3a08c5b3 100644
--- a/library/jesd204/jesd204_tx/jesd204_tx_header.v
+++ b/library/jesd204/jesd204_tx/jesd204_tx_header.v
@@ -61,13 +61,11 @@ module jesd204_tx_header (
   input [18:0] cmd,
 
   output [1:0] header
-
 );
 
   reg header_bit;
   reg [31:0] sync_word = 'h0;
 
-
   always @(posedge clk) begin
     if (reset) begin
       sync_word <= 'h0;
diff --git a/library/jesd204/jesd204_tx/jesd204_tx_lane.v b/library/jesd204/jesd204_tx/jesd204_tx_lane.v
index ff571def9..261fc68ab 100755
--- a/library/jesd204/jesd204_tx/jesd204_tx_lane.v
+++ b/library/jesd204/jesd204_tx/jesd204_tx_lane.v
@@ -69,115 +69,112 @@ module jesd204_tx_lane #(
   input cfg_disable_scrambler
 );
 
-wire [DATA_PATH_WIDTH*8-1:0] scrambled_data;
-wire [DATA_PATH_WIDTH*8-1:0] scrambled_data_d;
-wire                         cgs_enable_d;
-wire                         tx_ready_d;
-wire [DATA_PATH_WIDTH-1:0]   eof_d;
-wire [DATA_PATH_WIDTH-1:0]   eomf_d;
-wire [DATA_PATH_WIDTH*8-1:0] ilas_data_d;
-wire [DATA_PATH_WIDTH-1:0]   ilas_charisk_d;
-wire [DATA_PATH_WIDTH*8-1:0] data_replaced;
-wire [DATA_PATH_WIDTH-1:0]   charisk_replaced;
-wire [7:0]                   scrambled_char[0:DATA_PATH_WIDTH-1];
-reg  [7:0]                   char_align[0:DATA_PATH_WIDTH-1];
+  wire [DATA_PATH_WIDTH*8-1:0] scrambled_data;
+  wire [DATA_PATH_WIDTH*8-1:0] scrambled_data_d;
+  wire                         cgs_enable_d;
+  wire                         tx_ready_d;
+  wire [DATA_PATH_WIDTH-1:0]   eof_d;
+  wire [DATA_PATH_WIDTH-1:0]   eomf_d;
+  wire [DATA_PATH_WIDTH*8-1:0] ilas_data_d;
+  wire [DATA_PATH_WIDTH-1:0]   ilas_charisk_d;
+  wire [DATA_PATH_WIDTH*8-1:0] data_replaced;
+  wire [DATA_PATH_WIDTH-1:0]   charisk_replaced;
+  wire [7:0]                   scrambled_char[0:DATA_PATH_WIDTH-1];
+  reg  [7:0]                   char_align[0:DATA_PATH_WIDTH-1];
 
-jesd204_scrambler #(
-  .WIDTH(DATA_PATH_WIDTH*8),
-  .DESCRAMBLE(0)
-) i_scrambler (
-  .clk(clk),
-  .reset(~tx_ready),
-  .enable(~cfg_disable_scrambler),
-  .data_in(tx_data),
-  .data_out(scrambled_data)
-);
+  jesd204_scrambler #(
+    .WIDTH (DATA_PATH_WIDTH*8),
+    .DESCRAMBLE (0)
+  ) i_scrambler (
+    .clk (clk),
+    .reset (~tx_ready),
+    .enable (~cfg_disable_scrambler),
+    .data_in (tx_data),
+    .data_out (scrambled_data));
 
-pipeline_stage #(
-  .WIDTH((DATA_PATH_WIDTH*19) + 2),
-  .REGISTERED(1)
-) i_lane_pipeline_stage (
-  .clk(clk),
-  .in({
-    cgs_enable,
-    tx_ready,
-    eof,
-    eomf,
-    scrambled_data,
-    ilas_data,
-    ilas_charisk
-  }),
-  .out({
-    cgs_enable_d,
-    tx_ready_d,
-    eof_d,
-    eomf_d,
-    scrambled_data_d,
-    ilas_data_d,
-    ilas_charisk_d
-  })
-);
+  pipeline_stage #(
+    .WIDTH ((DATA_PATH_WIDTH*19) + 2),
+    .REGISTERED (1)
+  ) i_lane_pipeline_stage (
+    .clk(clk),
+    .in({
+      cgs_enable,
+      tx_ready,
+      eof,
+      eomf,
+      scrambled_data,
+      ilas_data,
+      ilas_charisk
+    }),
+    .out({
+      cgs_enable_d,
+      tx_ready_d,
+      eof_d,
+      eomf_d,
+      scrambled_data_d,
+      ilas_data_d,
+      ilas_charisk_d
+    }));
 
-jesd204_frame_align_replace #(
-  .DATA_PATH_WIDTH              (DATA_PATH_WIDTH),
-  .IS_RX                        (1'b0),
-  .ENABLED                      (ENABLE_CHAR_REPLACE)
-) i_align_replace (
-  .clk                          (clk),
-  .reset                        (~tx_ready_d),
-  .cfg_octets_per_frame         (cfg_octets_per_frame),
-  .cfg_disable_char_replacement (cfg_disable_char_replacement),
-  .cfg_disable_scrambler        (cfg_disable_scrambler),
-  .data                         (scrambled_data_d),
-  .eof                          (eof_d),
-  .rx_char_is_a                 ({DATA_PATH_WIDTH{1'b0}}),
-  .rx_char_is_f                 ({DATA_PATH_WIDTH{1'b0}}),
-  .tx_eomf                      (eomf_d),
-  .data_out                     (data_replaced),
-  .charisk_out                  (charisk_replaced)
-);
+  jesd204_frame_align_replace #(
+    .DATA_PATH_WIDTH (DATA_PATH_WIDTH),
+    .IS_RX (1'b0),
+    .ENABLED (ENABLE_CHAR_REPLACE)
+  ) i_align_replace (
+    .clk (clk),
+    .reset (~tx_ready_d),
+    .cfg_octets_per_frame (cfg_octets_per_frame),
+    .cfg_disable_char_replacement (cfg_disable_char_replacement),
+    .cfg_disable_scrambler (cfg_disable_scrambler),
+    .data (scrambled_data_d),
+    .eof (eof_d),
+    .rx_char_is_a ({DATA_PATH_WIDTH{1'b0}}),
+    .rx_char_is_f ({DATA_PATH_WIDTH{1'b0}}),
+    .tx_eomf (eomf_d),
+    .data_out (data_replaced),
+    .charisk_out (charisk_replaced));
 
-generate
-genvar i;
+  generate
+  genvar i;
 
-for (i = 0; i < DATA_PATH_WIDTH; i = i + 1) begin: gen_char
-  assign scrambled_char[i] = scrambled_data_d[i*8+7:i*8];
+  for (i = 0; i < DATA_PATH_WIDTH; i = i + 1) begin: gen_char
+    assign scrambled_char[i] = scrambled_data_d[i*8+7:i*8];
 
-  always @(*) begin
-    if (eomf_d[i]) begin
-      char_align[i] = 8'h7c; // /A/
-    end else begin
-      char_align[i] = 8'hfc; // /F/
+    always @(*) begin
+      if (eomf_d[i]) begin
+        char_align[i] = 8'h7c; // /A/
+      end else begin
+        char_align[i] = 8'hfc; // /F/
+      end
+    end
+
+    always @(posedge clk) begin
+      if (cgs_enable_d) begin
+        phy_charisk[i] <= 1'b1;
+      end else if (tx_ready_d) begin
+        if(!cfg_disable_scrambler) begin
+          phy_charisk[i] <= eof_d[i] && (scrambled_char[i] == char_align[i]);
+        end else begin
+          phy_charisk[i] <= charisk_replaced[i];
+        end
+      end else begin
+        phy_charisk[i] <= ilas_charisk_d[i];
+      end
     end
   end
 
+  endgenerate
+
   always @(posedge clk) begin
     if (cgs_enable_d) begin
-      phy_charisk[i] <= 1'b1;
-    end else if (tx_ready_d) begin
-      if(!cfg_disable_scrambler) begin
-        phy_charisk[i] <= eof_d[i] && (scrambled_char[i] == char_align[i]);
+      phy_data <= {DATA_PATH_WIDTH{8'hbc}};
+    end else begin
+      if(tx_ready_d) begin
+        phy_data <= data_replaced;
       end else begin
-        phy_charisk[i] <= charisk_replaced[i];
+        phy_data <= ilas_data_d;
       end
-    end else begin
-      phy_charisk[i] <= ilas_charisk_d[i];
     end
   end
-end
-
-endgenerate
-
-always @(posedge clk) begin
-  if (cgs_enable_d) begin
-    phy_data <= {DATA_PATH_WIDTH{8'hbc}};
-  end else begin
-    if(tx_ready_d) begin
-      phy_data <= data_replaced;
-    end else begin
-      phy_data <= ilas_data_d;
-    end
-  end
-end
 
 endmodule
diff --git a/library/jesd204/jesd204_tx/jesd204_tx_lane_64b.v b/library/jesd204/jesd204_tx/jesd204_tx_lane_64b.v
index 262aeb7dd..289d8c113 100644
--- a/library/jesd204/jesd204_tx/jesd204_tx_lane_64b.v
+++ b/library/jesd204/jesd204_tx/jesd204_tx_lane_64b.v
@@ -62,82 +62,76 @@ module jesd204_tx_lane_64b (
   input cfg_disable_scrambler,
   input [1:0] cfg_header_mode,
   input cfg_lane_disable
-
 );
 
-reg [63:0] scrambled_data;
-reg lmc_edge_d1 = 'b0;
-reg lmc_edge_d2 = 'b0;
-reg lmc_quarter_edge_d1 = 'b0;
-reg lmc_quarter_edge_d2 = 'b0;
-reg tx_ready_d1 = 'b0;
+  reg [63:0] scrambled_data;
+  reg lmc_edge_d1 = 'b0;
+  reg lmc_edge_d2 = 'b0;
+  reg lmc_quarter_edge_d1 = 'b0;
+  reg lmc_quarter_edge_d2 = 'b0;
+  reg tx_ready_d1 = 'b0;
 
-wire [63:0] tx_data_msb_s;
-wire [63:0] scrambled_data_r;
-wire [11:0] crc12;
+  wire [63:0] tx_data_msb_s;
+  wire [63:0] scrambled_data_r;
+  wire [11:0] crc12;
 
-/* Reorder octets MSB first */
-genvar i;
-generate
-  for (i = 0; i < 64; i = i + 8) begin: g_link_data
-    assign tx_data_msb_s[i+:8] = tx_data[64-1-i-:8];
+  /* Reorder octets MSB first */
+  genvar i;
+  generate
+    for (i = 0; i < 64; i = i + 8) begin: g_link_data
+      assign tx_data_msb_s[i+:8] = tx_data[64-1-i-:8];
+    end
+  endgenerate
+
+  jesd204_scrambler_64b #(
+    .WIDTH(64),
+    .DESCRAMBLE(0)
+  ) i_scrambler (
+    .clk(clk),
+    .reset(1'b0),
+    .enable(~cfg_disable_scrambler),
+    .data_in(tx_data_msb_s),
+    .data_out(scrambled_data_r));
+
+  always @(posedge clk) begin
+    lmc_edge_d1 <= lmc_edge;
+    lmc_edge_d2 <= lmc_edge_d1;
+    lmc_quarter_edge_d1 <= lmc_quarter_edge;
+    lmc_quarter_edge_d2 <= lmc_quarter_edge_d1;
   end
-endgenerate
 
-jesd204_scrambler_64b #(
-  .WIDTH(64),
-  .DESCRAMBLE(0)
-) i_scrambler (
-  .clk(clk),
-  .reset(1'b0),
-  .enable(~cfg_disable_scrambler),
-  .data_in(tx_data_msb_s),
-  .data_out(scrambled_data_r)
-);
+  always @(posedge clk) begin
+    scrambled_data <= scrambled_data_r;
+    phy_data <= scrambled_data;
+  end
 
-always @(posedge clk) begin
-  lmc_edge_d1 <= lmc_edge;
-  lmc_edge_d2 <= lmc_edge_d1;
-  lmc_quarter_edge_d1 <= lmc_quarter_edge;
-  lmc_quarter_edge_d2 <= lmc_quarter_edge_d1;
-end
+  always @(posedge clk) begin
+    tx_ready_d1 <= tx_ready;
+  end
 
-always @(posedge clk) begin
-  scrambled_data <= scrambled_data_r;
-  phy_data <= scrambled_data;
-end
+  jesd204_crc12 i_crc12 (
+    .clk(clk),
+    .reset(~tx_ready_d1),
+    .init(lmc_edge_d2),
+    .data_in(scrambled_data),
+    .crc12(crc12));
 
-always @(posedge clk) begin
-  tx_ready_d1 <= tx_ready;
-end
+  jesd204_tx_header i_header_gen (
+    .clk(clk),
+    .reset(~tx_ready | cfg_lane_disable),
 
-jesd204_crc12 i_crc12 (
-  .clk(clk),
-  .reset(~tx_ready_d1),
-  .init(lmc_edge_d2),
-  .data_in(scrambled_data),
-  .crc12(crc12)
-);
+    .cfg_header_mode(cfg_header_mode),
 
-jesd204_tx_header i_header_gen (
-  .clk(clk),
-  .reset(~tx_ready | cfg_lane_disable),
+    .lmc_edge(lmc_edge_d2),
+    .lmc_quarter_edge(lmc_quarter_edge_d2),
 
-  .cfg_header_mode(cfg_header_mode),
-
-  .lmc_edge(lmc_edge_d2),
-  .lmc_quarter_edge(lmc_quarter_edge_d2),
-
-  // Header content to be sent must be valid during lmc_edge
-  .eoemb(eoemb),
-  .crc3(3'b0),
-  .crc12(crc12),
-  .fec(26'b0),
-  .cmd(19'b0),
-
-  .header(phy_header)
-
-);
+    // Header content to be sent must be valid during lmc_edge
+    .eoemb(eoemb),
+    .crc3(3'b0),
+    .crc12(crc12),
+    .fec(26'b0),
+    .cmd(19'b0),
 
+    .header(phy_header));
 
 endmodule
diff --git a/library/jesd204/jesd204_tx_static_config/jesd204_ilas_cfg_static.v b/library/jesd204/jesd204_tx_static_config/jesd204_ilas_cfg_static.v
index 3a2b8dbfc..7e0ade95f 100755
--- a/library/jesd204/jesd204_tx_static_config/jesd204_ilas_cfg_static.v
+++ b/library/jesd204/jesd204_tx_static_config/jesd204_ilas_cfg_static.v
@@ -70,67 +70,67 @@ module jesd204_ilas_cfg_static #(
   output reg [NUM_LANES*DATA_PATH_WIDTH*8-1:0] ilas_config_data
 );
 
-wire [31:0] ilas_mem[0:3];
-reg  [31:0] ilas_lane_mem[0:NUM_LANES-1][0:3];
+  wire [31:0] ilas_mem[0:3];
+  reg  [31:0] ilas_lane_mem[0:NUM_LANES-1][0:3];
 
-assign ilas_mem[0][15:0] = 8'h00;
-assign ilas_mem[0][23:16] = DID;         // DID
-assign ilas_mem[0][27:24] = BID;         // BID
-assign ilas_mem[0][31:28] = 4'h0;        // ADJCNT
-assign ilas_mem[1][4:0] = 5'h00;         // LID
-assign ilas_mem[1][5] = 1'b0;            // PHADJ
-assign ilas_mem[1][6] = 1'b0;            // ADJDIR
-assign ilas_mem[1][7] = 1'b0;            // X
-assign ilas_mem[1][12:8] = L;            // L
-assign ilas_mem[1][14:13] = 2'b00;       // X
-assign ilas_mem[1][15] = SCR;            // SCR
-assign ilas_mem[1][23:16] = F;           // F
-assign ilas_mem[1][28:24] = K;           // K
-assign ilas_mem[1][31:29] = 3'b000;      // X
-assign ilas_mem[2][7:0] = M;             // M
-assign ilas_mem[2][12:8] = N;            // N
-assign ilas_mem[2][13] = 1'b0;           // X
-assign ilas_mem[2][15:14] = CS;          // CS
-assign ilas_mem[2][20:16] = NP;          // N'
-assign ilas_mem[2][23:21] = SUBCLASSV;   // SUBCLASSV
-assign ilas_mem[2][28:24] = S;           // S
-assign ilas_mem[2][31:29] = JESDV;       // JESDV
-assign ilas_mem[3][4:0] = CF;            // CF
-assign ilas_mem[3][6:5] = 2'b00;         // X
-assign ilas_mem[3][7] = HD;              // HD
-assign ilas_mem[3][23:8] = 16'h0000;     // X
-assign ilas_mem[3][31:24] = ilas_mem[0][23:16] + ilas_mem[0][31:24] +
-  ilas_mem[1][4:0] + ilas_mem[1][5] + ilas_mem[1][6] + ilas_mem[1][12:8] +
-  ilas_mem[1][15] + ilas_mem[1][23:16] + ilas_mem[1][28:24] +
-  ilas_mem[2][7:0] + ilas_mem[2][12:8] + ilas_mem[2][15:14] +
-  ilas_mem[2][20:16] + ilas_mem[2][23:21] + ilas_mem[2][28:24] +
-  ilas_mem[2][31:29] + ilas_mem[3][4:0] + ilas_mem[3][7];
+  assign ilas_mem[0][15:0] = 8'h00;
+  assign ilas_mem[0][23:16] = DID;         // DID
+  assign ilas_mem[0][27:24] = BID;         // BID
+  assign ilas_mem[0][31:28] = 4'h0;        // ADJCNT
+  assign ilas_mem[1][4:0] = 5'h00;         // LID
+  assign ilas_mem[1][5] = 1'b0;            // PHADJ
+  assign ilas_mem[1][6] = 1'b0;            // ADJDIR
+  assign ilas_mem[1][7] = 1'b0;            // X
+  assign ilas_mem[1][12:8] = L;            // L
+  assign ilas_mem[1][14:13] = 2'b00;       // X
+  assign ilas_mem[1][15] = SCR;            // SCR
+  assign ilas_mem[1][23:16] = F;           // F
+  assign ilas_mem[1][28:24] = K;           // K
+  assign ilas_mem[1][31:29] = 3'b000;      // X
+  assign ilas_mem[2][7:0] = M;             // M
+  assign ilas_mem[2][12:8] = N;            // N
+  assign ilas_mem[2][13] = 1'b0;           // X
+  assign ilas_mem[2][15:14] = CS;          // CS
+  assign ilas_mem[2][20:16] = NP;          // N'
+  assign ilas_mem[2][23:21] = SUBCLASSV;   // SUBCLASSV
+  assign ilas_mem[2][28:24] = S;           // S
+  assign ilas_mem[2][31:29] = JESDV;       // JESDV
+  assign ilas_mem[3][4:0] = CF;            // CF
+  assign ilas_mem[3][6:5] = 2'b00;         // X
+  assign ilas_mem[3][7] = HD;              // HD
+  assign ilas_mem[3][23:8] = 16'h0000;     // X
+  assign ilas_mem[3][31:24] = ilas_mem[0][23:16] + ilas_mem[0][31:24] +
+    ilas_mem[1][4:0] + ilas_mem[1][5] + ilas_mem[1][6] + ilas_mem[1][12:8] +
+    ilas_mem[1][15] + ilas_mem[1][23:16] + ilas_mem[1][28:24] +
+    ilas_mem[2][7:0] + ilas_mem[2][12:8] + ilas_mem[2][15:14] +
+    ilas_mem[2][20:16] + ilas_mem[2][23:21] + ilas_mem[2][28:24] +
+    ilas_mem[2][31:29] + ilas_mem[3][4:0] + ilas_mem[3][7];
 
-generate
-genvar i;
-genvar j;
+  generate
+  genvar i;
+  genvar j;
 
-for (i = 0; i < NUM_LANES; i = i + 1) begin: gen_lane
-  for(j = 0; j < 4; j = j + 1) begin : gen_word
-    always @(*) begin
-      ilas_lane_mem[i][j] = ilas_mem[j];
-      case(j)
-        1: ilas_lane_mem[i][j][4:0] = i;
-        3: ilas_lane_mem[i][j][31:24] = ilas_mem[3][31:24] + i;
-      endcase
+  for (i = 0; i < NUM_LANES; i = i + 1) begin: gen_lane
+    for(j = 0; j < 4; j = j + 1) begin : gen_word
+      always @(*) begin
+        ilas_lane_mem[i][j] = ilas_mem[j];
+        case(j)
+          1: ilas_lane_mem[i][j][4:0] = i;
+          3: ilas_lane_mem[i][j][31:24] = ilas_mem[3][31:24] + i;
+        endcase
+      end
     end
-  end
 
-  always @(posedge clk) begin
-    if (ilas_config_rd == 1'b1) begin
-      if(DATA_PATH_WIDTH == 4) begin
-        ilas_config_data[i*32+31:i*32] <= ilas_lane_mem[i][ilas_config_addr];
-      end else begin
-        ilas_config_data[i*64+63:i*64] <= {ilas_lane_mem[i][{ilas_config_addr[0], 1'b1}], ilas_lane_mem[i][{ilas_config_addr[0], 1'b0}]};
+    always @(posedge clk) begin
+      if (ilas_config_rd == 1'b1) begin
+        if(DATA_PATH_WIDTH == 4) begin
+          ilas_config_data[i*32+31:i*32] <= ilas_lane_mem[i][ilas_config_addr];
+        end else begin
+          ilas_config_data[i*64+63:i*64] <= {ilas_lane_mem[i][{ilas_config_addr[0], 1'b1}], ilas_lane_mem[i][{ilas_config_addr[0], 1'b0}]};
+        end
       end
     end
   end
-end
-endgenerate
+  endgenerate
 
 endmodule
diff --git a/library/jesd204/jesd204_tx_static_config/jesd204_tx_static_config.v b/library/jesd204/jesd204_tx_static_config/jesd204_tx_static_config.v
index 64f36f797..848f90a0a 100755
--- a/library/jesd204/jesd204_tx_static_config/jesd204_tx_static_config.v
+++ b/library/jesd204/jesd204_tx_static_config/jesd204_tx_static_config.v
@@ -86,47 +86,46 @@ module jesd204_tx_static_config #(
   output [NUM_LANES*DATA_PATH_WIDTH*8-1:0] ilas_config_data
 );
 
-assign cfg_lanes_disable = {NUM_LANES{1'b0}};
-assign cfg_links_disable = {NUM_LINKS{1'b0}};
-assign cfg_octets_per_multiframe = (FRAMES_PER_MULTIFRAME * OCTETS_PER_FRAME) - 1;
-assign cfg_octets_per_frame = OCTETS_PER_FRAME - 1;
-assign cfg_continuous_cgs = 1'b0;
-assign cfg_continuous_ilas = 1'b0;
-assign cfg_skip_ilas = 1'b0;
-assign cfg_mframes_per_ilas = 3;
-assign cfg_disable_char_replacement = 1'b0;
-assign cfg_disable_scrambler = SCR ? 1'b0 : 1'b1;
+  assign cfg_lanes_disable = {NUM_LANES{1'b0}};
+  assign cfg_links_disable = {NUM_LINKS{1'b0}};
+  assign cfg_octets_per_multiframe = (FRAMES_PER_MULTIFRAME * OCTETS_PER_FRAME) - 1;
+  assign cfg_octets_per_frame = OCTETS_PER_FRAME - 1;
+  assign cfg_continuous_cgs = 1'b0;
+  assign cfg_continuous_ilas = 1'b0;
+  assign cfg_skip_ilas = 1'b0;
+  assign cfg_mframes_per_ilas = 3;
+  assign cfg_disable_char_replacement = 1'b0;
+  assign cfg_disable_scrambler = SCR ? 1'b0 : 1'b1;
 
-assign device_cfg_octets_per_multiframe = (FRAMES_PER_MULTIFRAME * OCTETS_PER_FRAME) - 1;
-assign device_cfg_octets_per_frame = OCTETS_PER_FRAME - 1;
-assign device_cfg_beats_per_multiframe = ((FRAMES_PER_MULTIFRAME * OCTETS_PER_FRAME) /
-                                          TPL_DATA_PATH_WIDTH) - 1;
-assign device_cfg_lmfc_offset = 1;
-assign device_cfg_sysref_oneshot = SYSREF_ONE_SHOT;
-assign device_cfg_sysref_disable = SYSREF_DISABLE;
+  assign device_cfg_octets_per_multiframe = (FRAMES_PER_MULTIFRAME * OCTETS_PER_FRAME) - 1;
+  assign device_cfg_octets_per_frame = OCTETS_PER_FRAME - 1;
+  assign device_cfg_beats_per_multiframe = ((FRAMES_PER_MULTIFRAME * OCTETS_PER_FRAME) /
+                                            TPL_DATA_PATH_WIDTH) - 1;
+  assign device_cfg_lmfc_offset = 1;
+  assign device_cfg_sysref_oneshot = SYSREF_ONE_SHOT;
+  assign device_cfg_sysref_disable = SYSREF_DISABLE;
 
-jesd204_ilas_cfg_static #(
-  .DID(8'h00),
-  .BID(5'h00),
-  .L(NUM_LANES - 1),
-  .SCR(SCR),
-  .F(OCTETS_PER_FRAME - 1),
-  .K(FRAMES_PER_MULTIFRAME - 1),
-  .M(NUM_CONVERTERS - 1),
-  .N(N),
-  .NP(NP),
-  .SUBCLASSV(3'h1),
-  .S(5'h00),
-  .JESDV(3'h1),
-  .CF(5'h00),
-  .HD(HIGH_DENSITY),
-  .NUM_LANES(NUM_LANES),
-  .DATA_PATH_WIDTH(DATA_PATH_WIDTH)
-) i_ilas_config (
-  .clk(clk),
-  .ilas_config_addr(ilas_config_addr),
-  .ilas_config_rd(ilas_config_rd),
-  .ilas_config_data(ilas_config_data)
-);
+  jesd204_ilas_cfg_static #(
+    .DID(8'h00),
+    .BID(5'h00),
+    .L(NUM_LANES - 1),
+    .SCR(SCR),
+    .F(OCTETS_PER_FRAME - 1),
+    .K(FRAMES_PER_MULTIFRAME - 1),
+    .M(NUM_CONVERTERS - 1),
+    .N(N),
+    .NP(NP),
+    .SUBCLASSV(3'h1),
+    .S(5'h00),
+    .JESDV(3'h1),
+    .CF(5'h00),
+    .HD(HIGH_DENSITY),
+    .NUM_LANES(NUM_LANES),
+    .DATA_PATH_WIDTH(DATA_PATH_WIDTH)
+  ) i_ilas_config (
+    .clk(clk),
+    .ilas_config_addr(ilas_config_addr),
+    .ilas_config_rd(ilas_config_rd),
+    .ilas_config_data(ilas_config_data));
 
 endmodule
diff --git a/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx.v b/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx.v
index e88730ab6..fe6b4df4a 100644
--- a/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx.v
+++ b/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx.v
@@ -56,7 +56,6 @@ module  jesd204_versal_gt_adapter_rx (
   output          rx_block_sync,
 
   input           usr_clk
-
 );
 
   // Sync header alignment
@@ -92,7 +91,6 @@ module  jesd204_versal_gt_adapter_rx (
     .i_slip_done(rx_bitslip_done_cnt[4]),
     .o_data(rx_data),
     .o_header(rx_header),
-    .o_block_sync(rx_block_sync)
-  );
+    .o_block_sync(rx_block_sync));
 
 endmodule
diff --git a/library/jesd204/tb/axi_jesd204_rx_regmap_tb.v b/library/jesd204/tb/axi_jesd204_rx_regmap_tb.v
index 00aa12d62..46ab4503c 100644
--- a/library/jesd204/tb/axi_jesd204_rx_regmap_tb.v
+++ b/library/jesd204/tb/axi_jesd204_rx_regmap_tb.v
@@ -150,7 +150,6 @@ module axi_jesd204_rx_regmap_tb;
     end
   end
 
-
   task set_reset_reg_value;
   input [31:0] addr;
   input [31:0] value;
@@ -379,7 +378,6 @@ module axi_jesd204_rx_regmap_tb;
 
     .status_synth_params0(NUM_LANES),
     .status_synth_params1(2),
-    .status_synth_params2(NUM_LINKS)
-  );
+    .status_synth_params2(NUM_LINKS));
 
 endmodule
diff --git a/library/jesd204/tb/axi_jesd204_tx_regmap_tb.v b/library/jesd204/tb/axi_jesd204_tx_regmap_tb.v
index 626a81131..f3b684b7b 100644
--- a/library/jesd204/tb/axi_jesd204_tx_regmap_tb.v
+++ b/library/jesd204/tb/axi_jesd204_tx_regmap_tb.v
@@ -148,7 +148,6 @@ module axi_jesd204_tx_regmap_tb;
     end
   end
 
-
   task set_reset_reg_value;
   input [31:0] addr;
   input [31:0] value;
@@ -367,7 +366,6 @@ module axi_jesd204_tx_regmap_tb;
 
     .status_synth_params0(NUM_LANES),
     .status_synth_params1(2),
-    .status_synth_params2(NUM_LINKS)
-  );
+    .status_synth_params2(NUM_LINKS));
 
 endmodule
diff --git a/library/jesd204/tb/crc12_tb.v b/library/jesd204/tb/crc12_tb.v
index 0827e5888..56d1979c0 100644
--- a/library/jesd204/tb/crc12_tb.v
+++ b/library/jesd204/tb/crc12_tb.v
@@ -62,8 +62,7 @@ module crc12_tb;
     .reset (1'b0),
     .init (init),
     .data_in (data_in),
-    .crc12 (crc12)
-  );
+    .crc12 (crc12));
 
   // Test against dataset from the standard
   //  - Test contiguous input stream with init phase
@@ -95,7 +94,6 @@ module crc12_tb;
     end
   end
 
-
   always @(posedge clk) begin
     if (ref_crc12 != crc12 && failed == 1'b0 && test_en) begin
       failed <= 1'b1;
diff --git a/library/jesd204/tb/frame_align_tb.v b/library/jesd204/tb/frame_align_tb.v
index a2e5d2ce6..05a61918a 100755
--- a/library/jesd204/tb/frame_align_tb.v
+++ b/library/jesd204/tb/frame_align_tb.v
@@ -221,7 +221,6 @@ module frame_align_tb;
     end
   end
 
-
   wire [NUM_LANES-1:0] tx_cfg_lanes_disable;
   wire [NUM_LINKS-1:0] tx_cfg_links_disable;
   wire [9:0] tx_cfg_octets_per_multiframe;
@@ -289,8 +288,7 @@ module frame_align_tb;
 
     .ilas_config_rd(tx_ilas_config_rd),
     .ilas_config_addr(tx_ilas_config_addr),
-    .ilas_config_data(tx_ilas_config_data)
-  );
+    .ilas_config_data(tx_ilas_config_data));
 
   jesd204_tx #(
     .NUM_LANES(NUM_LANES),
@@ -358,8 +356,7 @@ module frame_align_tb;
 
     .status_synth_params0(),
     .status_synth_params1(),
-    .status_synth_params2()
-  );
+    .status_synth_params2());
 
   wire [NUM_LANES-1:0] rx_cfg_lanes_disable;
   wire [NUM_LINKS-1:0] rx_cfg_links_disable;
@@ -421,8 +418,7 @@ module frame_align_tb;
     .device_cfg_sysref_disable(rx_device_cfg_sysref_disable),
     .device_cfg_sysref_oneshot(rx_device_cfg_sysref_oneshot),
     .device_cfg_buffer_early_release(rx_device_cfg_buffer_early_release),
-    .device_cfg_buffer_delay(rx_device_cfg_buffer_delay)
-  );
+    .device_cfg_buffer_delay(rx_device_cfg_buffer_delay));
 
   jesd204_rx #(
     .NUM_LANES(NUM_LANES),
@@ -506,9 +502,8 @@ module frame_align_tb;
 
     .status_synth_params0(),
     .status_synth_params1(),
-    .status_synth_params2()
-  );
-  
+    .status_synth_params2());
+
   wire m_axis_aresetn;
   wire m_axis_ready;
   wire m_axis_valid;
@@ -528,15 +523,15 @@ module frame_align_tb;
   wire s_axis_full;
   wire s_axis_almost_full;
   wire error_inject = (align_err_f | align_err_mf);
-  
+
   reg invalid_data = 1'b0;
   reg read_flag = 1'b1;
-  
+
   assign s_axis_aresetn = ~error_inject;
   assign m_axis_aresetn = ~error_inject;
-  assign m_axis_ready = rx_valid; 
+  assign m_axis_ready = rx_valid;
   assign s_axis_valid = tx_ready;
-  
+
   //util_axis_fifo instance
   util_axis_fifo #(
     .DATA_WIDTH(DATA_PATH_WIDTH*8),
@@ -570,9 +565,8 @@ module frame_align_tb;
     .s_axis_tlast(s_axis_tlast),
     .s_axis_room(s_axis_room),
     .s_axis_full(s_axis_full),
-    .s_axis_almost_full(s_axis_almost_full)
-);
-          
+    .s_axis_almost_full(s_axis_almost_full));
+
   always @ (negedge error_inject) begin
     //get fifo out of reset
     #5000; //wait for tx_ready to rise up
@@ -585,12 +579,12 @@ module frame_align_tb;
     if (rx_valid == 1 && error_inject == 0) begin
       //remove from the queue first element and compare to rx_data
       //compare the data sent by tx with the data recieved
-      if(rx_data[DATA_PATH_WIDTH*8-1:0] !== m_axis_data) begin 
+      if(rx_data[DATA_PATH_WIDTH*8-1:0] !== m_axis_data) begin
         invalid_data <= 1'b1;
       end
-    end 
+    end
   end
-  
+
   assign cur_data_mismatch = (rx_data & rx_mask) !== ({NUM_LANES{rx_ref_data}} & rx_mask);
 
   always @(posedge clk) begin
@@ -621,7 +615,7 @@ module frame_align_tb;
   always @(*) begin
     if ((rx_valid == 1'b1 && invalid_data == 1'b1) || read_flag == 1'b0) begin
       failed <= 1'b1;
-    end 
+    end
   end
 
 endmodule
diff --git a/library/jesd204/tb/jesd204_frame_align_replace_tb.v b/library/jesd204/tb/jesd204_frame_align_replace_tb.v
index 51490ac5c..b84aca1d6 100755
--- a/library/jesd204/tb/jesd204_frame_align_replace_tb.v
+++ b/library/jesd204/tb/jesd204_frame_align_replace_tb.v
@@ -46,56 +46,53 @@
 
 module jesd204_frame_align_replace_tb;
 
+  parameter VCD_FILE = "jesd204_frame_align_replace_tb.vcd";
+  `define TIMEOUT 1000000
+  `include "tb_base.v"
 
-parameter VCD_FILE = "jesd204_frame_align_replace_tb.vcd";
-`define TIMEOUT 1000000
-`include "tb_base.v"
+  localparam DATA_PATH_WIDTH = 8;
+  localparam IS_RX = 1'b1;
 
-localparam DATA_PATH_WIDTH = 8;
-localparam IS_RX = 1'b1;
+  wire [7:0]                    cfg_octets_per_frame = 5;
+  wire                          cfg_disable_char_replacement = 1'b0;
+  wire                          cfg_disable_scrambler = 1'b1;
+  reg [DATA_PATH_WIDTH*8-1:0]   data;
+  reg [DATA_PATH_WIDTH-1:0]     eof;
+  reg [DATA_PATH_WIDTH-1:0]     eomf;
+  reg [DATA_PATH_WIDTH-1:0]     char_is_a;
+  reg [DATA_PATH_WIDTH-1:0]     char_is_f;
+  wire [DATA_PATH_WIDTH*8-1:0]  data_out;
+  wire [DATA_PATH_WIDTH-1:0]    charisk_out;
+  reg [31:00] ii;
 
-wire [7:0]                    cfg_octets_per_frame = 5;
-wire                          cfg_disable_char_replacement = 1'b0;
-wire                          cfg_disable_scrambler = 1'b1;
-reg [DATA_PATH_WIDTH*8-1:0]   data;
-reg [DATA_PATH_WIDTH-1:0]     eof;
-reg [DATA_PATH_WIDTH-1:0]     eomf;
-reg [DATA_PATH_WIDTH-1:0]     char_is_a;
-reg [DATA_PATH_WIDTH-1:0]     char_is_f;
-wire [DATA_PATH_WIDTH*8-1:0]  data_out;
-wire [DATA_PATH_WIDTH-1:0]    charisk_out;
-reg [31:00] ii;
-
-
-initial begin
-  forever begin
-    for(ii = 0; ii < DATA_PATH_WIDTH; ii = ii + 1) begin
-      eof[ii] = $urandom_range(cfg_octets_per_frame) == 0;
-      eomf[ii] = $urandom_range(cfg_octets_per_frame*4) == 0;
-      char_is_a[ii] = $urandom_range(cfg_octets_per_frame*2) == 0;
-      char_is_f[ii] = $urandom_range(cfg_octets_per_frame*2) == 0;
+  initial begin
+    forever begin
+      for(ii = 0; ii < DATA_PATH_WIDTH; ii = ii + 1) begin
+        eof[ii] = $urandom_range(cfg_octets_per_frame) == 0;
+        eomf[ii] = $urandom_range(cfg_octets_per_frame*4) == 0;
+        char_is_a[ii] = $urandom_range(cfg_octets_per_frame*2) == 0;
+        char_is_f[ii] = $urandom_range(cfg_octets_per_frame*2) == 0;
+      end
+      data = {$urandom, $urandom};
+      @(negedge clk);
     end
-    data = {$urandom, $urandom};
-    @(negedge clk);
   end
-end
 
-jesd204_frame_align_replace #(
-  .DATA_PATH_WIDTH              (DATA_PATH_WIDTH),
-  .IS_RX                        (IS_RX)
-) frame_align_replace (
-  .clk                          (clk),
-  .reset                        (reset),
-  .cfg_octets_per_frame         (cfg_octets_per_frame),
-  .cfg_disable_char_replacement (cfg_disable_char_replacement),
-  .cfg_disable_scrambler        (cfg_disable_scrambler),
-  .data                         (data),
-  .eof                          (eof),
-  .rx_char_is_a                 (char_is_a),
-  .rx_char_is_f                 (char_is_f),
-  .tx_eomf                      (eomf),
-  .data_out                     (data_out),
-  .charisk_out                  (charisk_out)
-);
+  jesd204_frame_align_replace #(
+    .DATA_PATH_WIDTH              (DATA_PATH_WIDTH),
+    .IS_RX                        (IS_RX)
+  ) frame_align_replace (
+    .clk                          (clk),
+    .reset                        (reset),
+    .cfg_octets_per_frame         (cfg_octets_per_frame),
+    .cfg_disable_char_replacement (cfg_disable_char_replacement),
+    .cfg_disable_scrambler        (cfg_disable_scrambler),
+    .data                         (data),
+    .eof                          (eof),
+    .rx_char_is_a                 (char_is_a),
+    .rx_char_is_f                 (char_is_f),
+    .tx_eomf                      (eomf),
+    .data_out                     (data_out),
+    .charisk_out                  (charisk_out));
 
 endmodule
diff --git a/library/jesd204/tb/jesd204_frame_mark_tb.v b/library/jesd204/tb/jesd204_frame_mark_tb.v
index 5d96040f7..7a05d8a36 100755
--- a/library/jesd204/tb/jesd204_frame_mark_tb.v
+++ b/library/jesd204/tb/jesd204_frame_mark_tb.v
@@ -46,34 +46,31 @@
 
 module jesd204_frame_mark_tb;
 
+  parameter VCD_FILE = "jesd204_frame_mark_tb.vcd";
+  `define TIMEOUT 1000000
+  `include "tb_base.v"
 
-parameter VCD_FILE = "jesd204_frame_mark_tb.vcd";
-`define TIMEOUT 1000000
-`include "tb_base.v"
+  localparam DATA_PATH_WIDTH = 8;
 
-localparam DATA_PATH_WIDTH = 8;
+  wire [9:0]                  cfg_octets_per_multiframe = 23;
+  wire [7:0]                  cfg_beats_per_multiframe = 2;
+  wire [7:0]                  cfg_octets_per_frame = 5;
+  wire [DATA_PATH_WIDTH-1:0]  sof;
+  wire [DATA_PATH_WIDTH-1:0]  somf;
+  wire [DATA_PATH_WIDTH-1:0]  eof;
+  wire [DATA_PATH_WIDTH-1:0]  eomf;
 
-wire [9:0]                  cfg_octets_per_multiframe = 23;
-wire [7:0]                  cfg_beats_per_multiframe = 2;
-wire [7:0]                  cfg_octets_per_frame = 5;
-wire [DATA_PATH_WIDTH-1:0]  sof;
-wire [DATA_PATH_WIDTH-1:0]  somf;
-wire [DATA_PATH_WIDTH-1:0]  eof;
-wire [DATA_PATH_WIDTH-1:0]  eomf;
-
-
-jesd204_frame_mark #(
-  .DATA_PATH_WIDTH            (DATA_PATH_WIDTH)
-) frame_mark (
-  .clk                        (clk),
-  .reset                      (reset),
-  .cfg_octets_per_multiframe  (cfg_octets_per_multiframe),
-  .cfg_beats_per_multiframe   (cfg_beats_per_multiframe),
-  .cfg_octets_per_frame       (cfg_octets_per_frame),
-  .sof                        (sof),
-  .eof                        (eof),
-  .somf                       (somf),
-  .eomf                       (eomf)
-);
+  jesd204_frame_mark #(
+    .DATA_PATH_WIDTH            (DATA_PATH_WIDTH)
+  ) frame_mark (
+    .clk                        (clk),
+    .reset                      (reset),
+    .cfg_octets_per_multiframe  (cfg_octets_per_multiframe),
+    .cfg_beats_per_multiframe   (cfg_beats_per_multiframe),
+    .cfg_octets_per_frame       (cfg_octets_per_frame),
+    .sof                        (sof),
+    .eof                        (eof),
+    .somf                       (somf),
+    .eomf                       (eomf));
 
 endmodule
diff --git a/library/jesd204/tb/loopback_64b_tb.v b/library/jesd204/tb/loopback_64b_tb.v
index 6aad1c58d..c8e845622 100644
--- a/library/jesd204/tb/loopback_64b_tb.v
+++ b/library/jesd204/tb/loopback_64b_tb.v
@@ -194,8 +194,7 @@ module loopback_64b_tb;
 
     .ilas_config_rd(tx_ilas_config_rd),
     .ilas_config_addr(tx_ilas_config_addr),
-    .ilas_config_data(tx_ilas_config_data)
-  );
+    .ilas_config_data(tx_ilas_config_data));
 
   jesd204_tx #(
     .NUM_LANES(NUM_LANES),
@@ -262,8 +261,7 @@ module loopback_64b_tb;
 
     .status_synth_params0(),
     .status_synth_params1(),
-    .status_synth_params2()
-  );
+    .status_synth_params2());
 
   wire [NUM_LANES-1:0] rx_cfg_lanes_disable;
   wire [NUM_LINKS-1:0] rx_cfg_links_disable;
@@ -307,8 +305,7 @@ module loopback_64b_tb;
     .device_cfg_sysref_disable(rx_device_cfg_sysref_disable),
     .device_cfg_sysref_oneshot(rx_device_cfg_sysref_oneshot),
     .device_cfg_buffer_early_release(rx_device_cfg_buffer_early_release),
-    .device_cfg_buffer_delay(rx_device_cfg_buffer_delay)
-  );
+    .device_cfg_buffer_delay(rx_device_cfg_buffer_delay));
 
   jesd204_rx #(
     .NUM_LANES(NUM_LANES),
@@ -387,8 +384,7 @@ module loopback_64b_tb;
 
     .status_synth_params0(),
     .status_synth_params1(),
-    .status_synth_params2()
-  );
+    .status_synth_params2());
 
   integer ii;
   reg rx_status_mismatch = 1'b0;
@@ -415,7 +411,6 @@ module loopback_64b_tb;
     end
   end
 
-
   always @(*) begin
     if (data_mismatch || rx_status_mismatch) begin
       failed <= 1'b1;
diff --git a/library/jesd204/tb/loopback_tb.v b/library/jesd204/tb/loopback_tb.v
index fe244e33f..905e464a9 100755
--- a/library/jesd204/tb/loopback_tb.v
+++ b/library/jesd204/tb/loopback_tb.v
@@ -233,8 +233,7 @@ module loopback_tb;
 
     .ilas_config_rd(tx_ilas_config_rd),
     .ilas_config_addr(tx_ilas_config_addr),
-    .ilas_config_data(tx_ilas_config_data)
-  );
+    .ilas_config_data(tx_ilas_config_data));
 
   jesd204_tx #(
     .NUM_LANES(NUM_LANES),
@@ -302,8 +301,7 @@ module loopback_tb;
 
     .status_synth_params0(),
     .status_synth_params1(),
-    .status_synth_params2()
-  );
+    .status_synth_params2());
 
   wire [NUM_LANES-1:0] rx_cfg_lanes_disable;
   wire [NUM_LINKS-1:0] rx_cfg_links_disable;
@@ -365,8 +363,7 @@ module loopback_tb;
     .device_cfg_sysref_disable(rx_device_cfg_sysref_disable),
     .device_cfg_sysref_oneshot(rx_device_cfg_sysref_oneshot),
     .device_cfg_buffer_early_release(rx_device_cfg_buffer_early_release),
-    .device_cfg_buffer_delay(rx_device_cfg_buffer_delay)
-  );
+    .device_cfg_buffer_delay(rx_device_cfg_buffer_delay));
 
   jesd204_rx #(
     .NUM_LANES(NUM_LANES),
@@ -450,8 +447,7 @@ module loopback_tb;
 
     .status_synth_params0(),
     .status_synth_params1(),
-    .status_synth_params2()
-  );
+    .status_synth_params2());
 
   always @(posedge clk) begin
     if (reset == 1'b1) begin
diff --git a/library/jesd204/tb/rx_cgs_tb.v b/library/jesd204/tb/rx_cgs_tb.v
index 84aa7c43e..04cf2dcd5 100644
--- a/library/jesd204/tb/rx_cgs_tb.v
+++ b/library/jesd204/tb/rx_cgs_tb.v
@@ -79,8 +79,7 @@ module rx_cgs_tb;
     .char_is_cgs(char_is_cgs),
     .char_is_error(char_is_error),
 
-    .ready(ready)
-  );
+    .ready(ready));
 
   reg lost_sync = 1'b0;
 
diff --git a/library/jesd204/tb/rx_ctrl_tb.v b/library/jesd204/tb/rx_ctrl_tb.v
index 3261d613c..0f622bcdf 100644
--- a/library/jesd204/tb/rx_ctrl_tb.v
+++ b/library/jesd204/tb/rx_ctrl_tb.v
@@ -88,7 +88,6 @@ module rx_ctrl_tb;
     end
   end
 
-
   always @(posedge clk or posedge cgs_reset) begin
     if (cgs_reset == 1'b1) begin
       cgs_counter <= 'h00;
@@ -108,7 +107,6 @@ module rx_ctrl_tb;
     .phy_ready(phy_ready),
     .phy_en_char_align(en_align),
     .cgs_reset(cgs_reset),
-    .cgs_ready(cgs_ready)
-  );
+    .cgs_ready(cgs_ready));
 
 endmodule
diff --git a/library/jesd204/tb/rx_lane_tb.v b/library/jesd204/tb/rx_lane_tb.v
index c8b162dfc..9eb77de2b 100644
--- a/library/jesd204/tb/rx_lane_tb.v
+++ b/library/jesd204/tb/rx_lane_tb.v
@@ -150,7 +150,6 @@ module rx_lane_tb;
     .status_cgs_state(status_cgs_state),
     .status_ifs_ready(status_ifs_ready),
     .status_frame_align(status_frame_align),
-    .status_frame_align_err_cnt()
-  );
+    .status_frame_align_err_cnt());
 
 endmodule
diff --git a/library/jesd204/tb/rx_tb.v b/library/jesd204/tb/rx_tb.v
index 829baf1a3..cbeee37c6 100644
--- a/library/jesd204/tb/rx_tb.v
+++ b/library/jesd204/tb/rx_tb.v
@@ -190,8 +190,7 @@ module rx_tb;
     .device_cfg_sysref_disable(device_cfg_sysref_disable),
     .device_cfg_sysref_oneshot(device_cfg_sysref_oneshot),
     .device_cfg_buffer_early_release(device_cfg_buffer_early_release),
-    .device_cfg_buffer_delay(device_cfg_buffer_delay)
-  );
+    .device_cfg_buffer_delay(device_cfg_buffer_delay));
 
   jesd204_rx #(
     .NUM_LANES(NUM_LANES),
@@ -267,8 +266,6 @@ module rx_tb;
 
     .status_synth_params0(),
     .status_synth_params1(),
-    .status_synth_params2()
-
-  );
+    .status_synth_params2());
 
 endmodule
diff --git a/library/jesd204/tb/scrambler_64b_tb.v b/library/jesd204/tb/scrambler_64b_tb.v
index 27d6262a1..8358f0f8d 100644
--- a/library/jesd204/tb/scrambler_64b_tb.v
+++ b/library/jesd204/tb/scrambler_64b_tb.v
@@ -67,7 +67,6 @@ module scrambler_64b_tb;
     end
   end
 
-
   jesd204_scrambler_64b #(
     .DESCRAMBLE(0)
   ) i_scrambler (
@@ -75,8 +74,7 @@ module scrambler_64b_tb;
     .reset(reset),
     .enable(1'b1),
     .data_in(data_in),
-    .data_out(data_scrambled)
-  );
+    .data_out(data_scrambled));
 
   jesd204_scrambler_64b #(
     .DESCRAMBLE(1)
@@ -85,8 +83,8 @@ module scrambler_64b_tb;
     .reset(reset),
     .enable(1'b1),
     .data_in(data_scrambled),
-    .data_out(data_out)
-  );
+    .data_out(data_out));
+
   always @(posedge clk) begin
     if (data_in != data_out && failed_t1 == 1'b0) begin
       failed_t1 <= 1'b1;
@@ -128,8 +126,7 @@ module scrambler_64b_tb;
     .reset(reset),
     .enable(1'b1),
     .data_in(descrambler_data_in),
-    .data_out(descrambler_data_out)
-  );
+    .data_out(descrambler_data_out));
 
   always @(posedge clk) begin
     if (data_ref != descrambler_data_out && failed_t2 == 1'b0 && t2_enable) begin
@@ -141,5 +138,4 @@ module scrambler_64b_tb;
     failed <= failed_t1 || failed_t2;
   end
 
-
 endmodule
diff --git a/library/jesd204/tb/scrambler_tb.v b/library/jesd204/tb/scrambler_tb.v
index 47f1f5da1..b2e93a0b8 100644
--- a/library/jesd204/tb/scrambler_tb.v
+++ b/library/jesd204/tb/scrambler_tb.v
@@ -69,8 +69,7 @@ module scrambler_tb;
     .reset(reset),
     .enable(1'b1),
     .data_in(data_in),
-    .data_out(data_scrambled)
-  );
+    .data_out(data_scrambled));
 
   jesd204_scrambler #(
     .DESCRAMBLE(1)
@@ -79,8 +78,7 @@ module scrambler_tb;
     .reset(reset),
     .enable(1'b1),
     .data_in(data_scrambled),
-    .data_out(data_out)
-  );
+    .data_out(data_out));
 
   always @(posedge clk) begin
     if (data_in != data_out && failed == 1'b0) begin
diff --git a/library/jesd204/tb/soft_pcs_8b10b_sequence_tb.v b/library/jesd204/tb/soft_pcs_8b10b_sequence_tb.v
index f28d56e41..dab6c5c5b 100644
--- a/library/jesd204/tb/soft_pcs_8b10b_sequence_tb.v
+++ b/library/jesd204/tb/soft_pcs_8b10b_sequence_tb.v
@@ -107,8 +107,7 @@ module soft_pcs_8b10b_sequence_tb;
     .out_char(raw_data),
 
     .in_disparity(encoder_disparity),
-    .out_disparity(encoder_disparity_s)
-  );
+    .out_disparity(encoder_disparity_s));
 
   jesd204_8b10b_decoder i_dec (
     .in_char(raw_data),
@@ -118,8 +117,7 @@ module soft_pcs_8b10b_sequence_tb;
     .out_charisk(decoder_charisk),
 
     .in_disparity(decoder_disparity),
-    .out_disparity(decoder_disparity_s)
-  );
+    .out_disparity(decoder_disparity_s));
 
    wire char_mismatch = encoder_char != decoder_char;
    wire charisk_mismatch = encoder_charisk != decoder_charisk;
diff --git a/library/jesd204/tb/soft_pcs_8b10b_table_tb.v b/library/jesd204/tb/soft_pcs_8b10b_table_tb.v
index 8570464d6..43533110a 100644
--- a/library/jesd204/tb/soft_pcs_8b10b_table_tb.v
+++ b/library/jesd204/tb/soft_pcs_8b10b_table_tb.v
@@ -105,8 +105,7 @@ module soft_pcs_8b10b_table_tb;
     .in_charisk(encoder_charisk),
     .in_disparity(encoder_disparity),
     .out_char(encoder_raw),
-    .out_disparity()
-  );
+    .out_disparity());
 
   always @(posedge clk) begin
     if (build_table == 1'b1) begin
@@ -134,8 +133,7 @@ module soft_pcs_8b10b_table_tb;
 
     .in_disparity(decoder_disparity),
     .out_disparity(decoder_disparity_s),
-    .out_disperr()
-  );
+    .out_disperr());
 
   wire decoder_should_be_in_table = valid_table[decoder_raw];
 
diff --git a/library/jesd204/tb/soft_pcs_loopback_tb.v b/library/jesd204/tb/soft_pcs_loopback_tb.v
index 14e0bdfd9..a86743ec2 100644
--- a/library/jesd204/tb/soft_pcs_loopback_tb.v
+++ b/library/jesd204/tb/soft_pcs_loopback_tb.v
@@ -108,8 +108,7 @@ module soft_pcs_loopback_tb;
     .char(tx_char_pcs),
     .charisk(tx_charisk_pcs),
 
-    .data(data_aligned)
-  );
+    .data(data_aligned));
 
   jesd204_soft_pcs_rx #(
     .DATA_PATH_WIDTH(DATA_PATH_WIDTH),
@@ -124,8 +123,7 @@ module soft_pcs_loopback_tb;
     .char(rx_char_pcs),
     .charisk(rx_charisk_pcs),
     .notintable(rx_notintable_pcs),
-    .disperr(rx_disperr_pcs)
-  );
+    .disperr(rx_disperr_pcs));
 
   always @(posedge clk) begin
     tx_char_pcs <= {tx_char,tx_char_pcs[DATA_PATH_WIDTH*8-1:8]};
diff --git a/library/jesd204/tb/soft_pcs_pattern_align_tb.v b/library/jesd204/tb/soft_pcs_pattern_align_tb.v
index bf6369d9c..1902040ad 100644
--- a/library/jesd204/tb/soft_pcs_pattern_align_tb.v
+++ b/library/jesd204/tb/soft_pcs_pattern_align_tb.v
@@ -111,7 +111,6 @@ module soft_pcs_pattern_align_tb;
     .patternalign_en(1'b1),
 
     .in_data(comma_unaligned),
-    .out_data(comma_aligned)
-  );
+    .out_data(comma_aligned));
 
 endmodule
diff --git a/library/jesd204/tb/tb_base.v b/library/jesd204/tb/tb_base.v
index 629836e98..87df5b171 100755
--- a/library/jesd204/tb/tb_base.v
+++ b/library/jesd204/tb/tb_base.v
@@ -78,7 +78,6 @@
 
   assign reset = reset_shift[3];
 
-
   initial begin
     #1000;
     @(posedge clk) sysref <= 1'b1;
diff --git a/library/jesd204/tb/tx_64b_tb.v b/library/jesd204/tb/tx_64b_tb.v
index b8eabe4ae..9d4aaa655 100644
--- a/library/jesd204/tb/tx_64b_tb.v
+++ b/library/jesd204/tb/tx_64b_tb.v
@@ -118,8 +118,7 @@ module tx_64b_tb;
 
     .ilas_config_rd(tx_ilas_config_rd),
     .ilas_config_addr(tx_ilas_config_addr),
-    .ilas_config_data(tx_ilas_config_data)
-  );
+    .ilas_config_data(tx_ilas_config_data));
 
   jesd204_tx #(
     .NUM_LANES(NUM_LANES),
@@ -183,9 +182,6 @@ module tx_64b_tb;
 
     .status_synth_params0(),
     .status_synth_params1(),
-    .status_synth_params2()
-
-  );
-
+    .status_synth_params2());
 
 endmodule
diff --git a/library/jesd204/tb/tx_ctrl_phase_tb.v b/library/jesd204/tb/tx_ctrl_phase_tb.v
index 870ae878f..9c5b60dcf 100644
--- a/library/jesd204/tb/tx_ctrl_phase_tb.v
+++ b/library/jesd204/tb/tx_ctrl_phase_tb.v
@@ -161,9 +161,7 @@ module tx_ctrl_phase_tb;
     .ctrl_manual_sync_request(1'b0),
 
     .status_sync(),
-    .status_state()
-
-  );
+    .status_state());
 
   jesd204_tx_ctrl i_tx_ctrl_b (
     .clk(clk),
@@ -200,9 +198,7 @@ module tx_ctrl_phase_tb;
     .ctrl_manual_sync_request(1'b0),
 
     .status_sync(),
-    .status_state()
-
-  );
+    .status_state());
 
   reg status = 1'b1;
 
diff --git a/library/jesd204/tb/tx_tb.v b/library/jesd204/tb/tx_tb.v
index 8b99588d1..b3ff94a99 100644
--- a/library/jesd204/tb/tx_tb.v
+++ b/library/jesd204/tb/tx_tb.v
@@ -53,7 +53,6 @@ module tx_tb;
 
   `include "tb_base.v"
 
-
   reg [NUM_LINKS-1:0] sync = {NUM_LINKS{1'b1}};
   reg [31:0] counter = 'h00;
   reg [31:0] tx_data = 'h00000000;
@@ -140,8 +139,7 @@ module tx_tb;
 
     .ilas_config_rd(tx_ilas_config_rd),
     .ilas_config_addr(tx_ilas_config_addr),
-    .ilas_config_data(tx_ilas_config_data)
-  );
+    .ilas_config_data(tx_ilas_config_data));
 
   jesd204_tx #(
     .NUM_LANES(NUM_LANES),
@@ -204,10 +202,6 @@ module tx_tb;
 
     .status_synth_params0(),
     .status_synth_params1(),
-    .status_synth_params2()
-
-
-  );
-
+    .status_synth_params2());
 
 endmodule
diff --git a/library/spi_engine/axi_spi_engine/axi_spi_engine.v b/library/spi_engine/axi_spi_engine/axi_spi_engine.v
index f95b6ba19..7a1a23af5 100644
--- a/library/spi_engine/axi_spi_engine/axi_spi_engine.v
+++ b/library/spi_engine/axi_spi_engine/axi_spi_engine.v
@@ -52,7 +52,8 @@ module axi_spi_engine #(
   parameter CFG_INFO_0 = 0,
   parameter CFG_INFO_1 = 0,
   parameter CFG_INFO_2 = 0,
-  parameter CFG_INFO_3 = 0) (
+  parameter CFG_INFO_3 = 0
+) (
 
   // Slave AXI interface
 
@@ -129,7 +130,8 @@ module axi_spi_engine #(
 
   output offload_sync_ready,
   input offload_sync_valid,
-  input [7:0] offload_sync_data);
+  input [7:0] offload_sync_data
+);
 
   localparam PCORE_VERSION = 'h010071;
   localparam S_AXI = 0;
@@ -228,8 +230,7 @@ module axi_spi_engine #(
       .up_rreq(up_rreq_s),
       .up_raddr(up_raddr_s),
       .up_rdata(up_rdata_ff),
-      .up_rack(up_rack_ff)
-    );
+      .up_rack(up_rack_ff));
 
     assign up_rdata = 32'b0;
     assign up_rack = 1'b0;
@@ -396,8 +397,7 @@ module axi_spi_engine #(
       .rst_async(up_sw_reset),
       .clk(spi_clk),
       .rst(spi_reset),
-      .rstn()
-    );
+      .rstn());
     assign spi_resetn = ~spi_reset;
   end else begin
     assign spi_resetn = ~up_sw_reset;
@@ -432,8 +432,7 @@ module axi_spi_engine #(
     .m_axis_tlast(),
     .m_axis_empty(),
     .m_axis_almost_empty(cmd_fifo_almost_empty),
-    .m_axis_level()
-  );
+    .m_axis_level());
 
   assign sdo_fifo_in_valid = up_wreq_s == 1'b1 && up_waddr_s == 8'h39;
   assign sdo_fifo_in_data = up_wdata_s[(DATA_WIDTH-1):0];
@@ -463,8 +462,7 @@ module axi_spi_engine #(
     .m_axis_tlast(),
     .m_axis_level(),
     .m_axis_empty(),
-    .m_axis_almost_empty(sdo_fifo_almost_empty)
-  );
+    .m_axis_almost_empty(sdo_fifo_almost_empty));
 
   assign sdi_fifo_out_ready = up_rreq_s == 1'b1 && up_raddr_s == 8'h3a;
 
@@ -493,8 +491,7 @@ module axi_spi_engine #(
     .m_axis_tlast(),
     .m_axis_level(sdi_fifo_level),
     .m_axis_empty(),
-    .m_axis_almost_empty()
-  );
+    .m_axis_almost_empty());
 
   generate if (ASYNC_SPI_CLK) begin
 
@@ -518,8 +515,7 @@ module axi_spi_engine #(
       .m_axis_valid(sync_fifo_valid),
       .m_axis_data(sync_fifo_data),
       .m_axis_level(),
-      .m_axis_empty()
-    );
+      .m_axis_empty());
 
     // synchronization FIFO for the offload command interface
     wire up_offload0_cmd_wr_en_s;
@@ -544,8 +540,7 @@ module axi_spi_engine #(
       .m_axis_valid(offload0_cmd_wr_en),
       .m_axis_data(offload0_cmd_wr_data),
       .m_axis_level(),
-      .m_axis_empty()
-    );
+      .m_axis_empty());
 
     assign up_offload0_cmd_wr_en_s = up_wreq_s == 1'b1 && up_waddr_s == 8'h44;
     assign up_offload0_cmd_wr_data_s = up_wdata_s[15:0];
@@ -573,8 +568,7 @@ module axi_spi_engine #(
       .m_axis_valid(offload0_sdo_wr_en),
       .m_axis_data(offload0_sdo_wr_data),
       .m_axis_level(),
-      .m_axis_empty()
-    );
+      .m_axis_empty());
 
     assign up_offload0_sdo_wr_en_s = up_wreq_s == 1'b1 && up_waddr_s == 8'h45;
     assign up_offload0_sdo_wr_data_s = up_wdata_s[DATA_WIDTH-1:0];
@@ -599,8 +593,7 @@ module axi_spi_engine #(
       .m_axis_valid(offload_sync_fifo_valid),
       .m_axis_data(offload_sync_fifo_data),
       .m_axis_level(),
-      .m_axis_empty()
-    );
+      .m_axis_empty());
 
   end else begin /* ASYNC_SPI_CLK == 0 */
 
diff --git a/library/spi_engine/spi_axis_reorder/spi_axis_reorder.v b/library/spi_engine/spi_axis_reorder/spi_axis_reorder.v
index 33a3b2f36..3731ac6fe 100644
--- a/library/spi_engine/spi_axis_reorder/spi_axis_reorder.v
+++ b/library/spi_engine/spi_axis_reorder/spi_axis_reorder.v
@@ -39,8 +39,8 @@
 //
 module spi_axis_reorder #(
 
-  parameter [3:0] NUM_OF_LANES = 2) (
-
+  parameter [3:0] NUM_OF_LANES = 2
+) (
   input                          axis_aclk,
   input                          axis_aresetn,
 
diff --git a/library/spi_engine/spi_engine_execution/spi_engine_execution.v b/library/spi_engine/spi_engine_execution/spi_engine_execution.v
index cb19cb0c6..04e26b827 100644
--- a/library/spi_engine/spi_engine_execution/spi_engine_execution.v
+++ b/library/spi_engine/spi_engine_execution/spi_engine_execution.v
@@ -44,8 +44,8 @@ module spi_engine_execution #(
   parameter NUM_OF_SDI = 1,
   parameter [0:0] SDO_DEFAULT = 1'b0,
   parameter ECHO_SCLK = 0,
-  parameter [1:0] SDI_DELAY = 2'b00) (
-
+  parameter [1:0] SDI_DELAY = 2'b00
+) (
   input clk,
   input resetn,
 
@@ -59,7 +59,6 @@ module spi_engine_execution #(
   output reg sdo_data_ready,
   input [(DATA_WIDTH-1):0] sdo_data,
 
-
   input sdi_data_ready,
   output reg sdi_data_valid,
   output [(NUM_OF_SDI * DATA_WIDTH)-1:0] sdi_data,
@@ -77,521 +76,521 @@ module spi_engine_execution #(
   output reg three_wire
 );
 
-localparam CMD_TRANSFER = 2'b00;
-localparam CMD_CHIPSELECT = 2'b01;
-localparam CMD_WRITE = 2'b10;
-localparam CMD_MISC = 2'b11;
+  localparam CMD_TRANSFER = 2'b00;
+  localparam CMD_CHIPSELECT = 2'b01;
+  localparam CMD_WRITE = 2'b10;
+  localparam CMD_MISC = 2'b11;
 
-localparam MISC_SYNC = 1'b0;
-localparam MISC_SLEEP = 1'b1;
+  localparam MISC_SYNC = 1'b0;
+  localparam MISC_SLEEP = 1'b1;
 
-localparam REG_CLK_DIV = 2'b00;
-localparam REG_CONFIG = 2'b01;
-localparam REG_WORD_LENGTH = 2'b10;
+  localparam REG_CLK_DIV = 2'b00;
+  localparam REG_CONFIG = 2'b01;
+  localparam REG_WORD_LENGTH = 2'b10;
 
-localparam BIT_COUNTER_WIDTH = DATA_WIDTH > 16 ? 5 :
-                               DATA_WIDTH > 8  ? 4 : 3;
+  localparam BIT_COUNTER_WIDTH = DATA_WIDTH > 16 ? 5 :
+                                 DATA_WIDTH > 8  ? 4 : 3;
 
-localparam BIT_COUNTER_CARRY = 2** (BIT_COUNTER_WIDTH + 1);
-localparam BIT_COUNTER_CLEAR = {{8{1'b1}}, {BIT_COUNTER_WIDTH{1'b0}}, 1'b1};
+  localparam BIT_COUNTER_CARRY = 2** (BIT_COUNTER_WIDTH + 1);
+  localparam BIT_COUNTER_CLEAR = {{8{1'b1}}, {BIT_COUNTER_WIDTH{1'b0}}, 1'b1};
 
-reg sclk_int = 1'b0;
-wire sdo_int_s;
-reg sdo_t_int = 1'b0;
+  reg sclk_int = 1'b0;
+  wire sdo_int_s;
+  reg sdo_t_int = 1'b0;
 
-reg idle;
+  reg idle;
 
-reg [7:0] clk_div_counter = 'h00;
-reg [7:0] clk_div_counter_next = 'h00;
-reg clk_div_last;
+  reg [7:0] clk_div_counter = 'h00;
+  reg [7:0] clk_div_counter_next = 'h00;
+  reg clk_div_last;
 
-reg [(BIT_COUNTER_WIDTH+8):0] counter = 'h00;
+  reg [(BIT_COUNTER_WIDTH+8):0] counter = 'h00;
 
-wire [7:0] sleep_counter = counter[(BIT_COUNTER_WIDTH+8):(BIT_COUNTER_WIDTH+1)];
-wire [1:0] cs_sleep_counter = counter[(BIT_COUNTER_WIDTH+2):(BIT_COUNTER_WIDTH+1)];
-wire [(BIT_COUNTER_WIDTH-1):0] bit_counter = counter[BIT_COUNTER_WIDTH:1];
-wire [7:0] transfer_counter = counter[(BIT_COUNTER_WIDTH+8):(BIT_COUNTER_WIDTH+1)];
-wire ntx_rx = counter[0];
+  wire [7:0] sleep_counter = counter[(BIT_COUNTER_WIDTH+8):(BIT_COUNTER_WIDTH+1)];
+  wire [1:0] cs_sleep_counter = counter[(BIT_COUNTER_WIDTH+2):(BIT_COUNTER_WIDTH+1)];
+  wire [(BIT_COUNTER_WIDTH-1):0] bit_counter = counter[BIT_COUNTER_WIDTH:1];
+  wire [7:0] transfer_counter = counter[(BIT_COUNTER_WIDTH+8):(BIT_COUNTER_WIDTH+1)];
+  wire ntx_rx = counter[0];
 
-reg trigger = 1'b0;
-reg trigger_next = 1'b0;
-reg wait_for_io = 1'b0;
-reg transfer_active = 1'b0;
+  reg trigger = 1'b0;
+  reg trigger_next = 1'b0;
+  reg wait_for_io = 1'b0;
+  reg transfer_active = 1'b0;
 
-wire last_bit;
-wire first_bit;
-reg last_transfer;
-reg [7:0] word_length = DATA_WIDTH;
-reg [7:0] left_aligned = 8'b0;
-wire end_of_word;
+  wire last_bit;
+  wire first_bit;
+  reg last_transfer;
+  reg [7:0] word_length = DATA_WIDTH;
+  reg [7:0] left_aligned = 8'b0;
+  wire end_of_word;
 
-reg [7:0] sdi_counter = 8'b0;
+  reg [7:0] sdi_counter = 8'b0;
 
-assign first_bit = ((bit_counter == 'h0) ||  (bit_counter == word_length));
+  assign first_bit = ((bit_counter == 'h0) ||  (bit_counter == word_length));
 
-reg [15:0] cmd_d1;
+  reg [15:0] cmd_d1;
 
-reg cpha = DEFAULT_SPI_CFG[0];
-reg cpol = DEFAULT_SPI_CFG[1];
-reg [7:0] clk_div = DEFAULT_CLK_DIV;
+  reg cpha = DEFAULT_SPI_CFG[0];
+  reg cpol = DEFAULT_SPI_CFG[1];
+  reg [7:0] clk_div = DEFAULT_CLK_DIV;
 
-reg sdo_enabled = 1'b0;
-reg sdi_enabled = 1'b0;
+  reg sdo_enabled = 1'b0;
+  reg sdi_enabled = 1'b0;
 
-reg [(DATA_WIDTH-1):0] data_sdo_shift = 'h0;
+  reg [(DATA_WIDTH-1):0] data_sdo_shift = 'h0;
 
-reg [SDI_DELAY+1:0] trigger_rx_d = {(SDI_DELAY+2){1'b0}};
+  reg [SDI_DELAY+1:0] trigger_rx_d = {(SDI_DELAY+2){1'b0}};
 
-wire [1:0] inst = cmd[13:12];
-wire [1:0] inst_d1 = cmd_d1[13:12];
+  wire [1:0] inst = cmd[13:12];
+  wire [1:0] inst_d1 = cmd_d1[13:12];
 
-wire exec_cmd = cmd_ready && cmd_valid;
-wire exec_transfer_cmd = exec_cmd && inst == CMD_TRANSFER;
+  wire exec_cmd = cmd_ready && cmd_valid;
+  wire exec_transfer_cmd = exec_cmd && inst == CMD_TRANSFER;
 
-wire exec_write_cmd = exec_cmd && inst == CMD_WRITE;
-wire exec_chipselect_cmd = exec_cmd && inst == CMD_CHIPSELECT;
-wire exec_misc_cmd = exec_cmd && inst == CMD_MISC;
-wire exec_sync_cmd = exec_misc_cmd && cmd[8] == MISC_SYNC;
+  wire exec_write_cmd = exec_cmd && inst == CMD_WRITE;
+  wire exec_chipselect_cmd = exec_cmd && inst == CMD_CHIPSELECT;
+  wire exec_misc_cmd = exec_cmd && inst == CMD_MISC;
+  wire exec_sync_cmd = exec_misc_cmd && cmd[8] == MISC_SYNC;
 
-wire trigger_tx;
-wire trigger_rx;
+  wire trigger_tx;
+  wire trigger_rx;
 
-wire sleep_counter_compare;
-wire cs_sleep_counter_compare;
+  wire sleep_counter_compare;
+  wire cs_sleep_counter_compare;
 
-wire io_ready1;
-wire io_ready2;
-wire trigger_rx_s;
+  wire io_ready1;
+  wire io_ready2;
+  wire trigger_rx_s;
 
-wire last_sdi_bit;
-wire end_of_sdi_latch;
+  wire last_sdi_bit;
+  wire end_of_sdi_latch;
 
-(* direct_enable = "yes" *) wire cs_gen;
+  (* direct_enable = "yes" *) wire cs_gen;
 
-assign cs_gen = inst_d1 == CMD_CHIPSELECT && cs_sleep_counter_compare == 1'b1;
-assign cmd_ready = idle;
+  assign cs_gen = inst_d1 == CMD_CHIPSELECT && cs_sleep_counter_compare == 1'b1;
+  assign cmd_ready = idle;
 
-always @(posedge clk) begin
-  if (exec_transfer_cmd) begin
-    sdo_enabled <= cmd[8];
-    sdi_enabled <= cmd[9];
+  always @(posedge clk) begin
+    if (exec_transfer_cmd) begin
+      sdo_enabled <= cmd[8];
+      sdi_enabled <= cmd[9];
+    end
   end
-end
 
-always @(posedge clk) begin
-  if (cmd_ready & cmd_valid)
-   cmd_d1 <= cmd;
-end
+  always @(posedge clk) begin
+    if (cmd_ready & cmd_valid)
+     cmd_d1 <= cmd;
+  end
 
-always @(posedge clk) begin
-  if (resetn == 1'b0) begin
-    active <= 1'b0;
-  end else begin
-    if (exec_cmd == 1'b1)
-      active <= 1'b1;
-    else if (sync_ready == 1'b1 && sync_valid == 1'b1)
+  always @(posedge clk) begin
+    if (resetn == 1'b0) begin
       active <= 1'b0;
-  end
-end
-
-// Load the interface configurations from the 'Configuration Write'
-// instruction
-always @(posedge clk) begin
-  if (resetn == 1'b0) begin
-    cpha <= DEFAULT_SPI_CFG[0];
-    cpol <= DEFAULT_SPI_CFG[1];
-    three_wire <= DEFAULT_SPI_CFG[2];
-    clk_div <= DEFAULT_CLK_DIV;
-    word_length <= DATA_WIDTH;
-    left_aligned <= 8'b0;
-  end else if (exec_write_cmd == 1'b1) begin
-    if (cmd[9:8] == REG_CONFIG) begin
-      cpha <= cmd[0];
-      cpol <= cmd[1];
-      three_wire <= cmd[2];
-    end else if (cmd[9:8] == REG_CLK_DIV) begin
-      clk_div <= cmd[7:0];
-    end else if (cmd[9:8] == REG_WORD_LENGTH) begin
-      // the max value of this reg must be DATA_WIDTH
-      word_length <= cmd[7:0];
-      left_aligned <= DATA_WIDTH - cmd[7:0];
+    end else begin
+      if (exec_cmd == 1'b1)
+        active <= 1'b1;
+      else if (sync_ready == 1'b1 && sync_valid == 1'b1)
+        active <= 1'b0;
     end
   end
-end
 
-always @(posedge clk) begin
-  if ((clk_div_last == 1'b0 && idle == 1'b0 && wait_for_io == 1'b0 &&
-    clk_div_counter == 'h01) || clk_div == 'h00)
-    clk_div_last <= 1'b1;
-  else
-    clk_div_last <= 1'b0;
-end
-
-always @(posedge clk) begin
-  if (clk_div_last == 1'b1 || idle == 1'b1 || wait_for_io == 1'b1) begin
-    clk_div_counter <= clk_div;
-    trigger <= 1'b1;
-  end else begin
-    clk_div_counter <= clk_div_counter - 1'b1;
-    trigger <= 1'b0;
-  end
-end
-
-assign trigger_tx = trigger == 1'b1 && ntx_rx == 1'b0;
-assign trigger_rx = trigger == 1'b1 && ntx_rx == 1'b1;
-
-assign sleep_counter_compare = sleep_counter == cmd_d1[7:0] && clk_div_last == 1'b1;
-assign cs_sleep_counter_compare = cs_sleep_counter == cmd_d1[9:8] && clk_div_last == 1'b1;
-
-always @(posedge clk) begin
-  if (idle == 1'b1) begin
-    counter <= 'h00;
-  end else if (clk_div_last == 1'b1 && wait_for_io == 1'b0) begin
-    if (bit_counter == word_length) begin
-        counter <= (counter & BIT_COUNTER_CLEAR) + (transfer_active ? 'h1 : 'h10) + BIT_COUNTER_CARRY;
-    end else begin
-      counter <= counter + (transfer_active ? 'h1 : 'h10);
+  // Load the interface configurations from the 'Configuration Write'
+  // instruction
+  always @(posedge clk) begin
+    if (resetn == 1'b0) begin
+      cpha <= DEFAULT_SPI_CFG[0];
+      cpol <= DEFAULT_SPI_CFG[1];
+      three_wire <= DEFAULT_SPI_CFG[2];
+      clk_div <= DEFAULT_CLK_DIV;
+      word_length <= DATA_WIDTH;
+      left_aligned <= 8'b0;
+    end else if (exec_write_cmd == 1'b1) begin
+      if (cmd[9:8] == REG_CONFIG) begin
+        cpha <= cmd[0];
+        cpol <= cmd[1];
+        three_wire <= cmd[2];
+      end else if (cmd[9:8] == REG_CLK_DIV) begin
+        clk_div <= cmd[7:0];
+      end else if (cmd[9:8] == REG_WORD_LENGTH) begin
+        // the max value of this reg must be DATA_WIDTH
+        word_length <= cmd[7:0];
+        left_aligned <= DATA_WIDTH - cmd[7:0];
+      end
     end
   end
-end
 
-always @(posedge clk) begin
-  if (resetn == 1'b0) begin
-    idle <= 1'b1;
-  end else begin
-    if (exec_transfer_cmd || exec_chipselect_cmd || exec_misc_cmd) begin
-      idle <= 1'b0;
+  always @(posedge clk) begin
+    if ((clk_div_last == 1'b0 && idle == 1'b0 && wait_for_io == 1'b0 &&
+      clk_div_counter == 'h01) || clk_div == 'h00)
+      clk_div_last <= 1'b1;
+    else
+      clk_div_last <= 1'b0;
+  end
+
+  always @(posedge clk) begin
+    if (clk_div_last == 1'b1 || idle == 1'b1 || wait_for_io == 1'b1) begin
+      clk_div_counter <= clk_div;
+      trigger <= 1'b1;
     end else begin
-      case (inst_d1)
-      CMD_TRANSFER: begin
-        if (transfer_active == 1'b0 && wait_for_io == 1'b0 && end_of_sdi_latch == 1'b1)
-          idle <= 1'b1;
+      clk_div_counter <= clk_div_counter - 1'b1;
+      trigger <= 1'b0;
+    end
+  end
+
+  assign trigger_tx = trigger == 1'b1 && ntx_rx == 1'b0;
+  assign trigger_rx = trigger == 1'b1 && ntx_rx == 1'b1;
+
+  assign sleep_counter_compare = sleep_counter == cmd_d1[7:0] && clk_div_last == 1'b1;
+  assign cs_sleep_counter_compare = cs_sleep_counter == cmd_d1[9:8] && clk_div_last == 1'b1;
+
+  always @(posedge clk) begin
+    if (idle == 1'b1) begin
+      counter <= 'h00;
+    end else if (clk_div_last == 1'b1 && wait_for_io == 1'b0) begin
+      if (bit_counter == word_length) begin
+          counter <= (counter & BIT_COUNTER_CLEAR) + (transfer_active ? 'h1 : 'h10) + BIT_COUNTER_CARRY;
+      end else begin
+        counter <= counter + (transfer_active ? 'h1 : 'h10);
       end
-      CMD_CHIPSELECT: begin
-        if (cs_sleep_counter_compare)
-          idle <= 1'b1;
-      end
-      CMD_MISC: begin
-        case (cmd_d1[8])
-        MISC_SLEEP: begin
-          if (sleep_counter_compare)
+    end
+  end
+
+  always @(posedge clk) begin
+    if (resetn == 1'b0) begin
+      idle <= 1'b1;
+    end else begin
+      if (exec_transfer_cmd || exec_chipselect_cmd || exec_misc_cmd) begin
+        idle <= 1'b0;
+      end else begin
+        case (inst_d1)
+        CMD_TRANSFER: begin
+          if (transfer_active == 1'b0 && wait_for_io == 1'b0 && end_of_sdi_latch == 1'b1)
             idle <= 1'b1;
         end
-        MISC_SYNC: begin
-          if (sync_ready)
+        CMD_CHIPSELECT: begin
+          if (cs_sleep_counter_compare)
             idle <= 1'b1;
         end
+        CMD_MISC: begin
+          case (cmd_d1[8])
+          MISC_SLEEP: begin
+            if (sleep_counter_compare)
+              idle <= 1'b1;
+          end
+          MISC_SYNC: begin
+            if (sync_ready)
+              idle <= 1'b1;
+          end
+          endcase
+        end
         endcase
       end
-      endcase
-    end
-  end
-end
-
-always @(posedge clk) begin
-  if (resetn == 1'b0) begin
-    cs <= 'hff;
-  end else if (cs_gen) begin
-    cs <= cmd_d1[NUM_OF_CS-1:0];
-  end
-end
-
-always @(posedge clk) begin
-  if (resetn == 1'b0) begin
-    sync_valid <= 1'b0;
-  end else begin
-    if (exec_sync_cmd == 1'b1) begin
-      sync_valid <= 1'b1;
-    end else if (sync_ready == 1'b1) begin
-      sync_valid <= 1'b0;
-    end
-  end
-end
-
-assign sync = cmd_d1[7:0];
-
-always @(posedge clk) begin
-  if (resetn == 1'b0)
-    sdo_data_ready <= 1'b0;
-  else if (sdo_enabled == 1'b1 && first_bit == 1'b1 && trigger_tx == 1'b1 && transfer_active == 1'b1)
-    sdo_data_ready <= 1'b1;
-  else if (sdo_data_valid == 1'b1)
-    sdo_data_ready <= 1'b0;
-end
-
-assign io_ready1 = (sdi_data_valid == 1'b0 || sdi_data_ready == 1'b1) &&
-        (sdo_enabled == 1'b0 || last_transfer == 1'b1 || sdo_data_valid == 1'b1);
-assign io_ready2 = (sdi_enabled == 1'b0 || sdi_data_ready == 1'b1) &&
-        (sdo_enabled == 1'b0 || last_transfer == 1'b1 || sdo_data_valid == 1'b1);
-
-always @(posedge clk) begin
-  if (idle == 1'b1) begin
-    last_transfer <= 1'b0;
-  end else if (trigger_tx == 1'b1 && transfer_active == 1'b1) begin
-    if (transfer_counter == cmd_d1[7:0])
-      last_transfer <= 1'b1;
-    else
-      last_transfer <= 1'b0;
-  end
-end
-
-always @(posedge clk) begin
-  if (resetn == 1'b0) begin
-    transfer_active <= 1'b0;
-    wait_for_io <= 1'b0;
-  end else begin
-    if (exec_transfer_cmd == 1'b1) begin
-      wait_for_io <= 1'b1;
-      transfer_active <= 1'b0;
-    end else if (wait_for_io == 1'b1 && io_ready1 == 1'b1) begin
-      wait_for_io <= 1'b0;
-      if (last_transfer == 1'b0)
-        transfer_active <= 1'b1;
-      else
-        transfer_active <= 1'b0;
-    end else if (transfer_active == 1'b1 && end_of_word == 1'b1) begin
-      if (last_transfer == 1'b1 || io_ready2 == 1'b0)
-        transfer_active <= 1'b0;
-      if (io_ready2 == 1'b0)
-        wait_for_io <= 1'b1;
-    end
-  end
-end
-
-always @(posedge clk) begin
-  if (transfer_active == 1'b1 || wait_for_io == 1'b1)
-  begin
-    sdo_t_int <= ~sdo_enabled;
-  end else begin
-    sdo_t_int <= 1'b1;
-  end
-end
-
-// Load the SDO parallel data into the SDO shift register. In case of a custom
-// data width, additional bit shifting must done at load.
-always @(posedge clk) begin
-  if ((inst_d1 == CMD_TRANSFER) && (!sdo_enabled)) begin
-    data_sdo_shift <= {DATA_WIDTH{SDO_DEFAULT}};
-  end else if (transfer_active == 1'b1 && trigger_tx == 1'b1) begin
-    if (first_bit == 1'b1)
-      data_sdo_shift <= sdo_data << left_aligned;
-    else
-      data_sdo_shift <= {data_sdo_shift[(DATA_WIDTH-2):0], 1'b0};
-  end
-end
-
-assign sdo_int_s = data_sdo_shift[DATA_WIDTH-1];
-
-// In case of an interface with high clock rate (SCLK > 50MHz), the latch of
-// the SDI line can be delayed with 1, 2 or 3 SPI core clock cycle.
-// Taking the fact that in high SCLK frequencies the pre-scaler most likely will
-// be set to 0, to reduce the core clock's speed, this delay will mean that SDI will
-// be latched at one of the next consecutive SCLK edge.
-
-always @(posedge clk) begin
-  trigger_rx_d <= {trigger_rx_d, trigger_rx};
-end
-
-assign trigger_rx_s = trigger_rx_d[SDI_DELAY+1];
-
-// Load the serial data into SDI shift register(s), then link it to the output
-// register of the module
-// NOTE: ECHO_SCLK mode can be used when the SCLK line is looped back to the FPGA
-// through an other level shifter, in order to remove the round-trip timing delays
-// introduced by the level shifters. This can improve the timing significantly
-// on higher SCLK rates. Devices like ad4630 have an echod SCLK, which can be
-// used to latch the MISO lines, improving the overall timing margin of the
-// interface.
-
-wire cs_active_s = (inst_d1 == CMD_CHIPSELECT) & ~(&cmd_d1[NUM_OF_CS-1:0]);
-genvar i;
-
-// NOTE: SPI configuration (CPOL/PHA) is only hardware configurable at this point
-generate
-if (ECHO_SCLK == 1) begin : g_echo_sclk_miso_latch
-
-  reg [7:0] sdi_counter_d = 8'b0;
-  reg [7:0] sdi_transfer_counter = 8'b0;
-  reg [7:0] num_of_transfers = 8'b0;
-  reg [(NUM_OF_SDI * DATA_WIDTH)-1:0] sdi_data_latch = {(NUM_OF_SDI * DATA_WIDTH){1'b0}};
-
-  if ((DEFAULT_SPI_CFG[1:0] == 2'b01) || (DEFAULT_SPI_CFG[1:0] == 2'b10)) begin : g_echo_miso_nshift_reg
-
-    // MISO shift register runs on negative echo_sclk
-    for (i=0; i<NUM_OF_SDI; i=i+1) begin: g_sdi_shift_reg
-      reg [DATA_WIDTH-1:0] data_sdi_shift;
-
-      always @(negedge echo_sclk or posedge cs_active_s) begin
-        if (cs_active_s) begin
-          data_sdi_shift <= 0;
-        end else begin
-          data_sdi_shift <= {data_sdi_shift, sdi[i]};
-        end
-      end
-
-      // intended LATCH
-      always @(negedge echo_sclk) begin
-        if (last_sdi_bit)
-          sdi_data_latch[i*DATA_WIDTH+:DATA_WIDTH] <= {data_sdi_shift, sdi[i]};
-      end
-
-    end
-
-    always @(posedge echo_sclk or posedge cs_active_s) begin
-      if (cs_active_s == 1'b1) begin
-        sdi_counter <= 8'b0;
-        sdi_counter_d <= 8'b0;
-      end else begin
-        sdi_counter <= (sdi_counter == word_length-1) ? 8'b0 : sdi_counter + 1'b1;
-        sdi_counter_d <= sdi_counter;
-      end
-    end
-
-  end else begin : g_echo_miso_pshift_reg
-
-    // MISO shift register runs on positive echo_sclk
-    for (i=0; i<NUM_OF_SDI; i=i+1) begin: g_sdi_shift_reg
-      reg [DATA_WIDTH-1:0] data_sdi_shift;
-      always @(posedge echo_sclk or posedge cs_active_s) begin
-        if (cs_active_s) begin
-          data_sdi_shift <= 0;
-        end else begin
-          data_sdi_shift <= {data_sdi_shift, sdi[i]};
-        end
-      end
-      // intended LATCH
-      always @(posedge echo_sclk) begin
-        if (last_sdi_bit)
-          sdi_data_latch[i*DATA_WIDTH+:DATA_WIDTH] <= data_sdi_shift;
-      end
-    end
-
-    always @(posedge echo_sclk or posedge cs_active_s) begin
-      if (cs_active_s == 1'b1) begin
-        sdi_counter <= 8'b0;
-        sdi_counter_d <= 8'b0;
-      end else begin
-        sdi_counter <= (sdi_counter == word_length-1) ? 8'b0 : sdi_counter + 1'b1;
-        sdi_counter_d <= sdi_counter;
-      end
-    end
-
-  end
-
-  assign sdi_data = sdi_data_latch;
-  assign last_sdi_bit = (sdi_counter == 0) && (sdi_counter_d == word_length-1);
-
-  // sdi_data_valid is synchronous to SPI clock, so synchronize the
-  // last_sdi_bit to SPI clock
-
-  reg [3:0] last_sdi_bit_m = 4'b0;
-  always @(posedge clk) begin
-    if (cs_active_s) begin
-      last_sdi_bit_m <= 4'b0;
-    end else begin
-      last_sdi_bit_m <= {last_sdi_bit_m, last_sdi_bit};
     end
   end
 
-  always @(posedge clk) begin
-    if (cs_active_s) begin
-      sdi_data_valid <= 1'b0;
-    end else if (sdi_enabled == 1'b1 &&
-                 last_sdi_bit_m[3] == 1'b0 &&
-                 last_sdi_bit_m[2] == 1'b1) begin
-      sdi_data_valid <= 1'b1;
-    end else if (sdi_data_ready == 1'b1) begin
-      sdi_data_valid <= 1'b0;
-    end
-  end
-
-  always @(posedge clk) begin
-    if (cs_active_s) begin
-      num_of_transfers <= 8'b0;
-    end else begin
-      if (cmd_d1[15:12] == 4'b0) begin
-        num_of_transfers <= cmd_d1[7:0] + 1'b1; // cmd_d1 contains the NUM_OF_TRANSFERS - 1
-      end
-    end
-  end
-
-  always @(posedge clk) begin
-    if (cs_active_s) begin
-      sdi_transfer_counter <= 0;
-    end else if (last_sdi_bit_m[2] == 1'b0 &&
-                 last_sdi_bit_m[1] == 1'b1) begin
-      sdi_transfer_counter <= sdi_transfer_counter + 1'b1;
-    end
-  end
-
-  assign end_of_sdi_latch = last_sdi_bit_m[2] & (sdi_transfer_counter == num_of_transfers);
-
-end /* g_echo_sclk_miso_latch */
-else
-begin : g_sclk_miso_latch
-
-  assign end_of_sdi_latch = 1'b1;
-
-  for (i=0; i<NUM_OF_SDI; i=i+1) begin: g_sdi_shift_reg
-
-    reg [DATA_WIDTH-1:0] data_sdi_shift;
-
-    always @(posedge clk) begin
-      if (cs_active_s) begin
-        data_sdi_shift <= 0;
-      end else begin
-        if (trigger_rx_s == 1'b1) begin
-          data_sdi_shift <= {data_sdi_shift, sdi[i]};
-        end
-      end
-    end
-
-    assign sdi_data[i*DATA_WIDTH+:DATA_WIDTH] = data_sdi_shift;
-
-  end
-
-  assign last_sdi_bit = (sdi_counter == word_length-1);
   always @(posedge clk) begin
     if (resetn == 1'b0) begin
-      sdi_counter <= 8'b0;
+      cs <= 'hff;
+    end else if (cs_gen) begin
+      cs <= cmd_d1[NUM_OF_CS-1:0];
+    end
+  end
+
+  always @(posedge clk) begin
+    if (resetn == 1'b0) begin
+      sync_valid <= 1'b0;
     end else begin
-      if (trigger_rx_s == 1'b1) begin
-        sdi_counter <= last_sdi_bit ? 8'b0 : sdi_counter + 1'b1;
+      if (exec_sync_cmd == 1'b1) begin
+        sync_valid <= 1'b1;
+      end else if (sync_ready == 1'b1) begin
+        sync_valid <= 1'b0;
       end
     end
   end
 
+  assign sync = cmd_d1[7:0];
+
   always @(posedge clk) begin
     if (resetn == 1'b0)
-      sdi_data_valid <= 1'b0;
-    else if (sdi_enabled == 1'b1 && last_sdi_bit == 1'b1 && trigger_rx_s == 1'b1)
-      sdi_data_valid <= 1'b1;
-    else if (sdi_data_ready == 1'b1)
-      sdi_data_valid <= 1'b0;
+      sdo_data_ready <= 1'b0;
+    else if (sdo_enabled == 1'b1 && first_bit == 1'b1 && trigger_tx == 1'b1 && transfer_active == 1'b1)
+      sdo_data_ready <= 1'b1;
+    else if (sdo_data_valid == 1'b1)
+      sdo_data_ready <= 1'b0;
   end
 
-end /* g_sclk_miso_latch */
-endgenerate
+  assign io_ready1 = (sdi_data_valid == 1'b0 || sdi_data_ready == 1'b1) &&
+          (sdo_enabled == 1'b0 || last_transfer == 1'b1 || sdo_data_valid == 1'b1);
+  assign io_ready2 = (sdi_enabled == 1'b0 || sdi_data_ready == 1'b1) &&
+          (sdo_enabled == 1'b0 || last_transfer == 1'b1 || sdo_data_valid == 1'b1);
 
-// end_of_word will signal the end of a transaction, pushing the command
-// stream execution to the next command. end_of_word in normal mode can be
-// generated using the global bit_counter
-assign last_bit = bit_counter == word_length - 1;
-assign end_of_word = last_bit == 1'b1 && ntx_rx == 1'b1 && clk_div_last == 1'b1;
-
-always @(posedge clk) begin
-  if (transfer_active == 1'b1) begin
-    sclk_int <= cpol ^ cpha ^ ntx_rx;
-  end else begin
-    sclk_int <= cpol;
+  always @(posedge clk) begin
+    if (idle == 1'b1) begin
+      last_transfer <= 1'b0;
+    end else if (trigger_tx == 1'b1 && transfer_active == 1'b1) begin
+      if (transfer_counter == cmd_d1[7:0])
+        last_transfer <= 1'b1;
+      else
+        last_transfer <= 1'b0;
+    end
   end
-end
 
-// Additional register stage to improve timing
-always @(posedge clk) begin
-  sclk <= sclk_int;
-  sdo <= sdo_int_s;
-  sdo_t <= sdo_t_int;
-end
+  always @(posedge clk) begin
+    if (resetn == 1'b0) begin
+      transfer_active <= 1'b0;
+      wait_for_io <= 1'b0;
+    end else begin
+      if (exec_transfer_cmd == 1'b1) begin
+        wait_for_io <= 1'b1;
+        transfer_active <= 1'b0;
+      end else if (wait_for_io == 1'b1 && io_ready1 == 1'b1) begin
+        wait_for_io <= 1'b0;
+        if (last_transfer == 1'b0)
+          transfer_active <= 1'b1;
+        else
+          transfer_active <= 1'b0;
+      end else if (transfer_active == 1'b1 && end_of_word == 1'b1) begin
+        if (last_transfer == 1'b1 || io_ready2 == 1'b0)
+          transfer_active <= 1'b0;
+        if (io_ready2 == 1'b0)
+          wait_for_io <= 1'b1;
+      end
+    end
+  end
+
+  always @(posedge clk) begin
+    if (transfer_active == 1'b1 || wait_for_io == 1'b1)
+    begin
+      sdo_t_int <= ~sdo_enabled;
+    end else begin
+      sdo_t_int <= 1'b1;
+    end
+  end
+
+  // Load the SDO parallel data into the SDO shift register. In case of a custom
+  // data width, additional bit shifting must done at load.
+  always @(posedge clk) begin
+    if ((inst_d1 == CMD_TRANSFER) && (!sdo_enabled)) begin
+      data_sdo_shift <= {DATA_WIDTH{SDO_DEFAULT}};
+    end else if (transfer_active == 1'b1 && trigger_tx == 1'b1) begin
+      if (first_bit == 1'b1)
+        data_sdo_shift <= sdo_data << left_aligned;
+      else
+        data_sdo_shift <= {data_sdo_shift[(DATA_WIDTH-2):0], 1'b0};
+    end
+  end
+
+  assign sdo_int_s = data_sdo_shift[DATA_WIDTH-1];
+
+  // In case of an interface with high clock rate (SCLK > 50MHz), the latch of
+  // the SDI line can be delayed with 1, 2 or 3 SPI core clock cycle.
+  // Taking the fact that in high SCLK frequencies the pre-scaler most likely will
+  // be set to 0, to reduce the core clock's speed, this delay will mean that SDI will
+  // be latched at one of the next consecutive SCLK edge.
+
+  always @(posedge clk) begin
+    trigger_rx_d <= {trigger_rx_d, trigger_rx};
+  end
+
+  assign trigger_rx_s = trigger_rx_d[SDI_DELAY+1];
+
+  // Load the serial data into SDI shift register(s), then link it to the output
+  // register of the module
+  // NOTE: ECHO_SCLK mode can be used when the SCLK line is looped back to the FPGA
+  // through an other level shifter, in order to remove the round-trip timing delays
+  // introduced by the level shifters. This can improve the timing significantly
+  // on higher SCLK rates. Devices like ad4630 have an echod SCLK, which can be
+  // used to latch the MISO lines, improving the overall timing margin of the
+  // interface.
+
+  wire cs_active_s = (inst_d1 == CMD_CHIPSELECT) & ~(&cmd_d1[NUM_OF_CS-1:0]);
+  genvar i;
+
+  // NOTE: SPI configuration (CPOL/PHA) is only hardware configurable at this point
+  generate
+  if (ECHO_SCLK == 1) begin : g_echo_sclk_miso_latch
+
+    reg [7:0] sdi_counter_d = 8'b0;
+    reg [7:0] sdi_transfer_counter = 8'b0;
+    reg [7:0] num_of_transfers = 8'b0;
+    reg [(NUM_OF_SDI * DATA_WIDTH)-1:0] sdi_data_latch = {(NUM_OF_SDI * DATA_WIDTH){1'b0}};
+
+    if ((DEFAULT_SPI_CFG[1:0] == 2'b01) || (DEFAULT_SPI_CFG[1:0] == 2'b10)) begin : g_echo_miso_nshift_reg
+
+      // MISO shift register runs on negative echo_sclk
+      for (i=0; i<NUM_OF_SDI; i=i+1) begin: g_sdi_shift_reg
+        reg [DATA_WIDTH-1:0] data_sdi_shift;
+
+        always @(negedge echo_sclk or posedge cs_active_s) begin
+          if (cs_active_s) begin
+            data_sdi_shift <= 0;
+          end else begin
+            data_sdi_shift <= {data_sdi_shift, sdi[i]};
+          end
+        end
+
+        // intended LATCH
+        always @(negedge echo_sclk) begin
+          if (last_sdi_bit)
+            sdi_data_latch[i*DATA_WIDTH+:DATA_WIDTH] <= {data_sdi_shift, sdi[i]};
+        end
+
+      end
+
+      always @(posedge echo_sclk or posedge cs_active_s) begin
+        if (cs_active_s == 1'b1) begin
+          sdi_counter <= 8'b0;
+          sdi_counter_d <= 8'b0;
+        end else begin
+          sdi_counter <= (sdi_counter == word_length-1) ? 8'b0 : sdi_counter + 1'b1;
+          sdi_counter_d <= sdi_counter;
+        end
+      end
+
+    end else begin : g_echo_miso_pshift_reg
+
+      // MISO shift register runs on positive echo_sclk
+      for (i=0; i<NUM_OF_SDI; i=i+1) begin: g_sdi_shift_reg
+        reg [DATA_WIDTH-1:0] data_sdi_shift;
+        always @(posedge echo_sclk or posedge cs_active_s) begin
+          if (cs_active_s) begin
+            data_sdi_shift <= 0;
+          end else begin
+            data_sdi_shift <= {data_sdi_shift, sdi[i]};
+          end
+        end
+        // intended LATCH
+        always @(posedge echo_sclk) begin
+          if (last_sdi_bit)
+            sdi_data_latch[i*DATA_WIDTH+:DATA_WIDTH] <= data_sdi_shift;
+        end
+      end
+
+      always @(posedge echo_sclk or posedge cs_active_s) begin
+        if (cs_active_s == 1'b1) begin
+          sdi_counter <= 8'b0;
+          sdi_counter_d <= 8'b0;
+        end else begin
+          sdi_counter <= (sdi_counter == word_length-1) ? 8'b0 : sdi_counter + 1'b1;
+          sdi_counter_d <= sdi_counter;
+        end
+      end
+
+    end
+
+    assign sdi_data = sdi_data_latch;
+    assign last_sdi_bit = (sdi_counter == 0) && (sdi_counter_d == word_length-1);
+
+    // sdi_data_valid is synchronous to SPI clock, so synchronize the
+    // last_sdi_bit to SPI clock
+
+    reg [3:0] last_sdi_bit_m = 4'b0;
+    always @(posedge clk) begin
+      if (cs_active_s) begin
+        last_sdi_bit_m <= 4'b0;
+      end else begin
+        last_sdi_bit_m <= {last_sdi_bit_m, last_sdi_bit};
+      end
+    end
+
+    always @(posedge clk) begin
+      if (cs_active_s) begin
+        sdi_data_valid <= 1'b0;
+      end else if (sdi_enabled == 1'b1 &&
+                   last_sdi_bit_m[3] == 1'b0 &&
+                   last_sdi_bit_m[2] == 1'b1) begin
+        sdi_data_valid <= 1'b1;
+      end else if (sdi_data_ready == 1'b1) begin
+        sdi_data_valid <= 1'b0;
+      end
+    end
+
+    always @(posedge clk) begin
+      if (cs_active_s) begin
+        num_of_transfers <= 8'b0;
+      end else begin
+        if (cmd_d1[15:12] == 4'b0) begin
+          num_of_transfers <= cmd_d1[7:0] + 1'b1; // cmd_d1 contains the NUM_OF_TRANSFERS - 1
+        end
+      end
+    end
+
+    always @(posedge clk) begin
+      if (cs_active_s) begin
+        sdi_transfer_counter <= 0;
+      end else if (last_sdi_bit_m[2] == 1'b0 &&
+                   last_sdi_bit_m[1] == 1'b1) begin
+        sdi_transfer_counter <= sdi_transfer_counter + 1'b1;
+      end
+    end
+
+    assign end_of_sdi_latch = last_sdi_bit_m[2] & (sdi_transfer_counter == num_of_transfers);
+
+  end /* g_echo_sclk_miso_latch */
+  else
+  begin : g_sclk_miso_latch
+
+    assign end_of_sdi_latch = 1'b1;
+
+    for (i=0; i<NUM_OF_SDI; i=i+1) begin: g_sdi_shift_reg
+
+      reg [DATA_WIDTH-1:0] data_sdi_shift;
+
+      always @(posedge clk) begin
+        if (cs_active_s) begin
+          data_sdi_shift <= 0;
+        end else begin
+          if (trigger_rx_s == 1'b1) begin
+            data_sdi_shift <= {data_sdi_shift, sdi[i]};
+          end
+        end
+      end
+
+      assign sdi_data[i*DATA_WIDTH+:DATA_WIDTH] = data_sdi_shift;
+
+    end
+
+    assign last_sdi_bit = (sdi_counter == word_length-1);
+    always @(posedge clk) begin
+      if (resetn == 1'b0) begin
+        sdi_counter <= 8'b0;
+      end else begin
+        if (trigger_rx_s == 1'b1) begin
+          sdi_counter <= last_sdi_bit ? 8'b0 : sdi_counter + 1'b1;
+        end
+      end
+    end
+
+    always @(posedge clk) begin
+      if (resetn == 1'b0)
+        sdi_data_valid <= 1'b0;
+      else if (sdi_enabled == 1'b1 && last_sdi_bit == 1'b1 && trigger_rx_s == 1'b1)
+        sdi_data_valid <= 1'b1;
+      else if (sdi_data_ready == 1'b1)
+        sdi_data_valid <= 1'b0;
+    end
+
+  end /* g_sclk_miso_latch */
+  endgenerate
+
+  // end_of_word will signal the end of a transaction, pushing the command
+  // stream execution to the next command. end_of_word in normal mode can be
+  // generated using the global bit_counter
+  assign last_bit = bit_counter == word_length - 1;
+  assign end_of_word = last_bit == 1'b1 && ntx_rx == 1'b1 && clk_div_last == 1'b1;
+
+  always @(posedge clk) begin
+    if (transfer_active == 1'b1) begin
+      sclk_int <= cpol ^ cpha ^ ntx_rx;
+    end else begin
+      sclk_int <= cpol;
+    end
+  end
+
+  // Additional register stage to improve timing
+  always @(posedge clk) begin
+    sclk <= sclk_int;
+    sdo <= sdo_int_s;
+    sdo_t <= sdo_t_int;
+  end
 
 endmodule
diff --git a/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v b/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v
index a5df47d2a..304b8e8c4 100644
--- a/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v
+++ b/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v
@@ -37,9 +37,9 @@
 
 module spi_engine_interconnect #(
 
-  parameter DATA_WIDTH = 8,                   // Valid data widths values are 8/16/24/32
-  parameter NUM_OF_SDI = 1 ) (
-
+  parameter DATA_WIDTH = 8, // Valid data widths values are 8/16/24/32
+  parameter NUM_OF_SDI = 1
+) (
   input clk,
   input resetn,
 
@@ -59,7 +59,6 @@ module spi_engine_interconnect #(
   output m_sync_ready,
   input [7:0] m_sync,
 
-
   input s0_cmd_valid,
   output s0_cmd_ready,
   input [15:0] s0_cmd_data,
@@ -76,7 +75,6 @@ module spi_engine_interconnect #(
   input s0_sync_ready,
   output [7:0] s0_sync,
 
-
   input s1_cmd_valid,
   output s1_cmd_ready,
   input [15:0] s1_cmd_data,
@@ -94,53 +92,53 @@ module spi_engine_interconnect #(
   output [7:0] s1_sync
 );
 
-reg s_active = 1'b0;
+  reg s_active = 1'b0;
 
-reg idle = 1'b1;
+  reg idle = 1'b1;
 
-`define spi_engine_interconnect_mux(s0, s1) (idle == 1'b1 ? 1'b0 : (s_active == 1'b0 ? s0 : s1))
+  `define spi_engine_interconnect_mux(s0, s1) (idle == 1'b1 ? 1'b0 : (s_active == 1'b0 ? s0 : s1))
 
-assign m_cmd_data   = s_active == 1'b0 ? s0_cmd_data : s1_cmd_data;
-assign m_cmd_valid  = `spi_engine_interconnect_mux(s0_cmd_valid, s1_cmd_valid);
-assign s0_cmd_ready = `spi_engine_interconnect_mux(m_cmd_ready, 1'b0);
-assign s1_cmd_ready = `spi_engine_interconnect_mux(1'b0, m_cmd_ready);
+  assign m_cmd_data   = s_active == 1'b0 ? s0_cmd_data : s1_cmd_data;
+  assign m_cmd_valid  = `spi_engine_interconnect_mux(s0_cmd_valid, s1_cmd_valid);
+  assign s0_cmd_ready = `spi_engine_interconnect_mux(m_cmd_ready, 1'b0);
+  assign s1_cmd_ready = `spi_engine_interconnect_mux(1'b0, m_cmd_ready);
 
-assign m_sdo_data   = s_active == 1'b0 ? s0_sdo_data : s1_sdo_data;
-assign m_sdo_valid  = `spi_engine_interconnect_mux(s0_sdo_valid, s1_sdo_valid);
-assign s0_sdo_ready = `spi_engine_interconnect_mux(m_sdo_ready, 1'b0);
-assign s1_sdo_ready = `spi_engine_interconnect_mux(1'b0, m_sdo_ready);
+  assign m_sdo_data   = s_active == 1'b0 ? s0_sdo_data : s1_sdo_data;
+  assign m_sdo_valid  = `spi_engine_interconnect_mux(s0_sdo_valid, s1_sdo_valid);
+  assign s0_sdo_ready = `spi_engine_interconnect_mux(m_sdo_ready, 1'b0);
+  assign s1_sdo_ready = `spi_engine_interconnect_mux(1'b0, m_sdo_ready);
 
-assign s0_sdi_data  = m_sdi_data;
-assign s1_sdi_data  = m_sdi_data;
-assign m_sdi_ready  = `spi_engine_interconnect_mux(s0_sdi_ready, s1_sdi_ready);
-assign s0_sdi_valid = `spi_engine_interconnect_mux(m_sdi_valid, 1'b0);
-assign s1_sdi_valid = `spi_engine_interconnect_mux(1'b0, m_sdi_valid);
+  assign s0_sdi_data  = m_sdi_data;
+  assign s1_sdi_data  = m_sdi_data;
+  assign m_sdi_ready  = `spi_engine_interconnect_mux(s0_sdi_ready, s1_sdi_ready);
+  assign s0_sdi_valid = `spi_engine_interconnect_mux(m_sdi_valid, 1'b0);
+  assign s1_sdi_valid = `spi_engine_interconnect_mux(1'b0, m_sdi_valid);
 
-assign s0_sync       = m_sync;
-assign s1_sync       = m_sync;
-assign m_sync_ready  = `spi_engine_interconnect_mux(s0_sync_ready, s1_sync_ready);
-assign s0_sync_valid = `spi_engine_interconnect_mux(m_sync_valid, 1'b0);
-assign s1_sync_valid = `spi_engine_interconnect_mux(1'b0, m_sync_valid);
+  assign s0_sync       = m_sync;
+  assign s1_sync       = m_sync;
+  assign m_sync_ready  = `spi_engine_interconnect_mux(s0_sync_ready, s1_sync_ready);
+  assign s0_sync_valid = `spi_engine_interconnect_mux(m_sync_valid, 1'b0);
+  assign s1_sync_valid = `spi_engine_interconnect_mux(1'b0, m_sync_valid);
 
-always @(posedge clk) begin
-  if (idle == 1'b1) begin
-    if (s0_cmd_valid)
-      s_active <= 1'b0;
-    else if (s1_cmd_valid)
-      s_active <= 1'b1;
-  end
-end
-
-always @(posedge clk) begin
-  if (resetn == 1'b0) begin
-    idle <= 1'b1;
-  end else begin
-    if (m_sync_valid == 1'b1 && m_sync_ready == 1'b1) begin
-      idle <= 1'b1;
-    end else if (s0_cmd_valid == 1'b1 || s1_cmd_valid == 1'b1) begin
-      idle <= 1'b0;
+  always @(posedge clk) begin
+    if (idle == 1'b1) begin
+      if (s0_cmd_valid)
+        s_active <= 1'b0;
+      else if (s1_cmd_valid)
+        s_active <= 1'b1;
+    end
+  end
+
+  always @(posedge clk) begin
+    if (resetn == 1'b0) begin
+      idle <= 1'b1;
+    end else begin
+      if (m_sync_valid == 1'b1 && m_sync_ready == 1'b1) begin
+        idle <= 1'b1;
+      end else if (s0_cmd_valid == 1'b1 || s1_cmd_valid == 1'b1) begin
+        idle <= 1'b0;
+      end
     end
   end
-end
 
 endmodule
diff --git a/library/spi_engine/spi_engine_offload/spi_engine_offload.v b/library/spi_engine/spi_engine_offload/spi_engine_offload.v
index 701c23465..544649d83 100644
--- a/library/spi_engine/spi_engine_offload/spi_engine_offload.v
+++ b/library/spi_engine/spi_engine_offload/spi_engine_offload.v
@@ -41,9 +41,9 @@ module spi_engine_offload #(
   parameter ASYNC_TRIG = 0,
   parameter CMD_MEM_ADDRESS_WIDTH = 4,
   parameter SDO_MEM_ADDRESS_WIDTH = 4,
-  parameter DATA_WIDTH = 8,                   // Valid data widths values are 8/16/24/32
-  parameter NUM_OF_SDI = 1 ) (
-
+  parameter DATA_WIDTH = 8, // Valid data widths values are 8/16/24/32
+  parameter NUM_OF_SDI = 1
+) (
   input ctrl_clk,
 
   input ctrl_cmd_wr_en,
@@ -86,224 +86,219 @@ module spi_engine_offload #(
   output [(NUM_OF_SDI * DATA_WIDTH-1):0] offload_sdi_data
 );
 
-reg spi_active = 1'b0;
+  reg spi_active = 1'b0;
 
-reg [CMD_MEM_ADDRESS_WIDTH-1:0] ctrl_cmd_wr_addr = 'h00;
-reg [CMD_MEM_ADDRESS_WIDTH-1:0] spi_cmd_rd_addr = 'h00;
-reg [SDO_MEM_ADDRESS_WIDTH-1:0] ctrl_sdo_wr_addr = 'h00;
-reg [SDO_MEM_ADDRESS_WIDTH-1:0] spi_sdo_rd_addr = 'h00;
+  reg [CMD_MEM_ADDRESS_WIDTH-1:0] ctrl_cmd_wr_addr = 'h00;
+  reg [CMD_MEM_ADDRESS_WIDTH-1:0] spi_cmd_rd_addr = 'h00;
+  reg [SDO_MEM_ADDRESS_WIDTH-1:0] ctrl_sdo_wr_addr = 'h00;
+  reg [SDO_MEM_ADDRESS_WIDTH-1:0] spi_sdo_rd_addr = 'h00;
 
-reg [15:0] cmd_mem[0:2**CMD_MEM_ADDRESS_WIDTH-1];
-reg [(DATA_WIDTH-1):0] sdo_mem[0:2**SDO_MEM_ADDRESS_WIDTH-1];
+  reg [15:0] cmd_mem[0:2**CMD_MEM_ADDRESS_WIDTH-1];
+  reg [(DATA_WIDTH-1):0] sdo_mem[0:2**SDO_MEM_ADDRESS_WIDTH-1];
 
-wire [15:0] cmd_int_s;
-wire [CMD_MEM_ADDRESS_WIDTH-1:0] spi_cmd_rd_addr_next;
-wire spi_enable;
+  wire [15:0] cmd_int_s;
+  wire [CMD_MEM_ADDRESS_WIDTH-1:0] spi_cmd_rd_addr_next;
+  wire spi_enable;
 
-assign cmd_valid = spi_active;
-assign sdo_data_valid = spi_active;
+  assign cmd_valid = spi_active;
+  assign sdo_data_valid = spi_active;
 
-assign offload_sdi_valid = sdi_data_valid;
+  assign offload_sdi_valid = sdi_data_valid;
 
-// we don't want to block the SDI interface after disabling the module
-// so just assert the SDI_READY if the sink module (DMA) is disabled
-assign sdi_data_ready = (spi_enable) ? offload_sdi_ready : 1'b1;
+  // we don't want to block the SDI interface after disabling the module
+  // so just assert the SDI_READY if the sink module (DMA) is disabled
+  assign sdi_data_ready = (spi_enable) ? offload_sdi_ready : 1'b1;
 
-assign offload_sdi_data = sdi_data;
+  assign offload_sdi_data = sdi_data;
 
-assign cmd_int_s = cmd_mem[spi_cmd_rd_addr];
-assign sdo_data = sdo_mem[spi_sdo_rd_addr];
+  assign cmd_int_s = cmd_mem[spi_cmd_rd_addr];
+  assign sdo_data = sdo_mem[spi_sdo_rd_addr];
 
-/* SYNC ID counter. The offload module increments the sync_id on each
- * transaction. The initial value of the sync_id is the value of the last
- * sync_id command loaded into the command buffer.
- */
+  /* SYNC ID counter. The offload module increments the sync_id on each
+   * transaction. The initial value of the sync_id is the value of the last
+   * sync_id command loaded into the command buffer.
+   */
 
-reg [ 7:0] ctrl_sync_id_init = 8'b0;
-reg        ctrl_sync_id_load = 1'b0;
-reg [ 7:0] spi_sync_id_counter = 8'b0;
+  reg [ 7:0] ctrl_sync_id_init = 8'b0;
+  reg        ctrl_sync_id_load = 1'b0;
+  reg [ 7:0] spi_sync_id_counter = 8'b0;
 
-wire [ 7:0] spi_sync_id_init_s;
+  wire [ 7:0] spi_sync_id_init_s;
 
-always @(posedge ctrl_clk) begin
-  if (ctrl_mem_reset == 1'b1) begin
-    ctrl_sync_id_init <= 8'b0;
-    ctrl_sync_id_load <= 1'b0;
-  end else begin
-    if (ctrl_cmd_wr_en && (ctrl_cmd_wr_data[15:8] == 8'h30)) begin
-      ctrl_sync_id_init <= ctrl_cmd_wr_data;
-      ctrl_sync_id_load <= 1'b1;
-    end else begin
+  always @(posedge ctrl_clk) begin
+    if (ctrl_mem_reset == 1'b1) begin
+      ctrl_sync_id_init <= 8'b0;
       ctrl_sync_id_load <= 1'b0;
+    end else begin
+      if (ctrl_cmd_wr_en && (ctrl_cmd_wr_data[15:8] == 8'h30)) begin
+        ctrl_sync_id_init <= ctrl_cmd_wr_data;
+        ctrl_sync_id_load <= 1'b1;
+      end else begin
+        ctrl_sync_id_load <= 1'b0;
+      end
     end
   end
-end
 
-wire spi_sync_id_load_s;
+  wire spi_sync_id_load_s;
 
-sync_event # (
+  sync_event #(
     .NUM_OF_EVENTS(1),
     .ASYNC_CLK(1)
-) i_sync_sync_id_load (
+  ) i_sync_sync_id_load (
     .in_clk (ctrl_clk),
     .in_event(ctrl_sync_id_load),
     .out_clk(spi_clk),
-    .out_event(spi_sync_id_load_s)
-);
+    .out_event(spi_sync_id_load_s));
 
-sync_bits # (
+  sync_bits #(
     .NUM_OF_BITS(8),
     .ASYNC_CLK(1)
-) i_sync_sync_id (
+  ) i_sync_sync_id (
     .in_bits(ctrl_sync_id_init),
     .out_clk(spi_clk),
     .out_resetn(1'b1),
-    .out_bits(spi_sync_id_init_s)
-);
+    .out_bits(spi_sync_id_init_s));
 
-always @(posedge spi_clk) begin
-  if (spi_resetn == 1'b0) begin
-    spi_sync_id_counter <= 8'b0;
-  end else begin
-    if (spi_sync_id_load_s) begin
-      spi_sync_id_counter <= spi_sync_id_init_s;
-    end else if(cmd_valid && cmd_ready && (cmd[15:8] == 8'h30)) begin
-      spi_sync_id_counter <= spi_sync_id_counter + 1'b1;
+  always @(posedge spi_clk) begin
+    if (spi_resetn == 1'b0) begin
+      spi_sync_id_counter <= 8'b0;
+    end else begin
+      if (spi_sync_id_load_s) begin
+        spi_sync_id_counter <= spi_sync_id_init_s;
+      end else if(cmd_valid && cmd_ready && (cmd[15:8] == 8'h30)) begin
+        spi_sync_id_counter <= spi_sync_id_counter + 1'b1;
+      end
     end
   end
-end
 
-assign cmd = (cmd_int_s[15:8] == 8'h30) ? {cmd_int_s[15:8], spi_sync_id_counter} : cmd_int_s;
+  assign cmd = (cmd_int_s[15:8] == 8'h30) ? {cmd_int_s[15:8], spi_sync_id_counter} : cmd_int_s;
 
-/*
- * Forwarded SYNC interface, this can be used to monitor the state of the
- * offload command sequence through SPI Engine regmap
- */
+  /*
+   * Forwarded SYNC interface, this can be used to monitor the state of the
+   * offload command sequence through SPI Engine regmap
+   */
 
-assign status_sync_data = sync_data;
-assign status_sync_valid = sync_valid;
-assign sync_ready = status_sync_ready;
+  assign status_sync_data = sync_data;
+  assign status_sync_valid = sync_valid;
+  assign sync_ready = status_sync_ready;
 
-generate if (ASYNC_SPI_CLK) begin
+  generate if (ASYNC_SPI_CLK) begin
 
-/*
- * The synchronization circuit takes care that there are no glitches on the
- * ctrl_enabled signal. ctrl_do_enable is asserted whenever ctrl_enable is
- * asserted, but only deasserted once the signal has been synchronized back from
- * the SPI domain. This makes sure that we can't end up in a state where the
- * enable signal in the SPI domain is asserted, but neither enable nor enabled
- * is asserted in the control domain.
- */
+  /*
+   * The synchronization circuit takes care that there are no glitches on the
+   * ctrl_enabled signal. ctrl_do_enable is asserted whenever ctrl_enable is
+   * asserted, but only deasserted once the signal has been synchronized back from
+   * the SPI domain. This makes sure that we can't end up in a state where the
+   * enable signal in the SPI domain is asserted, but neither enable nor enabled
+   * is asserted in the control domain.
+   */
 
-reg ctrl_do_enable = 1'b0;
-wire ctrl_is_enabled;
-reg spi_enabled = 1'b0;
+  reg ctrl_do_enable = 1'b0;
+  wire ctrl_is_enabled;
+  reg spi_enabled = 1'b0;
 
-always @(posedge ctrl_clk) begin
-  if (ctrl_enable == 1'b1) begin
-    ctrl_do_enable <= 1'b1;
-  end else if (ctrl_is_enabled == 1'b1) begin
-    ctrl_do_enable <= 1'b0;
+  always @(posedge ctrl_clk) begin
+    if (ctrl_enable == 1'b1) begin
+      ctrl_do_enable <= 1'b1;
+    end else if (ctrl_is_enabled == 1'b1) begin
+      ctrl_do_enable <= 1'b0;
+    end
   end
-end
 
-assign ctrl_enabled = ctrl_is_enabled | ctrl_do_enable;
+  assign ctrl_enabled = ctrl_is_enabled | ctrl_do_enable;
 
-always @(posedge spi_clk) begin
-  spi_enabled <= spi_enable | spi_active;
-end
+  always @(posedge spi_clk) begin
+    spi_enabled <= spi_enable | spi_active;
+  end
 
-sync_bits # (
+  sync_bits #(
     .NUM_OF_BITS(1),
     .ASYNC_CLK(1)
-) i_sync_enable (
+  ) i_sync_enable (
     .in_bits(ctrl_do_enable),
     .out_clk(spi_clk),
     .out_resetn(1'b1),
-    .out_bits(spi_enable)
-);
+    .out_bits(spi_enable));
 
-sync_bits # (
+  sync_bits #(
     .NUM_OF_BITS(1),
     .ASYNC_CLK(1)
-) i_sync_enabled (
+  ) i_sync_enabled (
     .in_bits(spi_enabled),
     .out_clk(ctrl_clk),
     .out_resetn(1'b1),
-    .out_bits(ctrl_is_enabled)
-);
+    .out_bits(ctrl_is_enabled));
 
-end else begin
-assign spi_enable = ctrl_enable;
-assign ctrl_enabled = spi_enable | spi_active;
-end endgenerate
-
-assign spi_cmd_rd_addr_next = spi_cmd_rd_addr + 1;
-
-wire trigger_s;
-sync_bits #(
-  .NUM_OF_BITS(1),
-  .ASYNC_CLK(ASYNC_TRIG)
-) i_sync_trigger (
-  .in_bits(trigger),
-  .out_clk(spi_clk),
-  .out_resetn(1'b1),
-  .out_bits(trigger_s)
-);
-
-always @(posedge spi_clk) begin
-  if (spi_resetn == 1'b0) begin
-    spi_active <= 1'b0;
   end else begin
-    if (spi_active == 1'b0) begin
-      // start offload when we have a valid trigger, offload is enabled and
-      // the DMA is enabled
-      if (trigger_s == 1'b1 && spi_enable == 1'b1 && offload_sdi_ready == 1'b1)
-        spi_active <= 1'b1;
-    end else if (cmd_ready == 1'b1 && spi_cmd_rd_addr_next == ctrl_cmd_wr_addr) begin
+  assign spi_enable = ctrl_enable;
+  assign ctrl_enabled = spi_enable | spi_active;
+  end endgenerate
+
+  assign spi_cmd_rd_addr_next = spi_cmd_rd_addr + 1;
+
+  wire trigger_s;
+  sync_bits #(
+    .NUM_OF_BITS(1),
+    .ASYNC_CLK(ASYNC_TRIG)
+  ) i_sync_trigger (
+    .in_bits(trigger),
+    .out_clk(spi_clk),
+    .out_resetn(1'b1),
+    .out_bits(trigger_s));
+
+  always @(posedge spi_clk) begin
+    if (spi_resetn == 1'b0) begin
       spi_active <= 1'b0;
+    end else begin
+      if (spi_active == 1'b0) begin
+        // start offload when we have a valid trigger, offload is enabled and
+        // the DMA is enabled
+        if (trigger_s == 1'b1 && spi_enable == 1'b1 && offload_sdi_ready == 1'b1)
+          spi_active <= 1'b1;
+      end else if (cmd_ready == 1'b1 && spi_cmd_rd_addr_next == ctrl_cmd_wr_addr) begin
+        spi_active <= 1'b0;
+      end
     end
   end
-end
 
-always @(posedge spi_clk) begin
-  if (cmd_valid == 1'b0) begin
-    spi_cmd_rd_addr <= 'h00;
-  end else if (cmd_ready == 1'b1) begin
-    spi_cmd_rd_addr <= spi_cmd_rd_addr_next;
+  always @(posedge spi_clk) begin
+    if (cmd_valid == 1'b0) begin
+      spi_cmd_rd_addr <= 'h00;
+    end else if (cmd_ready == 1'b1) begin
+      spi_cmd_rd_addr <= spi_cmd_rd_addr_next;
+    end
   end
-end
 
-always @(posedge spi_clk) begin
-  if (spi_active == 1'b0) begin
-    spi_sdo_rd_addr <= 'h00;
-  end else if (sdo_data_ready == 1'b1) begin
-    spi_sdo_rd_addr <= spi_sdo_rd_addr + 1'b1;
+  always @(posedge spi_clk) begin
+    if (spi_active == 1'b0) begin
+      spi_sdo_rd_addr <= 'h00;
+    end else if (sdo_data_ready == 1'b1) begin
+      spi_sdo_rd_addr <= spi_sdo_rd_addr + 1'b1;
+    end
   end
-end
 
-always @(posedge ctrl_clk) begin
-  if (ctrl_mem_reset == 1'b1)
-    ctrl_cmd_wr_addr <= 'h00;
-  else if (ctrl_cmd_wr_en == 1'b1)
-    ctrl_cmd_wr_addr <= ctrl_cmd_wr_addr + 1'b1;
-end
+  always @(posedge ctrl_clk) begin
+    if (ctrl_mem_reset == 1'b1)
+      ctrl_cmd_wr_addr <= 'h00;
+    else if (ctrl_cmd_wr_en == 1'b1)
+      ctrl_cmd_wr_addr <= ctrl_cmd_wr_addr + 1'b1;
+  end
 
-always @(posedge ctrl_clk) begin
-  if (ctrl_cmd_wr_en == 1'b1)
-    cmd_mem[ctrl_cmd_wr_addr] <= ctrl_cmd_wr_data;
-end
+  always @(posedge ctrl_clk) begin
+    if (ctrl_cmd_wr_en == 1'b1)
+      cmd_mem[ctrl_cmd_wr_addr] <= ctrl_cmd_wr_data;
+  end
 
-always @(posedge ctrl_clk) begin
-  if (ctrl_mem_reset == 1'b1)
-    ctrl_sdo_wr_addr <= 'h00;
-  else if (ctrl_sdo_wr_en == 1'b1)
-    ctrl_sdo_wr_addr <= ctrl_sdo_wr_addr + 1'b1;
-end
+  always @(posedge ctrl_clk) begin
+    if (ctrl_mem_reset == 1'b1)
+      ctrl_sdo_wr_addr <= 'h00;
+    else if (ctrl_sdo_wr_en == 1'b1)
+      ctrl_sdo_wr_addr <= ctrl_sdo_wr_addr + 1'b1;
+  end
 
-always @(posedge ctrl_clk) begin
-  if (ctrl_sdo_wr_en == 1'b1)
-    sdo_mem[ctrl_sdo_wr_addr] <= ctrl_sdo_wr_data;
-end
+  always @(posedge ctrl_clk) begin
+    if (ctrl_sdo_wr_en == 1'b1)
+      sdo_mem[ctrl_sdo_wr_addr] <= ctrl_sdo_wr_data;
+  end
 
 endmodule
diff --git a/library/sysid_rom/sysid_rom.v b/library/sysid_rom/sysid_rom.v
index e49b3a6b2..62c5ced2e 100755
--- a/library/sysid_rom/sysid_rom.v
+++ b/library/sysid_rom/sysid_rom.v
@@ -1,22 +1,57 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2019 - 2022 (c) Analog Devices, Inc. All rights reserved.
+//
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
+//
+// The user should read each of these license terms, and understand the
+// freedoms and responsibilities that he or she has by using this source/core.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+//   1. The GNU General Public License version 2 as published by the
+//      Free Software Foundation, which can be found in the top level directory
+//      of this repository (LICENSE_GPL2), and also online at:
+//      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+//
+// OR
+//
+//   2. An ADI specific BSD license, which can be found in the top level directory
+//      of this repository (LICENSE_ADIBSD), and also on-line at:
+//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      This will allow to generate bit files and not release the source code,
+//      as long as it attaches to an ADI device.
+//
+// ***************************************************************************
+
 `timescale 1ns / 1ps
 
-module sysid_rom#(
+module sysid_rom #(
   parameter ROM_WIDTH = 32,
   parameter ROM_ADDR_BITS = 6,
-  parameter PATH_TO_FILE = "path_to_mem_init_file" )(
-
+  parameter PATH_TO_FILE = "path_to_mem_init_file"
+) (
   input                             clk,
   input        [ROM_ADDR_BITS-1:0]  rom_addr,
-  output  reg  [ROM_WIDTH-1:0]      rom_data);
+  output  reg  [ROM_WIDTH-1:0]      rom_data
+);
 
-reg [ROM_WIDTH-1:0] lut_rom [(2**ROM_ADDR_BITS)-1:0];
+  reg [ROM_WIDTH-1:0] lut_rom [(2**ROM_ADDR_BITS)-1:0];
 
-initial begin
-  $readmemh(PATH_TO_FILE, lut_rom, 0, (2**ROM_ADDR_BITS)-1);
-end
+  initial begin
+    $readmemh(PATH_TO_FILE, lut_rom, 0, (2**ROM_ADDR_BITS)-1);
+  end
 
-always @(posedge clk) begin
-  rom_data = lut_rom[rom_addr];
-end
+  always @(posedge clk) begin
+    rom_data = lut_rom[rom_addr];
+  end
 
 endmodule
diff --git a/library/util_adcfifo/util_adcfifo.v b/library/util_adcfifo/util_adcfifo.v
index 972ece0af..5239e8aa3 100644
--- a/library/util_adcfifo/util_adcfifo.v
+++ b/library/util_adcfifo/util_adcfifo.v
@@ -41,7 +41,8 @@ module util_adcfifo #(
   parameter   ADC_DATA_WIDTH = 256,
   parameter   DMA_DATA_WIDTH =  64,
   parameter   DMA_READY_ENABLE = 1,
-  parameter   DMA_ADDRESS_WIDTH =  10) (
+  parameter   DMA_ADDRESS_WIDTH =  10
+) (
 
   // fifo interface
 
@@ -58,8 +59,8 @@ module util_adcfifo #(
   output      [DMA_DATA_WIDTH-1:0]      dma_wdata,
   input                                 dma_wready,
   input                                 dma_xfer_req,
-  output      [ 3:0]                    dma_xfer_status);
-
+  output      [ 3:0]                    dma_xfer_status
+);
 
   localparam  DMA_MEM_RATIO = ADC_DATA_WIDTH/DMA_DATA_WIDTH;
   localparam  ADDRESS_PADDING_WIDTH = (DMA_MEM_RATIO == 1) ? 0 :
@@ -165,8 +166,8 @@ module util_adcfifo #(
 
   sync_gray #(
     .DATA_WIDTH (ADC_ADDRESS_WIDTH),
-    .ASYNC_CLK (1))
-  i_dma_waddr_sync (
+    .ASYNC_CLK (1)
+  ) i_dma_waddr_sync (
     .in_clk (adc_clk),
     .in_resetn (1'b1),
     .in_count (adc_waddr_int),
@@ -223,8 +224,8 @@ module util_adcfifo #(
     .A_ADDRESS_WIDTH (ADC_ADDRESS_WIDTH),
     .A_DATA_WIDTH (ADC_DATA_WIDTH),
     .B_ADDRESS_WIDTH (DMA_ADDRESS_WIDTH),
-    .B_DATA_WIDTH (DMA_DATA_WIDTH))
-  i_mem_asym (
+    .B_DATA_WIDTH (DMA_DATA_WIDTH)
+  ) i_mem_asym (
     .clka (adc_clk),
     .wea (adc_wr_int),
     .addra (adc_waddr_int),
@@ -236,7 +237,9 @@ module util_adcfifo #(
   end
   endgenerate
 
- ad_axis_inf_rx #(.DATA_WIDTH(DMA_DATA_WIDTH)) i_axis_inf (
+  ad_axis_inf_rx #(
+    .DATA_WIDTH(DMA_DATA_WIDTH)
+  ) i_axis_inf (
     .clk (dma_clk),
     .rst (dma_read_rst_s),
     .valid (dma_rd_d),
@@ -248,6 +251,3 @@ module util_adcfifo #(
     .inf_ready (dma_wready));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/util_axis_fifo/util_axis_fifo.v b/library/util_axis_fifo/util_axis_fifo.v
index d4ad8b75a..79f2ca553 100644
--- a/library/util_axis_fifo/util_axis_fifo.v
+++ b/library/util_axis_fifo/util_axis_fifo.v
@@ -68,296 +68,291 @@ module util_axis_fifo #(
   output s_axis_almost_full
 );
 
-localparam MEM_WORD = (TKEEP_EN & TLAST_EN) ? (DATA_WIDTH+DATA_WIDTH/8+1) :
-                      (TKEEP_EN)            ? (DATA_WIDTH+DATA_WIDTH/8)   :
-                      (TLAST_EN)            ? (DATA_WIDTH+1)              :
-                                              (DATA_WIDTH);
+  localparam MEM_WORD = (TKEEP_EN & TLAST_EN) ? (DATA_WIDTH+DATA_WIDTH/8+1) :
+                        (TKEEP_EN)            ? (DATA_WIDTH+DATA_WIDTH/8)   :
+                        (TLAST_EN)            ? (DATA_WIDTH+1)              :
+                                                (DATA_WIDTH);
 
-wire [MEM_WORD-1:0] s_axis_data_int_s;
-wire [MEM_WORD-1:0] m_axis_data_int_s;
+  wire [MEM_WORD-1:0] s_axis_data_int_s;
+  wire [MEM_WORD-1:0] m_axis_data_int_s;
 
-generate if (ADDRESS_WIDTH == 0) begin : zerodeep /* it's not a real FIFO, just a 1 stage pipeline */
+  generate if (ADDRESS_WIDTH == 0) begin : zerodeep /* it's not a real FIFO, just a 1 stage pipeline */
 
-  if (ASYNC_CLK) begin
+    if (ASYNC_CLK) begin
 
-      (* KEEP = "yes" *) reg [DATA_WIDTH-1:0] cdc_sync_fifo_ram;
-      reg s_axis_waddr = 1'b0;
-      reg m_axis_raddr = 1'b0;
+        (* KEEP = "yes" *) reg [DATA_WIDTH-1:0] cdc_sync_fifo_ram;
+        reg s_axis_waddr = 1'b0;
+        reg m_axis_raddr = 1'b0;
 
-      wire m_axis_waddr;
-      wire s_axis_raddr;
+        wire m_axis_waddr;
+        wire s_axis_raddr;
 
-      sync_bits #(
-        .NUM_OF_BITS(1),
-        .ASYNC_CLK(ASYNC_CLK)
-      ) i_waddr_sync (
-        .out_clk(m_axis_aclk),
-        .out_resetn(m_axis_aresetn),
-        .in_bits(s_axis_waddr),
-        .out_bits(m_axis_waddr)
-      );
+        sync_bits #(
+          .NUM_OF_BITS(1),
+          .ASYNC_CLK(ASYNC_CLK)
+        ) i_waddr_sync (
+          .out_clk(m_axis_aclk),
+          .out_resetn(m_axis_aresetn),
+          .in_bits(s_axis_waddr),
+          .out_bits(m_axis_waddr));
 
-      sync_bits #(
-        .NUM_OF_BITS(1),
-        .ASYNC_CLK(ASYNC_CLK)
-      ) i_raddr_sync (
-        .out_clk(s_axis_aclk),
-        .out_resetn(s_axis_aresetn),
-        .in_bits(m_axis_raddr),
-        .out_bits(s_axis_raddr)
-      );
+        sync_bits #(
+          .NUM_OF_BITS(1),
+          .ASYNC_CLK(ASYNC_CLK)
+        ) i_raddr_sync (
+          .out_clk(s_axis_aclk),
+          .out_resetn(s_axis_aresetn),
+          .in_bits(m_axis_raddr),
+          .out_bits(s_axis_raddr));
 
-      assign m_axis_valid = m_axis_raddr != m_axis_waddr;
-      assign m_axis_level = ~m_axis_ready;
-      assign m_axis_empty = 0;
-      assign m_axis_almost_empty = 0;
-      assign s_axis_ready = s_axis_raddr == s_axis_waddr;
-      assign s_axis_full = 0;
-      assign s_axis_almost_full = 0;
-      assign s_axis_room = s_axis_ready;
-
-      always @(posedge s_axis_aclk) begin
-        if (s_axis_ready == 1'b1 && s_axis_valid == 1'b1)
-          cdc_sync_fifo_ram <= s_axis_data;
-      end
-
-      always @(posedge s_axis_aclk) begin
-        if (s_axis_aresetn == 1'b0) begin
-          s_axis_waddr <= 1'b0;
-        end else if (s_axis_ready & s_axis_valid) begin
-          s_axis_waddr <= s_axis_waddr + 1'b1;
-        end
-      end
-
-      always @(posedge m_axis_aclk) begin
-        if (m_axis_aresetn == 1'b0) begin
-          m_axis_raddr <= 1'b0;
-        end else begin
-        if (m_axis_valid & m_axis_ready)
-          m_axis_raddr <= m_axis_raddr + 1'b1;
-        end
-      end
-
-      assign m_axis_data = cdc_sync_fifo_ram;
-
-      // TLAST support
-      if (TLAST_EN) begin
-
-        reg axis_tlast_d;
+        assign m_axis_valid = m_axis_raddr != m_axis_waddr;
+        assign m_axis_level = ~m_axis_ready;
+        assign m_axis_empty = 0;
+        assign m_axis_almost_empty = 0;
+        assign s_axis_ready = s_axis_raddr == s_axis_waddr;
+        assign s_axis_full = 0;
+        assign s_axis_almost_full = 0;
+        assign s_axis_room = s_axis_ready;
 
         always @(posedge s_axis_aclk) begin
           if (s_axis_ready == 1'b1 && s_axis_valid == 1'b1)
+            cdc_sync_fifo_ram <= s_axis_data;
+        end
+
+        always @(posedge s_axis_aclk) begin
+          if (s_axis_aresetn == 1'b0) begin
+            s_axis_waddr <= 1'b0;
+          end else if (s_axis_ready & s_axis_valid) begin
+            s_axis_waddr <= s_axis_waddr + 1'b1;
+          end
+        end
+
+        always @(posedge m_axis_aclk) begin
+          if (m_axis_aresetn == 1'b0) begin
+            m_axis_raddr <= 1'b0;
+          end else begin
+          if (m_axis_valid & m_axis_ready)
+            m_axis_raddr <= m_axis_raddr + 1'b1;
+          end
+        end
+
+        assign m_axis_data = cdc_sync_fifo_ram;
+
+        // TLAST support
+        if (TLAST_EN) begin
+
+          reg axis_tlast_d;
+
+          always @(posedge s_axis_aclk) begin
+            if (s_axis_ready == 1'b1 && s_axis_valid == 1'b1)
+              axis_tlast_d <= s_axis_tlast;
+          end
+          assign m_axis_tlast = axis_tlast_d;
+
+        end
+
+        // TKEEP support
+        if (TKEEP_EN) begin
+
+          reg axis_tkeep_d;
+
+          always @(posedge s_axis_aclk) begin
+            if (s_axis_ready == 1'b1 && s_axis_valid == 1'b1)
+              axis_tkeep_d <= s_axis_tkeep;
+          end
+          assign m_axis_tkeep = axis_tkeep_d;
+
+        end
+
+    end /* zerodeep */
+    else
+    begin /* !ASYNC_CLK */
+
+      // Note: In this mode, the write and read interface must have a symmetric
+      // aspect ratio
+      reg [DATA_WIDTH-1:0] axis_data_d;
+      reg                  axis_valid_d;
+
+      always @(posedge s_axis_aclk) begin
+        if (!s_axis_aresetn) begin
+          axis_data_d <= {DATA_WIDTH{1'b0}};
+          axis_valid_d <= 1'b0;
+        end else if (s_axis_ready) begin
+          axis_data_d <= s_axis_data;
+          axis_valid_d <= s_axis_valid;
+        end
+      end
+
+      assign m_axis_data = axis_data_d;
+      assign m_axis_valid = axis_valid_d;
+      assign s_axis_ready = m_axis_ready | ~m_axis_valid;
+      assign m_axis_empty = 1'b0;
+      assign m_axis_almost_empty = 1'b0;
+      assign m_axis_level = 1'b0;
+      assign s_axis_full  = 1'b0;
+      assign s_axis_almost_full  = 1'b0;
+      assign s_axis_room  = 1'b0;
+
+      // TLAST support
+      if (TLAST_EN) begin
+        reg  axis_tlast_d;
+
+        always @(posedge s_axis_aclk) begin
+          if (!s_axis_aresetn) begin
+            axis_tlast_d <= 1'b0;
+          end else if (s_axis_ready) begin
             axis_tlast_d <= s_axis_tlast;
+          end
         end
         assign m_axis_tlast = axis_tlast_d;
-
       end
 
       // TKEEP support
       if (TKEEP_EN) begin
-
-        reg axis_tkeep_d;
+        reg  axis_tkeep_d;
 
         always @(posedge s_axis_aclk) begin
-          if (s_axis_ready == 1'b1 && s_axis_valid == 1'b1)
+          if (!s_axis_aresetn) begin
+            axis_tkeep_d <= 1'b0;
+          end else if (s_axis_ready) begin
             axis_tkeep_d <= s_axis_tkeep;
+          end
         end
         assign m_axis_tkeep = axis_tkeep_d;
 
       end
 
+     end /* !ASYNC_CLK */
 
-  end /* zerodeep */
-  else
-  begin /* !ASYNC_CLK */
+  end else begin : fifo /* ADDRESS_WIDTH != 0 - this is a real FIFO implementation */
 
-    // Note: In this mode, the write and read interface must have a symmetric
-    // aspect ratio
-    reg [DATA_WIDTH-1:0] axis_data_d;
-    reg                  axis_valid_d;
+    wire [ADDRESS_WIDTH-1:0] s_axis_waddr;
+    wire [ADDRESS_WIDTH-1:0] m_axis_raddr;
+    wire _m_axis_ready;
+    wire _m_axis_valid;
 
-    always @(posedge s_axis_aclk) begin
-      if (!s_axis_aresetn) begin
-        axis_data_d <= {DATA_WIDTH{1'b0}};
-        axis_valid_d <= 1'b0;
-      end else if (s_axis_ready) begin
-        axis_data_d <= s_axis_data;
-        axis_valid_d <= s_axis_valid;
-      end
-    end
+    wire s_mem_write;
+    wire m_mem_read;
 
-    assign m_axis_data = axis_data_d;
-    assign m_axis_valid = axis_valid_d;
-    assign s_axis_ready = m_axis_ready | ~m_axis_valid;
-    assign m_axis_empty = 1'b0;
-    assign m_axis_almost_empty = 1'b0;
-    assign m_axis_level = 1'b0;
-    assign s_axis_full  = 1'b0;
-    assign s_axis_almost_full  = 1'b0;
-    assign s_axis_room  = 1'b0;
+    reg valid = 1'b0;
 
-    // TLAST support
-    if (TLAST_EN) begin
-      reg  axis_tlast_d;
-
-      always @(posedge s_axis_aclk) begin
-        if (!s_axis_aresetn) begin
-          axis_tlast_d <= 1'b0;
-        end else if (s_axis_ready) begin
-          axis_tlast_d <= s_axis_tlast;
-        end
-      end
-      assign m_axis_tlast = axis_tlast_d;
-    end
-
-    // TKEEP support
-    if (TKEEP_EN) begin
-      reg  axis_tkeep_d;
-
-      always @(posedge s_axis_aclk) begin
-        if (!s_axis_aresetn) begin
-          axis_tkeep_d <= 1'b0;
-        end else if (s_axis_ready) begin
-          axis_tkeep_d <= s_axis_tkeep;
-        end
-      end
-      assign m_axis_tkeep = axis_tkeep_d;
-
-    end
-
-   end /* !ASYNC_CLK */
-
-end else begin : fifo /* ADDRESS_WIDTH != 0 - this is a real FIFO implementation */
-
-  wire [ADDRESS_WIDTH-1:0] s_axis_waddr;
-  wire [ADDRESS_WIDTH-1:0] m_axis_raddr;
-  wire _m_axis_ready;
-  wire _m_axis_valid;
-
-  wire s_mem_write;
-  wire m_mem_read;
-
-  reg valid = 1'b0;
-
-  /* Control for first falls through */
-  always @(posedge m_axis_aclk) begin
-    if (m_axis_aresetn == 1'b0) begin
-      valid <= 1'b0;
-    end else begin
-      if (_m_axis_valid)
-        valid <= 1'b1;
-      else if (m_axis_ready)
+    /* Control for first falls through */
+    always @(posedge m_axis_aclk) begin
+      if (m_axis_aresetn == 1'b0) begin
         valid <= 1'b0;
-    end
-  end
-
-  if (REMOVE_NULL_BEAT_EN) begin
-    // remove NULL bytes from the stream - NOTE: TKEEP is all-LOW or all-HIGH
-    assign s_mem_write = s_axis_ready & s_axis_valid & (&s_axis_tkeep);
-  end else begin
-    assign s_mem_write = s_axis_ready & s_axis_valid;
-  end
-  assign m_mem_read = (~valid || m_axis_ready) && _m_axis_valid;
-
-  util_axis_fifo_address_generator #(
-    .ASYNC_CLK(ASYNC_CLK),
-    .ADDRESS_WIDTH(ADDRESS_WIDTH),
-    .ALMOST_EMPTY_THRESHOLD (ALMOST_EMPTY_THRESHOLD),
-    .ALMOST_FULL_THRESHOLD (ALMOST_FULL_THRESHOLD))
-  i_address_gray (
-    .m_axis_aclk(m_axis_aclk),
-    .m_axis_aresetn(m_axis_aresetn),
-    .m_axis_ready(_m_axis_ready),
-    .m_axis_valid(_m_axis_valid),
-    .m_axis_raddr(m_axis_raddr),
-    .m_axis_level(m_axis_level),
-    .m_axis_empty(m_axis_empty),
-    .m_axis_almost_empty(m_axis_almost_empty),
-    .s_axis_aclk(s_axis_aclk),
-    .s_axis_aresetn(s_axis_aresetn),
-    .s_axis_ready(s_axis_ready),
-    .s_axis_valid(s_axis_valid),
-    .s_axis_full(s_axis_full),
-    .s_axis_almost_full(s_axis_almost_full),
-    .s_axis_waddr(s_axis_waddr),
-    .s_axis_room(s_axis_room)
-  );
-
-  // TLAST and TKEEP support
-  if (TLAST_EN & TKEEP_EN) begin
-    assign s_axis_data_int_s = {s_axis_tkeep, s_axis_tlast, s_axis_data};
-    assign m_axis_tkeep = m_axis_data_int_s[MEM_WORD-1-:DATA_WIDTH/8];
-    assign m_axis_tlast = m_axis_data_int_s[DATA_WIDTH];
-    assign m_axis_data = m_axis_data_int_s[DATA_WIDTH-1:0];
-  end else if (TKEEP_EN) begin
-    assign s_axis_data_int_s = {s_axis_tkeep, s_axis_data};
-    assign m_axis_tkeep = m_axis_data_int_s[MEM_WORD-1-:DATA_WIDTH/8];
-    assign m_axis_data = m_axis_data_int_s[DATA_WIDTH-1:0];
-  end else if (TLAST_EN) begin
-    assign s_axis_data_int_s = {s_axis_tlast, s_axis_data};
-    assign m_axis_tlast = m_axis_data_int_s[DATA_WIDTH];
-    assign m_axis_data = m_axis_data_int_s[DATA_WIDTH-1:0];
-  end else begin
-    assign s_axis_data_int_s = {s_axis_data};
-    assign m_axis_data = m_axis_data_int_s[DATA_WIDTH-1:0];
-  end
-
-  if (ASYNC_CLK == 1) begin : async_clocks /* Asynchronous WRITE/READ clocks */
-
-    // The assumption is that in this mode the M_AXIS_REGISTERED is 1
-    // When the clocks are asynchronous instantiate a block RAM
-    // regardless of the requested size to make sure we threat the
-    // clock crossing correctly
-    ad_mem #(
-      .DATA_WIDTH (MEM_WORD),
-      .ADDRESS_WIDTH (ADDRESS_WIDTH))
-    i_mem (
-      .clka(s_axis_aclk),
-      .wea(s_mem_write),
-      .addra(s_axis_waddr),
-      .dina(s_axis_data_int_s),
-      .clkb(m_axis_aclk),
-      .reb(m_mem_read),
-      .addrb(m_axis_raddr),
-      .doutb(m_axis_data_int_s)
-    );
-
-    assign _m_axis_ready = ~valid || m_axis_ready;
-    assign m_axis_valid = valid;
-
-  end else begin : sync_clocks /* Synchronous WRITE/READ clocks */
-
-    reg [MEM_WORD-1:0] ram[0:2**ADDRESS_WIDTH-1];
-
-    // When the clocks are synchronous use behavioral modeling for the SDP RAM
-    // Let the synthesizer decide what to infer (distributed or block RAM)
-    always @(posedge s_axis_aclk) begin
-      if (s_mem_write)
-        ram[s_axis_waddr] <= s_axis_data_int_s;
-    end
-
-    if (M_AXIS_REGISTERED == 1) begin
-
-      reg [MEM_WORD-1:0] data;
-
-      always @(posedge m_axis_aclk) begin
-        if (m_mem_read)
-          data <= ram[m_axis_raddr];
+      end else begin
+        if (_m_axis_valid)
+          valid <= 1'b1;
+        else if (m_axis_ready)
+          valid <= 1'b0;
       end
+    end
+
+    if (REMOVE_NULL_BEAT_EN) begin
+      // remove NULL bytes from the stream - NOTE: TKEEP is all-LOW or all-HIGH
+      assign s_mem_write = s_axis_ready & s_axis_valid & (&s_axis_tkeep);
+    end else begin
+      assign s_mem_write = s_axis_ready & s_axis_valid;
+    end
+    assign m_mem_read = (~valid || m_axis_ready) && _m_axis_valid;
+
+    util_axis_fifo_address_generator #(
+      .ASYNC_CLK(ASYNC_CLK),
+      .ADDRESS_WIDTH(ADDRESS_WIDTH),
+      .ALMOST_EMPTY_THRESHOLD (ALMOST_EMPTY_THRESHOLD),
+      .ALMOST_FULL_THRESHOLD (ALMOST_FULL_THRESHOLD)
+    ) i_address_gray (
+      .m_axis_aclk(m_axis_aclk),
+      .m_axis_aresetn(m_axis_aresetn),
+      .m_axis_ready(_m_axis_ready),
+      .m_axis_valid(_m_axis_valid),
+      .m_axis_raddr(m_axis_raddr),
+      .m_axis_level(m_axis_level),
+      .m_axis_empty(m_axis_empty),
+      .m_axis_almost_empty(m_axis_almost_empty),
+      .s_axis_aclk(s_axis_aclk),
+      .s_axis_aresetn(s_axis_aresetn),
+      .s_axis_ready(s_axis_ready),
+      .s_axis_valid(s_axis_valid),
+      .s_axis_full(s_axis_full),
+      .s_axis_almost_full(s_axis_almost_full),
+      .s_axis_waddr(s_axis_waddr),
+      .s_axis_room(s_axis_room));
+
+    // TLAST and TKEEP support
+    if (TLAST_EN & TKEEP_EN) begin
+      assign s_axis_data_int_s = {s_axis_tkeep, s_axis_tlast, s_axis_data};
+      assign m_axis_tkeep = m_axis_data_int_s[MEM_WORD-1-:DATA_WIDTH/8];
+      assign m_axis_tlast = m_axis_data_int_s[DATA_WIDTH];
+      assign m_axis_data = m_axis_data_int_s[DATA_WIDTH-1:0];
+    end else if (TKEEP_EN) begin
+      assign s_axis_data_int_s = {s_axis_tkeep, s_axis_data};
+      assign m_axis_tkeep = m_axis_data_int_s[MEM_WORD-1-:DATA_WIDTH/8];
+      assign m_axis_data = m_axis_data_int_s[DATA_WIDTH-1:0];
+    end else if (TLAST_EN) begin
+      assign s_axis_data_int_s = {s_axis_tlast, s_axis_data};
+      assign m_axis_tlast = m_axis_data_int_s[DATA_WIDTH];
+      assign m_axis_data = m_axis_data_int_s[DATA_WIDTH-1:0];
+    end else begin
+      assign s_axis_data_int_s = {s_axis_data};
+      assign m_axis_data = m_axis_data_int_s[DATA_WIDTH-1:0];
+    end
+
+    if (ASYNC_CLK == 1) begin : async_clocks /* Asynchronous WRITE/READ clocks */
+
+      // The assumption is that in this mode the M_AXIS_REGISTERED is 1
+      // When the clocks are asynchronous instantiate a block RAM
+      // regardless of the requested size to make sure we threat the
+      // clock crossing correctly
+      ad_mem #(
+        .DATA_WIDTH (MEM_WORD),
+        .ADDRESS_WIDTH (ADDRESS_WIDTH)
+      ) i_mem (
+        .clka(s_axis_aclk),
+        .wea(s_mem_write),
+        .addra(s_axis_waddr),
+        .dina(s_axis_data_int_s),
+        .clkb(m_axis_aclk),
+        .reb(m_mem_read),
+        .addrb(m_axis_raddr),
+        .doutb(m_axis_data_int_s));
 
       assign _m_axis_ready = ~valid || m_axis_ready;
-      assign m_axis_data_int_s = data;
       assign m_axis_valid = valid;
 
-    end else begin
+    end else begin : sync_clocks /* Synchronous WRITE/READ clocks */
 
-      assign _m_axis_ready = m_axis_ready;
-      assign m_axis_valid = _m_axis_valid;
-      assign m_axis_data_int_s = ram[m_axis_raddr];
+      reg [MEM_WORD-1:0] ram[0:2**ADDRESS_WIDTH-1];
 
+      // When the clocks are synchronous use behavioral modeling for the SDP RAM
+      // Let the synthesizer decide what to infer (distributed or block RAM)
+      always @(posedge s_axis_aclk) begin
+        if (s_mem_write)
+          ram[s_axis_waddr] <= s_axis_data_int_s;
+      end
+
+      if (M_AXIS_REGISTERED == 1) begin
+
+        reg [MEM_WORD-1:0] data;
+
+        always @(posedge m_axis_aclk) begin
+          if (m_mem_read)
+            data <= ram[m_axis_raddr];
+        end
+
+        assign _m_axis_ready = ~valid || m_axis_ready;
+        assign m_axis_data_int_s = data;
+        assign m_axis_valid = valid;
+
+      end else begin
+
+        assign _m_axis_ready = m_axis_ready;
+        assign m_axis_valid = _m_axis_valid;
+        assign m_axis_data_int_s = ram[m_axis_raddr];
+
+      end
     end
-  end
-end /* fifo */
-endgenerate
+  end /* fifo */
+  endgenerate
 
 endmodule
diff --git a/library/util_axis_fifo/util_axis_fifo_address_generator.v b/library/util_axis_fifo/util_axis_fifo_address_generator.v
index 59fd03b8a..10c56d747 100644
--- a/library/util_axis_fifo/util_axis_fifo_address_generator.v
+++ b/library/util_axis_fifo/util_axis_fifo_address_generator.v
@@ -32,6 +32,7 @@
 //
 // ***************************************************************************
 // ***************************************************************************
+
 `timescale 1ns/1ps
 
 module util_axis_fifo_address_generator #(
@@ -40,6 +41,7 @@ module util_axis_fifo_address_generator #(
   parameter [ADDRESS_WIDTH-1:0] ALMOST_EMPTY_THRESHOLD = 16,
   parameter [ADDRESS_WIDTH-1:0] ALMOST_FULL_THRESHOLD = 16
 ) (
+
   // Read interface - Sink side
 
   input m_axis_aclk,
@@ -63,130 +65,108 @@ module util_axis_fifo_address_generator #(
   output [ADDRESS_WIDTH-1:0] s_axis_room
 );
 
-//------------------------------------------------------------------------------
-// local parameters
-//------------------------------------------------------------------------------
+  localparam FIFO_DEPTH = {ADDRESS_WIDTH{1'b1}};
 
-localparam FIFO_DEPTH = {ADDRESS_WIDTH{1'b1}};
+  // Definition of address counters
+  // All the counters are wider with one bit to indicate wraparounds
+  reg [ADDRESS_WIDTH:0] s_axis_waddr_reg = 'h0;
+  reg [ADDRESS_WIDTH:0] m_axis_raddr_reg = 'h0;
 
-//------------------------------------------------------------------------------
-// registers
-//------------------------------------------------------------------------------
+  wire [ADDRESS_WIDTH:0] s_axis_raddr_reg;
+  wire [ADDRESS_WIDTH:0] m_axis_waddr_reg;
 
-// Definition of address counters
-// All the counters are wider with one bit to indicate wraparounds
-reg [ADDRESS_WIDTH:0] s_axis_waddr_reg = 'h0;
-reg [ADDRESS_WIDTH:0] m_axis_raddr_reg = 'h0;
+  wire s_axis_write_s;
+  wire s_axis_ready_s;
 
-//------------------------------------------------------------------------------
-// wires
-//------------------------------------------------------------------------------
+  wire m_axis_read_s;
+  wire m_axis_valid_s;
+  wire [ADDRESS_WIDTH-1:0] m_axis_level_s;
 
-wire [ADDRESS_WIDTH:0] s_axis_raddr_reg;
-wire [ADDRESS_WIDTH:0] m_axis_waddr_reg;
+  // Write address counter
 
-wire s_axis_write_s;
-wire s_axis_ready_s;
+  assign s_axis_write_s = s_axis_ready && s_axis_valid && ~s_axis_full;
+  always @(posedge s_axis_aclk)
+  begin
+    if (!s_axis_aresetn)
+      s_axis_waddr_reg <= 'h0;
+    else
+      if (s_axis_write_s)
+        s_axis_waddr_reg <= s_axis_waddr_reg + 1'b1;
+  end
 
-wire m_axis_read_s;
-wire m_axis_valid_s;
-wire [ADDRESS_WIDTH-1:0] m_axis_level_s;
+  // Read address counter
 
-//------------------------------------------------------------------------------
-// Write address counter
-//------------------------------------------------------------------------------
+  assign m_axis_read_s = m_axis_ready && m_axis_valid && ~m_axis_empty;
+  always @(posedge m_axis_aclk)
+  begin
+    if (!m_axis_aresetn)
+      m_axis_raddr_reg <= 'h0;
+    else
+      if (m_axis_read_s)
+        m_axis_raddr_reg <= m_axis_raddr_reg + 1'b1;
+  end
 
-assign s_axis_write_s = s_axis_ready && s_axis_valid && ~s_axis_full;
-always @(posedge s_axis_aclk)
-begin
-  if (!s_axis_aresetn)
-    s_axis_waddr_reg <= 'h0;
-  else
-    if (s_axis_write_s)
-      s_axis_waddr_reg <= s_axis_waddr_reg + 1'b1;
-end
+  // Output assignments
 
-//------------------------------------------------------------------------------
-// Read address counter
-//------------------------------------------------------------------------------
+  assign s_axis_waddr = s_axis_waddr_reg[ADDRESS_WIDTH-1:0];
+  assign m_axis_raddr = m_axis_raddr_reg[ADDRESS_WIDTH-1:0];
 
-assign m_axis_read_s = m_axis_ready && m_axis_valid && ~m_axis_empty;
-always @(posedge m_axis_aclk)
-begin
-  if (!m_axis_aresetn)
-    m_axis_raddr_reg <= 'h0;
-  else
-    if (m_axis_read_s)
-      m_axis_raddr_reg <= m_axis_raddr_reg + 1'b1;
-end
+  // CDC circuits for double clock configuration
 
-//------------------------------------------------------------------------------
-// Output assignments
-//------------------------------------------------------------------------------
+  generate if (ASYNC_CLK == 1) begin : g_async_clock
+    // CDC transfer of the write pointer to the read clock domain
+    sync_gray #(
+      .DATA_WIDTH(ADDRESS_WIDTH + 1)
+    ) i_waddr_sync_gray (
+      .in_clk(s_axis_aclk),
+      .in_resetn(s_axis_aresetn),
+      .out_clk(m_axis_aclk),
+      .out_resetn(m_axis_aresetn),
+      .in_count(s_axis_waddr_reg),
+      .out_count(m_axis_waddr_reg));
 
-assign s_axis_waddr = s_axis_waddr_reg[ADDRESS_WIDTH-1:0];
-assign m_axis_raddr = m_axis_raddr_reg[ADDRESS_WIDTH-1:0];
+    // CDC transfer of the read pointer to the write clock domain
+    sync_gray #(
+      .DATA_WIDTH(ADDRESS_WIDTH + 1)
+    ) i_raddr_sync_gray (
+      .in_clk(m_axis_aclk),
+      .in_resetn(m_axis_aresetn),
+      .out_clk(s_axis_aclk),
+      .out_resetn(s_axis_aresetn),
+      .in_count(m_axis_raddr_reg),
+      .out_count(s_axis_raddr_reg));
+  end else begin
+    assign m_axis_waddr_reg = s_axis_waddr_reg;
+    assign s_axis_raddr_reg = m_axis_raddr_reg;
+  end
+  endgenerate
 
-//------------------------------------------------------------------------------
-// CDC circuits for double clock configuration
-//------------------------------------------------------------------------------
+  //------------------------------------------------------------------------------
+  // FIFO write logic - upstream
+  //
+  // s_axis_full  - FIFO is full if next write pointer equal to read pointer
+  // s_axis_ready - FIFO is always ready, unless it's full
+  //
+  //------------------------------------------------------------------------------
 
-generate if (ASYNC_CLK == 1) begin : g_async_clock
-  // CDC transfer of the write pointer to the read clock domain
-  sync_gray #(
-    .DATA_WIDTH(ADDRESS_WIDTH + 1)
-  ) i_waddr_sync_gray (
-    .in_clk(s_axis_aclk),
-    .in_resetn(s_axis_aresetn),
-    .out_clk(m_axis_aclk),
-    .out_resetn(m_axis_aresetn),
-    .in_count(s_axis_waddr_reg),
-    .out_count(m_axis_waddr_reg)
-  );
+  wire [ADDRESS_WIDTH:0] s_axis_fifo_fill = s_axis_waddr_reg - s_axis_raddr_reg;
+  assign s_axis_full = (s_axis_fifo_fill == {ADDRESS_WIDTH{1'b1}});
+  assign s_axis_almost_full = s_axis_fifo_fill > {1'b0, ~ALMOST_FULL_THRESHOLD};
+  assign s_axis_ready = ~s_axis_full;
+  assign s_axis_room = ~s_axis_fifo_fill;
 
-  // CDC transfer of the read pointer to the write clock domain
-  sync_gray #(
-    .DATA_WIDTH(ADDRESS_WIDTH + 1)
-  ) i_raddr_sync_gray (
-    .in_clk(m_axis_aclk),
-    .in_resetn(m_axis_aresetn),
-    .out_clk(s_axis_aclk),
-    .out_resetn(s_axis_aresetn),
-    .in_count(m_axis_raddr_reg),
-    .out_count(s_axis_raddr_reg)
-  );
-end else begin
-  assign m_axis_waddr_reg = s_axis_waddr_reg;
-  assign s_axis_raddr_reg = m_axis_raddr_reg;
-end
-endgenerate
+  //------------------------------------------------------------------------------
+  // FIFO read logic - downstream
+  //
+  // m_axis_empty - FIFO is empty if read pointer equal to write pointer
+  // m_axis_valid - FIFO has a valid output data, if it's not empty
+  //
+  //------------------------------------------------------------------------------
 
-//------------------------------------------------------------------------------
-// FIFO write logic - upstream
-//
-// s_axis_full  - FIFO is full if next write pointer equal to read pointer
-// s_axis_ready - FIFO is always ready, unless it's full
-//
-//------------------------------------------------------------------------------
-
-wire [ADDRESS_WIDTH:0] s_axis_fifo_fill = s_axis_waddr_reg - s_axis_raddr_reg;
-assign s_axis_full = (s_axis_fifo_fill == {ADDRESS_WIDTH{1'b1}});
-assign s_axis_almost_full = s_axis_fifo_fill > {1'b0, ~ALMOST_FULL_THRESHOLD};
-assign s_axis_ready = ~s_axis_full;
-assign s_axis_room = ~s_axis_fifo_fill;
-
-//------------------------------------------------------------------------------
-// FIFO read logic - downstream
-//
-// m_axis_empty - FIFO is empty if read pointer equal to write pointer
-// m_axis_valid - FIFO has a valid output data, if it's not empty
-//
-//------------------------------------------------------------------------------
-
-wire [ADDRESS_WIDTH:0] m_axis_fifo_fill = m_axis_waddr_reg - m_axis_raddr_reg;
-assign m_axis_empty = m_axis_fifo_fill == 0;
-assign m_axis_almost_empty = (m_axis_fifo_fill < ALMOST_EMPTY_THRESHOLD);
-assign m_axis_valid = ~m_axis_empty;
-assign m_axis_level = m_axis_fifo_fill;
+  wire [ADDRESS_WIDTH:0] m_axis_fifo_fill = m_axis_waddr_reg - m_axis_raddr_reg;
+  assign m_axis_empty = m_axis_fifo_fill == 0;
+  assign m_axis_almost_empty = (m_axis_fifo_fill < ALMOST_EMPTY_THRESHOLD);
+  assign m_axis_valid = ~m_axis_empty;
+  assign m_axis_level = m_axis_fifo_fill;
 
 endmodule
diff --git a/library/util_axis_fifo_asym/util_axis_fifo_asym.v b/library/util_axis_fifo_asym/util_axis_fifo_asym.v
index ddaf1c81e..bb80469cd 100644
--- a/library/util_axis_fifo_asym/util_axis_fifo_asym.v
+++ b/library/util_axis_fifo_asym/util_axis_fifo_asym.v
@@ -68,242 +68,240 @@ module util_axis_fifo_asym #(
   output [S_ADDRESS_WIDTH-1:0] s_axis_room
 );
 
-// define which interface has a wider bus
-localparam RATIO_TYPE = (S_DATA_WIDTH >= M_DATA_WIDTH) ? 1 : 0;
+  // define which interface has a wider bus
+  localparam RATIO_TYPE = (S_DATA_WIDTH >= M_DATA_WIDTH) ? 1 : 0;
 
-// bus width ratio
-localparam RATIO = (RATIO_TYPE) ? S_DATA_WIDTH/M_DATA_WIDTH : M_DATA_WIDTH/S_DATA_WIDTH;
+  // bus width ratio
+  localparam RATIO = (RATIO_TYPE) ? S_DATA_WIDTH/M_DATA_WIDTH : M_DATA_WIDTH/S_DATA_WIDTH;
 
-// atomic parameters - NOTE: depth is always defined by the slave attributes
-localparam A_WIDTH = (RATIO_TYPE) ? M_DATA_WIDTH : S_DATA_WIDTH;
-localparam A_ADDRESS = (RATIO_TYPE) ? S_ADDRESS_WIDTH : (S_ADDRESS_WIDTH-$clog2(RATIO));
-localparam A_ALMOST_FULL_THRESHOLD = (RATIO_TYPE) ? ALMOST_FULL_THRESHOLD : (ALMOST_FULL_THRESHOLD/RATIO);
-localparam A_ALMOST_EMPTY_THRESHOLD = (RATIO_TYPE) ? (ALMOST_EMPTY_THRESHOLD/RATIO) : ALMOST_EMPTY_THRESHOLD;
+  // atomic parameters - NOTE: depth is always defined by the slave attributes
+  localparam A_WIDTH = (RATIO_TYPE) ? M_DATA_WIDTH : S_DATA_WIDTH;
+  localparam A_ADDRESS = (RATIO_TYPE) ? S_ADDRESS_WIDTH : (S_ADDRESS_WIDTH-$clog2(RATIO));
+  localparam A_ALMOST_FULL_THRESHOLD = (RATIO_TYPE) ? ALMOST_FULL_THRESHOLD : (ALMOST_FULL_THRESHOLD/RATIO);
+  localparam A_ALMOST_EMPTY_THRESHOLD = (RATIO_TYPE) ? (ALMOST_EMPTY_THRESHOLD/RATIO) : ALMOST_EMPTY_THRESHOLD;
 
-// slave and master sequencers
-reg [$clog2(RATIO)-1:0] s_axis_counter;
-reg [$clog2(RATIO)-1:0] m_axis_counter;
+  // slave and master sequencers
+  reg [$clog2(RATIO)-1:0] s_axis_counter;
+  reg [$clog2(RATIO)-1:0] m_axis_counter;
 
-wire [RATIO-1:0] m_axis_ready_int_s;
-wire [RATIO-1:0] m_axis_valid_int_s;
-wire [RATIO*A_WIDTH-1:0] m_axis_data_int_s;
-wire [RATIO*A_WIDTH/8-1:0] m_axis_tkeep_int_s;
-wire [RATIO-1:0] m_axis_tlast_int_s;
-wire [RATIO-1:0] m_axis_empty_int_s;
-wire [RATIO-1:0] m_axis_almost_empty_int_s;
-wire [RATIO*A_ADDRESS-1:0] m_axis_level_int_s;
-
-wire [RATIO-1:0] s_axis_ready_int_s;
-wire [RATIO-1:0] s_axis_valid_int_s;
-wire [RATIO*A_WIDTH-1:0] s_axis_data_int_s;
-wire [RATIO*A_WIDTH/8-1:0] s_axis_tkeep_int_s;
-wire [RATIO-1:0] s_axis_tlast_int_s;
-wire [RATIO-1:0] s_axis_full_int_s;
-wire [RATIO-1:0] s_axis_almost_full_int_s;
-wire [RATIO*A_ADDRESS-1:0] s_axis_room_int_s;
-
-// instantiate the FIFOs
-genvar i;
-generate
-  for (i=0; i<RATIO; i=i+1) begin
-    util_axis_fifo #(
-      .DATA_WIDTH (A_WIDTH),
-      .ADDRESS_WIDTH (A_ADDRESS),
-      .ASYNC_CLK (ASYNC_CLK),
-      .M_AXIS_REGISTERED (M_AXIS_REGISTERED),
-      .ALMOST_EMPTY_THRESHOLD (A_ALMOST_EMPTY_THRESHOLD),
-      .ALMOST_FULL_THRESHOLD (A_ALMOST_FULL_THRESHOLD),
-      .TKEEP_EN (TKEEP_EN),
-      .TLAST_EN (TLAST_EN))
-    i_fifo (
-      .m_axis_aclk    (m_axis_aclk),
-      .m_axis_aresetn (m_axis_aresetn),
-      .m_axis_ready   (m_axis_ready_int_s[i]),
-      .m_axis_valid   (m_axis_valid_int_s[i]),
-      .m_axis_data    (m_axis_data_int_s[A_WIDTH*i+:A_WIDTH]),
-      .m_axis_tlast   (m_axis_tlast_int_s[i]),
-      .m_axis_tkeep   (m_axis_tkeep_int_s[A_WIDTH/8*i+:A_WIDTH/8]),
-      .m_axis_level   (m_axis_level_int_s[A_ADDRESS*i+:A_ADDRESS]),
-      .m_axis_empty   (m_axis_empty_int_s[i]),
-      .m_axis_almost_empty (m_axis_almost_empty_int_s[i]),
-      .s_axis_aclk    (s_axis_aclk),
-      .s_axis_aresetn (s_axis_aresetn),
-      .s_axis_ready   (s_axis_ready_int_s[i]),
-      .s_axis_valid   (s_axis_valid_int_s[i]),
-      .s_axis_data    (s_axis_data_int_s[A_WIDTH*i+:A_WIDTH]),
-      .s_axis_tkeep   (s_axis_tkeep_int_s[A_WIDTH/8*i+:A_WIDTH/8]),
-      .s_axis_tlast   (s_axis_tlast_int_s[i]),
-      .s_axis_room    (s_axis_room_int_s[A_ADDRESS*i+:A_ADDRESS]),
-      .s_axis_full    (s_axis_full_int_s[i]),
-      .s_axis_almost_full (s_axis_almost_full_int_s[i])
-    );
-  end
-endgenerate
-
-// write or slave logic
-generate
-
-  if (RATIO_TYPE) begin : big_slave
+  wire [RATIO-1:0] m_axis_ready_int_s;
+  wire [RATIO-1:0] m_axis_valid_int_s;
+  wire [RATIO*A_WIDTH-1:0] m_axis_data_int_s;
+  wire [RATIO*A_WIDTH/8-1:0] m_axis_tkeep_int_s;
+  wire [RATIO-1:0] m_axis_tlast_int_s;
+  wire [RATIO-1:0] m_axis_empty_int_s;
+  wire [RATIO-1:0] m_axis_almost_empty_int_s;
+  wire [RATIO*A_ADDRESS-1:0] m_axis_level_int_s;
 
+  wire [RATIO-1:0] s_axis_ready_int_s;
+  wire [RATIO-1:0] s_axis_valid_int_s;
+  wire [RATIO*A_WIDTH-1:0] s_axis_data_int_s;
+  wire [RATIO*A_WIDTH/8-1:0] s_axis_tkeep_int_s;
+  wire [RATIO-1:0] s_axis_tlast_int_s;
+  wire [RATIO-1:0] s_axis_full_int_s;
+  wire [RATIO-1:0] s_axis_almost_full_int_s;
+  wire [RATIO*A_ADDRESS-1:0] s_axis_room_int_s;
 
+  // instantiate the FIFOs
+  genvar i;
+  generate
     for (i=0; i<RATIO; i=i+1) begin
-      assign s_axis_valid_int_s[i] = s_axis_valid & s_axis_ready;
-      assign s_axis_tlast_int_s[i] = s_axis_tlast;
+      util_axis_fifo #(
+        .DATA_WIDTH (A_WIDTH),
+        .ADDRESS_WIDTH (A_ADDRESS),
+        .ASYNC_CLK (ASYNC_CLK),
+        .M_AXIS_REGISTERED (M_AXIS_REGISTERED),
+        .ALMOST_EMPTY_THRESHOLD (A_ALMOST_EMPTY_THRESHOLD),
+        .ALMOST_FULL_THRESHOLD (A_ALMOST_FULL_THRESHOLD),
+        .TKEEP_EN (TKEEP_EN),
+        .TLAST_EN (TLAST_EN)
+      ) i_fifo (
+        .m_axis_aclk    (m_axis_aclk),
+        .m_axis_aresetn (m_axis_aresetn),
+        .m_axis_ready   (m_axis_ready_int_s[i]),
+        .m_axis_valid   (m_axis_valid_int_s[i]),
+        .m_axis_data    (m_axis_data_int_s[A_WIDTH*i+:A_WIDTH]),
+        .m_axis_tlast   (m_axis_tlast_int_s[i]),
+        .m_axis_tkeep   (m_axis_tkeep_int_s[A_WIDTH/8*i+:A_WIDTH/8]),
+        .m_axis_level   (m_axis_level_int_s[A_ADDRESS*i+:A_ADDRESS]),
+        .m_axis_empty   (m_axis_empty_int_s[i]),
+        .m_axis_almost_empty (m_axis_almost_empty_int_s[i]),
+        .s_axis_aclk    (s_axis_aclk),
+        .s_axis_aresetn (s_axis_aresetn),
+        .s_axis_ready   (s_axis_ready_int_s[i]),
+        .s_axis_valid   (s_axis_valid_int_s[i]),
+        .s_axis_data    (s_axis_data_int_s[A_WIDTH*i+:A_WIDTH]),
+        .s_axis_tkeep   (s_axis_tkeep_int_s[A_WIDTH/8*i+:A_WIDTH/8]),
+        .s_axis_tlast   (s_axis_tlast_int_s[i]),
+        .s_axis_room    (s_axis_room_int_s[A_ADDRESS*i+:A_ADDRESS]),
+        .s_axis_full    (s_axis_full_int_s[i]),
+        .s_axis_almost_full (s_axis_almost_full_int_s[i]));
+    end
+  endgenerate
+
+  // write or slave logic
+  generate
+
+    if (RATIO_TYPE) begin : big_slave
+
+      for (i=0; i<RATIO; i=i+1) begin
+        assign s_axis_valid_int_s[i] = s_axis_valid & s_axis_ready;
+        assign s_axis_tlast_int_s[i] = s_axis_tlast;
+      end
+
+      assign s_axis_tkeep_int_s = s_axis_tkeep;
+      assign s_axis_data_int_s = s_axis_data;
+      // if every instance is ready, the interface is ready
+      assign s_axis_ready = &(s_axis_ready_int_s);
+      // if one of the atomic instance is full, s_axis_full is asserted
+      assign s_axis_full = |s_axis_full_int_s;
+      assign s_axis_almost_full = |s_axis_almost_full_int_s;
+      // the FIFO has the same room as the atomic FIFO
+      assign s_axis_room = s_axis_room_int_s[A_ADDRESS-1:0];
+
+    end else begin : small_slave
+
+      reg [RATIO-1:0] s_axis_valid_int_d = {RATIO{1'b0}};
+
+      for (i=0; i<RATIO; i=i+1) begin
+        assign s_axis_data_int_s[A_WIDTH*i+:A_WIDTH] = s_axis_data;
+        assign s_axis_tkeep_int_s[A_WIDTH/8*i+:A_WIDTH/8] = (s_axis_counter == i) ? s_axis_tkeep : {A_WIDTH/8{1'b0}};
+        assign s_axis_tlast_int_s[i] = (s_axis_counter == i) ? s_axis_tlast : 1'b0;
+      end
+
+      // insert invalid writes (TKEEP==0) in case if the TLAST arrives before the RATIO
+      // boundary
+      always @(*) begin
+        case ({s_axis_valid, s_axis_tlast})
+          2'b00 : s_axis_valid_int_d = {RATIO{1'b0}};
+          2'b01 : s_axis_valid_int_d = {RATIO{1'b0}};
+          2'b10 : s_axis_valid_int_d = {{RATIO-1{1'b0}}, 1'b1} << s_axis_counter;
+          2'b11 : s_axis_valid_int_d = {RATIO{1'b1}} << s_axis_counter;
+        endcase
+      end
+      assign s_axis_valid_int_s = s_axis_valid_int_d;
+
+      // READY/FULL/ALMOST_FULL is driven by the current atomic instance
+      assign s_axis_ready = s_axis_ready_int_s >> s_axis_counter;
+      assign s_axis_almost_full = s_axis_almost_full_int_s >> s_axis_counter;
+
+      // the FIFO has the same room as the last atomic instance
+      // (NOTE: this is not the real room value, rather the value will be updated
+      // after every RATIO number of writes)
+      assign s_axis_full = s_axis_full_int_s[RATIO-1];
+      assign s_axis_room = {s_axis_room_int_s[A_ADDRESS*(RATIO-1)+:A_ADDRESS], {$clog2(RATIO){1'b1}}};
+
     end
 
-    assign s_axis_tkeep_int_s = s_axis_tkeep;
-    assign s_axis_data_int_s = s_axis_data;
-    // if every instance is ready, the interface is ready
-    assign s_axis_ready = &(s_axis_ready_int_s);
-    // if one of the atomic instance is full, s_axis_full is asserted
-    assign s_axis_full = |s_axis_full_int_s;
-    assign s_axis_almost_full = |s_axis_almost_full_int_s;
-    // the FIFO has the same room as the atomic FIFO
-    assign s_axis_room = s_axis_room_int_s[A_ADDRESS-1:0];
+  endgenerate
 
-  end else begin : small_slave
+  // read or slave logic
+  generate
+    if (RATIO_TYPE) begin : small_master
 
-    reg [RATIO-1:0] s_axis_valid_int_d = {RATIO{1'b0}};
+      for (i=0; i<RATIO; i=i+1) begin
+        assign m_axis_ready_int_s[i] = (m_axis_counter == i) ? m_axis_ready : 1'b0;
+      end
+
+      assign m_axis_data = m_axis_data_int_s >> (m_axis_counter*A_WIDTH) ;
+      assign m_axis_tkeep = m_axis_tkeep_int_s >> (m_axis_counter*A_WIDTH/8) ;
+
+      // VALID/EMPTY/ALMOST_EMPTY is driven by the current atomic instance
+      assign m_axis_valid = m_axis_valid_int_s >> m_axis_counter;
+
+      // the FIFO has the same level as the last atomic instance
+      // (NOTE: this is not the real level value, rather the value will be updated
+      // after every RATIO number of reads)
+      assign m_axis_level = {m_axis_level_int_s[A_ADDRESS-1:0], {$clog2(RATIO){1'b0}}};
+      assign m_axis_almost_empty = m_axis_almost_empty_int_s[RATIO-1];
+      assign m_axis_empty = m_axis_empty_int_s[RATIO-1];
+
+    end else begin : big_master
+
+      for (i=0; i<RATIO; i=i+1) begin
+        assign m_axis_ready_int_s[i] = m_axis_ready;
+      end
+
+      for (i=0; i<RATIO; i=i+1) begin
+        assign m_axis_tkeep[i*A_WIDTH/8+:A_WIDTH/8] = (m_axis_tlast_int_s[i:0] == 0) ||
+                                                      (m_axis_tlast_int_s[i]) ?
+                                                    m_axis_tkeep_int_s[i*A_WIDTH/8+:A_WIDTH/8] :
+                                                    {(A_WIDTH/8){1'b0}};
+      end
+
+      assign m_axis_data = m_axis_data_int_s;
+      // if every instance has a valid data, the interface has valid data,
+      // otherwise valid is asserted only if TLAST is asserted
+      assign m_axis_valid = (|m_axis_tlast_int_s) ? |m_axis_valid_int_s : &m_axis_valid_int_s;
+      // if one of the atomic instance is empty, m_axis_empty should be asserted
+      assign m_axis_empty = |m_axis_empty_int_s;
+      assign m_axis_almost_empty = |m_axis_almost_empty_int_s;
+
+      // the FIFO has the same room as the atomic FIFO
+      assign m_axis_level = m_axis_level_int_s[A_ADDRESS-1:0];
 
-    for (i=0; i<RATIO; i=i+1) begin
-      assign s_axis_data_int_s[A_WIDTH*i+:A_WIDTH] = s_axis_data;
-      assign s_axis_tkeep_int_s[A_WIDTH/8*i+:A_WIDTH/8] = (s_axis_counter == i) ? s_axis_tkeep : {A_WIDTH/8{1'b0}};
-      assign s_axis_tlast_int_s[i] = (s_axis_counter == i) ? s_axis_tlast : 1'b0;
     end
 
-    // insert invalid writes (TKEEP==0) in case if the TLAST arrives before the RATIO
-    // boundary
-    always @(*) begin
-      case ({s_axis_valid, s_axis_tlast})
-        2'b00 : s_axis_valid_int_d = {RATIO{1'b0}};
-        2'b01 : s_axis_valid_int_d = {RATIO{1'b0}};
-        2'b10 : s_axis_valid_int_d = {{RATIO-1{1'b0}}, 1'b1} << s_axis_counter;
-        2'b11 : s_axis_valid_int_d = {RATIO{1'b1}} << s_axis_counter;
-      endcase
-    end
-    assign s_axis_valid_int_s = s_axis_valid_int_d;
+    assign m_axis_tlast = (m_axis_valid) ? |m_axis_tlast_int_s : 1'b0;
 
-    // READY/FULL/ALMOST_FULL is driven by the current atomic instance
-    assign s_axis_ready = s_axis_ready_int_s >> s_axis_counter;
-    assign s_axis_almost_full = s_axis_almost_full_int_s >> s_axis_counter;
+  endgenerate
 
-    // the FIFO has the same room as the last atomic instance
-    // (NOTE: this is not the real room value, rather the value will be updated
-    // after every RATIO number of writes)
-    assign s_axis_full = s_axis_full_int_s[RATIO-1];
-    assign s_axis_room = {s_axis_room_int_s[A_ADDRESS*(RATIO-1)+:A_ADDRESS], {$clog2(RATIO){1'b1}}};
+  // slave handshake counter
 
+  reg s_axis_tlast_d = 0;
+  always @(posedge s_axis_aclk) begin
+    s_axis_tlast_d <= s_axis_tlast;
   end
 
-endgenerate
-
-// read or slave logic
-generate
-  if (RATIO_TYPE) begin : small_master
-
-    for (i=0; i<RATIO; i=i+1) begin
-      assign m_axis_ready_int_s[i] = (m_axis_counter == i) ? m_axis_ready : 1'b0;
-    end
-
-    assign m_axis_data = m_axis_data_int_s >> (m_axis_counter*A_WIDTH) ;
-    assign m_axis_tkeep = m_axis_tkeep_int_s >> (m_axis_counter*A_WIDTH/8) ;
-
-    // VALID/EMPTY/ALMOST_EMPTY is driven by the current atomic instance
-    assign m_axis_valid = m_axis_valid_int_s >> m_axis_counter;
-
-    // the FIFO has the same level as the last atomic instance
-    // (NOTE: this is not the real level value, rather the value will be updated
-    // after every RATIO number of reads)
-    assign m_axis_level = {m_axis_level_int_s[A_ADDRESS-1:0], {$clog2(RATIO){1'b0}}};
-    assign m_axis_almost_empty = m_axis_almost_empty_int_s[RATIO-1];
-    assign m_axis_empty = m_axis_empty_int_s[RATIO-1];
-
-  end else begin : big_master
-
-    for (i=0; i<RATIO; i=i+1) begin
-      assign m_axis_ready_int_s[i] = m_axis_ready;
-    end
-
-    for (i=0; i<RATIO; i=i+1) begin
-      assign m_axis_tkeep[i*A_WIDTH/8+:A_WIDTH/8] = (m_axis_tlast_int_s[i:0] == 0) ||
-                                                    (m_axis_tlast_int_s[i]) ?
-                                                  m_axis_tkeep_int_s[i*A_WIDTH/8+:A_WIDTH/8] :
-                                                  {(A_WIDTH/8){1'b0}};
-    end
-
-    assign m_axis_data = m_axis_data_int_s;
-    // if every instance has a valid data, the interface has valid data,
-    // otherwise valid is asserted only if TLAST is asserted
-    assign m_axis_valid = (|m_axis_tlast_int_s) ? |m_axis_valid_int_s : &m_axis_valid_int_s;
-    // if one of the atomic instance is empty, m_axis_empty should be asserted
-    assign m_axis_empty = |m_axis_empty_int_s;
-    assign m_axis_almost_empty = |m_axis_almost_empty_int_s;
-
-    // the FIFO has the same room as the atomic FIFO
-    assign m_axis_level = m_axis_level_int_s[A_ADDRESS-1:0];
-
-  end
-
-  assign m_axis_tlast = (m_axis_valid) ? |m_axis_tlast_int_s : 1'b0;
-
-endgenerate
-
-// slave handshake counter
-
-reg s_axis_tlast_d = 0;
-always @(posedge s_axis_aclk) begin
-  s_axis_tlast_d <= s_axis_tlast;
-end
-
-generate
-  if (RATIO == 1) begin
-    always @(*) begin
-      s_axis_counter <= 1'b1;
-    end
-  end else if (RATIO > 1) begin
-    if (RATIO_TYPE) begin
-      always @(posedge s_axis_aclk) begin
-        if (!s_axis_aresetn) begin
-          s_axis_counter <= 0;
-        end else begin
-          if (s_axis_ready && s_axis_valid) begin
-            s_axis_counter <= s_axis_counter + 1'b1;
+  generate
+    if (RATIO == 1) begin
+      always @(*) begin
+        s_axis_counter <= 1'b1;
+      end
+    end else if (RATIO > 1) begin
+      if (RATIO_TYPE) begin
+        always @(posedge s_axis_aclk) begin
+          if (!s_axis_aresetn) begin
+            s_axis_counter <= 0;
+          end else begin
+            if (s_axis_ready && s_axis_valid) begin
+              s_axis_counter <= s_axis_counter + 1'b1;
+            end
           end
         end
-      end
-    end else begin
-      // in case of a small slave, after an active TLAST reset the counter
-      always @(posedge s_axis_aclk) begin
-        if (!s_axis_aresetn || s_axis_tlast_d) begin
-          s_axis_counter <= 0;
-        end else begin
-          if (s_axis_ready && s_axis_valid) begin
-            s_axis_counter <= s_axis_counter + 1'b1;
-          end
-        end
-      end
-    end
-  end
-endgenerate
-
-// master handshake sequencer
-
-generate
-  if (RATIO == 1) begin
-    always @(*) begin
-      m_axis_counter <= 1'b0;
-    end
-  end else if (RATIO > 1) begin
-    always @(posedge m_axis_aclk) begin
-      if (!m_axis_aresetn) begin
-        m_axis_counter <= 0;
       end else begin
-        if (m_axis_ready && m_axis_valid) begin
-          m_axis_counter <= m_axis_counter + 1'b1;
+        // in case of a small slave, after an active TLAST reset the counter
+        always @(posedge s_axis_aclk) begin
+          if (!s_axis_aresetn || s_axis_tlast_d) begin
+            s_axis_counter <= 0;
+          end else begin
+            if (s_axis_ready && s_axis_valid) begin
+              s_axis_counter <= s_axis_counter + 1'b1;
+            end
+          end
         end
       end
     end
-  end
-endgenerate
+  endgenerate
+
+  // master handshake sequencer
+
+  generate
+    if (RATIO == 1) begin
+      always @(*) begin
+        m_axis_counter <= 1'b0;
+      end
+    end else if (RATIO > 1) begin
+      always @(posedge m_axis_aclk) begin
+        if (!m_axis_aresetn) begin
+          m_axis_counter <= 0;
+        end else begin
+          if (m_axis_ready && m_axis_valid) begin
+            m_axis_counter <= m_axis_counter + 1'b1;
+          end
+        end
+      end
+    end
+  endgenerate
 
 endmodule
diff --git a/library/util_axis_resize/util_axis_resize.v b/library/util_axis_resize/util_axis_resize.v
index 619100a75..d23b201d9 100644
--- a/library/util_axis_resize/util_axis_resize.v
+++ b/library/util_axis_resize/util_axis_resize.v
@@ -35,12 +35,12 @@
 
 `timescale 1ns/100ps
 
-module util_axis_resize # (
+module util_axis_resize #(
 
   parameter MASTER_DATA_WIDTH = 64,
   parameter SLAVE_DATA_WIDTH = 64,
-  parameter BIG_ENDIAN = 0)(
-
+  parameter BIG_ENDIAN = 0
+) (
   input                       clk,
   input                       resetn,
 
@@ -53,111 +53,111 @@ module util_axis_resize # (
   output [MASTER_DATA_WIDTH-1:0] m_data
 );
 
-localparam RATIO = (SLAVE_DATA_WIDTH < MASTER_DATA_WIDTH) ?
-                            MASTER_DATA_WIDTH / SLAVE_DATA_WIDTH :
-                            SLAVE_DATA_WIDTH / MASTER_DATA_WIDTH;
+  localparam RATIO = (SLAVE_DATA_WIDTH < MASTER_DATA_WIDTH) ?
+                              MASTER_DATA_WIDTH / SLAVE_DATA_WIDTH :
+                              SLAVE_DATA_WIDTH / MASTER_DATA_WIDTH;
 
-function integer clog2;
-  input integer value;
+  function integer clog2;
+    input integer value;
+    begin
+      value = value-1;
+    for (clog2=0; value>0; clog2=clog2+1)
+      value = value>>1;
+    end
+  endfunction
+
+  generate if (SLAVE_DATA_WIDTH == MASTER_DATA_WIDTH) begin
+
+  assign m_valid = s_valid;
+  assign s_ready = m_ready;
+  assign m_data = s_data;
+
+  end else if (SLAVE_DATA_WIDTH < MASTER_DATA_WIDTH) begin
+
+  reg [MASTER_DATA_WIDTH-1:0] data;
+  reg [clog2(RATIO)-1:0] count;
+  reg valid;
+
+  always @(posedge clk)
   begin
-    value = value-1;
-  for (clog2=0; value>0; clog2=clog2+1)
-    value = value>>1;
-  end
-endfunction
-
-generate if (SLAVE_DATA_WIDTH == MASTER_DATA_WIDTH) begin
-
-assign m_valid = s_valid;
-assign s_ready = m_ready;
-assign m_data = s_data;
-
-end else if (SLAVE_DATA_WIDTH < MASTER_DATA_WIDTH) begin
-
-reg [MASTER_DATA_WIDTH-1:0] data;
-reg [clog2(RATIO)-1:0] count;
-reg valid;
-
-always @(posedge clk)
-begin
-  if (resetn == 1'b0) begin
-    count <= RATIO - 1;
-    valid <= 1'b0;
-  end else begin
-    if (count == 'h00 && s_ready == 1'b1 && s_valid == 1'b1)
-      valid <= 1'b1;
-    else if (m_ready == 1'b1)
+    if (resetn == 1'b0) begin
+      count <= RATIO - 1;
       valid <= 1'b0;
+    end else begin
+      if (count == 'h00 && s_ready == 1'b1 && s_valid == 1'b1)
+        valid <= 1'b1;
+      else if (m_ready == 1'b1)
+        valid <= 1'b0;
 
+      if (s_ready == 1'b1 && s_valid == 1'b1) begin
+        if (count == 'h00)
+          count <= RATIO - 1;
+        else
+          count <= count - 1'b1;
+      end
+    end
+  end
+
+  always @(posedge clk)
+  begin
+    if (s_ready == 1'b1 && s_valid == 1'b1)
+      if (BIG_ENDIAN == 1) begin
+        data <= {data[MASTER_DATA_WIDTH-SLAVE_DATA_WIDTH-1:0], s_data};
+      end else begin
+        data <= {s_data, data[MASTER_DATA_WIDTH-1:SLAVE_DATA_WIDTH]};
+      end
+  end
+
+  assign s_ready = ~valid || m_ready;
+  assign m_valid = valid;
+  assign m_data = data;
+
+  end else begin
+
+  reg [SLAVE_DATA_WIDTH-1:0] data;
+  reg [clog2(RATIO)-1:0] count;
+  reg valid;
+
+  always @(posedge clk)
+  begin
+    if (resetn == 1'b0) begin
+      count <= RATIO - 1;
+      valid <= 1'b0;
+    end else begin
+      if (s_valid == 1'b1 && s_ready == 1'b1)
+        valid <= 1'b1;
+      else if (count == 'h0 && m_ready == 1'b1 && m_valid == 1'b1)
+        valid <= 1'b0;
+
+      if (m_ready == 1'b1 && m_valid == 1'b1) begin
+        if (count == 'h00)
+          count <= RATIO - 1;
+        else
+          count <= count - 1'b1;
+      end
+    end
+  end
+
+  always @(posedge clk)
+  begin
     if (s_ready == 1'b1 && s_valid == 1'b1) begin
-      if (count == 'h00)
-        count <= RATIO - 1;
-      else
-        count <= count - 1'b1;
+      data <= s_data;
+    end else if (m_ready == 1'b1 && m_valid == 1'b1) begin
+      if (BIG_ENDIAN == 1) begin
+        data[SLAVE_DATA_WIDTH-1:MASTER_DATA_WIDTH] <= data[SLAVE_DATA_WIDTH-MASTER_DATA_WIDTH-1:0];
+      end else begin
+        data[SLAVE_DATA_WIDTH-MASTER_DATA_WIDTH-1:0] <= data[SLAVE_DATA_WIDTH-1:MASTER_DATA_WIDTH];
+      end
     end
   end
-end
 
-always @(posedge clk)
-begin
-  if (s_ready == 1'b1 && s_valid == 1'b1)
-    if (BIG_ENDIAN == 1) begin
-      data <= {data[MASTER_DATA_WIDTH-SLAVE_DATA_WIDTH-1:0], s_data};
-    end else begin
-      data <= {s_data, data[MASTER_DATA_WIDTH-1:SLAVE_DATA_WIDTH]};
-    end
-end
+  assign s_ready = ~valid || (m_ready && count == 'h0);
+  assign m_valid = valid;
+  assign m_data = BIG_ENDIAN == 1 ?
+    data[SLAVE_DATA_WIDTH-1:SLAVE_DATA_WIDTH-MASTER_DATA_WIDTH] :
+    data[MASTER_DATA_WIDTH-1:0];
 
-assign s_ready = ~valid || m_ready;
-assign m_valid = valid;
-assign m_data = data;
-
-end else begin
-
-reg [SLAVE_DATA_WIDTH-1:0] data;
-reg [clog2(RATIO)-1:0] count;
-reg valid;
-
-always @(posedge clk)
-begin
-  if (resetn == 1'b0) begin
-    count <= RATIO - 1;
-    valid <= 1'b0;
-  end else begin
-    if (s_valid == 1'b1 && s_ready == 1'b1)
-      valid <= 1'b1;
-    else if (count == 'h0 && m_ready == 1'b1 && m_valid == 1'b1)
-      valid <= 1'b0;
-
-    if (m_ready == 1'b1 && m_valid == 1'b1) begin
-      if (count == 'h00)
-        count <= RATIO - 1;
-      else
-        count <= count - 1'b1;
-    end
   end
-end
-
-always @(posedge clk)
-begin
-  if (s_ready == 1'b1 && s_valid == 1'b1) begin
-    data <= s_data;
-  end else if (m_ready == 1'b1 && m_valid == 1'b1) begin
-    if (BIG_ENDIAN == 1) begin
-      data[SLAVE_DATA_WIDTH-1:MASTER_DATA_WIDTH] <= data[SLAVE_DATA_WIDTH-MASTER_DATA_WIDTH-1:0];
-    end else begin
-      data[SLAVE_DATA_WIDTH-MASTER_DATA_WIDTH-1:0] <= data[SLAVE_DATA_WIDTH-1:MASTER_DATA_WIDTH];
-    end
-  end
-end
-
-assign s_ready = ~valid || (m_ready && count == 'h0);
-assign m_valid = valid;
-assign m_data = BIG_ENDIAN == 1 ?
-  data[SLAVE_DATA_WIDTH-1:SLAVE_DATA_WIDTH-MASTER_DATA_WIDTH] :
-  data[MASTER_DATA_WIDTH-1:0];
-
-end
-endgenerate
+  endgenerate
 
 endmodule
diff --git a/library/util_bsplit/util_bsplit.v b/library/util_bsplit/util_bsplit.v
index bb81b27d5..1ae0d8fb4 100644
--- a/library/util_bsplit/util_bsplit.v
+++ b/library/util_bsplit/util_bsplit.v
@@ -38,9 +38,9 @@
 
 module util_bsplit #(
 
-  parameter   CHANNEL_DATA_WIDTH     = 1,
-  parameter   NUM_OF_CHANNELS    = 8) (
-
+  parameter   CHANNEL_DATA_WIDTH = 1,
+  parameter   NUM_OF_CHANNELS = 8
+) (
   input       [((NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH)-1):0]  data,
 
   output      [(CHANNEL_DATA_WIDTH-1):0]  split_data_0,
@@ -50,7 +50,8 @@ module util_bsplit #(
   output      [(CHANNEL_DATA_WIDTH-1):0]  split_data_4,
   output      [(CHANNEL_DATA_WIDTH-1):0]  split_data_5,
   output      [(CHANNEL_DATA_WIDTH-1):0]  split_data_6,
-  output      [(CHANNEL_DATA_WIDTH-1):0]  split_data_7);
+  output      [(CHANNEL_DATA_WIDTH-1):0]  split_data_7
+);
 
   localparam  NUM_OF_CHANNELS_M   = 9;
 
@@ -73,6 +74,3 @@ module util_bsplit #(
   assign split_data_7 = data_s[((CHANNEL_DATA_WIDTH*8)-1):(CHANNEL_DATA_WIDTH*7)];
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/util_cdc/sync_bits.v b/library/util_cdc/sync_bits.v
index 7d30fb908..3d2a4566f 100644
--- a/library/util_cdc/sync_bits.v
+++ b/library/util_cdc/sync_bits.v
@@ -49,31 +49,32 @@ module sync_bits #(
   parameter NUM_OF_BITS = 1,
   // Whether input and output clocks are asynchronous, if 0 the synchronizer will
   // be bypassed and the output signal equals the input signal.
-  parameter ASYNC_CLK = 1)(
-
+  parameter ASYNC_CLK = 1
+) (
   input [NUM_OF_BITS-1:0] in_bits,
   input out_resetn,
   input out_clk,
-  output [NUM_OF_BITS-1:0] out_bits);
+  output [NUM_OF_BITS-1:0] out_bits
+);
 
-generate if (ASYNC_CLK == 1) begin
-  reg [NUM_OF_BITS-1:0] cdc_sync_stage1 = 'h0;
-  reg [NUM_OF_BITS-1:0] cdc_sync_stage2 = 'h0;
+  generate if (ASYNC_CLK == 1) begin
+    reg [NUM_OF_BITS-1:0] cdc_sync_stage1 = 'h0;
+    reg [NUM_OF_BITS-1:0] cdc_sync_stage2 = 'h0;
 
-  always @(posedge out_clk)
-  begin
-    if (out_resetn == 1'b0) begin
-      cdc_sync_stage1 <= 'b0;
-      cdc_sync_stage2 <= 'b0;
-    end else begin
-      cdc_sync_stage1 <= in_bits;
-      cdc_sync_stage2 <= cdc_sync_stage1;
+    always @(posedge out_clk)
+    begin
+      if (out_resetn == 1'b0) begin
+        cdc_sync_stage1 <= 'b0;
+        cdc_sync_stage2 <= 'b0;
+      end else begin
+        cdc_sync_stage1 <= in_bits;
+        cdc_sync_stage2 <= cdc_sync_stage1;
+      end
     end
-  end
 
-  assign out_bits = cdc_sync_stage2;
-end else begin
-  assign out_bits = in_bits;
-end endgenerate
+    assign out_bits = cdc_sync_stage2;
+  end else begin
+    assign out_bits = in_bits;
+  end endgenerate
 
 endmodule
diff --git a/library/util_cdc/sync_data.v b/library/util_cdc/sync_data.v
index 164838ef4..5f13ac032 100644
--- a/library/util_cdc/sync_data.v
+++ b/library/util_cdc/sync_data.v
@@ -45,53 +45,51 @@ module sync_data #(
   output reg [NUM_OF_BITS-1:0] out_data
 );
 
-generate
-if (ASYNC_CLK == 1) begin
+  generate
+  if (ASYNC_CLK == 1) begin
 
-wire out_toggle;
-wire in_toggle;
+  wire out_toggle;
+  wire in_toggle;
 
-reg out_toggle_d1 = 1'b0;
-reg in_toggle_d1 = 1'b0;
+  reg out_toggle_d1 = 1'b0;
+  reg in_toggle_d1 = 1'b0;
 
-reg [NUM_OF_BITS-1:0] cdc_hold;
+  reg [NUM_OF_BITS-1:0] cdc_hold;
 
-sync_bits i_sync_out (
-  .in_bits(in_toggle_d1),
-  .out_clk(out_clk),
-  .out_resetn(1'b1),
-  .out_bits(out_toggle)
-);
+  sync_bits i_sync_out (
+    .in_bits(in_toggle_d1),
+    .out_clk(out_clk),
+    .out_resetn(1'b1),
+    .out_bits(out_toggle));
 
-sync_bits i_sync_in (
-  .in_bits(out_toggle_d1),
-  .out_clk(in_clk),
-  .out_resetn(1'b1),
-  .out_bits(in_toggle)
-);
+  sync_bits i_sync_in (
+    .in_bits(out_toggle_d1),
+    .out_clk(in_clk),
+    .out_resetn(1'b1),
+    .out_bits(in_toggle));
 
-wire in_load = in_toggle == in_toggle_d1;
-wire out_load = out_toggle ^ out_toggle_d1;
+  wire in_load = in_toggle == in_toggle_d1;
+  wire out_load = out_toggle ^ out_toggle_d1;
 
-always @(posedge in_clk) begin
-  if (in_load == 1'b1) begin
-    cdc_hold <= in_data;
-    in_toggle_d1 <= ~in_toggle_d1;
+  always @(posedge in_clk) begin
+    if (in_load == 1'b1) begin
+      cdc_hold <= in_data;
+      in_toggle_d1 <= ~in_toggle_d1;
+    end
   end
-end
 
-always @(posedge out_clk) begin
-  if (out_load == 1'b1) begin
-    out_data <= cdc_hold;
+  always @(posedge out_clk) begin
+    if (out_load == 1'b1) begin
+      out_data <= cdc_hold;
+    end
+    out_toggle_d1 <= out_toggle;
   end
-  out_toggle_d1 <= out_toggle;
-end
 
-end else begin
-  always @(*) begin
-    out_data <= in_data;
+  end else begin
+    always @(*) begin
+      out_data <= in_data;
+    end
   end
-end
-endgenerate
+  endgenerate
 
 endmodule
diff --git a/library/util_cdc/sync_event.v b/library/util_cdc/sync_event.v
index 33f011089..d0d051205 100644
--- a/library/util_cdc/sync_event.v
+++ b/library/util_cdc/sync_event.v
@@ -45,76 +45,74 @@ module sync_event #(
   output reg [NUM_OF_EVENTS-1:0] out_event
 );
 
-generate
-if (ASYNC_CLK == 1) begin
+  generate
+  if (ASYNC_CLK == 1) begin
 
-wire out_toggle;
-wire in_toggle;
+  wire out_toggle;
+  wire in_toggle;
 
-reg out_toggle_d1 = 1'b0;
-reg in_toggle_d1 = 1'b0;
+  reg out_toggle_d1 = 1'b0;
+  reg in_toggle_d1 = 1'b0;
 
-sync_bits i_sync_out (
-  .in_bits(in_toggle_d1),
-  .out_clk(out_clk),
-  .out_resetn(1'b1),
-  .out_bits(out_toggle)
-);
+  sync_bits i_sync_out (
+    .in_bits(in_toggle_d1),
+    .out_clk(out_clk),
+    .out_resetn(1'b1),
+    .out_bits(out_toggle));
 
-sync_bits i_sync_in (
-  .in_bits(out_toggle_d1),
-  .out_clk(in_clk),
-  .out_resetn(1'b1),
-  .out_bits(in_toggle)
-);
+  sync_bits i_sync_in (
+    .in_bits(out_toggle_d1),
+    .out_clk(in_clk),
+    .out_resetn(1'b1),
+    .out_bits(in_toggle));
 
-wire in_ready = in_toggle == in_toggle_d1;
-wire load_out = out_toggle ^ out_toggle_d1;
+  wire in_ready = in_toggle == in_toggle_d1;
+  wire load_out = out_toggle ^ out_toggle_d1;
 
-reg [NUM_OF_EVENTS-1:0] in_event_sticky = 'h00;
-wire [NUM_OF_EVENTS-1:0] pending_events = in_event_sticky | in_event;
-wire [NUM_OF_EVENTS-1:0] out_event_s;
-
-always @(posedge in_clk) begin
-  if (in_ready == 1'b1) begin
-    in_event_sticky <= {NUM_OF_EVENTS{1'b0}};
-    if (|pending_events == 1'b1) begin
-      in_toggle_d1 <= ~in_toggle_d1;
-    end
-  end else begin
-    in_event_sticky <= pending_events;
-  end
-end
-
-if (NUM_OF_EVENTS > 1) begin
-  reg [NUM_OF_EVENTS-1:0] cdc_hold = 'h00;
+  reg [NUM_OF_EVENTS-1:0] in_event_sticky = 'h00;
+  wire [NUM_OF_EVENTS-1:0] pending_events = in_event_sticky | in_event;
+  wire [NUM_OF_EVENTS-1:0] out_event_s;
 
   always @(posedge in_clk) begin
     if (in_ready == 1'b1) begin
-      cdc_hold <= pending_events;
+      in_event_sticky <= {NUM_OF_EVENTS{1'b0}};
+      if (|pending_events == 1'b1) begin
+        in_toggle_d1 <= ~in_toggle_d1;
+      end
+    end else begin
+      in_event_sticky <= pending_events;
     end
   end
 
-  assign out_event_s = cdc_hold;
-end else begin
-  // When there is only one event, we know that it is set.
-  assign out_event_s = 1'b1;
-end
+  if (NUM_OF_EVENTS > 1) begin
+    reg [NUM_OF_EVENTS-1:0] cdc_hold = 'h00;
 
-always @(posedge out_clk) begin
-  if (load_out == 1'b1) begin
-    out_event <= out_event_s;
+    always @(posedge in_clk) begin
+      if (in_ready == 1'b1) begin
+        cdc_hold <= pending_events;
+      end
+    end
+
+    assign out_event_s = cdc_hold;
   end else begin
-    out_event <= {NUM_OF_EVENTS{1'b0}};
+    // When there is only one event, we know that it is set.
+    assign out_event_s = 1'b1;
   end
-  out_toggle_d1 <= out_toggle;
-end
 
-end else begin
-  always @(*) begin
-    out_event <= in_event;
+  always @(posedge out_clk) begin
+    if (load_out == 1'b1) begin
+      out_event <= out_event_s;
+    end else begin
+      out_event <= {NUM_OF_EVENTS{1'b0}};
+    end
+    out_toggle_d1 <= out_toggle;
   end
-end
-endgenerate
+
+  end else begin
+    always @(*) begin
+      out_event <= in_event;
+    end
+  end
+  endgenerate
 
 endmodule
diff --git a/library/util_cdc/sync_gray.v b/library/util_cdc/sync_gray.v
index 9382d9ddd..f16cfff4a 100644
--- a/library/util_cdc/sync_gray.v
+++ b/library/util_cdc/sync_gray.v
@@ -48,68 +48,69 @@ module sync_gray #(
   parameter DATA_WIDTH = 1,
   // Whether the input and output clock are asynchronous, if set to 0 the
   // synchronizer will be bypassed and out_count will be in_count.
-  parameter ASYNC_CLK = 1)(
-
+  parameter ASYNC_CLK = 1
+) (
   input in_clk,
   input in_resetn,
   input [DATA_WIDTH-1:0] in_count,
   input out_resetn,
   input out_clk,
-  output [DATA_WIDTH-1:0] out_count);
+  output [DATA_WIDTH-1:0] out_count
+);
 
-generate if (ASYNC_CLK == 1) begin
-  reg [DATA_WIDTH-1:0] cdc_sync_stage0 = 'h0;
-  reg [DATA_WIDTH-1:0] cdc_sync_stage1 = 'h0;
-  reg [DATA_WIDTH-1:0] cdc_sync_stage2 = 'h0;
-  reg [DATA_WIDTH-1:0] out_count_m = 'h0;
+  generate if (ASYNC_CLK == 1) begin
+    reg [DATA_WIDTH-1:0] cdc_sync_stage0 = 'h0;
+    reg [DATA_WIDTH-1:0] cdc_sync_stage1 = 'h0;
+    reg [DATA_WIDTH-1:0] cdc_sync_stage2 = 'h0;
+    reg [DATA_WIDTH-1:0] out_count_m = 'h0;
 
-  function [DATA_WIDTH-1:0] g2b;
-    input [DATA_WIDTH-1:0] g;
-    reg   [DATA_WIDTH-1:0] b;
-    integer i;
-    begin
-      b[DATA_WIDTH-1] = g[DATA_WIDTH-1];
-      for (i = DATA_WIDTH - 2; i >= 0; i =  i - 1)
-        b[i] = b[i + 1] ^ g[i];
-      g2b = b;
+    function [DATA_WIDTH-1:0] g2b;
+      input [DATA_WIDTH-1:0] g;
+      reg   [DATA_WIDTH-1:0] b;
+      integer i;
+      begin
+        b[DATA_WIDTH-1] = g[DATA_WIDTH-1];
+        for (i = DATA_WIDTH - 2; i >= 0; i =  i - 1)
+          b[i] = b[i + 1] ^ g[i];
+        g2b = b;
+      end
+    endfunction
+
+    function [DATA_WIDTH-1:0] b2g;
+      input [DATA_WIDTH-1:0] b;
+      reg [DATA_WIDTH-1:0] g;
+      integer i;
+      begin
+        g[DATA_WIDTH-1] = b[DATA_WIDTH-1];
+        for (i = DATA_WIDTH - 2; i >= 0; i = i -1)
+            g[i] = b[i + 1] ^ b[i];
+        b2g = g;
+      end
+    endfunction
+
+    always @(posedge in_clk) begin
+      if (in_resetn == 1'b0) begin
+        cdc_sync_stage0 <= 'h00;
+      end else begin
+        cdc_sync_stage0 <= b2g(in_count);
+      end
     end
-  endfunction
 
-  function [DATA_WIDTH-1:0] b2g;
-    input [DATA_WIDTH-1:0] b;
-    reg [DATA_WIDTH-1:0] g;
-    integer i;
-    begin
-      g[DATA_WIDTH-1] = b[DATA_WIDTH-1];
-      for (i = DATA_WIDTH - 2; i >= 0; i = i -1)
-          g[i] = b[i + 1] ^ b[i];
-      b2g = g;
+    always @(posedge out_clk) begin
+      if (out_resetn == 1'b0) begin
+        cdc_sync_stage1 <= 'h00;
+        cdc_sync_stage2 <= 'h00;
+        out_count_m <= 'h00;
+      end else begin
+        cdc_sync_stage1 <= cdc_sync_stage0;
+        cdc_sync_stage2 <= cdc_sync_stage1;
+        out_count_m <= g2b(cdc_sync_stage2);
+      end
     end
-  endfunction
 
-  always @(posedge in_clk) begin
-    if (in_resetn == 1'b0) begin
-      cdc_sync_stage0 <= 'h00;
-    end else begin
-      cdc_sync_stage0 <= b2g(in_count);
-    end
-  end
-
-  always @(posedge out_clk) begin
-    if (out_resetn == 1'b0) begin
-      cdc_sync_stage1 <= 'h00;
-      cdc_sync_stage2 <= 'h00;
-      out_count_m <= 'h00;
-    end else begin
-      cdc_sync_stage1 <= cdc_sync_stage0;
-      cdc_sync_stage2 <= cdc_sync_stage1;
-      out_count_m <= g2b(cdc_sync_stage2);
-    end
-  end
-
-  assign out_count = out_count_m;
-end else begin
-  assign out_count = in_count;
-end endgenerate
+    assign out_count = out_count_m;
+  end else begin
+    assign out_count = in_count;
+  end endgenerate
 
 endmodule
diff --git a/library/util_cic/cic_comb.v b/library/util_cic/cic_comb.v
index 3db33c067..5a3b32777 100644
--- a/library/util_cic/cic_comb.v
+++ b/library/util_cic/cic_comb.v
@@ -48,84 +48,84 @@ module cic_comb #(
   output [DATA_WIDTH-1:0] data_out
 );
 
-reg [SEQ-1:0] storage[0:DATA_WIDTH-1];
-reg [DATA_WIDTH-1:0] state = 'h00;
+  reg [SEQ-1:0] storage[0:DATA_WIDTH-1];
+  reg [DATA_WIDTH-1:0] state = 'h00;
 
-reg [2:0] counter = 'h00;
-reg active = 1'b0;
+  reg [2:0] counter = 'h00;
+  reg active = 1'b0;
 
-integer x;
+  integer x;
 
-initial begin
-  for (x = 0; x < DATA_WIDTH; x = x + 1) begin
-    storage[x] = 'h00;
-  end
-end
-
-generate if (SEQ != 1) begin
-
-always @(posedge clk) begin
-  if (ce == 1'b1) begin
-    counter <= SEQ-1;
-    active <= 1'b1;
-  end else if (active == 1'b1) begin
-    counter <= counter - 1'b1;
-    if (counter == 'h1) begin
-      active <= 1'b0;
+  initial begin
+    for (x = 0; x < DATA_WIDTH; x = x + 1) begin
+      storage[x] = 'h00;
     end
   end
-end
 
-end
-endgenerate
-
-wire [DATA_WIDTH-1:0] mask;
-reg [DATA_WIDTH-1:0] data_in_seq;
-wire [DATA_WIDTH-1:0] storage_out;
-wire [DATA_WIDTH-1:0] diff = (data_in_seq | ~mask) - (storage_out & mask);
-
-always @(*) begin
-  if (ce == 1'b1) begin
-    data_in_seq <= data_in;
-  end else begin
-    data_in_seq <= SEQ != 1 ? state : 'h00;
-  end
-end
-
-generate
-genvar i, j;
-
-for (j = 0; j < NUM_STAGES; j = j + 1) begin
-  localparam k = NUM_STAGES - j - 1;
-  localparam H = DATA_WIDTH - STAGE_WIDTH * j - 1;
-  localparam L = k == 0 ? 0 : DATA_WIDTH - STAGE_WIDTH * (j+1);
-
-  assign mask[H:L] = {{H-L{1'b1}},k != 0 ? enable[k] : 1'b1};
-
-  for (i = L; i <= H; i = i + 1) begin: shift_r
-    always @(posedge clk) begin
-      if (enable[k] == 1'b1 && (ce == 1'b1 || active == 1'b1)) begin
-        if (SEQ > 1) begin
-          storage[i] <= {storage[i][SEQ-2:0],data_in_seq[i]};
-        end else begin
-          storage[i] <= data_in_seq[i];
-        end
-      end
-    end
-
-    assign storage_out[i] = storage[i][SEQ-1];
-
-  end
+  generate if (SEQ != 1) begin
 
   always @(posedge clk) begin
-    if (enable[k] == 1'b1 && (ce == 1'b1 || active == 1'b1)) begin
-      state[H:L] <= diff[H:L];
+    if (ce == 1'b1) begin
+      counter <= SEQ-1;
+      active <= 1'b1;
+    end else if (active == 1'b1) begin
+      counter <= counter - 1'b1;
+      if (counter == 'h1) begin
+        active <= 1'b0;
+      end
     end
   end
-end
 
-endgenerate
+  end
+  endgenerate
 
-assign data_out = state;
+  wire [DATA_WIDTH-1:0] mask;
+  reg [DATA_WIDTH-1:0] data_in_seq;
+  wire [DATA_WIDTH-1:0] storage_out;
+  wire [DATA_WIDTH-1:0] diff = (data_in_seq | ~mask) - (storage_out & mask);
+
+  always @(*) begin
+    if (ce == 1'b1) begin
+      data_in_seq <= data_in;
+    end else begin
+      data_in_seq <= SEQ != 1 ? state : 'h00;
+    end
+  end
+
+  generate
+  genvar i, j;
+
+  for (j = 0; j < NUM_STAGES; j = j + 1) begin
+    localparam k = NUM_STAGES - j - 1;
+    localparam H = DATA_WIDTH - STAGE_WIDTH * j - 1;
+    localparam L = k == 0 ? 0 : DATA_WIDTH - STAGE_WIDTH * (j+1);
+
+    assign mask[H:L] = {{H-L{1'b1}},k != 0 ? enable[k] : 1'b1};
+
+    for (i = L; i <= H; i = i + 1) begin: shift_r
+      always @(posedge clk) begin
+        if (enable[k] == 1'b1 && (ce == 1'b1 || active == 1'b1)) begin
+          if (SEQ > 1) begin
+            storage[i] <= {storage[i][SEQ-2:0],data_in_seq[i]};
+          end else begin
+            storage[i] <= data_in_seq[i];
+          end
+        end
+      end
+
+      assign storage_out[i] = storage[i][SEQ-1];
+
+    end
+
+    always @(posedge clk) begin
+      if (enable[k] == 1'b1 && (ce == 1'b1 || active == 1'b1)) begin
+        state[H:L] <= diff[H:L];
+      end
+    end
+  end
+
+  endgenerate
+
+  assign data_out = state;
 
 endmodule
diff --git a/library/util_cic/cic_int.v b/library/util_cic/cic_int.v
index 10d351f7e..da2e7bb30 100644
--- a/library/util_cic/cic_int.v
+++ b/library/util_cic/cic_int.v
@@ -46,29 +46,29 @@ module cic_int #(
   output [DATA_WIDTH-1:0] data_out
 );
 
-reg [DATA_WIDTH-1:0] state = 'h00;
-wire [DATA_WIDTH-1:0] sum;
-wire [DATA_WIDTH-1:0] mask;
+  reg [DATA_WIDTH-1:0] state = 'h00;
+  wire [DATA_WIDTH-1:0] sum;
+  wire [DATA_WIDTH-1:0] mask;
 
-assign data_out = state;
-assign sum = (data_in & mask) + (state & mask);
-generate
-genvar i;
+  assign data_out = state;
+  assign sum = (data_in & mask) + (state & mask);
+  generate
+  genvar i;
 
-for (i = 0; i < NUM_STAGES; i = i + 1) begin
-  localparam j = NUM_STAGES - i - 1;
-  localparam H = DATA_WIDTH - STAGE_WIDTH * i - 1;
-  localparam L = j == 0 ? 0 : DATA_WIDTH - STAGE_WIDTH * (i+1);
+  for (i = 0; i < NUM_STAGES; i = i + 1) begin
+    localparam j = NUM_STAGES - i - 1;
+    localparam H = DATA_WIDTH - STAGE_WIDTH * i - 1;
+    localparam L = j == 0 ? 0 : DATA_WIDTH - STAGE_WIDTH * (i+1);
 
-  assign mask[H:L] = {{H-L{1'b1}},j != 0 ? ce[j] : 1'b1};
+    assign mask[H:L] = {{H-L{1'b1}},j != 0 ? ce[j] : 1'b1};
 
-  always @(posedge clk) begin
-    if (ce[j] == 1'b1) begin
-      state[H:L] <= sum[H:L];
+    always @(posedge clk) begin
+      if (ce[j] == 1'b1) begin
+        state[H:L] <= sum[H:L];
+      end
     end
   end
-end
 
-endgenerate
+  endgenerate
 
 endmodule
diff --git a/library/util_dacfifo/util_dacfifo.v b/library/util_dacfifo/util_dacfifo.v
index 431e6d996..c9555e67f 100644
--- a/library/util_dacfifo/util_dacfifo.v
+++ b/library/util_dacfifo/util_dacfifo.v
@@ -38,7 +38,8 @@
 module util_dacfifo #(
 
   parameter       ADDRESS_WIDTH = 6,
-  parameter       DATA_WIDTH = 128) (
+  parameter       DATA_WIDTH = 128
+) (
 
   // DMA interface
 
@@ -59,8 +60,8 @@ module util_dacfifo #(
   output  reg             dac_dunf,
   output  reg             dac_xfer_out,
 
-  input                   bypass);
-
+  input                   bypass
+);
 
   localparam  FIFO_THRESHOLD_HI = {(ADDRESS_WIDTH){1'b1}} - 4;
 
@@ -110,7 +111,6 @@ module util_dacfifo #(
   wire                                dac_xfer_posedge_s;
   wire                                dac_rst_int_s;
 
-
   // internal reset generation
 
   always @(posedge dma_clk) begin
@@ -160,8 +160,8 @@ module util_dacfifo #(
   end
 
   ad_b2g #(
-    .DATA_WIDTH (ADDRESS_WIDTH))
-  i_dma_waddr_b2g (
+    .DATA_WIDTH (ADDRESS_WIDTH)
+  ) i_dma_waddr_b2g (
     .din (dma_waddr),
     .dout (dma_waddr_b2g_s));
 
@@ -214,8 +214,8 @@ module util_dacfifo #(
   end
 
   ad_g2b #(
-    .DATA_WIDTH (ADDRESS_WIDTH))
-  i_dac_waddr_g2b (
+    .DATA_WIDTH (ADDRESS_WIDTH)
+  ) i_dac_waddr_g2b (
     .din (dac_waddr_m2),
     .dout (dac_waddr_g2b_s));
 
@@ -240,8 +240,8 @@ module util_dacfifo #(
   end
 
   ad_g2b #(
-    .DATA_WIDTH (ADDRESS_WIDTH))
-  i_dac_lastaddr_g2b (
+    .DATA_WIDTH (ADDRESS_WIDTH)
+  ) i_dac_lastaddr_g2b (
     .din (dac_lastaddr_m2),
     .dout (dac_lastaddr_g2b_s));
 
@@ -268,8 +268,8 @@ module util_dacfifo #(
 
   ad_mem #(
     .ADDRESS_WIDTH (ADDRESS_WIDTH),
-    .DATA_WIDTH (DATA_WIDTH))
-  i_mem_fifo (
+    .DATA_WIDTH (DATA_WIDTH)
+  ) i_mem_fifo (
     .clka (dma_clk),
     .wea (dma_wren_s),
     .addra (dma_waddr),
@@ -306,8 +306,7 @@ module util_dacfifo #(
     .dac_rst(dac_rst),
     .dac_valid(dac_valid),
     .dac_data(dac_data_bypass_s),
-    .dac_dunf(dac_dunf_bypass_s)
-  );
+    .dac_dunf(dac_dunf_bypass_s));
 
   always @(posedge dma_clk) begin
     dma_bypass_m1 <= bypass;
@@ -333,4 +332,3 @@ module util_dacfifo #(
   end
 
 endmodule
-
diff --git a/library/util_dacfifo/util_dacfifo_bypass.v b/library/util_dacfifo/util_dacfifo_bypass.v
index df94bdde2..bcc9f2e8c 100644
--- a/library/util_dacfifo/util_dacfifo_bypass.v
+++ b/library/util_dacfifo/util_dacfifo_bypass.v
@@ -38,7 +38,8 @@
 module util_dacfifo_bypass #(
 
   parameter   DAC_DATA_WIDTH = 64,
-  parameter   DMA_DATA_WIDTH = 64) (
+  parameter   DMA_DATA_WIDTH = 64
+) (
 
   // DMA FIFO interface
 
@@ -109,8 +110,8 @@ module util_dacfifo_bypass #(
     .A_ADDRESS_WIDTH (DMA_ADDRESS_WIDTH),
     .A_DATA_WIDTH (DMA_DATA_WIDTH),
     .B_ADDRESS_WIDTH (DAC_ADDRESS_WIDTH),
-    .B_DATA_WIDTH (DAC_DATA_WIDTH))
-  i_mem_asym (
+    .B_DATA_WIDTH (DAC_DATA_WIDTH)
+  ) i_mem_asym (
     .clka (dma_clk),
     .wea (dma_mem_wea_s),
     .addra (dma_mem_waddr),
@@ -144,8 +145,8 @@ module util_dacfifo_bypass #(
   end
 
   ad_b2g #(
-    .DATA_WIDTH (DMA_ADDRESS_WIDTH))
-  i_dma_mem_waddr_b2g (
+    .DATA_WIDTH (DMA_ADDRESS_WIDTH)
+  ) i_dma_mem_waddr_b2g (
     .din (dma_mem_waddr),
     .dout (dma_mem_waddr_b2g_s));
 
@@ -172,8 +173,8 @@ module util_dacfifo_bypass #(
   end
 
   ad_g2b #(
-    .DATA_WIDTH (DAC_ADDRESS_WIDTH))
-  i_dma_mem_raddr_g2b (
+    .DATA_WIDTH (DAC_ADDRESS_WIDTH)
+  ) i_dma_mem_raddr_g2b (
     .din (dma_mem_raddr_m2),
     .dout (dma_mem_raddr_m2_g2b_s));
 
@@ -187,7 +188,6 @@ module util_dacfifo_bypass #(
                                  (MEM_RATIO == 2) ? ({dma_mem_raddr, 1'b0}) :
                                  (MEM_RATIO == 4) ? ({dma_mem_raddr, 2'b0}) : ({dma_mem_raddr, 3'b0}));
 
-
   // relative address offset on DAC domain
   assign dac_mem_waddr_s = (DAC_DATA_WIDTH>DMA_DATA_WIDTH) ?
                                 ((MEM_RATIO == 1) ? (dac_mem_waddr) :
@@ -218,8 +218,8 @@ module util_dacfifo_bypass #(
   end
 
   ad_b2g #(
-    .DATA_WIDTH (DAC_ADDRESS_WIDTH))
-  i_dac_mem_raddr_b2g (
+    .DATA_WIDTH (DAC_ADDRESS_WIDTH)
+  ) i_dac_mem_raddr_b2g (
     .din (dac_mem_raddr),
     .dout (dac_mem_raddr_b2g_s));
 
@@ -238,8 +238,8 @@ module util_dacfifo_bypass #(
   end
 
   ad_g2b #(
-    .DATA_WIDTH (DMA_ADDRESS_WIDTH))
-  i_dac_mem_waddr_g2b (
+    .DATA_WIDTH (DMA_ADDRESS_WIDTH)
+  ) i_dac_mem_waddr_g2b (
     .din (dac_mem_waddr_m2),
     .dout (dac_mem_waddr_m2_g2b_s));
 
@@ -267,4 +267,3 @@ module util_dacfifo_bypass #(
   end
 
 endmodule
-
diff --git a/library/util_do_ram/util_do_ram.v b/library/util_do_ram/util_do_ram.v
index f83a96e2c..351c8f3b9 100644
--- a/library/util_do_ram/util_do_ram.v
+++ b/library/util_do_ram/util_do_ram.v
@@ -43,7 +43,6 @@ module util_do_ram #(
 
   parameter LENGTH_WIDTH = 16
 ) (
-
   input                                    wr_request_enable,
   input                                    wr_request_valid,
   output  reg                              wr_request_ready = 1'b0,
@@ -78,205 +77,201 @@ module util_do_ram #(
   output [DST_DATA_WIDTH/8-1:0]            m_axis_keep,
   output [0:0]                             m_axis_user,
   output                                   m_axis_last
-
 );
-//   src = s_axis_* = wr
-//   dst = m_axis_* = rd
-//
 
-localparam RAM_LATENCY = 2;
+  //   src = s_axis_* = wr
+  //   dst = m_axis_* = rd
+  //
 
-localparam SRC_ADDR_ALIGN = $clog2(SRC_DATA_WIDTH/8);
-localparam DST_ADDR_ALIGN = $clog2(DST_DATA_WIDTH/8);
+  localparam RAM_LATENCY = 2;
 
-localparam SRC_ADDRESS_WIDTH = LENGTH_WIDTH - SRC_ADDR_ALIGN;
-localparam DST_ADDRESS_WIDTH = LENGTH_WIDTH - DST_ADDR_ALIGN;
+  localparam SRC_ADDR_ALIGN = $clog2(SRC_DATA_WIDTH/8);
+  localparam DST_ADDR_ALIGN = $clog2(DST_DATA_WIDTH/8);
 
-wire  wr_enable;
-wire  [DST_DATA_WIDTH-1:0]    rd_data;
-wire  [1:0] rd_fifo_room;
-wire        rd_enable;
-wire        rd_last_beat;
-wire        rd_fifo_s_ready;
-wire        rd_fifo_s_valid;
+  localparam SRC_ADDRESS_WIDTH = LENGTH_WIDTH - SRC_ADDR_ALIGN;
+  localparam DST_ADDRESS_WIDTH = LENGTH_WIDTH - DST_ADDR_ALIGN;
 
-reg [SRC_ADDRESS_WIDTH-1:0] wr_length = 'h0;
-reg [SRC_ADDRESS_WIDTH-1:0] wr_addr = 'h0;
-reg   [DST_DATA_WIDTH-1:0]    rd_data_l2 = 'h0;
-reg   [DST_ADDRESS_WIDTH-1:0] rd_length = 'h0;
-reg   [DST_ADDRESS_WIDTH-1:0] rd_addr = 'h0;
-reg  rd_pending = 1'b0;
+  wire  wr_enable;
+  wire  [DST_DATA_WIDTH-1:0] rd_data;
+  wire  [1:0] rd_fifo_room;
+  wire        rd_enable;
+  wire        rd_last_beat;
+  wire        rd_fifo_s_ready;
+  wire        rd_fifo_s_valid;
 
+  reg [SRC_ADDRESS_WIDTH-1:0] wr_length = 'h0;
+  reg [SRC_ADDRESS_WIDTH-1:0] wr_addr = 'h0;
+  reg [DST_DATA_WIDTH-1:0]    rd_data_l2 = 'h0;
+  reg [DST_ADDRESS_WIDTH-1:0] rd_length = 'h0;
+  reg [DST_ADDRESS_WIDTH-1:0] rd_addr = 'h0;
+  reg rd_pending = 1'b0;
 
-always @(posedge s_axis_aclk) begin
-  if (~s_axis_aresetn)
-    wr_request_ready <= 1'b1;
-  else if (wr_request_valid)
-    wr_request_ready <= 1'b0;
-  else if (wr_response_eot)
-    wr_request_ready <= 1'b1;
-end
-
-always @(posedge s_axis_aclk) begin
-  if (wr_request_valid & wr_request_ready)
-    wr_length <= wr_request_length[LENGTH_WIDTH-1:SRC_ADDR_ALIGN];
+  always @(posedge s_axis_aclk) begin
+    if (~s_axis_aresetn)
+      wr_request_ready <= 1'b1;
+    else if (wr_request_valid)
+      wr_request_ready <= 1'b0;
+    else if (wr_response_eot)
+      wr_request_ready <= 1'b1;
   end
 
-wire wr_last_beat;
-assign wr_last_beat = s_axis_valid & s_axis_ready & ((wr_addr == wr_length) | s_axis_last);
+  always @(posedge s_axis_aclk) begin
+    if (wr_request_valid & wr_request_ready)
+      wr_length <= wr_request_length[LENGTH_WIDTH-1:SRC_ADDR_ALIGN];
+    end
 
-always @(posedge s_axis_aclk) begin
-  if (~wr_request_enable)
-    s_axis_ready <= 1'b0;
-  else if (wr_request_valid & wr_request_ready)
-    s_axis_ready <= 1'b1;
-  else if (wr_last_beat) begin
-    s_axis_ready <= 1'b0;
+  wire wr_last_beat;
+  assign wr_last_beat = s_axis_valid & s_axis_ready & ((wr_addr == wr_length) | s_axis_last);
+
+  always @(posedge s_axis_aclk) begin
+    if (~wr_request_enable)
+      s_axis_ready <= 1'b0;
+    else if (wr_request_valid & wr_request_ready)
+      s_axis_ready <= 1'b1;
+    else if (wr_last_beat) begin
+      s_axis_ready <= 1'b0;
+    end
   end
-end
 
-always @(posedge s_axis_aclk) begin
-  if (s_axis_valid & s_axis_ready)
-    wr_response_eot <= s_axis_last | (wr_addr == wr_length);
-  else
-    wr_response_eot <= 1'b0;
-end
+  always @(posedge s_axis_aclk) begin
+    if (s_axis_valid & s_axis_ready)
+      wr_response_eot <= s_axis_last | (wr_addr == wr_length);
+    else
+      wr_response_eot <= 1'b0;
+  end
 
-always @(posedge s_axis_aclk) begin
-  if (wr_last_beat)
-    wr_response_measured_length <= {wr_addr, {SRC_ADDR_ALIGN{1'b1}}};
-end
+  always @(posedge s_axis_aclk) begin
+    if (wr_last_beat)
+      wr_response_measured_length <= {wr_addr, {SRC_ADDR_ALIGN{1'b1}}};
+  end
 
-reg wr_full = 1'b0;
-// Protect against larger transfers than storage
-always @(posedge s_axis_aclk) begin
-  if (wr_request_valid & wr_request_ready)
-    wr_full <= 1'b0;
-  else if (&wr_addr & (s_axis_valid & s_axis_ready))
-    wr_full <= 1'b1;
-end
+  reg wr_full = 1'b0;
+  // Protect against larger transfers than storage
+  always @(posedge s_axis_aclk) begin
+    if (wr_request_valid & wr_request_ready)
+      wr_full <= 1'b0;
+    else if (&wr_addr & (s_axis_valid & s_axis_ready))
+      wr_full <= 1'b1;
+  end
 
-// Do not roll over write address
-always @(posedge s_axis_aclk) begin
-  if (~wr_request_enable | wr_last_beat)
-    wr_addr <= 'h0;
-  else if (s_axis_valid & s_axis_ready & (~(&wr_addr)))
-    wr_addr <= wr_addr + 1;
-end
-assign wr_enable = s_axis_valid & s_axis_ready & ~wr_full;
+  // Do not roll over write address
+  always @(posedge s_axis_aclk) begin
+    if (~wr_request_enable | wr_last_beat)
+      wr_addr <= 'h0;
+    else if (s_axis_valid & s_axis_ready & (~(&wr_addr)))
+      wr_addr <= wr_addr + 1;
+  end
+  assign wr_enable = s_axis_valid & s_axis_ready & ~wr_full;
 
-ad_mem_asym #(
-   .A_ADDRESS_WIDTH (SRC_ADDRESS_WIDTH),
-   .A_DATA_WIDTH (SRC_DATA_WIDTH),
-   .B_ADDRESS_WIDTH (DST_ADDRESS_WIDTH),
-   .B_DATA_WIDTH (DST_DATA_WIDTH)
-) i_mem (
-  .clka (s_axis_aclk),
-  .wea (wr_enable),
-  .addra (wr_addr),
-  .dina (s_axis_data),
+  ad_mem_asym #(
+    .A_ADDRESS_WIDTH (SRC_ADDRESS_WIDTH),
+    .A_DATA_WIDTH (SRC_DATA_WIDTH),
+    .B_ADDRESS_WIDTH (DST_ADDRESS_WIDTH),
+    .B_DATA_WIDTH (DST_DATA_WIDTH)
+  ) i_mem (
+    .clka (s_axis_aclk),
+    .wea (wr_enable),
+    .addra (wr_addr),
+    .dina (s_axis_data),
 
-  .clkb (m_axis_aclk),
-  .reb (1'b1),
-  .addrb (rd_addr),
-  .doutb (rd_data)
-);
+    .clkb (m_axis_aclk),
+    .reb (1'b1),
+    .addrb (rd_addr),
+    .doutb (rd_data));
 
-reg rd_active = 1'b0;
-reg [1:0] rd_req_cnt = 2'b0;
-always @(posedge m_axis_aclk) begin
-  if (rd_request_valid & rd_request_ready)
-    rd_req_cnt <= rd_req_cnt + 2'b1;
-  else if (rd_response_eot)
-    rd_req_cnt <= rd_req_cnt - 2'b1;
-end
+  reg rd_active = 1'b0;
+  reg [1:0] rd_req_cnt = 2'b0;
+  always @(posedge m_axis_aclk) begin
+    if (rd_request_valid & rd_request_ready)
+      rd_req_cnt <= rd_req_cnt + 2'b1;
+    else if (rd_response_eot)
+      rd_req_cnt <= rd_req_cnt - 2'b1;
+  end
 
-assign rd_request_ready = ~rd_req_cnt[1];
+  assign rd_request_ready = ~rd_req_cnt[1];
 
-always @(posedge m_axis_aclk) begin
-  if (rd_request_valid & rd_request_ready)
-    rd_length <= rd_request_length[LENGTH_WIDTH-1:DST_ADDR_ALIGN];
-end
+  always @(posedge m_axis_aclk) begin
+    if (rd_request_valid & rd_request_ready)
+      rd_length <= rd_request_length[LENGTH_WIDTH-1:DST_ADDR_ALIGN];
+  end
 
-assign rd_last_beat = (rd_addr == rd_length) & rd_enable;
-assign rd_response_eot = m_axis_last & m_axis_valid & m_axis_ready;
+  assign rd_last_beat = (rd_addr == rd_length) & rd_enable;
+  assign rd_response_eot = m_axis_last & m_axis_valid & m_axis_ready;
 
-// Read logic
-always @(posedge m_axis_aclk) begin
-  if (rd_request_valid & rd_request_ready)
-    rd_active <= 1'b1;
-  else if (rd_last_beat)
-    rd_active <= rd_req_cnt == 2;
-end
+  // Read logic
+  always @(posedge m_axis_aclk) begin
+    if (rd_request_valid & rd_request_ready)
+      rd_active <= 1'b1;
+    else if (rd_last_beat)
+      rd_active <= rd_req_cnt == 2;
+  end
 
-assign rd_enable = rd_fifo_s_ready & rd_active &
-    (rd_fifo_room >= (m_axis_valid&m_axis_ready ? 1 : RAM_LATENCY));
+  assign rd_enable = rd_fifo_s_ready & rd_active &
+      (rd_fifo_room >= (m_axis_valid&m_axis_ready ? 1 : RAM_LATENCY));
 
-always @(posedge m_axis_aclk) begin
-  if (~rd_request_enable | rd_last_beat)
-    rd_addr <= 'h0;
-  else if (rd_enable)
-    rd_addr <= rd_addr + 1;
-end
+  always @(posedge m_axis_aclk) begin
+    if (~rd_request_enable | rd_last_beat)
+      rd_addr <= 'h0;
+    else if (rd_enable)
+      rd_addr <= rd_addr + 1;
+  end
 
-// Delay read enable with latency cycles
-// <TODO> make this depend on parameter
-reg rd_valid_l1 = 1'b0;
-reg rd_valid_l2 = 1'b0;
-reg rd_last_l1 = 1'b0;
-reg rd_last_l2 = 1'b0;
-always @(posedge m_axis_aclk) begin
-  rd_valid_l1 <= rd_enable;
-  rd_last_l1 <= rd_last_beat;
-end
+  // Delay read enable with latency cycles
+  // <TODO> make this depend on parameter
+  reg rd_valid_l1 = 1'b0;
+  reg rd_valid_l2 = 1'b0;
+  reg rd_last_l1 = 1'b0;
+  reg rd_last_l2 = 1'b0;
+  always @(posedge m_axis_aclk) begin
+    rd_valid_l1 <= rd_enable;
+    rd_last_l1 <= rd_last_beat;
+  end
 
-// Extra pipeline to be sucked in by the BRAM/URAM output stage
-always @(posedge m_axis_aclk) begin
-  if (rd_valid_l1)
-    rd_data_l2 <= rd_data;
- end
+  // Extra pipeline to be sucked in by the BRAM/URAM output stage
+  always @(posedge m_axis_aclk) begin
+    if (rd_valid_l1)
+      rd_data_l2 <= rd_data;
+   end
 
- always @(posedge m_axis_aclk) begin
-  if (rd_valid_l1)
-    rd_valid_l2 <= 1'b1;
-  else if (rd_fifo_s_ready)
-    rd_valid_l2 <= 1'b0;
+   always @(posedge m_axis_aclk) begin
+    if (rd_valid_l1)
+      rd_valid_l2 <= 1'b1;
+    else if (rd_fifo_s_ready)
+      rd_valid_l2 <= 1'b0;
 
-  if (rd_valid_l1)
-    rd_last_l2 <= rd_last_l1;
-end
+    if (rd_valid_l1)
+      rd_last_l2 <= rd_last_l1;
+  end
 
-assign rd_fifo_s_valid = rd_valid_l2;
+  assign rd_fifo_s_valid = rd_valid_l2;
 
-// Read datapath to AXIS logic
-util_axis_fifo #(
-  .DATA_WIDTH(DST_DATA_WIDTH+1),
-  .ADDRESS_WIDTH(2),
-  .ASYNC_CLK(0),
-  .M_AXIS_REGISTERED(0)
-) i_rd_fifo (
-  .s_axis_aclk(m_axis_aclk),
-  .s_axis_aresetn(m_axis_aresetn),
-  .s_axis_valid(rd_fifo_s_valid),
-  .s_axis_ready(rd_fifo_s_ready),
-  .s_axis_full(),
-  .s_axis_data({rd_last_l2,rd_data_l2}),
-  .s_axis_room(rd_fifo_room),
-  .s_axis_tkeep(),
-  .s_axis_tlast(),
-  .s_axis_almost_full(),
+  // Read datapath to AXIS logic
+  util_axis_fifo #(
+    .DATA_WIDTH(DST_DATA_WIDTH+1),
+    .ADDRESS_WIDTH(2),
+    .ASYNC_CLK(0),
+    .M_AXIS_REGISTERED(0)
+  ) i_rd_fifo (
+    .s_axis_aclk(m_axis_aclk),
+    .s_axis_aresetn(m_axis_aresetn),
+    .s_axis_valid(rd_fifo_s_valid),
+    .s_axis_ready(rd_fifo_s_ready),
+    .s_axis_full(),
+    .s_axis_data({rd_last_l2,rd_data_l2}),
+    .s_axis_room(rd_fifo_room),
+    .s_axis_tkeep(),
+    .s_axis_tlast(),
+    .s_axis_almost_full(),
 
-  .m_axis_aclk(m_axis_aclk),
-  .m_axis_aresetn(m_axis_aresetn),
-  .m_axis_valid(m_axis_valid),
-  .m_axis_ready(m_axis_ready),
-  .m_axis_data({m_axis_last,m_axis_data}),
-  .m_axis_level(),
-  .m_axis_empty(),
-  .m_axis_tkeep(),
-  .m_axis_tlast(),
-  .m_axis_almost_empty()
-);
+    .m_axis_aclk(m_axis_aclk),
+    .m_axis_aresetn(m_axis_aresetn),
+    .m_axis_valid(m_axis_valid),
+    .m_axis_ready(m_axis_ready),
+    .m_axis_data({m_axis_last,m_axis_data}),
+    .m_axis_level(),
+    .m_axis_empty(),
+    .m_axis_tkeep(),
+    .m_axis_tlast(),
+    .m_axis_almost_empty());
 
 endmodule
-
diff --git a/library/util_extract/util_extract.v b/library/util_extract/util_extract.v
index 88a5ec6a8..a4f55dd93 100644
--- a/library/util_extract/util_extract.v
+++ b/library/util_extract/util_extract.v
@@ -38,8 +38,8 @@
 module util_extract #(
 
   parameter  NUM_OF_CHANNELS = 2,
-  parameter  DATA_WIDTH = NUM_OF_CHANNELS * 16) (
-
+  parameter  DATA_WIDTH = NUM_OF_CHANNELS * 16
+) (
   input                         clk,
 
   input       [DATA_WIDTH-1:0]  data_in,
@@ -79,6 +79,3 @@ module util_extract #(
   end
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/util_fir_dec/util_fir_dec.v b/library/util_fir_dec/util_fir_dec.v
index 66d63eb94..66771c433 100644
--- a/library/util_fir_dec/util_fir_dec.v
+++ b/library/util_fir_dec/util_fir_dec.v
@@ -43,7 +43,8 @@ module util_fir_dec (
   input       [15:0]  channel_1,
   input               decimate,
   output              m_axis_data_tvalid,
-  output      [31:0]  m_axis_data_tdata);
+  output      [31:0]  m_axis_data_tdata
+);
 
   wire [31:0] s_axis_data_tdata;
 
@@ -61,8 +62,6 @@ module util_fir_dec (
     .s_axis_data_tready(s_axis_data_tready),
     .s_axis_data_tdata(s_axis_data_tdata),
     .m_axis_data_tvalid(m_axis_data_tvalid_s),
-    .m_axis_data_tdata(m_axis_data_tdata_s)
-  );
-
-endmodule  // util_fir_dec
+    .m_axis_data_tdata(m_axis_data_tdata_s));
 
+endmodule
diff --git a/library/util_fir_int/util_fir_int.v b/library/util_fir_int/util_fir_int.v
index 2c1d10ed2..362f8b9ca 100644
--- a/library/util_fir_int/util_fir_int.v
+++ b/library/util_fir_int/util_fir_int.v
@@ -44,7 +44,8 @@ module util_fir_int (
   output      [15:0]  channel_1,
   output              m_axis_data_tvalid,
   input               interpolate,
-  input               dac_read);
+  input               dac_read
+);
 
   wire [31:0] m_axis_data_tdata_s;
   wire        s_axis_data_tvalid_s;
@@ -73,8 +74,6 @@ module util_fir_int (
     .s_axis_data_tready(),
     .s_axis_data_tdata(s_axis_data_tdata),
     .m_axis_data_tvalid(m_axis_data_tvalid),
-    .m_axis_data_tdata(m_axis_data_tdata_s)
-  );
-
-endmodule  // util_fir_int
+    .m_axis_data_tdata(m_axis_data_tdata_s));
 
+endmodule
diff --git a/library/util_gmii_to_rgmii/mdc_mdio.v b/library/util_gmii_to_rgmii/mdc_mdio.v
index 18cc412ce..db698a9e1 100644
--- a/library/util_gmii_to_rgmii/mdc_mdio.v
+++ b/library/util_gmii_to_rgmii/mdc_mdio.v
@@ -1,5 +1,3 @@
-`timescale 1ns/100ps
-
 // ***************************************************************************
 // ***************************************************************************
 // Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
@@ -35,17 +33,18 @@
 // ***************************************************************************
 // ***************************************************************************
 
+`timescale 1ns/100ps
+
 module mdc_mdio #(
-
-  parameter PHY_AD = 5'b10000) (
-
+  parameter PHY_AD = 5'b10000
+) (
   input                   mdio_mdc,
   input                   mdio_in_w,
   input                   mdio_in_r,
 
   output  reg [ 1:0]      speed_select,
-  output  reg             duplex_mode);
-
+  output  reg             duplex_mode
+);
 
   localparam IDLE     = 2'b01;
   localparam ACQUIRE  = 2'b10;
diff --git a/library/util_gmii_to_rgmii/util_gmii_to_rgmii.v b/library/util_gmii_to_rgmii/util_gmii_to_rgmii.v
index d466ce250..5ff964aa3 100644
--- a/library/util_gmii_to_rgmii/util_gmii_to_rgmii.v
+++ b/library/util_gmii_to_rgmii/util_gmii_to_rgmii.v
@@ -44,8 +44,8 @@ module util_gmii_to_rgmii #(
   parameter IODELAY_CTRL = 1'b0,
   parameter IDELAY_VALUE = 18,
   parameter IODELAY_GROUP = "if_delay_group",
-  parameter REFCLK_FREQUENCY = 200) (
-
+  parameter REFCLK_FREQUENCY = 200
+) (
   input                   clk_20m,
   input                   clk_25m,
   input                   clk_125m,
@@ -73,8 +73,8 @@ module util_gmii_to_rgmii #(
   output  reg [ 7:0]      gmii_rxd,
   output  reg             gmii_rx_dv,
   output  reg             gmii_rx_er,
-  output                  gmii_rx_clk);
-
+  output                  gmii_rx_clk
+);
 
   // wires
   wire            clk_2_5m;
@@ -284,11 +284,11 @@ module util_gmii_to_rgmii #(
   mdc_mdio  #(
     .PHY_AD(PHY_AD)
   ) mdc_mdio_in(
-      .mdio_mdc(mdio_mdc),
-      .mdio_in_w(mdio_in_w),
-      .mdio_in_r(mdio_in_r),
-      .speed_select(speed_selection),
-      .duplex_mode(duplex_mode));
+    .mdio_mdc(mdio_mdc),
+    .mdio_in_w(mdio_in_w),
+    .mdio_in_r(mdio_in_r),
+    .speed_select(speed_selection),
+    .duplex_mode(duplex_mode));
 
   // DELAY CONTROLLER
   generate
diff --git a/library/util_hbm/util_hbm.v b/library/util_hbm/util_hbm.v
index 86accffb3..055be7211 100644
--- a/library/util_hbm/util_hbm.v
+++ b/library/util_hbm/util_hbm.v
@@ -35,7 +35,7 @@
 
 // This IP serves as storage interfacing element for external memories like
 // HBM or DDR4 which have AXI3 or AXI4 data interfaces.
-// 
+//
 // The core leverages the axi_dmac as building blocks by merging an array of
 // simplex DMA channels into duplex AXI channels. The core will split the
 // incoming data from the source AXIS interface to multiple AXI channels,
@@ -43,10 +43,10 @@
 // AXIS destination interface.
 // The number of duplex channels is set by syntheses parameter and must be
 // set with the ratio of AXIS and AXI3/4 interface.
-// 
+//
 // Underflow or Overflow conditions are reported back to the data offload
 // through the control/status interface.
-// 
+//
 
 // Constraints:
 //   min(SRC_DATA_WIDTH,DST_DATA_WIDTH) / NUM_M >= 8
@@ -84,7 +84,6 @@ module util_hbm #(
   parameter SRC_FIFO_SIZE = 8, // In AXI bursts
   parameter DST_FIFO_SIZE = 8
 ) (
-
   input                                    wr_request_enable,
   input                                    wr_request_valid,
   output                                   wr_request_ready,
@@ -160,415 +159,411 @@ module util_hbm #(
   input  [NUM_M-1:0]                       m_axi_rvalid,
   input  [NUM_M*2-1:0]                     m_axi_rresp,
   input  [NUM_M-1:0]                       m_axi_rlast
-
 );
 
-localparam DMA_TYPE_AXI_MM = 0;
-localparam DMA_TYPE_AXI_STREAM = 1;
-localparam DMA_TYPE_FIFO = 2;
+  localparam DMA_TYPE_AXI_MM = 0;
+  localparam DMA_TYPE_AXI_STREAM = 1;
+  localparam DMA_TYPE_FIFO = 2;
 
-localparam SRC_DATA_WIDTH_PER_M = SRC_DATA_WIDTH / NUM_M;
-localparam DST_DATA_WIDTH_PER_M = DST_DATA_WIDTH / NUM_M;
+  localparam SRC_DATA_WIDTH_PER_M = SRC_DATA_WIDTH / NUM_M;
+  localparam DST_DATA_WIDTH_PER_M = DST_DATA_WIDTH / NUM_M;
 
-localparam AXI_BYTES_PER_BEAT_WIDTH = $clog2(AXI_DATA_WIDTH/8);
-localparam SRC_BYTES_PER_BEAT_WIDTH = $clog2(SRC_DATA_WIDTH_PER_M/8);
-localparam DST_BYTES_PER_BEAT_WIDTH = $clog2(DST_DATA_WIDTH_PER_M/8);
+  localparam AXI_BYTES_PER_BEAT_WIDTH = $clog2(AXI_DATA_WIDTH/8);
+  localparam SRC_BYTES_PER_BEAT_WIDTH = $clog2(SRC_DATA_WIDTH_PER_M/8);
+  localparam DST_BYTES_PER_BEAT_WIDTH = $clog2(DST_DATA_WIDTH_PER_M/8);
 
-// Size bursts to the max possible size
-//  AXI 3 1 burst is 16 beats
-//  AXI 4 1 burst is 256 beats
-// Limit one burst to 4096 bytes
-localparam MAX_BYTES_PER_BURST = (AXI_PROTOCOL ? 16 : 256) * AXI_DATA_WIDTH/8;
-localparam MAX_BYTES_PER_BURST_LMT = MAX_BYTES_PER_BURST >= 4096 ? 4096 :
-                                     MAX_BYTES_PER_BURST;
-localparam BYTES_PER_BURST_WIDTH = $clog2(MAX_BYTES_PER_BURST_LMT);
+  // Size bursts to the max possible size
+  //  AXI 3 1 burst is 16 beats
+  //  AXI 4 1 burst is 256 beats
+  // Limit one burst to 4096 bytes
+  localparam MAX_BYTES_PER_BURST = (AXI_PROTOCOL ? 16 : 256) * AXI_DATA_WIDTH/8;
+  localparam MAX_BYTES_PER_BURST_LMT = MAX_BYTES_PER_BURST >= 4096 ? 4096 :
+                                       MAX_BYTES_PER_BURST;
+  localparam BYTES_PER_BURST_WIDTH = $clog2(MAX_BYTES_PER_BURST_LMT);
 
-localparam AXI_ALEN = (8-(4*AXI_PROTOCOL));
+  localparam AXI_ALEN = (8-(4*AXI_PROTOCOL));
 
-localparam NUM_M_LOG2 = $clog2(NUM_M);
+  localparam NUM_M_LOG2 = $clog2(NUM_M);
 
-genvar i;
+  genvar i;
 
-wire [NUM_M-1:0] wr_request_ready_loc;
-wire [NUM_M-1:0] rd_request_ready_loc;
-wire [NUM_M-1:0] wr_request_eot_loc;
-wire [NUM_M-1:0] rd_request_eot_loc;
-wire [NUM_M-1:0] rd_response_valid_loc;
-wire [NUM_M-1:0] wr_response_valid_loc;
-wire             wr_eot_pending_all;
-wire             rd_eot_pending_all;
+  wire [NUM_M-1:0] wr_request_ready_loc;
+  wire [NUM_M-1:0] rd_request_ready_loc;
+  wire [NUM_M-1:0] wr_request_eot_loc;
+  wire [NUM_M-1:0] rd_request_eot_loc;
+  wire [NUM_M-1:0] rd_response_valid_loc;
+  wire [NUM_M-1:0] wr_response_valid_loc;
+  wire             wr_eot_pending_all;
+  wire             rd_eot_pending_all;
 
-assign wr_request_ready = &wr_request_ready_loc;
-assign rd_request_ready = &rd_request_ready_loc;
+  assign wr_request_ready = &wr_request_ready_loc;
+  assign rd_request_ready = &rd_request_ready_loc;
 
-// Aggregate end of transfer from all masters
-reg [NUM_M-1:0] wr_eot_pending = {NUM_M{1'b0}};
-reg [NUM_M-1:0] rd_eot_pending = {NUM_M{1'b0}};
+  // Aggregate end of transfer from all masters
+  reg [NUM_M-1:0] wr_eot_pending = {NUM_M{1'b0}};
+  reg [NUM_M-1:0] rd_eot_pending = {NUM_M{1'b0}};
 
-assign wr_eot_pending_all = &wr_eot_pending;
-assign rd_eot_pending_all = &rd_eot_pending;
+  assign wr_eot_pending_all = &wr_eot_pending;
+  assign rd_eot_pending_all = &rd_eot_pending;
 
-wire [NUM_M-1:0] s_axis_ready_loc;
-assign s_axis_ready = &s_axis_ready_loc;
+  wire [NUM_M-1:0] s_axis_ready_loc;
+  assign s_axis_ready = &s_axis_ready_loc;
 
-wire [NUM_M-1:0] m_axis_last_loc;
-assign m_axis_last = &m_axis_last_loc;
+  wire [NUM_M-1:0] m_axis_last_loc;
+  assign m_axis_last = &m_axis_last_loc;
 
-wire [NUM_M-1:0] m_axis_valid_loc;
-assign m_axis_valid = &m_axis_valid_loc;
+  wire [NUM_M-1:0] m_axis_valid_loc;
+  assign m_axis_valid = &m_axis_valid_loc;
 
-wire [NUM_M-1:0] wr_response_ready_loc;
-wire [NUM_M-1:0] rd_response_ready_loc;
+  wire [NUM_M-1:0] wr_response_ready_loc;
+  wire [NUM_M-1:0] rd_response_ready_loc;
 
-wire [NUM_M-1:0] wr_overflow_loc;
-wire [NUM_M-1:0] rd_underflow_loc;
+  wire [NUM_M-1:0] wr_overflow_loc;
+  wire [NUM_M-1:0] rd_underflow_loc;
 
-// Measure stored data in case transfer is shorter than programmed,
-//  do the measurement only with the first master, all others should be
-//  similar.
-localparam LW_PER_M = LENGTH_WIDTH-NUM_M_LOG2;
-wire [NUM_M*BYTES_PER_BURST_WIDTH-1:0] wr_measured_burst_length;
-reg [LW_PER_M-1:0] wr_response_measured_length_per_m = 'h0;
-always @(posedge s_axis_aclk) begin
-  if (wr_request_enable == 1'b0) begin
-    wr_response_measured_length_per_m <= {LW_PER_M{1'h0}};
-  end else if (wr_response_valid_loc[0] == 1'b1 && wr_response_ready_loc[0] == 1'b1) begin
-    wr_response_measured_length_per_m <= wr_response_measured_length_per_m +
-      {{LW_PER_M-BYTES_PER_BURST_WIDTH{1'b0}},wr_measured_burst_length[BYTES_PER_BURST_WIDTH-1:0]} +
-      {{LW_PER_M-1{1'b0}},~wr_request_eot_loc[0]};
-  end else if (wr_response_eot == 1'b1) begin
-    wr_response_measured_length_per_m <= {LW_PER_M{1'h0}};
+  // Measure stored data in case transfer is shorter than programmed,
+  //  do the measurement only with the first master, all others should be
+  //  similar.
+  localparam LW_PER_M = LENGTH_WIDTH-NUM_M_LOG2;
+  wire [NUM_M*BYTES_PER_BURST_WIDTH-1:0] wr_measured_burst_length;
+  reg [LW_PER_M-1:0] wr_response_measured_length_per_m = 'h0;
+  always @(posedge s_axis_aclk) begin
+    if (wr_request_enable == 1'b0) begin
+      wr_response_measured_length_per_m <= {LW_PER_M{1'h0}};
+    end else if (wr_response_valid_loc[0] == 1'b1 && wr_response_ready_loc[0] == 1'b1) begin
+      wr_response_measured_length_per_m <= wr_response_measured_length_per_m +
+        {{LW_PER_M-BYTES_PER_BURST_WIDTH{1'b0}},wr_measured_burst_length[BYTES_PER_BURST_WIDTH-1:0]} +
+        {{LW_PER_M-1{1'b0}},~wr_request_eot_loc[0]};
+    end else if (wr_response_eot == 1'b1) begin
+      wr_response_measured_length_per_m <= {LW_PER_M{1'h0}};
+    end
   end
-end
-assign wr_response_measured_length = {wr_response_measured_length_per_m,{NUM_M_LOG2{1'b1}}};
-
-always @(posedge s_axis_aclk) begin
-  wr_response_eot <= wr_eot_pending_all;
-end
-
-always @(posedge m_axis_aclk) begin
-  rd_response_eot <= rd_eot_pending_all;
-end
-
-generate
-for (i = 0; i < NUM_M; i=i+1) begin
-
-  wire [11:0] rd_dbg_status;
-  wire rd_needs_reset;
-  wire s_axis_xfer_req;
-  wire m_axis_xfer_req;
-
-  reg rd_needs_reset_d = 1'b0;
-
-  // 2Gb (256MB) per segment
-  localparam ADDR_OFFSET = (MEM_TYPE == 1) ? DDR_BASE_ADDDRESS :
-     (HBM_SEGMENT_INDEX+i) * HBM_SEGMENTS_PER_MASTER * 256 * 1024 * 1024 ;
+  assign wr_response_measured_length = {wr_response_measured_length_per_m,{NUM_M_LOG2{1'b1}}};
 
   always @(posedge s_axis_aclk) begin
-    if (wr_eot_pending_all) begin
-      wr_eot_pending[i] <= 1'b0;
-    end else if (wr_request_eot_loc[i] & wr_response_valid_loc[i]) begin
-      wr_eot_pending[i] <= 1'b1;
-    end
+    wr_response_eot <= wr_eot_pending_all;
   end
 
-  // For last burst wait until all masters are done
-  assign wr_response_ready_loc[i] = wr_request_eot_loc[i] ? wr_eot_pending_all : wr_response_valid_loc[i];
-
-  // Overflow whenever s_axis_ready deasserts during capture (RX_PATH)
-  assign wr_overflow_loc[i] =  TX_RX_N[0] ? 1'b0 : s_axis_xfer_req & ~s_axis_ready_loc[i];
-
-  // AXIS to AXI3
-  axi_dmac_transfer #(
-    .DMA_DATA_WIDTH_SRC(SRC_DATA_WIDTH_PER_M),
-    .DMA_DATA_WIDTH_DEST(AXI_DATA_WIDTH),
-    .DMA_LENGTH_WIDTH(LENGTH_WIDTH),
-    .DMA_LENGTH_ALIGN(SRC_BYTES_PER_BEAT_WIDTH),
-    .BYTES_PER_BEAT_WIDTH_DEST(AXI_BYTES_PER_BEAT_WIDTH),
-    .BYTES_PER_BEAT_WIDTH_SRC(SRC_BYTES_PER_BEAT_WIDTH),
-    .BYTES_PER_BURST_WIDTH(BYTES_PER_BURST_WIDTH),
-    .DMA_TYPE_DEST(DMA_TYPE_AXI_MM),
-    .DMA_TYPE_SRC(DMA_TYPE_AXI_STREAM),
-    .DMA_AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
-    .DMA_2D_TRANSFER(1'b0),
-    .ASYNC_CLK_REQ_SRC(0),
-    .ASYNC_CLK_SRC_DEST(1),
-    .ASYNC_CLK_DEST_REQ(1),
-    .AXI_SLICE_DEST(1),
-    .AXI_SLICE_SRC(1),
-    .MAX_BYTES_PER_BURST(MAX_BYTES_PER_BURST_LMT),
-    .FIFO_SIZE(SRC_FIFO_SIZE),
-    .ID_WIDTH($clog2(SRC_FIFO_SIZE)),
-    .AXI_LENGTH_WIDTH_SRC(8-(4*AXI_PROTOCOL)),
-    .AXI_LENGTH_WIDTH_DEST(8-(4*AXI_PROTOCOL)),
-    .ENABLE_DIAGNOSTICS_IF(0),
-    .ALLOW_ASYM_MEM(1)
-  ) i_wr_transfer (
-    .ctrl_clk(s_axis_aclk),
-    .ctrl_resetn(s_axis_aresetn),
-
-     // Control interface
-    .ctrl_enable(wr_request_enable),
-    .ctrl_pause(1'b0),
-
-    .req_valid(wr_request_valid),
-    .req_ready(wr_request_ready_loc[i]),
-    .req_dest_address(ADDR_OFFSET[AXI_ADDR_WIDTH-1:AXI_BYTES_PER_BEAT_WIDTH]),
-    .req_src_address('h0),
-    .req_x_length(wr_request_length >> NUM_M_LOG2),
-    .req_y_length(0),
-    .req_dest_stride(0),
-    .req_src_stride(0),
-    .req_sync_transfer_start(1'b0),
-    .req_last(1'b1),
-
-    .req_eot(wr_request_eot_loc[i]),
-    .req_measured_burst_length(wr_measured_burst_length[BYTES_PER_BURST_WIDTH*i+:BYTES_PER_BURST_WIDTH]),
-    .req_response_partial(),
-    .req_response_valid(wr_response_valid_loc[i]),
-    .req_response_ready(wr_response_ready_loc[i]),
-
-    .m_dest_axi_aclk(m_axi_aclk),
-    .m_dest_axi_aresetn(m_axi_aresetn),
-    .m_src_axi_aclk(1'b0),
-    .m_src_axi_aresetn(1'b0),
-
-    .m_axi_awaddr(m_axi_awaddr[AXI_ADDR_WIDTH*i+:AXI_ADDR_WIDTH]),
-    .m_axi_awlen(m_axi_awlen[AXI_ALEN*i+:AXI_ALEN]),
-    .m_axi_awsize(m_axi_awsize[3*i+:3]),
-    .m_axi_awburst(m_axi_awburst[2*i+:2]),
-    .m_axi_awprot(),
-    .m_axi_awcache(),
-    .m_axi_awvalid(m_axi_awvalid[i]),
-    .m_axi_awready(m_axi_awready[i]),
-
-    .m_axi_wdata(m_axi_wdata[AXI_DATA_WIDTH*i+:AXI_DATA_WIDTH]),
-    .m_axi_wstrb(m_axi_wstrb[(AXI_DATA_WIDTH/8)*i+:(AXI_DATA_WIDTH/8)]),
-    .m_axi_wready(m_axi_wready[i]),
-    .m_axi_wvalid(m_axi_wvalid[i]),
-    .m_axi_wlast(m_axi_wlast[i]),
-
-    .m_axi_bvalid(m_axi_bvalid[i]),
-    .m_axi_bresp(m_axi_bresp[2*i+:2]),
-    .m_axi_bready(m_axi_bready[i]),
-
-    .m_axi_arready(),
-    .m_axi_arvalid(),
-    .m_axi_araddr(),
-    .m_axi_arlen(),
-    .m_axi_arsize(),
-    .m_axi_arburst(),
-    .m_axi_arprot(),
-    .m_axi_arcache(),
-
-    .m_axi_rdata(),
-    .m_axi_rready(),
-    .m_axi_rvalid(),
-    .m_axi_rlast(),
-    .m_axi_rresp(),
-
-    .s_axis_aclk(s_axis_aclk),
-    .s_axis_ready(s_axis_ready_loc[i]),
-    .s_axis_valid(s_axis_valid),
-    .s_axis_data(s_axis_data[SRC_DATA_WIDTH_PER_M*i+:SRC_DATA_WIDTH_PER_M]),
-    .s_axis_user(s_axis_user),
-    .s_axis_last(s_axis_last),
-    .s_axis_xfer_req(s_axis_xfer_req),
-
-    .m_axis_aclk(1'b0),
-    .m_axis_ready(1'b1),
-    .m_axis_valid(),
-    .m_axis_data(),
-    .m_axis_last(),
-    .m_axis_xfer_req(),
-
-    .fifo_wr_clk(1'b0),
-    .fifo_wr_en(1'b0),
-    .fifo_wr_din('b0),
-    .fifo_wr_overflow(),
-    .fifo_wr_sync(),
-    .fifo_wr_xfer_req(),
-
-    .fifo_rd_clk(1'b0),
-    .fifo_rd_en(1'b0),
-    .fifo_rd_valid(),
-    .fifo_rd_dout(),
-    .fifo_rd_underflow(),
-    .fifo_rd_xfer_req(),
-
-    // DBG
-    .dbg_dest_request_id(),
-    .dbg_dest_address_id(),
-    .dbg_dest_data_id(),
-    .dbg_dest_response_id(),
-    .dbg_src_request_id(),
-    .dbg_src_address_id(),
-    .dbg_src_data_id(),
-    .dbg_src_response_id(),
-    .dbg_status(),
-
-    .dest_diag_level_bursts()
-  );
-
   always @(posedge m_axis_aclk) begin
-    rd_needs_reset_d <= rd_needs_reset;
+    rd_response_eot <= rd_eot_pending_all;
   end
 
-  // Generate an end of transfer at the end of flush marked by rd_needs_reset
-  always @(posedge m_axis_aclk) begin
-    if (rd_eot_pending_all) begin
-      rd_eot_pending[i] <= 1'b0;
-    end else if ((rd_request_eot_loc[i] & rd_response_valid_loc[i]) ||
-                 (~rd_needs_reset & rd_needs_reset_d)) begin
-      rd_eot_pending[i] <= 1'b1;
+  generate
+  for (i = 0; i < NUM_M; i=i+1) begin
+
+    wire [11:0] rd_dbg_status;
+    wire rd_needs_reset;
+    wire s_axis_xfer_req;
+    wire m_axis_xfer_req;
+
+    reg rd_needs_reset_d = 1'b0;
+
+    // 2Gb (256MB) per segment
+    localparam ADDR_OFFSET = (MEM_TYPE == 1) ? DDR_BASE_ADDDRESS :
+       (HBM_SEGMENT_INDEX+i) * HBM_SEGMENTS_PER_MASTER * 256 * 1024 * 1024 ;
+
+    always @(posedge s_axis_aclk) begin
+      if (wr_eot_pending_all) begin
+        wr_eot_pending[i] <= 1'b0;
+      end else if (wr_request_eot_loc[i] & wr_response_valid_loc[i]) begin
+        wr_eot_pending[i] <= 1'b1;
+      end
     end
+
+    // For last burst wait until all masters are done
+    assign wr_response_ready_loc[i] = wr_request_eot_loc[i] ? wr_eot_pending_all : wr_response_valid_loc[i];
+
+    // Overflow whenever s_axis_ready deasserts during capture (RX_PATH)
+    assign wr_overflow_loc[i] =  TX_RX_N[0] ? 1'b0 : s_axis_xfer_req & ~s_axis_ready_loc[i];
+
+    // AXIS to AXI3
+    axi_dmac_transfer #(
+      .DMA_DATA_WIDTH_SRC(SRC_DATA_WIDTH_PER_M),
+      .DMA_DATA_WIDTH_DEST(AXI_DATA_WIDTH),
+      .DMA_LENGTH_WIDTH(LENGTH_WIDTH),
+      .DMA_LENGTH_ALIGN(SRC_BYTES_PER_BEAT_WIDTH),
+      .BYTES_PER_BEAT_WIDTH_DEST(AXI_BYTES_PER_BEAT_WIDTH),
+      .BYTES_PER_BEAT_WIDTH_SRC(SRC_BYTES_PER_BEAT_WIDTH),
+      .BYTES_PER_BURST_WIDTH(BYTES_PER_BURST_WIDTH),
+      .DMA_TYPE_DEST(DMA_TYPE_AXI_MM),
+      .DMA_TYPE_SRC(DMA_TYPE_AXI_STREAM),
+      .DMA_AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
+      .DMA_2D_TRANSFER(1'b0),
+      .ASYNC_CLK_REQ_SRC(0),
+      .ASYNC_CLK_SRC_DEST(1),
+      .ASYNC_CLK_DEST_REQ(1),
+      .AXI_SLICE_DEST(1),
+      .AXI_SLICE_SRC(1),
+      .MAX_BYTES_PER_BURST(MAX_BYTES_PER_BURST_LMT),
+      .FIFO_SIZE(SRC_FIFO_SIZE),
+      .ID_WIDTH($clog2(SRC_FIFO_SIZE)),
+      .AXI_LENGTH_WIDTH_SRC(8-(4*AXI_PROTOCOL)),
+      .AXI_LENGTH_WIDTH_DEST(8-(4*AXI_PROTOCOL)),
+      .ENABLE_DIAGNOSTICS_IF(0),
+      .ALLOW_ASYM_MEM(1)
+    ) i_wr_transfer (
+      .ctrl_clk(s_axis_aclk),
+      .ctrl_resetn(s_axis_aresetn),
+
+       // Control interface
+      .ctrl_enable(wr_request_enable),
+      .ctrl_pause(1'b0),
+
+      .req_valid(wr_request_valid),
+      .req_ready(wr_request_ready_loc[i]),
+      .req_dest_address(ADDR_OFFSET[AXI_ADDR_WIDTH-1:AXI_BYTES_PER_BEAT_WIDTH]),
+      .req_src_address('h0),
+      .req_x_length(wr_request_length >> NUM_M_LOG2),
+      .req_y_length(0),
+      .req_dest_stride(0),
+      .req_src_stride(0),
+      .req_sync_transfer_start(1'b0),
+      .req_last(1'b1),
+
+      .req_eot(wr_request_eot_loc[i]),
+      .req_measured_burst_length(wr_measured_burst_length[BYTES_PER_BURST_WIDTH*i+:BYTES_PER_BURST_WIDTH]),
+      .req_response_partial(),
+      .req_response_valid(wr_response_valid_loc[i]),
+      .req_response_ready(wr_response_ready_loc[i]),
+
+      .m_dest_axi_aclk(m_axi_aclk),
+      .m_dest_axi_aresetn(m_axi_aresetn),
+      .m_src_axi_aclk(1'b0),
+      .m_src_axi_aresetn(1'b0),
+
+      .m_axi_awaddr(m_axi_awaddr[AXI_ADDR_WIDTH*i+:AXI_ADDR_WIDTH]),
+      .m_axi_awlen(m_axi_awlen[AXI_ALEN*i+:AXI_ALEN]),
+      .m_axi_awsize(m_axi_awsize[3*i+:3]),
+      .m_axi_awburst(m_axi_awburst[2*i+:2]),
+      .m_axi_awprot(),
+      .m_axi_awcache(),
+      .m_axi_awvalid(m_axi_awvalid[i]),
+      .m_axi_awready(m_axi_awready[i]),
+
+      .m_axi_wdata(m_axi_wdata[AXI_DATA_WIDTH*i+:AXI_DATA_WIDTH]),
+      .m_axi_wstrb(m_axi_wstrb[(AXI_DATA_WIDTH/8)*i+:(AXI_DATA_WIDTH/8)]),
+      .m_axi_wready(m_axi_wready[i]),
+      .m_axi_wvalid(m_axi_wvalid[i]),
+      .m_axi_wlast(m_axi_wlast[i]),
+
+      .m_axi_bvalid(m_axi_bvalid[i]),
+      .m_axi_bresp(m_axi_bresp[2*i+:2]),
+      .m_axi_bready(m_axi_bready[i]),
+
+      .m_axi_arready(),
+      .m_axi_arvalid(),
+      .m_axi_araddr(),
+      .m_axi_arlen(),
+      .m_axi_arsize(),
+      .m_axi_arburst(),
+      .m_axi_arprot(),
+      .m_axi_arcache(),
+
+      .m_axi_rdata(),
+      .m_axi_rready(),
+      .m_axi_rvalid(),
+      .m_axi_rlast(),
+      .m_axi_rresp(),
+
+      .s_axis_aclk(s_axis_aclk),
+      .s_axis_ready(s_axis_ready_loc[i]),
+      .s_axis_valid(s_axis_valid),
+      .s_axis_data(s_axis_data[SRC_DATA_WIDTH_PER_M*i+:SRC_DATA_WIDTH_PER_M]),
+      .s_axis_user(s_axis_user),
+      .s_axis_last(s_axis_last),
+      .s_axis_xfer_req(s_axis_xfer_req),
+
+      .m_axis_aclk(1'b0),
+      .m_axis_ready(1'b1),
+      .m_axis_valid(),
+      .m_axis_data(),
+      .m_axis_last(),
+      .m_axis_xfer_req(),
+
+      .fifo_wr_clk(1'b0),
+      .fifo_wr_en(1'b0),
+      .fifo_wr_din('b0),
+      .fifo_wr_overflow(),
+      .fifo_wr_sync(),
+      .fifo_wr_xfer_req(),
+
+      .fifo_rd_clk(1'b0),
+      .fifo_rd_en(1'b0),
+      .fifo_rd_valid(),
+      .fifo_rd_dout(),
+      .fifo_rd_underflow(),
+      .fifo_rd_xfer_req(),
+
+      // DBG
+      .dbg_dest_request_id(),
+      .dbg_dest_address_id(),
+      .dbg_dest_data_id(),
+      .dbg_dest_response_id(),
+      .dbg_src_request_id(),
+      .dbg_src_address_id(),
+      .dbg_src_data_id(),
+      .dbg_src_response_id(),
+      .dbg_status(),
+
+      .dest_diag_level_bursts());
+
+    always @(posedge m_axis_aclk) begin
+      rd_needs_reset_d <= rd_needs_reset;
+    end
+
+    // Generate an end of transfer at the end of flush marked by rd_needs_reset
+    always @(posedge m_axis_aclk) begin
+      if (rd_eot_pending_all) begin
+        rd_eot_pending[i] <= 1'b0;
+      end else if ((rd_request_eot_loc[i] & rd_response_valid_loc[i]) ||
+                   (~rd_needs_reset & rd_needs_reset_d)) begin
+        rd_eot_pending[i] <= 1'b1;
+      end
+    end
+
+    assign rd_response_ready_loc[i] = rd_request_eot_loc[i] ? rd_eot_pending_all : rd_response_valid_loc[i];
+
+    // Underflow whenever m_axis_valid deasserts during play (TX_PATH)
+    assign rd_underflow_loc[i] = ~TX_RX_N[0] ? 1'b0 : m_axis_xfer_req & m_axis_ready & ~m_axis_valid_loc[i];
+
+    // AXI3 to MAXIS
+    axi_dmac_transfer #(
+      .DMA_DATA_WIDTH_SRC(AXI_DATA_WIDTH),
+      .DMA_DATA_WIDTH_DEST(DST_DATA_WIDTH_PER_M),
+      .DMA_LENGTH_WIDTH(LENGTH_WIDTH),
+      .DMA_LENGTH_ALIGN(DST_BYTES_PER_BEAT_WIDTH),
+      .BYTES_PER_BEAT_WIDTH_DEST(DST_BYTES_PER_BEAT_WIDTH),
+      .BYTES_PER_BEAT_WIDTH_SRC(AXI_BYTES_PER_BEAT_WIDTH),
+      .BYTES_PER_BURST_WIDTH(BYTES_PER_BURST_WIDTH),
+      .DMA_TYPE_DEST(DMA_TYPE_AXI_STREAM),
+      .DMA_TYPE_SRC(DMA_TYPE_AXI_MM),
+      .DMA_AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
+      .DMA_2D_TRANSFER(1'b0),
+      .ASYNC_CLK_REQ_SRC(1),
+      .ASYNC_CLK_SRC_DEST(1),
+      .ASYNC_CLK_DEST_REQ(0),
+      .AXI_SLICE_DEST(1),
+      .AXI_SLICE_SRC(1),
+      .MAX_BYTES_PER_BURST(MAX_BYTES_PER_BURST_LMT),
+      .FIFO_SIZE(DST_FIFO_SIZE),
+      .ID_WIDTH($clog2(DST_FIFO_SIZE)),
+      .AXI_LENGTH_WIDTH_SRC(8-(4*AXI_PROTOCOL)),
+      .AXI_LENGTH_WIDTH_DEST(8-(4*AXI_PROTOCOL)),
+      .ENABLE_DIAGNOSTICS_IF(0),
+      .ALLOW_ASYM_MEM(1)
+    ) i_rd_transfer (
+      .ctrl_clk(m_axis_aclk),
+      .ctrl_resetn(m_axis_aresetn),
+
+       // Control interface
+      .ctrl_enable(rd_request_enable),
+      .ctrl_pause(1'b0),
+
+      .req_valid(rd_request_valid),
+      .req_ready(rd_request_ready_loc[i]),
+      .req_dest_address(0),
+      .req_src_address(ADDR_OFFSET[AXI_ADDR_WIDTH-1:AXI_BYTES_PER_BEAT_WIDTH]),
+      .req_x_length(rd_request_length >> NUM_M_LOG2),
+      .req_y_length(0),
+      .req_dest_stride(0),
+      .req_src_stride(0),
+      .req_sync_transfer_start(1'b0),
+      .req_last(1'b1),
+
+      .req_eot(rd_request_eot_loc[i]),
+      .req_measured_burst_length(),
+      .req_response_partial(),
+      .req_response_valid(rd_response_valid_loc[i]),
+      .req_response_ready(rd_response_ready_loc[i]),
+
+      .m_dest_axi_aclk(1'b0),
+      .m_dest_axi_aresetn(1'b0),
+      .m_src_axi_aclk(m_axi_aclk),
+      .m_src_axi_aresetn(m_axi_aresetn),
+
+      .m_axi_awaddr(),
+      .m_axi_awlen(),
+      .m_axi_awsize(),
+      .m_axi_awburst(),
+      .m_axi_awprot(),
+      .m_axi_awcache(),
+      .m_axi_awvalid(),
+      .m_axi_awready(1'b1),
+
+      .m_axi_wdata(),
+      .m_axi_wstrb(),
+      .m_axi_wready(1'b1),
+      .m_axi_wvalid(),
+      .m_axi_wlast(),
+
+      .m_axi_bvalid(1'b0),
+      .m_axi_bresp(),
+      .m_axi_bready(),
+
+      .m_axi_arready(m_axi_arready[i]),
+      .m_axi_arvalid(m_axi_arvalid[i]),
+      .m_axi_araddr(m_axi_araddr[AXI_ADDR_WIDTH*i+:AXI_ADDR_WIDTH]),
+      .m_axi_arlen(m_axi_arlen[AXI_ALEN*i+:AXI_ALEN]),
+      .m_axi_arsize(m_axi_arsize[3*i+:3]),
+      .m_axi_arburst(m_axi_arburst[2*i+:2]),
+      .m_axi_arprot(),
+      .m_axi_arcache(),
+
+      .m_axi_rdata(m_axi_rdata[AXI_DATA_WIDTH*i+:AXI_DATA_WIDTH]),
+      .m_axi_rready(m_axi_rready[i]),
+      .m_axi_rvalid(m_axi_rvalid[i]),
+      .m_axi_rlast(m_axi_rlast[i]),
+      .m_axi_rresp(m_axi_rresp[2*i+:2]),
+
+      .s_axis_aclk(1'b0),
+      .s_axis_ready(),
+      .s_axis_valid(1'b0),
+      .s_axis_data(),
+      .s_axis_user(),
+      .s_axis_last(),
+      .s_axis_xfer_req(),
+
+      .m_axis_aclk(m_axis_aclk),
+      .m_axis_ready((m_axis_ready & m_axis_valid) | rd_needs_reset),
+      .m_axis_valid(m_axis_valid_loc[i]),
+      .m_axis_data(m_axis_data[DST_DATA_WIDTH_PER_M*i+:DST_DATA_WIDTH_PER_M]),
+      .m_axis_last(m_axis_last_loc[i]),
+      .m_axis_xfer_req(m_axis_xfer_req),
+
+      .fifo_wr_clk(1'b0),
+      .fifo_wr_en(1'b0),
+      .fifo_wr_din('b0),
+      .fifo_wr_overflow(),
+      .fifo_wr_sync(),
+      .fifo_wr_xfer_req(),
+
+      .fifo_rd_clk(1'b0),
+      .fifo_rd_en(1'b0),
+      .fifo_rd_valid(),
+      .fifo_rd_dout(),
+      .fifo_rd_underflow(),
+      .fifo_rd_xfer_req(),
+
+      // DBG
+      .dbg_dest_request_id(),
+      .dbg_dest_address_id(),
+      .dbg_dest_data_id(),
+      .dbg_dest_response_id(),
+      .dbg_src_request_id(),
+      .dbg_src_address_id(),
+      .dbg_src_data_id(),
+      .dbg_src_response_id(),
+      .dbg_status(rd_dbg_status),
+
+      .dest_diag_level_bursts());
+
+    assign rd_needs_reset = rd_dbg_status[11];
+
   end
+  endgenerate
 
-  assign rd_response_ready_loc[i] = rd_request_eot_loc[i] ? rd_eot_pending_all : rd_response_valid_loc[i];
+  assign wr_overflow = |wr_overflow_loc;
 
-  // Underflow whenever m_axis_valid deasserts during play (TX_PATH)
-  assign rd_underflow_loc[i] = ~TX_RX_N[0] ? 1'b0 : m_axis_xfer_req & m_axis_ready & ~m_axis_valid_loc[i];
-
-  // AXI3 to MAXIS
-  axi_dmac_transfer #(
-    .DMA_DATA_WIDTH_SRC(AXI_DATA_WIDTH),
-    .DMA_DATA_WIDTH_DEST(DST_DATA_WIDTH_PER_M),
-    .DMA_LENGTH_WIDTH(LENGTH_WIDTH),
-    .DMA_LENGTH_ALIGN(DST_BYTES_PER_BEAT_WIDTH),
-    .BYTES_PER_BEAT_WIDTH_DEST(DST_BYTES_PER_BEAT_WIDTH),
-    .BYTES_PER_BEAT_WIDTH_SRC(AXI_BYTES_PER_BEAT_WIDTH),
-    .BYTES_PER_BURST_WIDTH(BYTES_PER_BURST_WIDTH),
-    .DMA_TYPE_DEST(DMA_TYPE_AXI_STREAM),
-    .DMA_TYPE_SRC(DMA_TYPE_AXI_MM),
-    .DMA_AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
-    .DMA_2D_TRANSFER(1'b0),
-    .ASYNC_CLK_REQ_SRC(1),
-    .ASYNC_CLK_SRC_DEST(1),
-    .ASYNC_CLK_DEST_REQ(0),
-    .AXI_SLICE_DEST(1),
-    .AXI_SLICE_SRC(1),
-    .MAX_BYTES_PER_BURST(MAX_BYTES_PER_BURST_LMT),
-    .FIFO_SIZE(DST_FIFO_SIZE),
-    .ID_WIDTH($clog2(DST_FIFO_SIZE)),
-    .AXI_LENGTH_WIDTH_SRC(8-(4*AXI_PROTOCOL)),
-    .AXI_LENGTH_WIDTH_DEST(8-(4*AXI_PROTOCOL)),
-    .ENABLE_DIAGNOSTICS_IF(0),
-    .ALLOW_ASYM_MEM(1)
-  ) i_rd_transfer (
-    .ctrl_clk(m_axis_aclk),
-    .ctrl_resetn(m_axis_aresetn),
-
-     // Control interface
-    .ctrl_enable(rd_request_enable),
-    .ctrl_pause(1'b0),
-
-    .req_valid(rd_request_valid),
-    .req_ready(rd_request_ready_loc[i]),
-    .req_dest_address(0),
-    .req_src_address(ADDR_OFFSET[AXI_ADDR_WIDTH-1:AXI_BYTES_PER_BEAT_WIDTH]),
-    .req_x_length(rd_request_length >> NUM_M_LOG2),
-    .req_y_length(0),
-    .req_dest_stride(0),
-    .req_src_stride(0),
-    .req_sync_transfer_start(1'b0),
-    .req_last(1'b1),
-
-    .req_eot(rd_request_eot_loc[i]),
-    .req_measured_burst_length(),
-    .req_response_partial(),
-    .req_response_valid(rd_response_valid_loc[i]),
-    .req_response_ready(rd_response_ready_loc[i]),
-
-    .m_dest_axi_aclk(1'b0),
-    .m_dest_axi_aresetn(1'b0),
-    .m_src_axi_aclk(m_axi_aclk),
-    .m_src_axi_aresetn(m_axi_aresetn),
-
-    .m_axi_awaddr(),
-    .m_axi_awlen(),
-    .m_axi_awsize(),
-    .m_axi_awburst(),
-    .m_axi_awprot(),
-    .m_axi_awcache(),
-    .m_axi_awvalid(),
-    .m_axi_awready(1'b1),
-
-    .m_axi_wdata(),
-    .m_axi_wstrb(),
-    .m_axi_wready(1'b1),
-    .m_axi_wvalid(),
-    .m_axi_wlast(),
-
-    .m_axi_bvalid(1'b0),
-    .m_axi_bresp(),
-    .m_axi_bready(),
-
-    .m_axi_arready(m_axi_arready[i]),
-    .m_axi_arvalid(m_axi_arvalid[i]),
-    .m_axi_araddr(m_axi_araddr[AXI_ADDR_WIDTH*i+:AXI_ADDR_WIDTH]),
-    .m_axi_arlen(m_axi_arlen[AXI_ALEN*i+:AXI_ALEN]),
-    .m_axi_arsize(m_axi_arsize[3*i+:3]),
-    .m_axi_arburst(m_axi_arburst[2*i+:2]),
-    .m_axi_arprot(),
-    .m_axi_arcache(),
-
-    .m_axi_rdata(m_axi_rdata[AXI_DATA_WIDTH*i+:AXI_DATA_WIDTH]),
-    .m_axi_rready(m_axi_rready[i]),
-    .m_axi_rvalid(m_axi_rvalid[i]),
-    .m_axi_rlast(m_axi_rlast[i]),
-    .m_axi_rresp(m_axi_rresp[2*i+:2]),
-
-    .s_axis_aclk(1'b0),
-    .s_axis_ready(),
-    .s_axis_valid(1'b0),
-    .s_axis_data(),
-    .s_axis_user(),
-    .s_axis_last(),
-    .s_axis_xfer_req(),
-
-    .m_axis_aclk(m_axis_aclk),
-    .m_axis_ready((m_axis_ready & m_axis_valid) | rd_needs_reset),
-    .m_axis_valid(m_axis_valid_loc[i]),
-    .m_axis_data(m_axis_data[DST_DATA_WIDTH_PER_M*i+:DST_DATA_WIDTH_PER_M]),
-    .m_axis_last(m_axis_last_loc[i]),
-    .m_axis_xfer_req(m_axis_xfer_req),
-
-    .fifo_wr_clk(1'b0),
-    .fifo_wr_en(1'b0),
-    .fifo_wr_din('b0),
-    .fifo_wr_overflow(),
-    .fifo_wr_sync(),
-    .fifo_wr_xfer_req(),
-
-    .fifo_rd_clk(1'b0),
-    .fifo_rd_en(1'b0),
-    .fifo_rd_valid(),
-    .fifo_rd_dout(),
-    .fifo_rd_underflow(),
-    .fifo_rd_xfer_req(),
-
-    // DBG
-    .dbg_dest_request_id(),
-    .dbg_dest_address_id(),
-    .dbg_dest_data_id(),
-    .dbg_dest_response_id(),
-    .dbg_src_request_id(),
-    .dbg_src_address_id(),
-    .dbg_src_data_id(),
-    .dbg_src_response_id(),
-    .dbg_status(rd_dbg_status),
-
-    .dest_diag_level_bursts()
-  );
-
-  assign rd_needs_reset = rd_dbg_status[11];
-
-end
-endgenerate
-
-assign wr_overflow = |wr_overflow_loc;
-
-assign rd_underflow = |rd_underflow_loc;
+  assign rd_underflow = |rd_underflow_loc;
 
 endmodule
-
diff --git a/library/util_mfifo/util_mfifo.v b/library/util_mfifo/util_mfifo.v
index f02ccbb4e..4e0fc6165 100644
--- a/library/util_mfifo/util_mfifo.v
+++ b/library/util_mfifo/util_mfifo.v
@@ -39,7 +39,8 @@ module util_mfifo #(
 
   parameter   NUM_OF_CHANNELS = 4,
   parameter   DIN_DATA_WIDTH = 32,
-  parameter   ADDRESS_WIDTH = 8) (
+  parameter   ADDRESS_WIDTH = 8
+) (
 
   // d-in interface
 
@@ -67,8 +68,8 @@ module util_mfifo #(
   output      [15:0]      dout_data_4,
   output      [15:0]      dout_data_5,
   output      [15:0]      dout_data_6,
-  output      [15:0]      dout_data_7);
-
+  output      [15:0]      dout_data_7
+);
 
   // internal registers
 
@@ -254,8 +255,8 @@ module util_mfifo #(
   for (n = 0; n < NUM_OF_CHANNELS; n = n + 1) begin: g_channels
   ad_mem #(
     .ADDRESS_WIDTH (ADDRESS_WIDTH),
-    .DATA_WIDTH (DIN_DATA_WIDTH))
-  i_mem (
+    .DATA_WIDTH (DIN_DATA_WIDTH)
+  ) i_mem (
     .clka (din_clk),
     .wea (din_wr),
     .addra (din_waddr),
@@ -269,6 +270,3 @@ module util_mfifo #(
   endgenerate
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/util_mii_to_rmii/mac_phy_link.v b/library/util_mii_to_rmii/mac_phy_link.v
index ca18c379e..9aca343b1 100644
--- a/library/util_mii_to_rmii/mac_phy_link.v
+++ b/library/util_mii_to_rmii/mac_phy_link.v
@@ -35,17 +35,17 @@
 `timescale 1ns/100ps
 
 module mac_phy_link #(
-    parameter RATE_10_100 = 0
-  ) (
-    input              ref_clk,
-    input    [3:0]     mac_txd,
-    input              reset_n,
-    input              mac_tx_en,
-    input              mac_tx_er,
-    output             rmii_tx_en,
-    output   [1:0]     rmii_txd,
-    output             mii_tx_clk
-  );
+  parameter RATE_10_100 = 0
+) (
+  input              ref_clk,
+  input    [3:0]     mac_txd,
+  input              reset_n,
+  input              mac_tx_en,
+  input              mac_tx_er,
+  output             rmii_tx_en,
+  output   [1:0]     rmii_txd,
+  output             mii_tx_clk
+);
 
   wire              dibit_sample;
   wire    [3:0]     num_w;
diff --git a/library/util_mii_to_rmii/phy_mac_link.v b/library/util_mii_to_rmii/phy_mac_link.v
index 5359beda8..bc028fd37 100644
--- a/library/util_mii_to_rmii/phy_mac_link.v
+++ b/library/util_mii_to_rmii/phy_mac_link.v
@@ -36,7 +36,7 @@
 
 module phy_mac_link  #(
   parameter RATE_10_100 = 0
-  ) (
+) (
   input             ref_clk,
   input             reset_n,
   input   [1:0]     phy_rxd,
@@ -48,7 +48,7 @@ module phy_mac_link  #(
   output            mii_crs,
   output            mii_col,
   output            mii_rx_clk
-  );
+);
 
   wire              clk_phase_res;
   wire              data_valid_w;
diff --git a/library/util_mii_to_rmii/util_mii_to_rmii.v b/library/util_mii_to_rmii/util_mii_to_rmii.v
index 9721b3531..4d7301fc9 100644
--- a/library/util_mii_to_rmii/util_mii_to_rmii.v
+++ b/library/util_mii_to_rmii/util_mii_to_rmii.v
@@ -38,7 +38,8 @@
 module util_mii_to_rmii #(
   parameter         INTF_CFG = 0,
   parameter         RATE_10_100 = 0
-  )   (
+) (
+
   // MAC to MII(PHY)
   input             mac_tx_en,
   input    [3:0]    mac_txd,
@@ -61,7 +62,7 @@ module util_mii_to_rmii #(
   // External
   input             ref_clk,
   input             reset_n
-  );
+);
 
   reg                mac_tx_en_r1 = 1'b0;
   reg       [3:0]    mac_txd_r1 = 4'b0;
diff --git a/library/util_pack/tb/cpack_tb.v b/library/util_pack/tb/cpack_tb.v
index b1b6f4fbf..8279510f3 100644
--- a/library/util_pack/tb/cpack_tb.v
+++ b/library/util_pack/tb/cpack_tb.v
@@ -172,7 +172,6 @@ module cpack_tb;
 
     .packed_fifo_wr_en(packed_fifo_wr_en),
     .packed_fifo_wr_data(packed_fifo_wr_data),
-    .packed_fifo_wr_overflow(1'b0)
-  );
+    .packed_fifo_wr_overflow(1'b0));
 
 endmodule
diff --git a/library/util_pack/tb/underflow_tb.v b/library/util_pack/tb/underflow_tb.v
index db348096a..a214b86bf 100644
--- a/library/util_pack/tb/underflow_tb.v
+++ b/library/util_pack/tb/underflow_tb.v
@@ -113,7 +113,6 @@ module underflow_tb;
 
     .s_axis_valid(s_axis_valid),
     .s_axis_ready(s_axis_ready),
-    .s_axis_data(s_axis_data)
-  );
+    .s_axis_data(s_axis_data));
 
 endmodule
diff --git a/library/util_pack/tb/upack_tb.v b/library/util_pack/tb/upack_tb.v
index e4cbe4460..aab311435 100644
--- a/library/util_pack/tb/upack_tb.v
+++ b/library/util_pack/tb/upack_tb.v
@@ -163,7 +163,6 @@ module upack_tb;
 
     .s_axis_valid(s_axis_valid),
     .s_axis_ready(s_axis_ready),
-    .s_axis_data(s_axis_valid ? s_axis_data : {NUM_OF_PORTS{8'hx}})
-  );
+    .s_axis_data(s_axis_valid ? s_axis_data : {NUM_OF_PORTS{8'hx}}));
 
 endmodule
diff --git a/library/util_pack/util_cpack2/util_cpack2.v b/library/util_pack/util_cpack2/util_cpack2.v
index 873e381ef..1f604f2f2 100644
--- a/library/util_pack/util_cpack2/util_cpack2.v
+++ b/library/util_pack/util_cpack2/util_cpack2.v
@@ -182,121 +182,120 @@ module util_cpack2 #(
   output [2**$clog2(NUM_OF_CHANNELS)*SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] packed_fifo_wr_data
 );
 
-localparam CHANNEL_DATA_WIDTH = SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL;
-/*
- * Round up to the next power of two and zero out the additional channels
- * internally.
- */
-localparam REAL_NUM_OF_CHANNELS = NUM_OF_CHANNELS > 32 ? 64 :
-   NUM_OF_CHANNELS > 16 ? 32 :
-   NUM_OF_CHANNELS > 8 ? 16 :
-   NUM_OF_CHANNELS > 4 ? 8 :
-   NUM_OF_CHANNELS > 2 ? 4 :
-   NUM_OF_CHANNELS > 1 ? 2 : 1;
+  localparam CHANNEL_DATA_WIDTH = SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL;
+  /*
+   * Round up to the next power of two and zero out the additional channels
+   * internally.
+   */
+  localparam REAL_NUM_OF_CHANNELS = NUM_OF_CHANNELS > 32 ? 64 :
+     NUM_OF_CHANNELS > 16 ? 32 :
+     NUM_OF_CHANNELS > 8 ? 16 :
+     NUM_OF_CHANNELS > 4 ? 8 :
+     NUM_OF_CHANNELS > 2 ? 4 :
+     NUM_OF_CHANNELS > 1 ? 2 : 1;
 
-/* FIXME: Find out how to do this in the IP-XACT */
+  /* FIXME: Find out how to do this in the IP-XACT */
 
-wire [REAL_NUM_OF_CHANNELS-1:0] enable;
-wire [63:0] enable_s;
-wire [CHANNEL_DATA_WIDTH*REAL_NUM_OF_CHANNELS-1:0] fifo_wr_data;
-wire [CHANNEL_DATA_WIDTH*64-1:0] fifo_wr_data_s;
+  wire [REAL_NUM_OF_CHANNELS-1:0] enable;
+  wire [63:0] enable_s;
+  wire [CHANNEL_DATA_WIDTH*REAL_NUM_OF_CHANNELS-1:0] fifo_wr_data;
+  wire [CHANNEL_DATA_WIDTH*64-1:0] fifo_wr_data_s;
 
-assign enable_s = {
-  enable_63,enable_62,enable_61,enable_60,enable_59,enable_58,enable_57,enable_56,
-  enable_55,enable_54,enable_53,enable_52,enable_51,enable_50,enable_49,enable_48,
-  enable_47,enable_46,enable_45,enable_44,enable_43,enable_42,enable_41,enable_40,
-  enable_39,enable_38,enable_37,enable_36,enable_35,enable_34,enable_33,enable_32,
-  enable_31,enable_30,enable_29,enable_28,enable_27,enable_26,enable_25,enable_24,
-  enable_23,enable_22,enable_21,enable_20,enable_19,enable_18,enable_17,enable_16,
-	enable_15,enable_14,enable_13,enable_12,enable_11,enable_10,enable_9,enable_8,
-	enable_7,enable_6,enable_5,enable_4,enable_3,enable_2,enable_1,enable_0
-};
-assign enable = enable_s[REAL_NUM_OF_CHANNELS-1:0];
+  assign enable_s = {
+    enable_63,enable_62,enable_61,enable_60,enable_59,enable_58,enable_57,enable_56,
+    enable_55,enable_54,enable_53,enable_52,enable_51,enable_50,enable_49,enable_48,
+    enable_47,enable_46,enable_45,enable_44,enable_43,enable_42,enable_41,enable_40,
+    enable_39,enable_38,enable_37,enable_36,enable_35,enable_34,enable_33,enable_32,
+    enable_31,enable_30,enable_29,enable_28,enable_27,enable_26,enable_25,enable_24,
+    enable_23,enable_22,enable_21,enable_20,enable_19,enable_18,enable_17,enable_16,
+  	enable_15,enable_14,enable_13,enable_12,enable_11,enable_10,enable_9,enable_8,
+  	enable_7,enable_6,enable_5,enable_4,enable_3,enable_2,enable_1,enable_0
+  };
+  assign enable = enable_s[REAL_NUM_OF_CHANNELS-1:0];
 
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*0+:CHANNEL_DATA_WIDTH] = fifo_wr_data_0;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*1+:CHANNEL_DATA_WIDTH] = fifo_wr_data_1;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*2+:CHANNEL_DATA_WIDTH] = fifo_wr_data_2;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*3+:CHANNEL_DATA_WIDTH] = fifo_wr_data_3;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*4+:CHANNEL_DATA_WIDTH] = fifo_wr_data_4;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*5+:CHANNEL_DATA_WIDTH] = fifo_wr_data_5;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*6+:CHANNEL_DATA_WIDTH] = fifo_wr_data_6;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*7+:CHANNEL_DATA_WIDTH] = fifo_wr_data_7;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*8+:CHANNEL_DATA_WIDTH] = fifo_wr_data_8;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*9+:CHANNEL_DATA_WIDTH] = fifo_wr_data_9;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*10+:CHANNEL_DATA_WIDTH] = fifo_wr_data_10;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*11+:CHANNEL_DATA_WIDTH] = fifo_wr_data_11;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*12+:CHANNEL_DATA_WIDTH] = fifo_wr_data_12;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*13+:CHANNEL_DATA_WIDTH] = fifo_wr_data_13;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*14+:CHANNEL_DATA_WIDTH] = fifo_wr_data_14;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*15+:CHANNEL_DATA_WIDTH] = fifo_wr_data_15;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*16+:CHANNEL_DATA_WIDTH] = fifo_wr_data_16;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*17+:CHANNEL_DATA_WIDTH] = fifo_wr_data_17;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*18+:CHANNEL_DATA_WIDTH] = fifo_wr_data_18;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*19+:CHANNEL_DATA_WIDTH] = fifo_wr_data_19;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*20+:CHANNEL_DATA_WIDTH] = fifo_wr_data_20;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*21+:CHANNEL_DATA_WIDTH] = fifo_wr_data_21;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*22+:CHANNEL_DATA_WIDTH] = fifo_wr_data_22;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*23+:CHANNEL_DATA_WIDTH] = fifo_wr_data_23;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*24+:CHANNEL_DATA_WIDTH] = fifo_wr_data_24;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*25+:CHANNEL_DATA_WIDTH] = fifo_wr_data_25;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*26+:CHANNEL_DATA_WIDTH] = fifo_wr_data_26;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*27+:CHANNEL_DATA_WIDTH] = fifo_wr_data_27;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*28+:CHANNEL_DATA_WIDTH] = fifo_wr_data_28;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*29+:CHANNEL_DATA_WIDTH] = fifo_wr_data_29;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*30+:CHANNEL_DATA_WIDTH] = fifo_wr_data_30;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*31+:CHANNEL_DATA_WIDTH] = fifo_wr_data_31;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*32+:CHANNEL_DATA_WIDTH] = fifo_wr_data_32;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*33+:CHANNEL_DATA_WIDTH] = fifo_wr_data_33;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*34+:CHANNEL_DATA_WIDTH] = fifo_wr_data_34;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*35+:CHANNEL_DATA_WIDTH] = fifo_wr_data_35;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*36+:CHANNEL_DATA_WIDTH] = fifo_wr_data_36;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*37+:CHANNEL_DATA_WIDTH] = fifo_wr_data_37;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*38+:CHANNEL_DATA_WIDTH] = fifo_wr_data_38;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*39+:CHANNEL_DATA_WIDTH] = fifo_wr_data_39;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*40+:CHANNEL_DATA_WIDTH] = fifo_wr_data_40;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*41+:CHANNEL_DATA_WIDTH] = fifo_wr_data_41;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*42+:CHANNEL_DATA_WIDTH] = fifo_wr_data_42;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*43+:CHANNEL_DATA_WIDTH] = fifo_wr_data_43;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*44+:CHANNEL_DATA_WIDTH] = fifo_wr_data_44;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*45+:CHANNEL_DATA_WIDTH] = fifo_wr_data_45;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*46+:CHANNEL_DATA_WIDTH] = fifo_wr_data_46;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*47+:CHANNEL_DATA_WIDTH] = fifo_wr_data_47;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*48+:CHANNEL_DATA_WIDTH] = fifo_wr_data_48;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*49+:CHANNEL_DATA_WIDTH] = fifo_wr_data_49;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*50+:CHANNEL_DATA_WIDTH] = fifo_wr_data_50;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*51+:CHANNEL_DATA_WIDTH] = fifo_wr_data_51;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*52+:CHANNEL_DATA_WIDTH] = fifo_wr_data_52;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*53+:CHANNEL_DATA_WIDTH] = fifo_wr_data_53;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*54+:CHANNEL_DATA_WIDTH] = fifo_wr_data_54;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*55+:CHANNEL_DATA_WIDTH] = fifo_wr_data_55;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*56+:CHANNEL_DATA_WIDTH] = fifo_wr_data_56;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*57+:CHANNEL_DATA_WIDTH] = fifo_wr_data_57;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*58+:CHANNEL_DATA_WIDTH] = fifo_wr_data_58;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*59+:CHANNEL_DATA_WIDTH] = fifo_wr_data_59;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*60+:CHANNEL_DATA_WIDTH] = fifo_wr_data_60;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*61+:CHANNEL_DATA_WIDTH] = fifo_wr_data_61;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*62+:CHANNEL_DATA_WIDTH] = fifo_wr_data_62;
-assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*63+:CHANNEL_DATA_WIDTH] = fifo_wr_data_63;
-assign fifo_wr_data = fifo_wr_data_s[0+:REAL_NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH];
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*0+:CHANNEL_DATA_WIDTH] = fifo_wr_data_0;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*1+:CHANNEL_DATA_WIDTH] = fifo_wr_data_1;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*2+:CHANNEL_DATA_WIDTH] = fifo_wr_data_2;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*3+:CHANNEL_DATA_WIDTH] = fifo_wr_data_3;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*4+:CHANNEL_DATA_WIDTH] = fifo_wr_data_4;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*5+:CHANNEL_DATA_WIDTH] = fifo_wr_data_5;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*6+:CHANNEL_DATA_WIDTH] = fifo_wr_data_6;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*7+:CHANNEL_DATA_WIDTH] = fifo_wr_data_7;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*8+:CHANNEL_DATA_WIDTH] = fifo_wr_data_8;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*9+:CHANNEL_DATA_WIDTH] = fifo_wr_data_9;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*10+:CHANNEL_DATA_WIDTH] = fifo_wr_data_10;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*11+:CHANNEL_DATA_WIDTH] = fifo_wr_data_11;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*12+:CHANNEL_DATA_WIDTH] = fifo_wr_data_12;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*13+:CHANNEL_DATA_WIDTH] = fifo_wr_data_13;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*14+:CHANNEL_DATA_WIDTH] = fifo_wr_data_14;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*15+:CHANNEL_DATA_WIDTH] = fifo_wr_data_15;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*16+:CHANNEL_DATA_WIDTH] = fifo_wr_data_16;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*17+:CHANNEL_DATA_WIDTH] = fifo_wr_data_17;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*18+:CHANNEL_DATA_WIDTH] = fifo_wr_data_18;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*19+:CHANNEL_DATA_WIDTH] = fifo_wr_data_19;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*20+:CHANNEL_DATA_WIDTH] = fifo_wr_data_20;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*21+:CHANNEL_DATA_WIDTH] = fifo_wr_data_21;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*22+:CHANNEL_DATA_WIDTH] = fifo_wr_data_22;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*23+:CHANNEL_DATA_WIDTH] = fifo_wr_data_23;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*24+:CHANNEL_DATA_WIDTH] = fifo_wr_data_24;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*25+:CHANNEL_DATA_WIDTH] = fifo_wr_data_25;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*26+:CHANNEL_DATA_WIDTH] = fifo_wr_data_26;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*27+:CHANNEL_DATA_WIDTH] = fifo_wr_data_27;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*28+:CHANNEL_DATA_WIDTH] = fifo_wr_data_28;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*29+:CHANNEL_DATA_WIDTH] = fifo_wr_data_29;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*30+:CHANNEL_DATA_WIDTH] = fifo_wr_data_30;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*31+:CHANNEL_DATA_WIDTH] = fifo_wr_data_31;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*32+:CHANNEL_DATA_WIDTH] = fifo_wr_data_32;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*33+:CHANNEL_DATA_WIDTH] = fifo_wr_data_33;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*34+:CHANNEL_DATA_WIDTH] = fifo_wr_data_34;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*35+:CHANNEL_DATA_WIDTH] = fifo_wr_data_35;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*36+:CHANNEL_DATA_WIDTH] = fifo_wr_data_36;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*37+:CHANNEL_DATA_WIDTH] = fifo_wr_data_37;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*38+:CHANNEL_DATA_WIDTH] = fifo_wr_data_38;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*39+:CHANNEL_DATA_WIDTH] = fifo_wr_data_39;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*40+:CHANNEL_DATA_WIDTH] = fifo_wr_data_40;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*41+:CHANNEL_DATA_WIDTH] = fifo_wr_data_41;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*42+:CHANNEL_DATA_WIDTH] = fifo_wr_data_42;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*43+:CHANNEL_DATA_WIDTH] = fifo_wr_data_43;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*44+:CHANNEL_DATA_WIDTH] = fifo_wr_data_44;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*45+:CHANNEL_DATA_WIDTH] = fifo_wr_data_45;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*46+:CHANNEL_DATA_WIDTH] = fifo_wr_data_46;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*47+:CHANNEL_DATA_WIDTH] = fifo_wr_data_47;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*48+:CHANNEL_DATA_WIDTH] = fifo_wr_data_48;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*49+:CHANNEL_DATA_WIDTH] = fifo_wr_data_49;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*50+:CHANNEL_DATA_WIDTH] = fifo_wr_data_50;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*51+:CHANNEL_DATA_WIDTH] = fifo_wr_data_51;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*52+:CHANNEL_DATA_WIDTH] = fifo_wr_data_52;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*53+:CHANNEL_DATA_WIDTH] = fifo_wr_data_53;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*54+:CHANNEL_DATA_WIDTH] = fifo_wr_data_54;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*55+:CHANNEL_DATA_WIDTH] = fifo_wr_data_55;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*56+:CHANNEL_DATA_WIDTH] = fifo_wr_data_56;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*57+:CHANNEL_DATA_WIDTH] = fifo_wr_data_57;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*58+:CHANNEL_DATA_WIDTH] = fifo_wr_data_58;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*59+:CHANNEL_DATA_WIDTH] = fifo_wr_data_59;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*60+:CHANNEL_DATA_WIDTH] = fifo_wr_data_60;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*61+:CHANNEL_DATA_WIDTH] = fifo_wr_data_61;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*62+:CHANNEL_DATA_WIDTH] = fifo_wr_data_62;
+  assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*63+:CHANNEL_DATA_WIDTH] = fifo_wr_data_63;
+  assign fifo_wr_data = fifo_wr_data_s[0+:REAL_NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH];
 
-util_cpack2_impl #(
-  .NUM_OF_CHANNELS (REAL_NUM_OF_CHANNELS),
-  .SAMPLE_DATA_WIDTH (SAMPLE_DATA_WIDTH),
-  .SAMPLES_PER_CHANNEL (SAMPLES_PER_CHANNEL)
-) i_cpack (
-  .clk (clk),
-  .reset (reset),
+  util_cpack2_impl #(
+    .NUM_OF_CHANNELS (REAL_NUM_OF_CHANNELS),
+    .SAMPLE_DATA_WIDTH (SAMPLE_DATA_WIDTH),
+    .SAMPLES_PER_CHANNEL (SAMPLES_PER_CHANNEL)
+  ) i_cpack (
+    .clk (clk),
+    .reset (reset),
 
-  .enable (enable),
+    .enable (enable),
 
-  .fifo_wr_en ({REAL_NUM_OF_CHANNELS{fifo_wr_en}}),
-  .fifo_wr_overflow (fifo_wr_overflow),
-  .fifo_wr_data (fifo_wr_data),
+    .fifo_wr_en ({REAL_NUM_OF_CHANNELS{fifo_wr_en}}),
+    .fifo_wr_overflow (fifo_wr_overflow),
+    .fifo_wr_data (fifo_wr_data),
 
-  .packed_fifo_wr_en (packed_fifo_wr_en),
-  .packed_fifo_wr_overflow (packed_fifo_wr_overflow),
-  .packed_fifo_wr_data (packed_fifo_wr_data),
-  .packed_fifo_wr_sync (packed_fifo_wr_sync)
-);
+    .packed_fifo_wr_en (packed_fifo_wr_en),
+    .packed_fifo_wr_overflow (packed_fifo_wr_overflow),
+    .packed_fifo_wr_data (packed_fifo_wr_data),
+    .packed_fifo_wr_sync (packed_fifo_wr_sync));
 
 endmodule
diff --git a/library/util_pack/util_cpack2/util_cpack2_impl.v b/library/util_pack/util_cpack2/util_cpack2_impl.v
index cb72dda53..3d621eb1c 100644
--- a/library/util_pack/util_cpack2/util_cpack2_impl.v
+++ b/library/util_pack/util_cpack2/util_cpack2_impl.v
@@ -54,22 +54,17 @@ module util_cpack2_impl #(
   output reg packed_fifo_wr_sync = 1'b1,
   output reg [NUM_OF_CHANNELS*SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] packed_fifo_wr_data = 'h00
 );
+
   localparam TOTAL_DATA_WIDTH = SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL * NUM_OF_CHANNELS;
 
-  /*
-   * Control signals from the pack shell.
-   */
+  // Control signals from the pack shell.
   wire reset_data;
   wire ready;
 
-  /*
-   * Interleaved version of `fifo_wr_data`.
-   */
+  // Interleaved version of `fifo_wr_data`.
   wire [TOTAL_DATA_WIDTH-1:0] interleaved_data;
 
-  /*
-   * Output data and corresponding control signal from the routing network.
-   */
+  // Output data and corresponding control signal from the routing network.
   wire [TOTAL_DATA_WIDTH-1:0] out_data;
   wire out_sync;
   wire [NUM_OF_CHANNELS*SAMPLES_PER_CHANNEL-1:0] out_valid;
@@ -99,8 +94,7 @@ module util_cpack2_impl #(
     .WORD_WIDTH (SAMPLE_DATA_WIDTH)
   ) i_interleave (
     .data_in (fifo_wr_data),
-    .data_out (interleaved_data)
-  );
+    .data_out (interleaved_data));
 
   pack_shell #(
     .NUM_OF_CHANNELS (NUM_OF_CHANNELS),
@@ -119,8 +113,7 @@ module util_cpack2_impl #(
     .in_data (interleaved_data),
     .out_data (out_data),
     .out_sync (out_sync),
-    .out_valid (out_valid)
-  );
+    .out_valid (out_valid));
 
   always @(posedge clk) begin
     if (reset_data == 1'b1) begin
@@ -135,7 +128,6 @@ module util_cpack2_impl #(
     end
   end
 
-
   always @(posedge clk) begin: gen_packed_fifo_wr_data
     integer i;
 
diff --git a/library/util_pack/util_pack_common/pack_ctrl.v b/library/util_pack/util_pack_common/pack_ctrl.v
index e5ca94e0a..1966bf9eb 100644
--- a/library/util_pack/util_pack_common/pack_ctrl.v
+++ b/library/util_pack/util_pack_common/pack_ctrl.v
@@ -65,19 +65,19 @@ module pack_ctrl #(
 
   localparam z = 2**MUX_ORDER;
 
-  /* This part is magic */
+  // This part is magic
   for (i = 0; i < NUM_STAGES; i = i + 1) begin: ctrl_gen_outer
     localparam k0 = 2**(PORT_ADDRESS_WIDTH - MUX_ORDER*(i+1)-MIN_STAGE);
     localparam k1 = 2**(MUX_ORDER*(1+i)+MIN_STAGE);
 
     for (j = 0; j < NUM_OF_PORTS; j = j + 1) begin: ctrl_gen_inner
-      /* Offset in the ctrl signal */
+      // Offset in the ctrl signal
       localparam s = (i*NUM_OF_PORTS+j)*MUX_ORDER;
       localparam m = (j % k1) * k0;
       localparam n = j / k1;
 
       if (MUX_ORDER == 1 && j % 2 == 0) begin
-        /* This is an optimization that only works for 2:1 MUXes */
+        // This is an optimization that only works for 2:1 MUXes
         assign ctrl1[s] = ~ctrl1[s+1];
       end else begin
         assign ctrl1[s+:MUX_ORDER] = (j - (prefix_count[m*PORT_ADDRESS_WIDTH+:PORT_ADDRESS_WIDTH] + n - rotate) / k0) % z;
@@ -86,7 +86,7 @@ module pack_ctrl #(
   end
 
   if (PACK == 0 || MUX_ORDER == 1) begin
-    /* For 2:1 MUXes pack and unpack control is the same */
+    // For 2:1 MUXes pack and unpack control is the same
     assign ctrl = ctrl1;
   end else begin
     /*
diff --git a/library/util_pack/util_pack_common/pack_interconnect.v b/library/util_pack/util_pack_common/pack_interconnect.v
index 350ab3421..d3ba07e12 100644
--- a/library/util_pack/util_pack_common/pack_interconnect.v
+++ b/library/util_pack/util_pack_common/pack_interconnect.v
@@ -72,28 +72,27 @@ module pack_interconnect #(
     localparam w = PORT_DATA_WIDTH;
     localparam NUM_SWITCHES = NUM_PORTS / z;
 
-    /* Do perfect shuffle, either in forward or reverse direction */
+    // Do perfect shuffle, either in forward or reverse direction
     for (i = 0; i < NUM_STAGES; i = i + 1) begin: gen_stages
-      /* Pack network are in the opposite direction */
+      // Pack network are in the opposite direction
       localparam ctrl_stage = PACK ? NUM_STAGES - i - 1 : i;
       wire [TOTAL_DATA_WIDTH-1:0] shuffle_in;
       wire [TOTAL_DATA_WIDTH-1:0] shuffle_out;
       wire [TOTAL_DATA_WIDTH-1:0] mux_in;
       wire [TOTAL_DATA_WIDTH-1:0] mux_out;
 
-      /* Unpack uses forward shuffle and pack a reverse shuffle */
+      // Unpack uses forward shuffle and pack a reverse shuffle
       ad_perfect_shuffle #(
         .NUM_GROUPS (PACK ? NUM_SWITCHES : z),
         .WORDS_PER_GROUP (PACK ? z : NUM_SWITCHES),
         .WORD_WIDTH (w)
       ) i_shuffle (
         .data_in (shuffle_in),
-        .data_out (shuffle_out)
-      );
+        .data_out (shuffle_out));
 
       for (j = 0; j < NUM_PORTS; j = j + 1) begin: gen_ports
         localparam ctrl_base = (ctrl_stage * NUM_PORTS + j) * MUX_ORDER;
-        localparam sel_base = j & ~(z-1); /* base increments in 2**MUX_ORDER steps */
+        localparam sel_base = j & ~(z-1); // base increments in 2**MUX_ORDER steps
 
         /*
          * To be able to better share MUX control signals and reduce overall
diff --git a/library/util_pack/util_pack_common/pack_network.v b/library/util_pack/util_pack_common/pack_network.v
index b6e53a828..20ff2d516 100644
--- a/library/util_pack/util_pack_common/pack_network.v
+++ b/library/util_pack/util_pack_common/pack_network.v
@@ -68,8 +68,7 @@ module pack_network #(
   ) i_ctrl (
     .rotate(rotate),
     .prefix_count(prefix_count),
-    .ctrl(ctrl_s)
-  );
+    .ctrl(ctrl_s));
 
   always @(posedge clk) begin
     if (ce_ctrl == 1'b1) begin
@@ -103,7 +102,6 @@ module pack_network #(
     .ctrl(ctrl_),
 
     .data_in(data_in),
-    .data_out(data_out)
-  );
+    .data_out(data_out));
 
 endmodule
diff --git a/library/util_pack/util_pack_common/pack_shell.v b/library/util_pack/util_pack_common/pack_shell.v
index c1396eecd..be48c6900 100644
--- a/library/util_pack/util_pack_common/pack_shell.v
+++ b/library/util_pack/util_pack_common/pack_shell.v
@@ -57,7 +57,8 @@ module pack_shell #(
   output out_sync,
   output [NUM_OF_CHANNELS*SAMPLES_PER_CHANNEL-1:0] out_valid
 );
-  /* If the number of active channels can be a non-power of two */
+
+  // If the number of active channels can be a non-power of two
   localparam NON_POWER_OF_TWO = NUM_OF_CHANNELS > 2;
 
   localparam CHANNEL_DATA_WIDTH = SAMPLES_PER_CHANNEL * SAMPLE_DATA_WIDTH;
@@ -251,7 +252,6 @@ module pack_shell #(
          */
         reg rotate_msb = 1'b0;
 
-
         /*
          * Extended version of the normal control and data signals that can
          * handle 2*NUM_OF_CHANNELS channels.
@@ -348,8 +348,7 @@ module pack_shell #(
           .prefix_count (ext_prefix_count),
 
           .data_in (ext_data_in),
-          .data_out (ext_data_out)
-        );
+          .data_out (ext_data_out));
 
         /*
          * In order to go from this stage that has 2 * NUM_OF_SAMPLES inputs
@@ -365,9 +364,8 @@ module pack_shell #(
           .WORDS_PER_GROUP (2),
           .WORD_WIDTH (2 * SAMPLE_DATA_WIDTH)
         ) i_ext_shuffle (
-           .data_in (ext_data_out),
-           .data_out (ext_data_shuffled)
-        );
+          .data_in (ext_data_out),
+          .data_out (ext_data_shuffled));
 
         assign ext_data_in = {data_d1,{2*CHANNEL_DATA_WIDTH{1'b0}},in_data};
         assign data[0] = ext_data_shuffled[0+:TOTAL_DATA_WIDTH];
@@ -427,8 +425,7 @@ module pack_shell #(
             .prefix_count (prefix_count),
 
             .data_in (data[i]),
-            .data_out (data[i+1])
-          );
+            .data_out (data[i+1]));
         end else begin
           assign data[i+1] = data[i];
         end
diff --git a/library/util_pack/util_upack2/util_upack2.v b/library/util_pack/util_upack2/util_upack2.v
index d2cee780b..e0523470a 100644
--- a/library/util_pack/util_upack2/util_upack2.v
+++ b/library/util_pack/util_upack2/util_upack2.v
@@ -177,126 +177,124 @@ module util_upack2 #(
   output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_62,
   output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_63,
 
-
   input s_axis_valid,
   output s_axis_ready,
   input [2**$clog2(NUM_OF_CHANNELS)*SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] s_axis_data
 );
 
-localparam CHANNEL_DATA_WIDTH = SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL;
-/*
- * Round up to the next power of two and zero out the additional channels
- * internally.
- */
-localparam REAL_NUM_OF_CHANNELS = NUM_OF_CHANNELS > 32 ? 64 :
-   NUM_OF_CHANNELS > 16 ? 32 :
-   NUM_OF_CHANNELS > 8 ? 16 :
-   NUM_OF_CHANNELS > 4 ? 8 :
-   NUM_OF_CHANNELS > 2 ? 4 :
-   NUM_OF_CHANNELS > 1 ? 2 : 1;
+  localparam CHANNEL_DATA_WIDTH = SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL;
+  /*
+   * Round up to the next power of two and zero out the additional channels
+   * internally.
+   */
+  localparam REAL_NUM_OF_CHANNELS = NUM_OF_CHANNELS > 32 ? 64 :
+     NUM_OF_CHANNELS > 16 ? 32 :
+     NUM_OF_CHANNELS > 8 ? 16 :
+     NUM_OF_CHANNELS > 4 ? 8 :
+     NUM_OF_CHANNELS > 2 ? 4 :
+     NUM_OF_CHANNELS > 1 ? 2 : 1;
 
-/* FIXME: Find out how to do this in the IP-XACT */
+  /* FIXME: Find out how to do this in the IP-XACT */
 
-wire [63:0] enable_s;
-wire [CHANNEL_DATA_WIDTH*REAL_NUM_OF_CHANNELS-1:0] fifo_rd_data;
-wire [CHANNEL_DATA_WIDTH*64-1:0] fifo_rd_data_s;
+  wire [63:0] enable_s;
+  wire [CHANNEL_DATA_WIDTH*REAL_NUM_OF_CHANNELS-1:0] fifo_rd_data;
+  wire [CHANNEL_DATA_WIDTH*64-1:0] fifo_rd_data_s;
 
-util_upack2_impl #(
-  .NUM_OF_CHANNELS(REAL_NUM_OF_CHANNELS),
-  .SAMPLE_DATA_WIDTH(SAMPLE_DATA_WIDTH),
-  .SAMPLES_PER_CHANNEL(SAMPLES_PER_CHANNEL)
-) i_upack (
-  .clk (clk),
-  .reset (reset),
+  util_upack2_impl #(
+    .NUM_OF_CHANNELS(REAL_NUM_OF_CHANNELS),
+    .SAMPLE_DATA_WIDTH(SAMPLE_DATA_WIDTH),
+    .SAMPLES_PER_CHANNEL(SAMPLES_PER_CHANNEL)
+  ) i_upack (
+    .clk (clk),
+    .reset (reset),
 
-  .enable (enable_s[REAL_NUM_OF_CHANNELS-1:0]),
+    .enable (enable_s[REAL_NUM_OF_CHANNELS-1:0]),
 
-  .fifo_rd_en ({REAL_NUM_OF_CHANNELS{fifo_rd_en}}),
-  .fifo_rd_valid (fifo_rd_valid),
-  .fifo_rd_underflow (fifo_rd_underflow),
-  .fifo_rd_data (fifo_rd_data),
+    .fifo_rd_en ({REAL_NUM_OF_CHANNELS{fifo_rd_en}}),
+    .fifo_rd_valid (fifo_rd_valid),
+    .fifo_rd_underflow (fifo_rd_underflow),
+    .fifo_rd_data (fifo_rd_data),
 
-  .s_axis_valid (s_axis_valid),
-  .s_axis_ready (s_axis_ready),
-  .s_axis_data (s_axis_data)
-);
+    .s_axis_valid (s_axis_valid),
+    .s_axis_ready (s_axis_ready),
+    .s_axis_data (s_axis_data));
 
-assign enable_s = {
-  enable_63,enable_62,enable_61,enable_60,enable_59,enable_58,enable_57,enable_56,
-  enable_55,enable_54,enable_53,enable_52,enable_51,enable_50,enable_49,enable_48,
-  enable_47,enable_46,enable_45,enable_44,enable_43,enable_42,enable_41,enable_40,
-  enable_39,enable_38,enable_37,enable_36,enable_35,enable_34,enable_33,enable_32,
-  enable_31,enable_30,enable_29,enable_28,enable_27,enable_26,enable_25,enable_24,
-  enable_23,enable_22,enable_21,enable_20,enable_19,enable_18,enable_17,enable_16,
-  enable_15,enable_14,enable_13,enable_12,enable_11,enable_10,enable_9,enable_8,
-  enable_7,enable_6,enable_5,enable_4,enable_3,enable_2,enable_1,enable_0
-};
+  assign enable_s = {
+    enable_63,enable_62,enable_61,enable_60,enable_59,enable_58,enable_57,enable_56,
+    enable_55,enable_54,enable_53,enable_52,enable_51,enable_50,enable_49,enable_48,
+    enable_47,enable_46,enable_45,enable_44,enable_43,enable_42,enable_41,enable_40,
+    enable_39,enable_38,enable_37,enable_36,enable_35,enable_34,enable_33,enable_32,
+    enable_31,enable_30,enable_29,enable_28,enable_27,enable_26,enable_25,enable_24,
+    enable_23,enable_22,enable_21,enable_20,enable_19,enable_18,enable_17,enable_16,
+    enable_15,enable_14,enable_13,enable_12,enable_11,enable_10,enable_9,enable_8,
+    enable_7,enable_6,enable_5,enable_4,enable_3,enable_2,enable_1,enable_0
+  };
 
-assign fifo_rd_data_s = {{(64-NUM_OF_CHANNELS)*CHANNEL_DATA_WIDTH{1'b0}},fifo_rd_data};
+  assign fifo_rd_data_s = {{(64-NUM_OF_CHANNELS)*CHANNEL_DATA_WIDTH{1'b0}},fifo_rd_data};
 
-assign fifo_rd_data_0 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*0+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_1 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*1+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_2 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*2+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_3 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*3+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_4 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*4+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_5 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*5+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_6 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*6+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_7 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*7+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_8 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*8+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_9 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*9+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_10 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*10+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_11 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*11+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_12 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*12+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_13 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*13+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_14 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*14+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_15 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*15+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_16 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*16+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_17 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*17+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_18 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*18+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_19 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*19+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_20 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*20+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_21 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*21+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_22 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*22+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_23 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*23+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_24 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*24+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_25 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*25+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_26 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*26+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_27 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*27+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_28 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*28+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_29 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*29+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_30 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*30+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_31 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*31+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_32 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*32+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_33 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*33+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_34 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*34+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_35 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*35+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_36 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*36+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_37 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*37+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_38 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*38+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_39 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*39+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_40 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*40+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_41 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*41+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_42 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*42+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_43 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*43+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_44 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*44+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_45 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*45+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_46 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*46+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_47 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*47+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_48 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*48+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_49 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*49+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_50 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*50+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_51 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*51+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_52 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*52+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_53 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*53+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_54 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*54+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_55 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*55+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_56 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*56+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_57 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*57+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_58 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*58+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_59 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*59+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_60 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*60+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_61 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*61+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_62 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*62+:CHANNEL_DATA_WIDTH];
-assign fifo_rd_data_63 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*63+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_0 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*0+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_1 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*1+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_2 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*2+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_3 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*3+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_4 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*4+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_5 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*5+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_6 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*6+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_7 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*7+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_8 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*8+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_9 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*9+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_10 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*10+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_11 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*11+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_12 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*12+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_13 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*13+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_14 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*14+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_15 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*15+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_16 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*16+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_17 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*17+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_18 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*18+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_19 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*19+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_20 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*20+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_21 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*21+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_22 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*22+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_23 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*23+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_24 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*24+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_25 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*25+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_26 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*26+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_27 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*27+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_28 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*28+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_29 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*29+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_30 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*30+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_31 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*31+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_32 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*32+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_33 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*33+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_34 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*34+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_35 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*35+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_36 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*36+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_37 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*37+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_38 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*38+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_39 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*39+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_40 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*40+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_41 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*41+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_42 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*42+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_43 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*43+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_44 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*44+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_45 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*45+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_46 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*46+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_47 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*47+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_48 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*48+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_49 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*49+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_50 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*50+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_51 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*51+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_52 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*52+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_53 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*53+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_54 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*54+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_55 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*55+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_56 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*56+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_57 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*57+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_58 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*58+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_59 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*59+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_60 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*60+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_61 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*61+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_62 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*62+:CHANNEL_DATA_WIDTH];
+  assign fifo_rd_data_63 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*63+:CHANNEL_DATA_WIDTH];
 
 endmodule
diff --git a/library/util_pack/util_upack2/util_upack2_impl.v b/library/util_pack/util_upack2/util_upack2_impl.v
index 6ab584e4c..836426067 100644
--- a/library/util_pack/util_upack2/util_upack2_impl.v
+++ b/library/util_pack/util_upack2/util_upack2_impl.v
@@ -106,8 +106,7 @@ module util_upack2_impl #(
     .out_data (out_data),
 
     .out_valid (),
-    .out_sync ()
-  );
+    .out_sync ());
 
   /*
    * Data at the output of the routing network is interleaved. The upack
@@ -120,8 +119,7 @@ module util_upack2_impl #(
     .WORD_WIDTH (SAMPLE_DATA_WIDTH)
   ) i_deinterleave (
     .data_in (out_data),
-    .data_out (deinterleaved_data)
-  );
+    .data_out (deinterleaved_data));
 
   always @(posedge clk) begin
     /* In case of an underflow the output vector should be zeroed */
diff --git a/library/util_pad/util_pad.v b/library/util_pad/util_pad.v
index 84caf244b..5c48781d0 100644
--- a/library/util_pad/util_pad.v
+++ b/library/util_pad/util_pad.v
@@ -34,38 +34,38 @@ module util_pad #(
   output reg [NUM_OF_SAMPLES*OUT_BITS_PER_SAMPLE-1:0] data_out
 );
 
-// Remove padding
-if (IN_BITS_PER_SAMPLE >= OUT_BITS_PER_SAMPLE) begin
-  integer i;
-  always @(*) begin
-    for (i=0;i<NUM_OF_SAMPLES;i=i+1) begin
-      if (PADDING_TO_MSB_LSB_N==1) begin
-        data_out[i*OUT_BITS_PER_SAMPLE +: OUT_BITS_PER_SAMPLE] =
-          data_in[i*IN_BITS_PER_SAMPLE +: OUT_BITS_PER_SAMPLE];
-      end else begin
-        data_out[i*OUT_BITS_PER_SAMPLE +: OUT_BITS_PER_SAMPLE] =
-          data_in[((i+1)*IN_BITS_PER_SAMPLE)-1 -: OUT_BITS_PER_SAMPLE];
+  // Remove padding
+  if (IN_BITS_PER_SAMPLE >= OUT_BITS_PER_SAMPLE) begin
+    integer i;
+    always @(*) begin
+      for (i=0;i<NUM_OF_SAMPLES;i=i+1) begin
+        if (PADDING_TO_MSB_LSB_N==1) begin
+          data_out[i*OUT_BITS_PER_SAMPLE +: OUT_BITS_PER_SAMPLE] =
+            data_in[i*IN_BITS_PER_SAMPLE +: OUT_BITS_PER_SAMPLE];
+        end else begin
+          data_out[i*OUT_BITS_PER_SAMPLE +: OUT_BITS_PER_SAMPLE] =
+            data_in[((i+1)*IN_BITS_PER_SAMPLE)-1 -: OUT_BITS_PER_SAMPLE];
+        end
       end
     end
   end
-end
 
-// Add padding
-if (IN_BITS_PER_SAMPLE < OUT_BITS_PER_SAMPLE) begin
-  integer i;
-  always @(*) begin
-    for (i=0;i<NUM_OF_SAMPLES;i=i+1) begin
-      if (PADDING_TO_MSB_LSB_N==1) begin
-        data_out[i*OUT_BITS_PER_SAMPLE +: OUT_BITS_PER_SAMPLE] =
-          {{OUT_BITS_PER_SAMPLE-IN_BITS_PER_SAMPLE{data_in[(i+1)*IN_BITS_PER_SAMPLE-1]&SIGN_EXTEND[0]}},
-          data_in[i*IN_BITS_PER_SAMPLE +: OUT_BITS_PER_SAMPLE]};
-      end else begin
-        data_out[i*OUT_BITS_PER_SAMPLE +: OUT_BITS_PER_SAMPLE] =
-          {data_in[((i+1)*IN_BITS_PER_SAMPLE)-1 -: OUT_BITS_PER_SAMPLE],
-          {OUT_BITS_PER_SAMPLE-IN_BITS_PER_SAMPLE{1'b0}}};
+  // Add padding
+  if (IN_BITS_PER_SAMPLE < OUT_BITS_PER_SAMPLE) begin
+    integer i;
+    always @(*) begin
+      for (i=0;i<NUM_OF_SAMPLES;i=i+1) begin
+        if (PADDING_TO_MSB_LSB_N==1) begin
+          data_out[i*OUT_BITS_PER_SAMPLE +: OUT_BITS_PER_SAMPLE] =
+            {{OUT_BITS_PER_SAMPLE-IN_BITS_PER_SAMPLE{data_in[(i+1)*IN_BITS_PER_SAMPLE-1]&SIGN_EXTEND[0]}},
+            data_in[i*IN_BITS_PER_SAMPLE +: OUT_BITS_PER_SAMPLE]};
+        end else begin
+          data_out[i*OUT_BITS_PER_SAMPLE +: OUT_BITS_PER_SAMPLE] =
+            {data_in[((i+1)*IN_BITS_PER_SAMPLE)-1 -: OUT_BITS_PER_SAMPLE],
+            {OUT_BITS_PER_SAMPLE-IN_BITS_PER_SAMPLE{1'b0}}};
+        end
       end
     end
   end
-end
 
 endmodule
diff --git a/library/util_rfifo/util_rfifo.v b/library/util_rfifo/util_rfifo.v
index dd1ff888d..4fa0ed3c8 100644
--- a/library/util_rfifo/util_rfifo.v
+++ b/library/util_rfifo/util_rfifo.v
@@ -40,7 +40,8 @@ module util_rfifo #(
   parameter   NUM_OF_CHANNELS = 4,
   parameter   DIN_DATA_WIDTH = 32,
   parameter   DOUT_DATA_WIDTH = 64,
-  parameter   DIN_ADDRESS_WIDTH = 8) (
+  parameter   DIN_ADDRESS_WIDTH = 8
+) (
 
   // d-in interface
 
@@ -116,8 +117,8 @@ module util_rfifo #(
   input                                   dout_valid_7,
   output                                  dout_valid_out_7,
   output      [DOUT_DATA_WIDTH-1:0]       dout_data_7,
-  output  reg                             dout_unf);
-
+  output  reg                             dout_unf
+);
 
   localparam  M_MEM_RATIO = DOUT_DATA_WIDTH/DIN_DATA_WIDTH;
   localparam  ADDRESS_WIDTH = (DIN_ADDRESS_WIDTH > 5) ? DIN_ADDRESS_WIDTH : 5;
@@ -162,7 +163,6 @@ module util_rfifo #(
 
   // variables
 
-
   // enables & valids
 
   assign din_enable_7 = din_enable[7];
@@ -389,7 +389,10 @@ module util_rfifo #(
 
   // instantiations
 
-  ad_mem #(.ADDRESS_WIDTH(ADDRESS_WIDTH), .DATA_WIDTH(DATA_WIDTH)) i_mem (
+  ad_mem #(
+    .ADDRESS_WIDTH(ADDRESS_WIDTH),
+    .DATA_WIDTH(DATA_WIDTH)
+  ) i_mem (
     .clka (din_clk),
     .wea (din_wr),
     .addra (din_waddr),
@@ -400,6 +403,3 @@ module util_rfifo #(
     .doutb (dout_rdata_s));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/util_sigma_delta_spi/util_sigma_delta_spi.v b/library/util_sigma_delta_spi/util_sigma_delta_spi.v
index e4dac4886..d0454163b 100644
--- a/library/util_sigma_delta_spi/util_sigma_delta_spi.v
+++ b/library/util_sigma_delta_spi/util_sigma_delta_spi.v
@@ -39,8 +39,8 @@ module util_sigma_delta_spi #(
 
   parameter NUM_OF_CS = 1,
   parameter CS_PIN = 0,
-  parameter IDLE_TIMEOUT = 63 ) (
-
+  parameter IDLE_TIMEOUT = 63
+) (
   input clk,
   input resetn,
 
@@ -58,53 +58,54 @@ module util_sigma_delta_spi #(
   input m_sdi,
   output [NUM_OF_CS-1:0] m_cs,
 
-  output reg data_ready);
+  output reg data_ready
+);
 
-/*
- * For converters from the ADI SigmaDelta family the data ready interrupt signal
- * uses the same physical wire as the the DOUT signal for the SPI bus. This
- * module extracts the data ready signal from the SPI bus and makes sure to
- * suppress false positives. The data ready signal is indicated by the converter
- * by pulling DOUT low. This will only happen if the CS pin for the converter is
- * low and no SPI transfer is active. There is a small delay between the end of
- * the SPI transfer and the point where the converter starts to indicate the
- * data ready signal. IDLE_TIMEOUT allows to specify the amount of clock cycles
- * the bus needs to be idle before the data ready signal is detected.
- */
+ /*
+  * For converters from the ADI SigmaDelta family the data ready interrupt signal
+  * uses the same physical wire as the the DOUT signal for the SPI bus. This
+  * module extracts the data ready signal from the SPI bus and makes sure to
+  * suppress false positives. The data ready signal is indicated by the converter
+  * by pulling DOUT low. This will only happen if the CS pin for the converter is
+  * low and no SPI transfer is active. There is a small delay between the end of
+  * the SPI transfer and the point where the converter starts to indicate the
+  * data ready signal. IDLE_TIMEOUT allows to specify the amount of clock cycles
+  * the bus needs to be idle before the data ready signal is detected.
+  */
 
-assign m_sclk = s_sclk;
-assign m_sdo = s_sdo;
-assign m_sdo_t = s_sdo_t;
-assign s_sdi = m_sdi;
-assign m_cs = s_cs;
+  assign m_sclk = s_sclk;
+  assign m_sdo = s_sdo;
+  assign m_sdo_t = s_sdo_t;
+  assign s_sdi = m_sdi;
+  assign m_cs = s_cs;
 
-reg [$clog2(IDLE_TIMEOUT)-1:0] counter = IDLE_TIMEOUT;
-reg [2:0] sdi_d = 'h00;
+  reg [$clog2(IDLE_TIMEOUT)-1:0] counter = IDLE_TIMEOUT;
+  reg [2:0] sdi_d = 'h00;
 
-always @(posedge clk) begin
-  if (resetn == 1'b0) begin
-    counter <= IDLE_TIMEOUT;
-  end else begin
-    if (s_cs[CS_PIN] == 1'b0 && spi_active == 1'b0) begin
-      if (counter != 'h00)
-        counter <= counter - 1'b1;
-    end else begin
+  always @(posedge clk) begin
+    if (resetn == 1'b0) begin
       counter <= IDLE_TIMEOUT;
+    end else begin
+      if (s_cs[CS_PIN] == 1'b0 && spi_active == 1'b0) begin
+        if (counter != 'h00)
+          counter <= counter - 1'b1;
+      end else begin
+        counter <= IDLE_TIMEOUT;
+      end
     end
   end
-end
 
-always @(posedge clk) begin
-  /* The data ready signal is fully asynchronous */
-  sdi_d <= {sdi_d[1:0], m_sdi};
-end
-
-always @(posedge clk) begin
-  if (counter == 'h00 && sdi_d[2] == 1'b0) begin
-    data_ready <= 1'b1;
-  end else begin
-    data_ready <= 1'b0;
+  always @(posedge clk) begin
+    /* The data ready signal is fully asynchronous */
+    sdi_d <= {sdi_d[1:0], m_sdi};
+  end
+
+  always @(posedge clk) begin
+    if (counter == 'h00 && sdi_d[2] == 1'b0) begin
+      data_ready <= 1'b1;
+    end else begin
+      data_ready <= 1'b0;
+    end
   end
-end
 
 endmodule
diff --git a/library/util_tdd_sync/util_tdd_sync.v b/library/util_tdd_sync/util_tdd_sync.v
index 874bd5269..fc708872c 100644
--- a/library/util_tdd_sync/util_tdd_sync.v
+++ b/library/util_tdd_sync/util_tdd_sync.v
@@ -43,15 +43,16 @@
 
 module util_tdd_sync #(
 
-  parameter     TDD_SYNC_PERIOD = 100000000) (
+  parameter     TDD_SYNC_PERIOD = 100000000
+) (
   input                   clk,
   input                   rstn,
 
   input                   sync_mode,
 
   input                   sync_in,
-  output  reg             sync_out);
-
+  output  reg             sync_out
+);
 
   reg           sync_mode_d1 = 1'b0;
   reg           sync_mode_d2 = 1'b0;
@@ -63,15 +64,13 @@ module util_tdd_sync #(
 
   util_pulse_gen #(
     .PULSE_PERIOD(TDD_SYNC_PERIOD)
-  )
-    i_tdd_sync (
+  ) i_tdd_sync (
     .clk (clk),
     .rstn (rstn),
     .pulse_width (32'd0),
     .pulse_period (32'd0),
     .load_config (1'd0),
-    .pulse (sync_internal)
-  );
+    .pulse (sync_internal));
 
   // synchronization logic
 
@@ -97,4 +96,3 @@ module util_tdd_sync #(
   end
 
 endmodule
-
diff --git a/library/util_var_fifo/util_var_fifo.v b/library/util_var_fifo/util_var_fifo.v
index 3e5c90291..57d00506b 100644
--- a/library/util_var_fifo/util_var_fifo.v
+++ b/library/util_var_fifo/util_var_fifo.v
@@ -40,8 +40,8 @@ module util_var_fifo #(
   // parameters
 
   parameter DATA_WIDTH = 32,
-  parameter ADDRESS_WIDTH =  13) (
-
+  parameter ADDRESS_WIDTH =  13
+) (
   input                       clk,
   input                       rst,
 
@@ -59,11 +59,11 @@ module util_var_fifo #(
   output  [DATA_WIDTH-1:0]    din_w,
   output                      en_r,
   output  [ADDRESS_WIDTH-1:0] addr_r,
-  input   [DATA_WIDTH-1:0]    dout_r);
+  input   [DATA_WIDTH-1:0]    dout_r
+);
 
   localparam      MAX_DEPTH = (2 ** ADDRESS_WIDTH) - 1;
 
-
   // internal registers
 
   reg [ADDRESS_WIDTH-1:0]    addra = 'd0;
@@ -168,6 +168,3 @@ module util_var_fifo #(
   end
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/util_wfifo/util_wfifo.v b/library/util_wfifo/util_wfifo.v
index ecf222850..c74f0584f 100644
--- a/library/util_wfifo/util_wfifo.v
+++ b/library/util_wfifo/util_wfifo.v
@@ -40,7 +40,8 @@ module util_wfifo #(
   parameter   NUM_OF_CHANNELS = 4,
   parameter   DIN_DATA_WIDTH = 32,
   parameter   DOUT_DATA_WIDTH = 64,
-  parameter   DIN_ADDRESS_WIDTH = 8) (
+  parameter   DIN_ADDRESS_WIDTH = 8
+) (
 
   // d-in interface
 
@@ -100,8 +101,8 @@ module util_wfifo #(
   output                  dout_enable_7,
   output                  dout_valid_7,
   output      [DOUT_DATA_WIDTH-1:0]  dout_data_7,
-  input                   dout_ovf);
-
+  input                   dout_ovf
+);
 
   localparam  M_MEM_RATIO = DOUT_DATA_WIDTH/DIN_DATA_WIDTH;
   localparam  ADDRESS_WIDTH = (DIN_ADDRESS_WIDTH > 4) ? DIN_ADDRESS_WIDTH : 4;
@@ -208,7 +209,7 @@ module util_wfifo #(
       din_ovf <= 'd0;
     end else begin
       din_enable <= din_enable_s;
-     case (M_MEM_RATIO)
+      case (M_MEM_RATIO)
         8: din_wr <= din_valid_s[0] & din_dcnt_s[0] & din_dcnt_s[1] & din_dcnt_s[2];
         4: din_wr <= din_valid_s[0] & din_dcnt_s[0] & din_dcnt_s[1];
         2: din_wr <= din_valid_s[0] & din_dcnt_s[0];
@@ -326,7 +327,10 @@ module util_wfifo #(
 
   // instantiations
 
-  ad_mem #(.ADDRESS_WIDTH(ADDRESS_WIDTH), .DATA_WIDTH(DATA_WIDTH)) i_mem (
+  ad_mem #(
+    .ADDRESS_WIDTH(ADDRESS_WIDTH),
+    .DATA_WIDTH(DATA_WIDTH)
+  ) i_mem (
     .clka (din_clk),
     .wea (din_wr),
     .addra (din_waddr),
@@ -337,6 +341,3 @@ module util_wfifo #(
     .doutb (dout_rdata_s));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/xilinx/axi_adcfifo/axi_adcfifo.v b/library/xilinx/axi_adcfifo/axi_adcfifo.v
index 1e9f9a1e5..e6a858eb1 100644
--- a/library/xilinx/axi_adcfifo/axi_adcfifo.v
+++ b/library/xilinx/axi_adcfifo/axi_adcfifo.v
@@ -44,7 +44,8 @@ module axi_adcfifo #(
   parameter   AXI_SIZE = 2,
   parameter   AXI_LENGTH = 16,
   parameter   AXI_ADDRESS = 32'h00000000,
-  parameter   AXI_ADDRESS_LIMIT = 32'hffffffff) (
+  parameter   AXI_ADDRESS_LIMIT = 32'hffffffff
+) (
 
   // fifo interface
 
@@ -108,8 +109,8 @@ module axi_adcfifo #(
   input       [ 1:0]      axi_rresp,
   input                   axi_rlast,
   input       [AXI_DATA_WIDTH-1:0]  axi_rdata,
-  output                  axi_rready);
-
+  output                  axi_rready
+);
 
   // internal signals
 
@@ -127,8 +128,8 @@ module axi_adcfifo #(
 
   axi_adcfifo_adc #(
     .AXI_DATA_WIDTH (AXI_DATA_WIDTH),
-    .ADC_DATA_WIDTH (ADC_DATA_WIDTH))
-  i_adc_if (
+    .ADC_DATA_WIDTH (ADC_DATA_WIDTH)
+  ) i_adc_if (
     .adc_rst (adc_rst),
     .adc_clk (adc_clk),
     .adc_wr (adc_wr),
@@ -145,8 +146,8 @@ module axi_adcfifo #(
     .AXI_SIZE (AXI_SIZE),
     .AXI_LENGTH (AXI_LENGTH),
     .AXI_ADDRESS (AXI_ADDRESS),
-    .AXI_ADDRESS_LIMIT (AXI_ADDRESS_LIMIT))
-  i_wr (
+    .AXI_ADDRESS_LIMIT (AXI_ADDRESS_LIMIT)
+  ) i_wr (
     .dma_xfer_req (dma_xfer_req),
     .axi_rd_req (axi_rd_req_s),
     .axi_rd_addr (axi_rd_addr_s),
@@ -188,8 +189,8 @@ module axi_adcfifo #(
     .AXI_SIZE (AXI_SIZE),
     .AXI_LENGTH (AXI_LENGTH),
     .AXI_ADDRESS (AXI_ADDRESS),
-    .AXI_ADDRESS_LIMIT (AXI_ADDRESS_LIMIT))
-  i_rd (
+    .AXI_ADDRESS_LIMIT (AXI_ADDRESS_LIMIT)
+  ) i_rd (
     .dma_xfer_req (dma_xfer_req),
     .axi_rd_req (axi_rd_req_s),
     .axi_rd_addr (axi_rd_addr_s),
@@ -223,8 +224,8 @@ module axi_adcfifo #(
   axi_adcfifo_dma #(
     .AXI_DATA_WIDTH (AXI_DATA_WIDTH),
     .DMA_DATA_WIDTH (DMA_DATA_WIDTH),
-    .DMA_READY_ENABLE (DMA_READY_ENABLE))
-  i_dma_if (
+    .DMA_READY_ENABLE (DMA_READY_ENABLE)
+  ) i_dma_if (
     .axi_clk (axi_clk),
     .axi_drst (axi_drst_s),
     .axi_dvalid (axi_dvalid_s),
@@ -239,6 +240,3 @@ module axi_adcfifo #(
     .dma_xfer_status (dma_xfer_status));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/xilinx/axi_adcfifo/axi_adcfifo_adc.v b/library/xilinx/axi_adcfifo/axi_adcfifo_adc.v
index e1fa517a0..a5191f664 100644
--- a/library/xilinx/axi_adcfifo/axi_adcfifo_adc.v
+++ b/library/xilinx/axi_adcfifo/axi_adcfifo_adc.v
@@ -38,7 +38,8 @@
 module axi_adcfifo_adc #(
 
   parameter   ADC_DATA_WIDTH = 128,
-  parameter   AXI_DATA_WIDTH = 512) (
+  parameter   AXI_DATA_WIDTH = 512
+) (
 
   // fifo interface
 
@@ -54,7 +55,8 @@ module axi_adcfifo_adc #(
 
   input                   axi_drst,
   input                   axi_clk,
-  input       [ 3:0]      axi_xfer_status);
+  input       [ 3:0]      axi_xfer_status
+);
 
   localparam  ADC_MEM_RATIO = AXI_DATA_WIDTH/ADC_DATA_WIDTH;
 
@@ -111,7 +113,9 @@ module axi_adcfifo_adc #(
 
   // instantiations
 
-  up_xfer_status #(.DATA_WIDTH(4)) i_xfer_status (
+  up_xfer_status #(
+    .DATA_WIDTH(4)
+  ) i_xfer_status (
     .up_rstn (~adc_rst),
     .up_clk (adc_clk),
     .up_data_status (adc_xfer_status_s),
@@ -120,6 +124,3 @@ module axi_adcfifo_adc #(
     .d_data_status (axi_xfer_status));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/xilinx/axi_adcfifo/axi_adcfifo_dma.v b/library/xilinx/axi_adcfifo/axi_adcfifo_dma.v
index 998722a1a..101023f64 100644
--- a/library/xilinx/axi_adcfifo/axi_adcfifo_dma.v
+++ b/library/xilinx/axi_adcfifo/axi_adcfifo_dma.v
@@ -39,8 +39,8 @@ module axi_adcfifo_dma #(
 
   parameter   AXI_DATA_WIDTH = 512,
   parameter   DMA_DATA_WIDTH =  64,
-  parameter   DMA_READY_ENABLE = 1) (
-
+  parameter   DMA_READY_ENABLE = 1
+) (
   input                   axi_clk,
   input                   axi_drst,
   input                   axi_dvalid,
@@ -53,15 +53,14 @@ module axi_adcfifo_dma #(
   output      [DMA_DATA_WIDTH-1:0]  dma_wdata,
   input                   dma_wready,
   input                   dma_xfer_req,
-  output      [ 3:0]      dma_xfer_status);
-
+  output      [ 3:0]      dma_xfer_status
+);
 
   localparam  DMA_MEM_RATIO = AXI_DATA_WIDTH/DMA_DATA_WIDTH;
   localparam  DMA_ADDRESS_WIDTH = 8;
   localparam  AXI_ADDRESS_WIDTH = (DMA_MEM_RATIO == 2) ? (DMA_ADDRESS_WIDTH - 1) :
     ((DMA_MEM_RATIO == 4) ? (DMA_ADDRESS_WIDTH - 2) : (DMA_ADDRESS_WIDTH - 3));
 
-
   // internal registers
 
   reg     [AXI_ADDRESS_WIDTH-1:0]    axi_waddr = 'd0;
@@ -191,8 +190,8 @@ module axi_adcfifo_dma #(
     .A_ADDRESS_WIDTH (AXI_ADDRESS_WIDTH),
     .A_DATA_WIDTH (AXI_DATA_WIDTH),
     .B_ADDRESS_WIDTH (DMA_ADDRESS_WIDTH),
-    .B_DATA_WIDTH (DMA_DATA_WIDTH))
-  i_mem_asym (
+    .B_DATA_WIDTH (DMA_DATA_WIDTH)
+  ) i_mem_asym (
     .clka (axi_clk),
     .wea (axi_dvalid),
     .addra (axi_waddr),
@@ -202,7 +201,9 @@ module axi_adcfifo_dma #(
     .addrb (dma_raddr),
     .doutb (dma_rdata_s));
 
-  ad_axis_inf_rx #(.DATA_WIDTH(DMA_DATA_WIDTH)) i_axis_inf (
+  ad_axis_inf_rx #(
+    .DATA_WIDTH(DMA_DATA_WIDTH)
+  ) i_axis_inf (
     .clk (dma_clk),
     .rst (dma_rst),
     .valid (dma_rd_d),
@@ -213,7 +214,9 @@ module axi_adcfifo_dma #(
     .inf_data (dma_wdata),
     .inf_ready (dma_wready));
 
-  up_xfer_status #(.DATA_WIDTH(4)) i_xfer_status (
+  up_xfer_status #(
+    .DATA_WIDTH(4)
+  ) i_xfer_status (
     .up_rstn (~dma_rst),
     .up_clk (dma_clk),
     .up_data_status (dma_xfer_status),
@@ -222,6 +225,3 @@ module axi_adcfifo_dma #(
     .d_data_status (axi_xfer_status));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/xilinx/axi_adcfifo/axi_adcfifo_rd.v b/library/xilinx/axi_adcfifo/axi_adcfifo_rd.v
index 21ba7df20..7aa23b24e 100644
--- a/library/xilinx/axi_adcfifo/axi_adcfifo_rd.v
+++ b/library/xilinx/axi_adcfifo/axi_adcfifo_rd.v
@@ -41,7 +41,8 @@ module axi_adcfifo_rd #(
   parameter   AXI_SIZE = 2,
   parameter   AXI_LENGTH = 16,
   parameter   AXI_ADDRESS = 32'h00000000,
-  parameter   AXI_ADDRESS_LIMIT = 32'h00000000) (
+  parameter   AXI_ADDRESS_LIMIT = 32'h00000000
+) (
 
   // request and synchronization
 
@@ -85,7 +86,8 @@ module axi_adcfifo_rd #(
   output  reg             axi_drst,
   output  reg             axi_dvalid,
   output  reg [AXI_DATA_WIDTH-1:0]  axi_ddata,
-  input                   axi_dready);
+  input                   axi_dready
+);
 
   localparam  AXI_BYTE_WIDTH = AXI_DATA_WIDTH/8;
   localparam  AXI_AWINCR = AXI_LENGTH * AXI_BYTE_WIDTH;
@@ -197,6 +199,3 @@ module axi_adcfifo_rd #(
   end
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/xilinx/axi_adcfifo/axi_adcfifo_wr.v b/library/xilinx/axi_adcfifo/axi_adcfifo_wr.v
index a0a5d9663..01695f935 100644
--- a/library/xilinx/axi_adcfifo/axi_adcfifo_wr.v
+++ b/library/xilinx/axi_adcfifo/axi_adcfifo_wr.v
@@ -41,7 +41,8 @@ module axi_adcfifo_wr #(
   parameter   AXI_SIZE = 2,
   parameter   AXI_LENGTH = 16,
   parameter   AXI_ADDRESS = 32'h00000000,
-  parameter   AXI_ADDRESS_LIMIT = 32'h00000000) (
+  parameter   AXI_ADDRESS_LIMIT = 32'h00000000
+) (
 
   // request and synchronization
 
@@ -91,7 +92,8 @@ module axi_adcfifo_wr #(
 
   output  reg             axi_dwovf,
   output  reg             axi_dwunf,
-  output  reg             axi_werror);
+  output  reg             axi_werror
+);
 
   localparam  AXI_BYTE_WIDTH = AXI_DATA_WIDTH/8;
   localparam  AXI_AWINCR = AXI_LENGTH * AXI_BYTE_WIDTH;
@@ -389,7 +391,9 @@ module axi_adcfifo_wr #(
 
   // interface handler
 
-  ad_axis_inf_rx #(.DATA_WIDTH(AXI_DATA_WIDTH)) i_axis_inf (
+  ad_axis_inf_rx #(
+    .DATA_WIDTH(AXI_DATA_WIDTH)
+  ) i_axis_inf (
     .clk (axi_clk),
     .rst (axi_reset),
     .valid (axi_rd_d),
@@ -402,7 +406,10 @@ module axi_adcfifo_wr #(
 
   // buffer
 
-  ad_mem #(.DATA_WIDTH(AXI_DATA_WIDTH), .ADDRESS_WIDTH(8)) i_mem (
+  ad_mem #(
+    .DATA_WIDTH(AXI_DATA_WIDTH),
+    .ADDRESS_WIDTH(8)
+  ) i_mem (
     .clka (adc_clk),
     .wea (adc_wr),
     .addra (adc_waddr),
@@ -413,6 +420,3 @@ module axi_adcfifo_wr #(
     .doutb (axi_rdata_s));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/xilinx/axi_adxcvr/axi_adxcvr.v b/library/xilinx/axi_adxcvr/axi_adxcvr.v
index dff1a1c20..0e9914cf8 100644
--- a/library/xilinx/axi_adxcvr/axi_adxcvr.v
+++ b/library/xilinx/axi_adxcvr/axi_adxcvr.v
@@ -57,8 +57,8 @@ module axi_adxcvr #(
   parameter   [ 4:0]  TX_POSTCURSOR = 5'd0,
   parameter   [ 4:0]  TX_PRECURSOR = 5'd0,
   parameter   [ 1:0]  SYS_CLK_SEL = 2'd3,
-  parameter   [ 2:0]  OUT_CLK_SEL = 3'd4) (
-
+  parameter   [ 2:0]  OUT_CLK_SEL = 3'd4
+) (
   output          up_cm_enb_0,
   output  [11:0]  up_cm_addr_0,
   output          up_cm_wr_0,
@@ -658,7 +658,8 @@ module axi_adxcvr #(
   input           m_axi_rvalid,
   input   [31:0]  m_axi_rdata,
   input   [ 1:0]  m_axi_rresp,
-  output          m_axi_rready);
+  output          m_axi_rready
+);
 
   // internal signals
 
@@ -894,8 +895,8 @@ module axi_adxcvr #(
 
   axi_adxcvr_mdrp #(
     .XCVR_ID (0),
-    .NUM_OF_LANES (NUM_OF_LANES))
-  i_mdrp_cm_0 (
+    .NUM_OF_LANES (NUM_OF_LANES)
+  ) i_mdrp_cm_0 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_cm_sel),
@@ -914,8 +915,8 @@ module axi_adxcvr #(
 
   axi_adxcvr_mdrp #(
     .XCVR_ID (0),
-    .NUM_OF_LANES (NUM_OF_LANES))
-  i_mdrp_es_0 (
+    .NUM_OF_LANES (NUM_OF_LANES)
+  ) i_mdrp_es_0 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_es_sel),
@@ -944,8 +945,8 @@ module axi_adxcvr #(
 
   axi_adxcvr_mstatus #(
     .XCVR_ID (0),
-    .NUM_OF_LANES (NUM_OF_LANES))
-  i_mstatus_ch_0 (
+    .NUM_OF_LANES (NUM_OF_LANES)
+  ) i_mstatus_ch_0 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_pll_locked_in (1'd1),
@@ -970,8 +971,8 @@ module axi_adxcvr #(
 
   axi_adxcvr_mdrp #(
     .XCVR_ID (0),
-    .NUM_OF_LANES (NUM_OF_LANES))
-  i_mdrp_ch_0 (
+    .NUM_OF_LANES (NUM_OF_LANES)
+  ) i_mdrp_ch_0 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_ch_sel),
@@ -990,8 +991,8 @@ module axi_adxcvr #(
 
   axi_adxcvr_mdrp #(
     .XCVR_ID (1),
-    .NUM_OF_LANES (NUM_OF_LANES))
-  i_mdrp_es_1 (
+    .NUM_OF_LANES (NUM_OF_LANES)
+  ) i_mdrp_es_1 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_es_sel),
@@ -1020,8 +1021,8 @@ module axi_adxcvr #(
 
   axi_adxcvr_mstatus #(
     .XCVR_ID (1),
-    .NUM_OF_LANES (NUM_OF_LANES))
-  i_mstatus_ch_1 (
+    .NUM_OF_LANES (NUM_OF_LANES)
+  ) i_mstatus_ch_1 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_pll_locked_in (up_ch_pll_locked_0_s),
@@ -1046,8 +1047,8 @@ module axi_adxcvr #(
 
   axi_adxcvr_mdrp #(
     .XCVR_ID (1),
-    .NUM_OF_LANES (NUM_OF_LANES))
-  i_mdrp_ch_1 (
+    .NUM_OF_LANES (NUM_OF_LANES)
+  ) i_mdrp_ch_1 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_ch_sel),
@@ -1066,8 +1067,8 @@ module axi_adxcvr #(
 
   axi_adxcvr_mdrp #(
     .XCVR_ID (2),
-    .NUM_OF_LANES (NUM_OF_LANES))
-  i_mdrp_es_2 (
+    .NUM_OF_LANES (NUM_OF_LANES)
+  ) i_mdrp_es_2 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_es_sel),
@@ -1096,8 +1097,8 @@ module axi_adxcvr #(
 
   axi_adxcvr_mstatus #(
     .XCVR_ID (2),
-    .NUM_OF_LANES (NUM_OF_LANES))
-  i_mstatus_ch_2 (
+    .NUM_OF_LANES (NUM_OF_LANES)
+  ) i_mstatus_ch_2 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_pll_locked_in (up_ch_pll_locked_1_s),
@@ -1122,8 +1123,8 @@ module axi_adxcvr #(
 
   axi_adxcvr_mdrp #(
     .XCVR_ID (2),
-    .NUM_OF_LANES (NUM_OF_LANES))
-  i_mdrp_ch_2 (
+    .NUM_OF_LANES (NUM_OF_LANES)
+  ) i_mdrp_ch_2 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_ch_sel),
@@ -1142,8 +1143,8 @@ module axi_adxcvr #(
 
   axi_adxcvr_mdrp #(
     .XCVR_ID (3),
-    .NUM_OF_LANES (NUM_OF_LANES))
-  i_mdrp_es_3 (
+    .NUM_OF_LANES (NUM_OF_LANES)
+  ) i_mdrp_es_3 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_es_sel),
@@ -1172,8 +1173,8 @@ module axi_adxcvr #(
 
   axi_adxcvr_mstatus #(
     .XCVR_ID (3),
-    .NUM_OF_LANES (NUM_OF_LANES))
-  i_mstatus_ch_3 (
+    .NUM_OF_LANES (NUM_OF_LANES)
+  ) i_mstatus_ch_3 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_pll_locked_in (up_ch_pll_locked_2_s),
@@ -1198,8 +1199,8 @@ module axi_adxcvr #(
 
   axi_adxcvr_mdrp #(
     .XCVR_ID (3),
-    .NUM_OF_LANES (NUM_OF_LANES))
-  i_mdrp_ch_3 (
+    .NUM_OF_LANES (NUM_OF_LANES)
+  ) i_mdrp_ch_3 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_ch_sel),
@@ -1218,8 +1219,8 @@ module axi_adxcvr #(
 
   axi_adxcvr_mdrp #(
     .XCVR_ID (4),
-    .NUM_OF_LANES (NUM_OF_LANES))
-  i_mdrp_cm_4 (
+    .NUM_OF_LANES (NUM_OF_LANES)
+  ) i_mdrp_cm_4 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_cm_sel),
@@ -1238,8 +1239,8 @@ module axi_adxcvr #(
 
   axi_adxcvr_mdrp #(
     .XCVR_ID (4),
-    .NUM_OF_LANES (NUM_OF_LANES))
-  i_mdrp_es_4 (
+    .NUM_OF_LANES (NUM_OF_LANES)
+  ) i_mdrp_es_4 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_es_sel),
@@ -1268,8 +1269,8 @@ module axi_adxcvr #(
 
   axi_adxcvr_mstatus #(
     .XCVR_ID (4),
-    .NUM_OF_LANES (NUM_OF_LANES))
-  i_mstatus_ch_4 (
+    .NUM_OF_LANES (NUM_OF_LANES)
+  ) i_mstatus_ch_4 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_pll_locked_in (up_ch_pll_locked_3_s),
@@ -1294,8 +1295,8 @@ module axi_adxcvr #(
 
   axi_adxcvr_mdrp #(
     .XCVR_ID (4),
-    .NUM_OF_LANES (NUM_OF_LANES))
-  i_mdrp_ch_4 (
+    .NUM_OF_LANES (NUM_OF_LANES)
+  ) i_mdrp_ch_4 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_ch_sel),
@@ -1314,8 +1315,8 @@ module axi_adxcvr #(
 
   axi_adxcvr_mdrp #(
     .XCVR_ID (5),
-    .NUM_OF_LANES (NUM_OF_LANES))
-  i_mdrp_es_5 (
+    .NUM_OF_LANES (NUM_OF_LANES)
+  ) i_mdrp_es_5 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_es_sel),
@@ -1344,8 +1345,8 @@ module axi_adxcvr #(
 
   axi_adxcvr_mstatus #(
     .XCVR_ID (5),
-    .NUM_OF_LANES (NUM_OF_LANES))
-  i_mstatus_ch_5 (
+    .NUM_OF_LANES (NUM_OF_LANES)
+  ) i_mstatus_ch_5 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_pll_locked_in (up_ch_pll_locked_4_s),
@@ -1370,8 +1371,8 @@ module axi_adxcvr #(
 
   axi_adxcvr_mdrp #(
     .XCVR_ID (5),
-    .NUM_OF_LANES (NUM_OF_LANES))
-  i_mdrp_ch_5 (
+    .NUM_OF_LANES (NUM_OF_LANES)
+  ) i_mdrp_ch_5 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_ch_sel),
@@ -1390,8 +1391,8 @@ module axi_adxcvr #(
 
   axi_adxcvr_mdrp #(
     .XCVR_ID (6),
-    .NUM_OF_LANES (NUM_OF_LANES))
-  i_mdrp_es_6 (
+    .NUM_OF_LANES (NUM_OF_LANES)
+  ) i_mdrp_es_6 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_es_sel),
@@ -1420,8 +1421,8 @@ module axi_adxcvr #(
 
   axi_adxcvr_mstatus #(
     .XCVR_ID (6),
-    .NUM_OF_LANES (NUM_OF_LANES))
-  i_mstatus_ch_6 (
+    .NUM_OF_LANES (NUM_OF_LANES)
+  ) i_mstatus_ch_6 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_pll_locked_in (up_ch_pll_locked_5_s),
@@ -1446,8 +1447,8 @@ module axi_adxcvr #(
 
   axi_adxcvr_mdrp #(
     .XCVR_ID (6),
-    .NUM_OF_LANES (NUM_OF_LANES))
-  i_mdrp_ch_6 (
+    .NUM_OF_LANES (NUM_OF_LANES)
+  ) i_mdrp_ch_6 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_ch_sel),
@@ -1466,8 +1467,8 @@ module axi_adxcvr #(
 
   axi_adxcvr_mdrp #(
     .XCVR_ID (7),
-    .NUM_OF_LANES (NUM_OF_LANES))
-  i_mdrp_es_7 (
+    .NUM_OF_LANES (NUM_OF_LANES)
+  ) i_mdrp_es_7 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_es_sel),
@@ -1496,8 +1497,8 @@ module axi_adxcvr #(
 
   axi_adxcvr_mstatus #(
     .XCVR_ID (7),
-    .NUM_OF_LANES (NUM_OF_LANES))
-  i_mstatus_ch_7 (
+    .NUM_OF_LANES (NUM_OF_LANES)
+  ) i_mstatus_ch_7 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_pll_locked_in (up_ch_pll_locked_6_s),
@@ -1522,8 +1523,8 @@ module axi_adxcvr #(
 
   axi_adxcvr_mdrp #(
     .XCVR_ID (7),
-    .NUM_OF_LANES (NUM_OF_LANES))
-  i_mdrp_ch_7 (
+    .NUM_OF_LANES (NUM_OF_LANES)
+  ) i_mdrp_ch_7 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_ch_sel),
@@ -1542,8 +1543,8 @@ module axi_adxcvr #(
 
   axi_adxcvr_mdrp #(
     .XCVR_ID (8),
-    .NUM_OF_LANES (NUM_OF_LANES))
-  i_mdrp_cm_8 (
+    .NUM_OF_LANES (NUM_OF_LANES)
+  ) i_mdrp_cm_8 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_cm_sel),
@@ -1562,8 +1563,8 @@ module axi_adxcvr #(
 
   axi_adxcvr_mdrp #(
     .XCVR_ID (8),
-    .NUM_OF_LANES (NUM_OF_LANES))
-  i_mdrp_es_8 (
+    .NUM_OF_LANES (NUM_OF_LANES)
+  ) i_mdrp_es_8 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_es_sel),
@@ -1592,8 +1593,8 @@ module axi_adxcvr #(
 
   axi_adxcvr_mstatus #(
     .XCVR_ID (8),
-    .NUM_OF_LANES (NUM_OF_LANES))
-  i_mstatus_ch_8 (
+    .NUM_OF_LANES (NUM_OF_LANES)
+  ) i_mstatus_ch_8 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_pll_locked_in (up_ch_pll_locked_7_s),
@@ -1618,8 +1619,8 @@ module axi_adxcvr #(
 
   axi_adxcvr_mdrp #(
     .XCVR_ID (8),
-    .NUM_OF_LANES (NUM_OF_LANES))
-  i_mdrp_ch_8 (
+    .NUM_OF_LANES (NUM_OF_LANES)
+  ) i_mdrp_ch_8 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_ch_sel),
@@ -1638,8 +1639,8 @@ module axi_adxcvr #(
 
   axi_adxcvr_mdrp #(
     .XCVR_ID (9),
-    .NUM_OF_LANES (NUM_OF_LANES))
-  i_mdrp_es_9 (
+    .NUM_OF_LANES (NUM_OF_LANES)
+  ) i_mdrp_es_9 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_es_sel),
@@ -1668,8 +1669,8 @@ module axi_adxcvr #(
 
   axi_adxcvr_mstatus #(
     .XCVR_ID (9),
-    .NUM_OF_LANES (NUM_OF_LANES))
-  i_mstatus_ch_9 (
+    .NUM_OF_LANES (NUM_OF_LANES)
+  ) i_mstatus_ch_9 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_pll_locked_in (up_ch_pll_locked_8_s),
@@ -1694,8 +1695,8 @@ module axi_adxcvr #(
 
   axi_adxcvr_mdrp #(
     .XCVR_ID (9),
-    .NUM_OF_LANES (NUM_OF_LANES))
-  i_mdrp_ch_9 (
+    .NUM_OF_LANES (NUM_OF_LANES)
+  ) i_mdrp_ch_9 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_ch_sel),
@@ -1714,8 +1715,8 @@ module axi_adxcvr #(
 
   axi_adxcvr_mdrp #(
     .XCVR_ID (10),
-    .NUM_OF_LANES (NUM_OF_LANES))
-  i_mdrp_es_10 (
+    .NUM_OF_LANES (NUM_OF_LANES)
+  ) i_mdrp_es_10 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_es_sel),
@@ -1744,8 +1745,8 @@ module axi_adxcvr #(
 
   axi_adxcvr_mstatus #(
     .XCVR_ID (10),
-    .NUM_OF_LANES (NUM_OF_LANES))
-  i_mstatus_ch_10 (
+    .NUM_OF_LANES (NUM_OF_LANES)
+  ) i_mstatus_ch_10 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_pll_locked_in (up_ch_pll_locked_9_s),
@@ -1770,8 +1771,8 @@ module axi_adxcvr #(
 
   axi_adxcvr_mdrp #(
     .XCVR_ID (10),
-    .NUM_OF_LANES (NUM_OF_LANES))
-  i_mdrp_ch_10 (
+    .NUM_OF_LANES (NUM_OF_LANES)
+  ) i_mdrp_ch_10 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_ch_sel),
@@ -1790,8 +1791,8 @@ module axi_adxcvr #(
 
   axi_adxcvr_mdrp #(
     .XCVR_ID (11),
-    .NUM_OF_LANES (NUM_OF_LANES))
-  i_mdrp_es_11 (
+    .NUM_OF_LANES (NUM_OF_LANES)
+  ) i_mdrp_es_11 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_es_sel),
@@ -1820,8 +1821,8 @@ module axi_adxcvr #(
 
   axi_adxcvr_mstatus #(
     .XCVR_ID (11),
-    .NUM_OF_LANES (NUM_OF_LANES))
-  i_mstatus_ch_11 (
+    .NUM_OF_LANES (NUM_OF_LANES)
+  ) i_mstatus_ch_11 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_pll_locked_in (up_ch_pll_locked_10_s),
@@ -1846,8 +1847,8 @@ module axi_adxcvr #(
 
   axi_adxcvr_mdrp #(
     .XCVR_ID (11),
-    .NUM_OF_LANES (NUM_OF_LANES))
-  i_mdrp_ch_11 (
+    .NUM_OF_LANES (NUM_OF_LANES)
+  ) i_mdrp_ch_11 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_ch_sel),
@@ -1866,8 +1867,8 @@ module axi_adxcvr #(
 
   axi_adxcvr_mdrp #(
     .XCVR_ID (12),
-    .NUM_OF_LANES (NUM_OF_LANES))
-  i_mdrp_cm_12 (
+    .NUM_OF_LANES (NUM_OF_LANES)
+  ) i_mdrp_cm_12 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_cm_sel),
@@ -1886,8 +1887,8 @@ module axi_adxcvr #(
 
   axi_adxcvr_mdrp #(
     .XCVR_ID (12),
-    .NUM_OF_LANES (NUM_OF_LANES))
-  i_mdrp_es_12 (
+    .NUM_OF_LANES (NUM_OF_LANES)
+  ) i_mdrp_es_12 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_es_sel),
@@ -1916,8 +1917,8 @@ module axi_adxcvr #(
 
   axi_adxcvr_mstatus #(
     .XCVR_ID (12),
-    .NUM_OF_LANES (NUM_OF_LANES))
-  i_mstatus_ch_12 (
+    .NUM_OF_LANES (NUM_OF_LANES)
+  ) i_mstatus_ch_12 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_pll_locked_in (up_ch_pll_locked_11_s),
@@ -1942,8 +1943,8 @@ module axi_adxcvr #(
 
   axi_adxcvr_mdrp #(
     .XCVR_ID (12),
-    .NUM_OF_LANES (NUM_OF_LANES))
-  i_mdrp_ch_12 (
+    .NUM_OF_LANES (NUM_OF_LANES)
+  ) i_mdrp_ch_12 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_ch_sel),
@@ -1962,8 +1963,8 @@ module axi_adxcvr #(
 
   axi_adxcvr_mdrp #(
     .XCVR_ID (13),
-    .NUM_OF_LANES (NUM_OF_LANES))
-  i_mdrp_es_13 (
+    .NUM_OF_LANES (NUM_OF_LANES)
+  ) i_mdrp_es_13 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_es_sel),
@@ -1992,8 +1993,8 @@ module axi_adxcvr #(
 
   axi_adxcvr_mstatus #(
     .XCVR_ID (13),
-    .NUM_OF_LANES (NUM_OF_LANES))
-  i_mstatus_ch_13 (
+    .NUM_OF_LANES (NUM_OF_LANES)
+  ) i_mstatus_ch_13 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_pll_locked_in (up_ch_pll_locked_12_s),
@@ -2018,8 +2019,8 @@ module axi_adxcvr #(
 
   axi_adxcvr_mdrp #(
     .XCVR_ID (13),
-    .NUM_OF_LANES (NUM_OF_LANES))
-  i_mdrp_ch_13 (
+    .NUM_OF_LANES (NUM_OF_LANES)
+  ) i_mdrp_ch_13 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_ch_sel),
@@ -2038,8 +2039,8 @@ module axi_adxcvr #(
 
   axi_adxcvr_mdrp #(
     .XCVR_ID (14),
-    .NUM_OF_LANES (NUM_OF_LANES))
-  i_mdrp_es_14 (
+    .NUM_OF_LANES (NUM_OF_LANES)
+  ) i_mdrp_es_14 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_es_sel),
@@ -2068,8 +2069,8 @@ module axi_adxcvr #(
 
   axi_adxcvr_mstatus #(
     .XCVR_ID (14),
-    .NUM_OF_LANES (NUM_OF_LANES))
-  i_mstatus_ch_14 (
+    .NUM_OF_LANES (NUM_OF_LANES)
+  ) i_mstatus_ch_14 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_pll_locked_in (up_ch_pll_locked_13_s),
@@ -2094,8 +2095,8 @@ module axi_adxcvr #(
 
   axi_adxcvr_mdrp #(
     .XCVR_ID (14),
-    .NUM_OF_LANES (NUM_OF_LANES))
-  i_mdrp_ch_14 (
+    .NUM_OF_LANES (NUM_OF_LANES)
+  ) i_mdrp_ch_14 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_ch_sel),
@@ -2114,8 +2115,8 @@ module axi_adxcvr #(
 
   axi_adxcvr_mdrp #(
     .XCVR_ID (15),
-    .NUM_OF_LANES (NUM_OF_LANES))
-  i_mdrp_es_15 (
+    .NUM_OF_LANES (NUM_OF_LANES)
+  ) i_mdrp_es_15 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_es_sel),
@@ -2144,8 +2145,8 @@ module axi_adxcvr #(
 
   axi_adxcvr_mstatus #(
     .XCVR_ID (15),
-    .NUM_OF_LANES (NUM_OF_LANES))
-  i_mstatus_ch_15 (
+    .NUM_OF_LANES (NUM_OF_LANES)
+  ) i_mstatus_ch_15 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_pll_locked_in (up_ch_pll_locked_14_s),
@@ -2170,8 +2171,8 @@ module axi_adxcvr #(
 
   axi_adxcvr_mdrp #(
     .XCVR_ID (15),
-    .NUM_OF_LANES (NUM_OF_LANES))
-  i_mdrp_ch_15 (
+    .NUM_OF_LANES (NUM_OF_LANES)
+  ) i_mdrp_ch_15 (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_ch_sel),
@@ -2186,8 +2187,8 @@ module axi_adxcvr #(
 
   axi_adxcvr_es #(
     .XCVR_TYPE (XCVR_TYPE),
-    .TX_OR_RX_N (TX_OR_RX_N))
-  i_es (
+    .TX_OR_RX_N (TX_OR_RX_N)
+  ) i_es (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_es_enb (up_es_enb),
@@ -2247,8 +2248,8 @@ module axi_adxcvr #(
     .TX_POSTCURSOR (TX_POSTCURSOR),
     .TX_PRECURSOR (TX_PRECURSOR),
     .SYS_CLK_SEL (SYS_CLK_SEL),
-    .OUT_CLK_SEL (OUT_CLK_SEL))
-  i_up (
+    .OUT_CLK_SEL (OUT_CLK_SEL)
+  ) i_up (
     .up_cm_sel (up_cm_sel),
     .up_cm_enb (up_cm_enb),
     .up_cm_addr (up_cm_addr),
@@ -2308,7 +2309,9 @@ module axi_adxcvr #(
     .up_rdata (up_rdata),
     .up_rack (up_rack));
 
-  up_axi #(.AXI_ADDRESS_WIDTH (12)) i_axi (
+  up_axi #(
+    .AXI_ADDRESS_WIDTH (12)
+  ) i_axi (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_axi_awvalid (s_axi_awvalid),
@@ -2338,7 +2341,3 @@ module axi_adxcvr #(
     .up_rack (up_rack));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
-
diff --git a/library/xilinx/axi_adxcvr/axi_adxcvr_es.v b/library/xilinx/axi_adxcvr/axi_adxcvr_es.v
index 922fe56c6..78a042a3d 100644
--- a/library/xilinx/axi_adxcvr/axi_adxcvr_es.v
+++ b/library/xilinx/axi_adxcvr/axi_adxcvr_es.v
@@ -81,7 +81,8 @@ module axi_adxcvr_es (
   input           up_axi_rvalid,
   input   [31:0]  up_axi_rdata,
   input   [ 1:0]  up_axi_rresp,
-  output          up_axi_rready);
+  output          up_axi_rready
+);
 
   // parameters
 
@@ -567,6 +568,3 @@ module axi_adxcvr_es (
   end
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/xilinx/axi_adxcvr/axi_adxcvr_mdrp.v b/library/xilinx/axi_adxcvr/axi_adxcvr_mdrp.v
index 8c78b4a20..74a04492f 100644
--- a/library/xilinx/axi_adxcvr/axi_adxcvr_mdrp.v
+++ b/library/xilinx/axi_adxcvr/axi_adxcvr_mdrp.v
@@ -48,7 +48,8 @@ module axi_adxcvr_mdrp (
   input   [15:0]  up_rdata,
   input           up_ready,
   output  [15:0]  up_rdata_out,
-  output          up_ready_out);
+  output          up_ready_out
+);
 
   // parameters
 
@@ -156,7 +157,3 @@ module axi_adxcvr_mdrp (
   endgenerate
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
-
diff --git a/library/xilinx/axi_adxcvr/axi_adxcvr_mstatus.v b/library/xilinx/axi_adxcvr/axi_adxcvr_mstatus.v
index 63bd47b8b..389a79fd2 100644
--- a/library/xilinx/axi_adxcvr/axi_adxcvr_mstatus.v
+++ b/library/xilinx/axi_adxcvr/axi_adxcvr_mstatus.v
@@ -54,7 +54,8 @@ module axi_adxcvr_mstatus (
   output          up_rst_done_out,
   output          up_prbserr_out,
   output          up_prbslocked_out,
-  output  [ 1:0]  up_bufstatus_out);
+  output  [ 1:0]  up_bufstatus_out
+);
 
   // parameters
 
@@ -109,7 +110,3 @@ module axi_adxcvr_mstatus (
   end
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
-
diff --git a/library/xilinx/axi_adxcvr/axi_adxcvr_up.v b/library/xilinx/axi_adxcvr/axi_adxcvr_up.v
index 5c92e5962..213e6e467 100644
--- a/library/xilinx/axi_adxcvr/axi_adxcvr_up.v
+++ b/library/xilinx/axi_adxcvr/axi_adxcvr_up.v
@@ -56,7 +56,8 @@ module axi_adxcvr_up #(
   parameter   [ 4:0]  TX_POSTCURSOR = 5'd0,
   parameter   [ 4:0]  TX_PRECURSOR = 5'd0,
   parameter   [ 1:0]  SYS_CLK_SEL = 2'd3,
-  parameter   [ 2:0]  OUT_CLK_SEL = 3'd4) (
+  parameter   [ 2:0]  OUT_CLK_SEL = 3'd4
+) (
 
   // common
 
@@ -129,7 +130,8 @@ module axi_adxcvr_up #(
   input               up_rreq,
   input      [ 9:0]   up_raddr,
   output     [31:0]   up_rdata,
-  output              up_rack);
+  output              up_rack
+);
 
   // parameters
 
@@ -572,6 +574,3 @@ module axi_adxcvr_up #(
   end
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/xilinx/axi_dacfifo/axi_dacfifo.v b/library/xilinx/axi_dacfifo/axi_dacfifo.v
index 2813ab70a..2fea95bcb 100644
--- a/library/xilinx/axi_dacfifo/axi_dacfifo.v
+++ b/library/xilinx/axi_dacfifo/axi_dacfifo.v
@@ -43,7 +43,8 @@ module axi_dacfifo #(
   parameter   AXI_SIZE = 2,
   parameter   AXI_LENGTH = 15,
   parameter   AXI_ADDRESS = 32'h00000000,
-  parameter   AXI_ADDRESS_LIMIT = 32'hffffffff) (
+  parameter   AXI_ADDRESS_LIMIT = 32'hffffffff
+) (
 
   // dma interface (AXI Stream)
 
@@ -106,7 +107,8 @@ module axi_dacfifo #(
   input       [ 1:0]      axi_rresp,
   input                   axi_rlast,
   input       [(AXI_DATA_WIDTH-1):0]  axi_rdata,
-  output                  axi_rready);
+  output                  axi_rready
+);
 
   localparam  FIFO_BYPASS = (DAC_DATA_WIDTH == DMA_DATA_WIDTH) ? 1 : 0;
 
@@ -231,8 +233,7 @@ module axi_dacfifo #(
       .dac_rst(dac_rst),
       .dac_valid(dac_valid),
       .dac_data(dac_data_bypass_s),
-      .dac_dunf(dac_dunf_bypass_s)
-    );
+      .dac_dunf(dac_dunf_bypass_s));
 
     always @(posedge dma_clk) begin
       dma_bypass_m1 <= bypass;
@@ -279,4 +280,3 @@ module axi_dacfifo #(
   endgenerate
 
 endmodule
-
diff --git a/library/xilinx/axi_dacfifo/axi_dacfifo_address_buffer.v b/library/xilinx/axi_dacfifo/axi_dacfifo_address_buffer.v
index 5c94d3b99..a1499dfdd 100644
--- a/library/xilinx/axi_dacfifo/axi_dacfifo_address_buffer.v
+++ b/library/xilinx/axi_dacfifo/axi_dacfifo_address_buffer.v
@@ -38,20 +38,20 @@
 module axi_dacfifo_address_buffer #(
 
   parameter ADDRESS_WIDTH = 4,
-  parameter DATA_WIDTH = 16)(
-
+  parameter DATA_WIDTH = 16
+) (
   input                         clk,
   input                         rst,
   input                         wea,
   input      [DATA_WIDTH-1:0]   din,
 
   input                         rea,
-  output     [DATA_WIDTH-1:0]   dout);
+  output     [DATA_WIDTH-1:0]   dout
+);
 
   reg   [ADDRESS_WIDTH-1:0]     waddr;
   reg   [ADDRESS_WIDTH-1:0]     raddr;
 
-
   always @(posedge clk) begin
     if (rst == 1'b1) begin
       waddr <= 0;
@@ -64,8 +64,8 @@ module axi_dacfifo_address_buffer #(
 
   ad_mem #(
     .DATA_WIDTH (DATA_WIDTH),
-    .ADDRESS_WIDTH (ADDRESS_WIDTH))
-  i_mem (
+    .ADDRESS_WIDTH (ADDRESS_WIDTH)
+  ) i_mem (
     .clka (clk),
     .wea (wea),
     .addra (waddr),
@@ -76,4 +76,3 @@ module axi_dacfifo_address_buffer #(
     .doutb (dout));
 
 endmodule
-
diff --git a/library/xilinx/axi_dacfifo/axi_dacfifo_rd.v b/library/xilinx/axi_dacfifo/axi_dacfifo_rd.v
index ea7b7882d..969568c3b 100644
--- a/library/xilinx/axi_dacfifo/axi_dacfifo_rd.v
+++ b/library/xilinx/axi_dacfifo/axi_dacfifo_rd.v
@@ -42,9 +42,10 @@ module axi_dacfifo_rd #(
   parameter   AXI_LENGTH = 15,
   parameter   AXI_ADDRESS = 32'h00000000,
   parameter   DAC_DATA_WIDTH = 64,
-  parameter   DAC_MEM_ADDRESS_WIDTH = 8) (
+  parameter   DAC_MEM_ADDRESS_WIDTH = 8
+) (
 
- // xfer last for read/write synchronization
+  // xfer last for read/write synchronization
 
   input                               axi_xfer_req,
   input       [31:0]                  axi_last_raddr,
@@ -85,12 +86,12 @@ module axi_dacfifo_rd #(
   input                               dac_valid,
   output      [(DAC_DATA_WIDTH-1):0]  dac_data,
   output                              dac_xfer_out,
-  output  reg                         dac_dunf);
+  output  reg                         dac_dunf
+);
 
   `define max(a,b) {(a) > (b) ? (a) : (b)}
   `define min(a,b) {(a) < (b) ? (a) : (b)}
 
-
   localparam  AXI_BYTE_WIDTH = AXI_DATA_WIDTH/8;
   localparam  AXI_ARINCR = (AXI_LENGTH + 1) * AXI_BYTE_WIDTH;
 
@@ -119,9 +120,9 @@ module axi_dacfifo_rd #(
   reg                                   axi_data_req = 1'b0;
   reg     [ 4:0]                        axi_read_state = 5'b0;
   reg     [(AXI_MEM_ADDRESS_WIDTH-1):0] axi_mem_waddr = 'd0;
- (* dont_touch = "true" *) reg     [(AXI_MEM_ADDRESS_WIDTH-1):0] axi_mem_laddr = 'd0;
+  (* dont_touch = "true" *) reg     [(AXI_MEM_ADDRESS_WIDTH-1):0] axi_mem_laddr = 'd0;
   reg     [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_waddr_g = 'd0;
- (* dont_touch = "true" *) reg                                  axi_mem_laddr_toggle = 1'b0;
+  (* dont_touch = "true" *) reg                                  axi_mem_laddr_toggle = 1'b0;
   reg     [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_raddr = 'd0;
   reg     [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_raddr_m1 = 'd0;
   reg     [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_raddr_m2 = 'd0;
@@ -166,8 +167,8 @@ module axi_dacfifo_rd #(
     .A_ADDRESS_WIDTH (AXI_MEM_ADDRESS_WIDTH),
     .A_DATA_WIDTH (AXI_DATA_WIDTH),
     .B_ADDRESS_WIDTH (DAC_MEM_ADDRESS_WIDTH),
-    .B_DATA_WIDTH (DAC_DATA_WIDTH))
-  i_mem_asym (
+    .B_DATA_WIDTH (DAC_DATA_WIDTH)
+  ) i_mem_asym (
     .clka (axi_clk),
     .wea (axi_dvalid_s),
     .addra (axi_mem_waddr),
@@ -302,7 +303,7 @@ module axi_dacfifo_rd #(
     end
   end
 
-  ad_b2g # (
+  ad_b2g #(
     .DATA_WIDTH(DAC_MEM_ADDRESS_WIDTH)
   ) i_axi_mem_waddr_b2g (
     .din (axi_mem_waddr_s),
@@ -392,8 +393,8 @@ module axi_dacfifo_rd #(
 
   axi_dacfifo_address_buffer #(
     .ADDRESS_WIDTH (4),
-    .DATA_WIDTH (DAC_MEM_ADDRESS_WIDTH))
-  i_laddress_buffer (
+    .DATA_WIDTH (DAC_MEM_ADDRESS_WIDTH)
+  ) i_laddress_buffer (
     .clk (dac_clk),
     .rst (dac_fifo_reset_s),
     .wea (dac_laddr_wea),
@@ -461,7 +462,7 @@ module axi_dacfifo_rd #(
     end
   end
 
-  ad_b2g # (
+  ad_b2g #(
     .DATA_WIDTH(DAC_MEM_ADDRESS_WIDTH)
   ) i_dac_mem_raddr_b2g (
     .din (dac_mem_raddr),
@@ -480,6 +481,3 @@ module axi_dacfifo_rd #(
   end
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/xilinx/axi_dacfifo/axi_dacfifo_wr.v b/library/xilinx/axi_dacfifo/axi_dacfifo_wr.v
index 631c11456..0756bae43 100644
--- a/library/xilinx/axi_dacfifo/axi_dacfifo_wr.v
+++ b/library/xilinx/axi_dacfifo/axi_dacfifo_wr.v
@@ -42,7 +42,8 @@ module axi_dacfifo_wr #(
   parameter       AXI_LENGTH = 15,
   parameter       AXI_ADDRESS = 32'h00000000,
   parameter       AXI_ADDRESS_LIMIT = 32'h00000000,
-  parameter       DMA_MEM_ADDRESS_WIDTH = 8) (
+  parameter       DMA_MEM_ADDRESS_WIDTH = 8
+) (
 
   // dma fifo interface
 
@@ -57,7 +58,7 @@ module axi_dacfifo_wr #(
 
   input                   dma_xfer_req,
   input                   dma_xfer_last,
- (* dont_touch = "true" *) output  reg [ 3:0]      dma_last_beats,
+  (* dont_touch = "true" *) output  reg [ 3:0]      dma_last_beats,
 
   // last address for read side
 
@@ -90,7 +91,8 @@ module axi_dacfifo_wr #(
   input       [ 1:0]      axi_bresp,
   output                  axi_bready,
 
-  output  reg             axi_werror);
+  output  reg             axi_werror
+);
 
   `define max(a,b) {(a) > (b) ? (a) : (b)}
   `define min(a,b) {(a) < (b) ? (a) : (b)}
@@ -188,8 +190,8 @@ module axi_dacfifo_wr #(
     .A_ADDRESS_WIDTH (DMA_MEM_ADDRESS_WIDTH),
     .A_DATA_WIDTH (DMA_DATA_WIDTH),
     .B_ADDRESS_WIDTH (AXI_MEM_ADDRESS_WIDTH),
-    .B_DATA_WIDTH (AXI_DATA_WIDTH))
-  i_mem_asym (
+    .B_DATA_WIDTH (AXI_DATA_WIDTH)
+  ) i_mem_asym (
     .clka (dma_clk),
     .wea (dma_mem_wea_s),
     .addra (dma_mem_waddr),
@@ -200,7 +202,9 @@ module axi_dacfifo_wr #(
     .doutb (axi_mem_rdata_s));
 
   assign axi_reset_s = ~axi_resetn;
-  ad_axis_inf_rx #(.DATA_WIDTH(AXI_DATA_WIDTH)) i_axis_inf (
+  ad_axis_inf_rx #(
+    .DATA_WIDTH(AXI_DATA_WIDTH)
+  ) i_axis_inf (
     .clk (axi_clk),
     .rst (axi_reset_s),
     .valid (axi_mem_rvalid_d),
@@ -259,7 +263,7 @@ module axi_dacfifo_wr #(
     end
   end
 
-  ad_b2g # (
+  ad_b2g #(
     .DATA_WIDTH(DMA_MEM_ADDRESS_WIDTH)
   ) i_dma_mem_waddr_b2g (
     .din (dma_mem_waddr),
@@ -287,7 +291,7 @@ module axi_dacfifo_wr #(
     end
   end
 
-  ad_g2b # (
+  ad_g2b #(
     .DATA_WIDTH(AXI_MEM_ADDRESS_WIDTH)
   ) i_dma_mem_raddr_g2b (
     .din (dma_mem_raddr_m2),
@@ -408,7 +412,7 @@ module axi_dacfifo_wr #(
     end
   end
 
-  ad_g2b # (
+  ad_g2b #(
     .DATA_WIDTH(DMA_MEM_ADDRESS_WIDTH)
   ) i_axi_mem_waddr_g2b (
     .din (axi_mem_waddr_m2),
@@ -423,7 +427,6 @@ module axi_dacfifo_wr #(
                                               ((AXI_BIGGER == 1) ? axi_mem_waddr[(DMA_MEM_ADDRESS_WIDTH-1):4] : {axi_mem_waddr, 4'b0});
   assign axi_mem_addr_diff_s = {1'b1, axi_mem_waddr_s} - axi_mem_raddr;
 
-
   always @(posedge axi_clk) begin
     if (axi_fifo_reset_s == 1'b1) begin
       axi_mem_addr_diff <= 'b0;
@@ -467,7 +470,7 @@ module axi_dacfifo_wr #(
     end
   end
 
-  ad_b2g # (
+  ad_b2g #(
     .DATA_WIDTH(AXI_MEM_ADDRESS_WIDTH)
   ) i_axi_mem_raddr_b2g (
     .din (axi_mem_raddr),
diff --git a/library/xilinx/axi_xcvrlb/axi_xcvrlb.v b/library/xilinx/axi_xcvrlb/axi_xcvrlb.v
index 66a8e1792..dccbb8163 100644
--- a/library/xilinx/axi_xcvrlb/axi_xcvrlb.v
+++ b/library/xilinx/axi_xcvrlb/axi_xcvrlb.v
@@ -42,7 +42,8 @@ module axi_xcvrlb #(
   parameter   integer CPLL_FBDIV = 1,
   parameter   integer CPLL_FBDIV_4_5 = 5,
   parameter   NUM_OF_LANES = 1,
-  parameter   integer XCVR_TYPE = 2) (
+  parameter   integer XCVR_TYPE = 2
+) (
 
   // transceiver interface
 
@@ -74,7 +75,8 @@ module axi_xcvrlb #(
   output                        s_axi_rvalid,
   output  [ 1:0]                s_axi_rresp,
   output  [31:0]                s_axi_rdata,
-  input                         s_axi_rready);
+  input                         s_axi_rready
+);
 
   // internal registers
 
@@ -168,8 +170,8 @@ module axi_xcvrlb #(
   axi_xcvrlb_1 #(
     .XCVR_TYPE (XCVR_TYPE),
     .CPLL_FBDIV_4_5(CPLL_FBDIV_4_5),
-    .CPLL_FBDIV(CPLL_FBDIV))
-  i_xcvrlb_1 (
+    .CPLL_FBDIV(CPLL_FBDIV)
+  ) i_xcvrlb_1 (
     .ref_clk (ref_clk),
     .rx_p (rx_p[n]),
     .rx_n (rx_n[n]),
@@ -179,12 +181,13 @@ module axi_xcvrlb #(
     .up_clk (up_clk),
     .up_resetn (up_resetn),
     .up_status (up_status_s[n]),
-    .up_pll_locked (up_pll_locked_s[n])
-    );
+    .up_pll_locked (up_pll_locked_s[n]));
   end
   endgenerate
 
-  up_axi #(.AXI_ADDRESS_WIDTH (10)) i_axi (
+  up_axi #(
+    .AXI_ADDRESS_WIDTH (10)
+  ) i_axi (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_axi_awvalid (s_axi_awvalid),
@@ -214,7 +217,3 @@ module axi_xcvrlb #(
     .up_rack (up_rack));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
-
diff --git a/library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v b/library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v
index 6c4fdd713..90ba52db8 100644
--- a/library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v
+++ b/library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v
@@ -42,7 +42,7 @@ module axi_xcvrlb_1 #(
   parameter   CPLL_FBDIV = 1,
   parameter   CPLL_FBDIV_4_5 = 5,
   parameter   XCVR_TYPE = 2
-  )(
+) (
 
   // transceiver interface
 
@@ -58,7 +58,8 @@ module axi_xcvrlb_1 #(
   input           up_clk,
   input           up_resetn,
   output          up_status,
-  output          up_pll_locked);
+  output          up_pll_locked
+);
 
   // internal registers
 
@@ -233,7 +234,9 @@ module axi_xcvrlb_1 #(
 
   // instantiations
 
-  ad_pnmon #(.DATA_WIDTH(32)) i_pnmon (
+  ad_pnmon #(
+    .DATA_WIDTH(32)
+  ) i_pnmon (
     .adc_clk (clk),
     .adc_valid_in (1'b1),
     .adc_data_in (rx_data),
@@ -241,7 +244,9 @@ module axi_xcvrlb_1 #(
     .adc_pn_oos (rx_pn_oos_s),
     .adc_pn_err (rx_pn_err_s));
 
-  up_xfer_status #(.DATA_WIDTH(2)) i_xfer_status (
+  up_xfer_status #(
+    .DATA_WIDTH(2)
+  ) i_xfer_status (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_data_status ({up_pn_err_s, up_pn_oos_s}),
@@ -259,8 +264,8 @@ module axi_xcvrlb_1 #(
     .RX_CLK25_DIV (10),
     .RX_DFE_LPM_CFG (16'h0904),
     .RX_PMA_CFG ('h00018480),
-    .RX_CDR_CFG ('h03000023ff10200020))
-  i_xch (
+    .RX_CDR_CFG ('h03000023ff10200020)
+  ) i_xch (
     .qpll2ch_clk (1'b0),
     .qpll2ch_ref_clk (1'b0),
     .qpll2ch_locked (1'b1),
@@ -319,7 +324,3 @@ module axi_xcvrlb_1 #(
     .up_tx_ready ());
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
-
diff --git a/library/xilinx/common/ad_data_clk.v b/library/xilinx/common/ad_data_clk.v
index 6eea5cbd4..ffcac984b 100644
--- a/library/xilinx/common/ad_data_clk.v
+++ b/library/xilinx/common/ad_data_clk.v
@@ -37,14 +37,15 @@
 
 module ad_data_clk #(
 
-  parameter   SINGLE_ENDED = 0) (
-
+  parameter   SINGLE_ENDED = 0
+) (
   input               rst,
   output              locked,
 
   input               clk_in_p,
   input               clk_in_n,
-  output              clk);
+  output              clk
+);
 
   // internal signals
 
@@ -74,6 +75,3 @@ module ad_data_clk #(
     .O (clk));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/xilinx/common/ad_data_in.v b/library/xilinx/common/ad_data_in.v
index c0d17b191..62f3ebcc5 100644
--- a/library/xilinx/common/ad_data_in.v
+++ b/library/xilinx/common/ad_data_in.v
@@ -36,16 +36,14 @@
 `timescale 1ns/100ps
 
 module ad_data_in #(
-
-  // parameters
-
   parameter   SINGLE_ENDED = 0,
   parameter   FPGA_TECHNOLOGY = 0,
   parameter   IDDR_CLK_EDGE ="SAME_EDGE",
   parameter   IODELAY_ENABLE = 1,
   parameter   IODELAY_CTRL = 0,
   parameter   IODELAY_GROUP = "dev_if_delay_group",
-  parameter   REFCLK_FREQUENCY = 200) (
+  parameter   REFCLK_FREQUENCY = 200
+) (
 
   // data interface
 
@@ -66,7 +64,8 @@ module ad_data_in #(
 
   input               delay_clk,
   input               delay_rst,
-  output              delay_locked);
+  output              delay_locked
+);
 
   // internal parameters
 
@@ -93,13 +92,15 @@ module ad_data_in #(
 
   generate
   if (IODELAY_CTRL_ENABLED == 0) begin
-  assign delay_locked = 1'b1;
+    assign delay_locked = 1'b1;
   end else begin
-  (* IODELAY_GROUP = IODELAY_GROUP *)
-  IDELAYCTRL #(.SIM_DEVICE (IODELAY_CTRL_SIM_DEVICE)) i_delay_ctrl (
-    .RST (delay_rst),
-    .REFCLK (delay_clk),
-    .RDY (delay_locked));
+    (* IODELAY_GROUP = IODELAY_GROUP *)
+    IDELAYCTRL #(
+      .SIM_DEVICE (IODELAY_CTRL_SIM_DEVICE)
+    ) i_delay_ctrl (
+      .RST (delay_rst),
+      .REFCLK (delay_clk),
+      .RDY (delay_locked));
   end
   endgenerate
 
@@ -107,14 +108,14 @@ module ad_data_in #(
 
   generate
   if (SINGLE_ENDED == 1) begin
-  IBUF i_rx_data_ibuf (
-    .I (rx_data_in_p),
-    .O (rx_data_ibuf_s));
+    IBUF i_rx_data_ibuf (
+      .I (rx_data_in_p),
+      .O (rx_data_ibuf_s));
   end else begin
-  IBUFDS i_rx_data_ibuf (
-    .I (rx_data_in_p),
-    .IB (rx_data_in_n),
-    .O (rx_data_ibuf_s));
+    IBUFDS i_rx_data_ibuf (
+      .I (rx_data_in_p),
+      .IB (rx_data_in_n),
+      .O (rx_data_ibuf_s));
   end
   endgenerate
 
@@ -122,64 +123,64 @@ module ad_data_in #(
 
   generate
   if (IODELAY_FPGA_TECHNOLOGY == SEVEN_SERIES) begin
-  (* IODELAY_GROUP = IODELAY_GROUP *)
-  IDELAYE2 #(
-    .CINVCTRL_SEL ("FALSE"),
-    .DELAY_SRC ("IDATAIN"),
-    .HIGH_PERFORMANCE_MODE ("FALSE"),
-    .IDELAY_TYPE ("VAR_LOAD"),
-    .IDELAY_VALUE (0),
-    .REFCLK_FREQUENCY (REFCLK_FREQUENCY),
-    .PIPE_SEL ("FALSE"),
-    .SIGNAL_PATTERN ("DATA"))
-  i_rx_data_idelay (
-    .CE (1'b0),
-    .INC (1'b0),
-    .DATAIN (1'b0),
-    .LDPIPEEN (1'b0),
-    .CINVCTRL (1'b0),
-    .REGRST (1'b0),
-    .C (up_clk),
-    .IDATAIN (rx_data_ibuf_s),
-    .DATAOUT (rx_data_idelay_s),
-    .LD (up_dld),
-    .CNTVALUEIN (up_dwdata),
-    .CNTVALUEOUT (up_drdata));
+    (* IODELAY_GROUP = IODELAY_GROUP *)
+    IDELAYE2 #(
+      .CINVCTRL_SEL ("FALSE"),
+      .DELAY_SRC ("IDATAIN"),
+      .HIGH_PERFORMANCE_MODE ("FALSE"),
+      .IDELAY_TYPE ("VAR_LOAD"),
+      .IDELAY_VALUE (0),
+      .REFCLK_FREQUENCY (REFCLK_FREQUENCY),
+      .PIPE_SEL ("FALSE"),
+      .SIGNAL_PATTERN ("DATA")
+    ) i_rx_data_idelay (
+      .CE (1'b0),
+      .INC (1'b0),
+      .DATAIN (1'b0),
+      .LDPIPEEN (1'b0),
+      .CINVCTRL (1'b0),
+      .REGRST (1'b0),
+      .C (up_clk),
+      .IDATAIN (rx_data_ibuf_s),
+      .DATAOUT (rx_data_idelay_s),
+      .LD (up_dld),
+      .CNTVALUEIN (up_dwdata),
+      .CNTVALUEOUT (up_drdata));
   end
   endgenerate
 
   generate
   if ((IODELAY_FPGA_TECHNOLOGY == ULTRASCALE) || (IODELAY_FPGA_TECHNOLOGY == ULTRASCALE_PLUS)) begin
-  assign up_drdata = up_drdata_s[8:4];
-  (* IODELAY_GROUP = IODELAY_GROUP *)
-  IDELAYE3 #(
-    .SIM_DEVICE (IODELAY_SIM_DEVICE),
-    .DELAY_SRC ("IDATAIN"),
-    .DELAY_TYPE ("VAR_LOAD"),
-    .REFCLK_FREQUENCY (REFCLK_FREQUENCY),
-    .DELAY_FORMAT ("COUNT"))
-  i_rx_data_idelay (
-    .CASC_RETURN (1'b0),
-    .CASC_IN (1'b0),
-    .CASC_OUT (),
-    .CE (1'b0),
-    .CLK (up_clk),
-    .INC (1'b0),
-    .LOAD (up_dld),
-    .CNTVALUEIN ({up_dwdata, 4'd0}),
-    .CNTVALUEOUT (up_drdata_s),
-    .DATAIN (1'b0),
-    .IDATAIN (rx_data_ibuf_s),
-    .DATAOUT (rx_data_idelay_s),
-    .RST (1'b0),
-    .EN_VTC (~up_dld));
+    assign up_drdata = up_drdata_s[8:4];
+    (* IODELAY_GROUP = IODELAY_GROUP *)
+    IDELAYE3 #(
+      .SIM_DEVICE (IODELAY_SIM_DEVICE),
+      .DELAY_SRC ("IDATAIN"),
+      .DELAY_TYPE ("VAR_LOAD"),
+      .REFCLK_FREQUENCY (REFCLK_FREQUENCY),
+      .DELAY_FORMAT ("COUNT")
+    ) i_rx_data_idelay (
+      .CASC_RETURN (1'b0),
+      .CASC_IN (1'b0),
+      .CASC_OUT (),
+      .CE (1'b0),
+      .CLK (up_clk),
+      .INC (1'b0),
+      .LOAD (up_dld),
+      .CNTVALUEIN ({up_dwdata, 4'd0}),
+      .CNTVALUEOUT (up_drdata_s),
+      .DATAIN (1'b0),
+      .IDATAIN (rx_data_ibuf_s),
+      .DATAOUT (rx_data_idelay_s),
+      .RST (1'b0),
+      .EN_VTC (~up_dld));
   end
   endgenerate
 
   generate
   if (IODELAY_FPGA_TECHNOLOGY == NONE) begin
-  assign rx_data_idelay_s = rx_data_ibuf_s;
-	assign up_drdata = 5'd0;
+    assign rx_data_idelay_s = rx_data_ibuf_s;
+    assign up_drdata = 5'd0;
   end
   endgenerate
 
@@ -187,30 +188,31 @@ module ad_data_in #(
 
   generate
   if ((FPGA_TECHNOLOGY == ULTRASCALE) || (FPGA_TECHNOLOGY == ULTRASCALE_PLUS)) begin
-  IDDRE1 #(.DDR_CLK_EDGE (IDDR_CLK_EDGE)) i_rx_data_iddr (
-    .R (1'b0),
-    .C (rx_clk),
-    .CB (~rx_clk),
-    .D (rx_data_idelay_s),
-    .Q1 (rx_data_p),
-    .Q2 (rx_data_n));
+    IDDRE1 #(
+      .DDR_CLK_EDGE (IDDR_CLK_EDGE)
+    ) i_rx_data_iddr (
+      .R (1'b0),
+      .C (rx_clk),
+      .CB (~rx_clk),
+      .D (rx_data_idelay_s),
+      .Q1 (rx_data_p),
+      .Q2 (rx_data_n));
   end
   endgenerate
 
   generate
   if (FPGA_TECHNOLOGY == SEVEN_SERIES) begin
-  IDDR #(.DDR_CLK_EDGE (IDDR_CLK_EDGE)) i_rx_data_iddr (
-    .CE (1'b1),
-    .R (1'b0),
-    .S (1'b0),
-    .C (rx_clk),
-    .D (rx_data_idelay_s),
-    .Q1 (rx_data_p),
-    .Q2 (rx_data_n));
+    IDDR #(
+      .DDR_CLK_EDGE (IDDR_CLK_EDGE)
+    ) i_rx_data_iddr (
+      .CE (1'b1),
+      .R (1'b0),
+      .S (1'b0),
+      .C (rx_clk),
+      .D (rx_data_idelay_s),
+      .Q1 (rx_data_p),
+      .Q2 (rx_data_n));
   end
   endgenerate
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/xilinx/common/ad_data_out.v b/library/xilinx/common/ad_data_out.v
index 47358febf..88af5942f 100644
--- a/library/xilinx/common/ad_data_out.v
+++ b/library/xilinx/common/ad_data_out.v
@@ -43,7 +43,8 @@ module ad_data_out #(
   parameter   IODELAY_ENABLE = 0,
   parameter   IODELAY_CTRL = 0,
   parameter   IODELAY_GROUP = "dev_if_delay_group",
-  parameter   REFCLK_FREQUENCY = 200) (
+  parameter   REFCLK_FREQUENCY = 200
+) (
 
   // data interface
 
@@ -64,7 +65,8 @@ module ad_data_out #(
 
   input               delay_clk,
   input               delay_rst,
-  output              delay_locked);
+  output              delay_locked
+);
 
   localparam  NONE = -1;
   localparam  SEVEN_SERIES = 1;
@@ -91,7 +93,9 @@ module ad_data_out #(
   assign delay_locked = 1'b1;
   end else begin
   (* IODELAY_GROUP = IODELAY_GROUP *)
-  IDELAYCTRL #(.SIM_DEVICE (IODELAY_CTRL_SIM_DEVICE)) i_delay_ctrl (
+  IDELAYCTRL #(
+    .SIM_DEVICE (IODELAY_CTRL_SIM_DEVICE)
+  ) i_delay_ctrl (
     .RST (delay_rst),
     .REFCLK (delay_clk),
     .RDY (delay_locked));
@@ -113,7 +117,9 @@ module ad_data_out #(
 
   generate
   if (FPGA_TECHNOLOGY == SEVEN_SERIES) begin
-  ODDR #(.DDR_CLK_EDGE (IDDR_CLK_EDGE)) i_tx_data_oddr (
+  ODDR #(
+    .DDR_CLK_EDGE (IDDR_CLK_EDGE)
+  ) i_tx_data_oddr (
     .CE (1'b1),
     .R (1'b0),
     .S (1'b0),
@@ -137,8 +143,8 @@ module ad_data_out #(
     .ODELAY_VALUE (0),
     .REFCLK_FREQUENCY (REFCLK_FREQUENCY),
     .PIPE_SEL ("FALSE"),
-    .SIGNAL_PATTERN ("DATA"))
-  i_tx_data_odelay (
+    .SIGNAL_PATTERN ("DATA")
+  ) i_tx_data_odelay (
     .CE (1'b0),
     .CLKIN (1'b0),
     .INC (1'b0),
@@ -178,6 +184,3 @@ module ad_data_out #(
   endgenerate
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/xilinx/common/ad_dcfilter.v b/library/xilinx/common/ad_dcfilter.v
index 47a2db003..de853a928 100644
--- a/library/xilinx/common/ad_dcfilter.v
+++ b/library/xilinx/common/ad_dcfilter.v
@@ -40,7 +40,8 @@ module ad_dcfilter #(
 
   // data path disable
 
-  parameter   DISABLE = 0) (
+  parameter   DISABLE = 0
+) (
 
   // data interface
 
@@ -54,7 +55,8 @@ module ad_dcfilter #(
 
   input           dcfilt_enb,
   input   [15:0]  dcfilt_coeff,
-  input   [15:0]  dcfilt_offset);
+  input   [15:0]  dcfilt_offset
+);
 
   // internal registers
 
@@ -139,8 +141,8 @@ module ad_dcfilter #(
     .USE_DPORT ("TRUE"),
     .USE_MULT ("MULTIPLY"),
     .USE_PATTERN_DETECT ("NO_PATDET"),
-    .USE_SIMD ("ONE48"))
-  i_dsp48e1 (
+    .USE_SIMD ("ONE48")
+  ) i_dsp48e1 (
     .CLK (clk),
     .A ({{14{dc_offset_s[32]}}, dc_offset_s[32:17]}),
     .B ({{2{dcfilt_coeff_d[15]}}, dcfilt_coeff_d}),
@@ -192,6 +194,3 @@ module ad_dcfilter #(
     .RSTP (1'd0));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/xilinx/common/ad_mmcm_drp.v b/library/xilinx/common/ad_mmcm_drp.v
index 4ca57235c..86acf8584 100644
--- a/library/xilinx/common/ad_mmcm_drp.v
+++ b/library/xilinx/common/ad_mmcm_drp.v
@@ -48,7 +48,8 @@ module ad_mmcm_drp #(
   parameter   MMCM_CLK1_DIV = 6,
   parameter   MMCM_CLK1_PHASE = 0.000,
   parameter   MMCM_CLK2_DIV = 2.000,
-  parameter   MMCM_CLK2_PHASE = 0.000) (
+  parameter   MMCM_CLK2_PHASE = 0.000
+) (
 
   // clocks
 
@@ -70,13 +71,13 @@ module ad_mmcm_drp #(
   input       [15:0]      up_drp_wdata,
   output  reg [15:0]      up_drp_rdata,
   output  reg             up_drp_ready,
-  output  reg             up_drp_locked);
+  output  reg             up_drp_locked
+);
 
   localparam  SEVEN_SERIES = 1;
   localparam  ULTRASCALE = 2;
   localparam  ULTRASCALE_PLUS = 3;
 
-
   // internal registers
 
   reg             up_drp_locked_m1 = 'd0;
@@ -135,8 +136,8 @@ module ad_mmcm_drp #(
       .CLKOUT2_USE_FINE_PS ("FALSE"),
       .CLKIN1_PERIOD (MMCM_CLKIN_PERIOD),
       .CLKIN2_PERIOD (MMCM_CLKIN2_PERIOD),
-      .REF_JITTER1 (0.010))
-    i_mmcm (
+      .REF_JITTER1 (0.010)
+    ) i_mmcm (
       .CLKIN1 (clk),
       .CLKFBIN (bufg_fb_clk_s),
       .CLKFBOUT (mmcm_fb_clk_s),
@@ -171,10 +172,21 @@ module ad_mmcm_drp #(
       .PWRDWN (1'b0),
       .RST (mmcm_rst));
 
-      BUFG i_fb_clk_bufg  (.I (mmcm_fb_clk_s),  .O (bufg_fb_clk_s));
-      BUFG i_clk_0_bufg   (.I (mmcm_clk_0_s),   .O (mmcm_clk_0));
-      BUFG i_clk_1_bufg   (.I (mmcm_clk_1_s),   .O (mmcm_clk_1));
-      BUFG i_clk_2_bufg   (.I (mmcm_clk_2_s),   .O (mmcm_clk_2));
+      BUFG i_fb_clk_bufg (
+        .I (mmcm_fb_clk_s),
+        .O (bufg_fb_clk_s));
+
+      BUFG i_clk_0_bufg (
+        .I (mmcm_clk_0_s),
+        .O (mmcm_clk_0));
+
+      BUFG i_clk_1_bufg (
+        .I (mmcm_clk_1_s),
+        .O (mmcm_clk_1));
+
+      BUFG i_clk_2_bufg (
+        .I (mmcm_clk_2_s),
+        .O (mmcm_clk_2));
 
   end else if (FPGA_TECHNOLOGY == ULTRASCALE) begin
     MMCME3_ADV #(
@@ -201,8 +213,8 @@ module ad_mmcm_drp #(
       .CLKOUT2_USE_FINE_PS ("FALSE"),
       .CLKIN1_PERIOD (MMCM_CLKIN_PERIOD),
       .CLKIN2_PERIOD (MMCM_CLKIN2_PERIOD),
-      .REF_JITTER1 (0.010))
-    i_mmcme3 (
+      .REF_JITTER1 (0.010)
+    ) i_mmcme3 (
       .CLKIN1 (clk),
       .CLKFBIN (bufg_fb_clk_s),
       .CLKFBOUT (mmcm_fb_clk_s),
@@ -239,10 +251,21 @@ module ad_mmcm_drp #(
       .CDDCDONE (),
       .RST (mmcm_rst));
 
-      BUFG i_fb_clk_bufg  (.I (mmcm_fb_clk_s),  .O (bufg_fb_clk_s));
-      BUFG i_clk_0_bufg   (.I (mmcm_clk_0_s),   .O (mmcm_clk_0));
-      BUFG i_clk_1_bufg   (.I (mmcm_clk_1_s),   .O (mmcm_clk_1));
-      BUFG i_clk_2_bufg   (.I (mmcm_clk_2_s),   .O (mmcm_clk_2));
+      BUFG i_fb_clk_bufg (
+        .I (mmcm_fb_clk_s),
+        .O (bufg_fb_clk_s));
+
+      BUFG i_clk_0_bufg (
+        .I (mmcm_clk_0_s),
+        .O (mmcm_clk_0));
+
+      BUFG i_clk_1_bufg (
+        .I (mmcm_clk_1_s),
+        .O (mmcm_clk_1));
+
+      BUFG i_clk_2_bufg (
+        .I (mmcm_clk_2_s),
+        .O (mmcm_clk_2));
 
   end else if (FPGA_TECHNOLOGY == ULTRASCALE_PLUS) begin
     MMCME4_ADV #(
@@ -306,16 +329,23 @@ module ad_mmcm_drp #(
       .CDDCDONE (),
       .RST (mmcm_rst));
 
-      BUFG i_fb_clk_bufg  (.I (mmcm_fb_clk_s),  .O (bufg_fb_clk_s));
-      BUFG i_clk_0_bufg   (.I (mmcm_clk_0_s),   .O (mmcm_clk_0));
-      BUFG i_clk_1_bufg   (.I (mmcm_clk_1_s),   .O (mmcm_clk_1));
-      BUFG i_clk_2_bufg   (.I (mmcm_clk_2_s),   .O (mmcm_clk_2));
+      BUFG i_fb_clk_bufg (
+        .I (mmcm_fb_clk_s),
+        .O (bufg_fb_clk_s));
+
+      BUFG i_clk_0_bufg (
+        .I (mmcm_clk_0_s),
+        .O (mmcm_clk_0));
+
+      BUFG i_clk_1_bufg (
+        .I (mmcm_clk_1_s),
+        .O (mmcm_clk_1));
+
+      BUFG i_clk_2_bufg (
+        .I (mmcm_clk_2_s),
+        .O (mmcm_clk_2));
 
   end
   endgenerate
 
-
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/xilinx/common/ad_mul.v b/library/xilinx/common/ad_mul.v
index 9b64ebccc..30f38b6e3 100644
--- a/library/xilinx/common/ad_mul.v
+++ b/library/xilinx/common/ad_mul.v
@@ -39,7 +39,8 @@ module ad_mul #(
 
   parameter   A_DATA_WIDTH = 17,
   parameter   B_DATA_WIDTH = 17,
-  parameter   DELAY_DATA_WIDTH = 16) (
+  parameter   DELAY_DATA_WIDTH = 16
+) (
 
   // data_p = data_a * data_b;
 
@@ -51,8 +52,8 @@ module ad_mul #(
   // delay interface
 
   input       [(DELAY_DATA_WIDTH-1):0]  ddata_in,
-  output  reg [(DELAY_DATA_WIDTH-1):0]  ddata_out);
-
+  output  reg [(DELAY_DATA_WIDTH-1):0]  ddata_out
+);
 
   // internal registers
 
@@ -70,8 +71,8 @@ module ad_mul #(
   MULT_MACRO #(
     .LATENCY (3),
     .WIDTH_A (A_DATA_WIDTH),
-    .WIDTH_B (B_DATA_WIDTH))
-  i_mult_macro (
+    .WIDTH_B (B_DATA_WIDTH)
+  ) i_mult_macro (
     .CE (1'b1),
     .RST (1'b0),
     .CLK (clk),
@@ -80,6 +81,3 @@ module ad_mul #(
     .P (data_p));
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/xilinx/common/ad_serdes_clk.v b/library/xilinx/common/ad_serdes_clk.v
index c21e68de8..971de0910 100644
--- a/library/xilinx/common/ad_serdes_clk.v
+++ b/library/xilinx/common/ad_serdes_clk.v
@@ -47,7 +47,8 @@ module ad_serdes_clk #(
   parameter       MMCM_VCO_DIV  = 6,
   parameter       MMCM_VCO_MUL = 12.000,
   parameter       MMCM_CLK0_DIV = 2.000,
-  parameter       MMCM_CLK1_DIV = 6) (
+  parameter       MMCM_CLK1_DIV = 6
+) (
 
   // clock and divided clock
 
@@ -70,7 +71,8 @@ module ad_serdes_clk #(
   input   [31:0]  up_drp_wdata,
   output  [31:0]  up_drp_rdata,
   output          up_drp_ready,
-  output          up_drp_locked);
+  output          up_drp_locked
+);
 
   localparam BUFR_DIVIDE = (DDR_OR_SDR_N == 1'b1) ? SERDES_FACTOR / 2 : SERDES_FACTOR;
 
@@ -112,8 +114,8 @@ module ad_serdes_clk #(
       .MMCM_CLK1_DIV (MMCM_CLK1_DIV),
       .MMCM_CLK1_PHASE (0.0),
       .MMCM_CLK2_DIV (MMCM_CLK0_DIV),
-      .MMCM_CLK2_PHASE (90.0))
-    i_mmcm_drp (
+      .MMCM_CLK2_PHASE (90.0)
+    ) i_mmcm_drp (
       .clk (clk_in_s),
       .clk2 (1'b0),
       .clk_sel (1'b1),
@@ -139,7 +141,9 @@ module ad_serdes_clk #(
       .I (clk_in_s),
       .O (clk));
 
-    BUFR #(.BUFR_DIVIDE(BUFR_DIVIDE)) i_div_clk_buf (
+    BUFR #(
+      .BUFR_DIVIDE(BUFR_DIVIDE)
+    ) i_div_clk_buf (
       .CLR (1'b0),
       .CE (1'b1),
       .I (clk_in_s),
@@ -154,7 +158,3 @@ module ad_serdes_clk #(
   endgenerate
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
-
diff --git a/library/xilinx/common/ad_serdes_in.v b/library/xilinx/common/ad_serdes_in.v
index d4e1b20da..178d6c179 100644
--- a/library/xilinx/common/ad_serdes_in.v
+++ b/library/xilinx/common/ad_serdes_in.v
@@ -36,7 +36,6 @@
 `timescale 1ps/1ps
 
 module ad_serdes_in #(
-
   parameter   FPGA_TECHNOLOGY = 0,
   parameter   CMOS_LVDS_N = 0,
   parameter   DDR_OR_SDR_N = 0,
@@ -45,7 +44,8 @@ module ad_serdes_in #(
   parameter   DRP_WIDTH = 5,
   parameter   IODELAY_CTRL = 0,
   parameter   IODELAY_GROUP = "dev_if_delay_group",
-  parameter   REFCLK_FREQUENCY = 200) (
+  parameter   REFCLK_FREQUENCY = 200
+) (
 
   // reset and clocks
 
@@ -80,7 +80,8 @@ module ad_serdes_in #(
 
   input                           delay_clk,
   input                           delay_rst,
-  output                          delay_locked);
+  output                          delay_locked
+);
 
   localparam  SEVEN_SERIES  = 1;
   localparam  ULTRASCALE  = 2;
@@ -108,15 +109,15 @@ module ad_serdes_in #(
 
   generate
   if (IODELAY_CTRL == 1) begin
-  (* IODELAY_GROUP = IODELAY_GROUP *)
-  IDELAYCTRL #(
-    .SIM_DEVICE(SIM_DEVICE_IDELAYCTRL)
-  ) i_delay_ctrl (
-    .RST (delay_rst),
-    .REFCLK (delay_clk),
-    .RDY (delay_locked));
+    (* IODELAY_GROUP = IODELAY_GROUP *)
+    IDELAYCTRL #(
+      .SIM_DEVICE(SIM_DEVICE_IDELAYCTRL)
+    ) i_delay_ctrl (
+      .RST (delay_rst),
+      .REFCLK (delay_clk),
+      .RDY (delay_locked));
   end else begin
-  assign delay_locked = 1'b1;
+    assign delay_locked = 1'b1;
   end
   endgenerate
 
@@ -130,7 +131,7 @@ module ad_serdes_in #(
           .IB (data_in_n[l_inst]),
           .O (data_in_ibuf_s[l_inst]));
        end else begin
-        IBUF i_ibuf (
+         IBUF i_ibuf (
           .I (data_in_p[l_inst]),
           .O (data_in_ibuf_s[l_inst]));
        end
@@ -158,8 +159,8 @@ module ad_serdes_in #(
         .IDELAY_VALUE (0),
         .REFCLK_FREQUENCY (REFCLK_FREQUENCY),
         .PIPE_SEL ("FALSE"),
-        .SIGNAL_PATTERN ("DATA"))
-      i_idelay (
+        .SIGNAL_PATTERN ("DATA")
+      ) i_idelay (
         .CE (1'b0),
         .INC (1'b0),
         .DATAIN (1'b0),
@@ -190,8 +191,8 @@ module ad_serdes_in #(
         .SRVAL_Q1 (1'b0),
         .SRVAL_Q2 (1'b0),
         .SRVAL_Q3 (1'b0),
-        .SRVAL_Q4 (1'b0))
-      i_iserdes (
+        .SRVAL_Q4 (1'b0)
+      ) i_iserdes (
         .O (),
         .Q1 (data_s0[l_inst]),
         .Q2 (data_s1[l_inst]),
@@ -227,50 +228,45 @@ module ad_serdes_in #(
 
   generate if (FPGA_TECHNOLOGY == ULTRASCALE || FPGA_TECHNOLOGY == ULTRASCALE_PLUS) begin
 
-
     for (l_inst = 0; l_inst <= (DATA_WIDTH-1); l_inst = l_inst + 1) begin: g_data
 
     wire   div_dld;
     reg [4:0] vtc_cnt = {5{1'b1}};
 
-    sync_event  sync_load(
+    sync_event sync_load (
       .in_clk (up_clk),
       .in_event (up_dld[l_inst]),
       .out_clk (div_clk),
-      .out_event (div_dld)
-    );
+      .out_event (div_dld));
 
     (* IODELAY_GROUP = IODELAY_GROUP *)
     IDELAYE3 #(
-       .CASCADE ("NONE"),          // Cascade setting (MASTER, NONE, SLAVE_END, SLAVE_MIDDLE)
-       .DELAY_FORMAT ("TIME"),     // Units of the DELAY_VALUE (COUNT, TIME)
-       .DELAY_SRC ("IDATAIN"),     // Delay input (DATAIN, IDATAIN)
-       .DELAY_TYPE ("VAR_LOAD"),   // Set the type of tap delay line (FIXED, VARIABLE, VAR_LOAD)
-       .DELAY_VALUE (0),           // Input delay value setting
-       .IS_CLK_INVERTED (1'b0),    // Optional inversion for CLK
-       .IS_RST_INVERTED (1'b0),    // Optional inversion for RST
-       .REFCLK_FREQUENCY (500.0),  // IDELAYCTRL clock input frequency in MHz (200.0-2667.0)
-       .SIM_DEVICE (SIM_DEVICE),   // Set the device version (ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1,
-                                   // ULTRASCALE_PLUS_ES2)
-       .UPDATE_MODE ("ASYNC")      // Determines when updates to the delay will take effect (ASYNC, MANUAL, SYNC)
-    )
-    i_idelay(
-       .CASC_OUT (),                                       // 1-bit output: Cascade delay output to ODELAY input cascade
-       .CNTVALUEOUT (up_drdata[DRP_WIDTH*l_inst +: DRP_WIDTH]), // 9-bit output: Counter value output
-       .DATAOUT (data_in_idelay_s[l_inst]),                // 1-bit output: Delayed data output
-       .CASC_IN (1'b0),                                    // 1-bit input: Cascade delay input from slave ODELAY CASCADE_OUT
-       .CASC_RETURN (1'b0),                                // 1-bit input: Cascade delay returning from slave ODELAY DATAOUT
-       .CE (1'b0),                                         // 1-bit input: Active high enable increment/decrement input
-       .CLK (div_clk),                                     // 1-bit input: Clock input
-       .CNTVALUEIN (up_dwdata[DRP_WIDTH*l_inst +: DRP_WIDTH]),   // 9-bit input: Counter value input
-       .DATAIN (1'b0),                                     // 1-bit input: Data input from the logic
-       .EN_VTC (en_vtc),                                   // 1-bit input: Keep delay constant over VT
-       .IDATAIN (data_in_ibuf_s[l_inst]),                  // 1-bit input: Data input from the IOBUF
-       .INC (1'b0),                                        // 1-bit input: Increment / Decrement tap delay input
-       .LOAD (ld_cnt),                                     // 1-bit input: Load DELAY_VALUE input
-       .RST (rst)                                          // 1-bit input: Asynchronous Reset to the DELAY_VALUE
-    );
-
+      .CASCADE ("NONE"),          // Cascade setting (MASTER, NONE, SLAVE_END, SLAVE_MIDDLE)
+      .DELAY_FORMAT ("TIME"),     // Units of the DELAY_VALUE (COUNT, TIME)
+      .DELAY_SRC ("IDATAIN"),     // Delay input (DATAIN, IDATAIN)
+      .DELAY_TYPE ("VAR_LOAD"),   // Set the type of tap delay line (FIXED, VARIABLE, VAR_LOAD)
+      .DELAY_VALUE (0),           // Input delay value setting
+      .IS_CLK_INVERTED (1'b0),    // Optional inversion for CLK
+      .IS_RST_INVERTED (1'b0),    // Optional inversion for RST
+      .REFCLK_FREQUENCY (500.0),  // IDELAYCTRL clock input frequency in MHz (200.0-2667.0)
+      .SIM_DEVICE (SIM_DEVICE),   // Set the device version (ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1,
+                                  // ULTRASCALE_PLUS_ES2)
+      .UPDATE_MODE ("ASYNC")      // Determines when updates to the delay will take effect (ASYNC, MANUAL, SYNC)
+    ) i_idelay (
+      .CASC_OUT (),                                       // 1-bit output: Cascade delay output to ODELAY input cascade
+      .CNTVALUEOUT (up_drdata[DRP_WIDTH*l_inst +: DRP_WIDTH]), // 9-bit output: Counter value output
+      .DATAOUT (data_in_idelay_s[l_inst]),                // 1-bit output: Delayed data output
+      .CASC_IN (1'b0),                                    // 1-bit input: Cascade delay input from slave ODELAY CASCADE_OUT
+      .CASC_RETURN (1'b0),                                // 1-bit input: Cascade delay returning from slave ODELAY DATAOUT
+      .CE (1'b0),                                         // 1-bit input: Active high enable increment/decrement input
+      .CLK (div_clk),                                     // 1-bit input: Clock input
+      .CNTVALUEIN (up_dwdata[DRP_WIDTH*l_inst +: DRP_WIDTH]),   // 9-bit input: Counter value input
+      .DATAIN (1'b0),                                     // 1-bit input: Data input from the logic
+      .EN_VTC (en_vtc),                                   // 1-bit input: Keep delay constant over VT
+      .IDATAIN (data_in_ibuf_s[l_inst]),                  // 1-bit input: Data input from the IOBUF
+      .INC (1'b0),                                        // 1-bit input: Increment / Decrement tap delay input
+      .LOAD (ld_cnt),                                     // 1-bit input: Load DELAY_VALUE input
+      .RST (rst));                                        // 1-bit input: Asynchronous Reset to the DELAY_VALUE
 
     always @(posedge div_clk) begin
       if (div_dld) begin
@@ -284,41 +280,35 @@ module ad_serdes_in #(
     assign ld_cnt = ~vtc_cnt[4] & (&vtc_cnt[3:0]);
 
     ISERDESE3 #(
-       .DATA_WIDTH (8),            // Parallel data width (4,8)
-       .FIFO_ENABLE ("FALSE"),     // Enables the use of the FIFO
-       .FIFO_SYNC_MODE ("FALSE"),  // Enables the use of internal 2-stage synchronizers on the FIFO
-       .IS_CLK_B_INVERTED (1'b0),  // Optional inversion for CLK_B
-       .IS_CLK_INVERTED (1'b0),    // Optional inversion for CLK
-       .IS_RST_INVERTED (1'b0),    // Optional inversion for RST
-       .SIM_DEVICE (SIM_DEVICE)    // Set the device version (ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1,
-                                   // ULTRASCALE_PLUS_ES2)
-    )
-    i_iserdes(
-       .FIFO_EMPTY (),                // 1-bit output: FIFO empty flag
-       .INTERNAL_DIVCLK (),           // 1-bit output: Internally divided down clock used when FIFO is
-                                      // disabled (do not connect)
-
-       .Q ({data_s0[l_inst],
-            data_s1[l_inst],
-            data_s2[l_inst],
-            data_s3[l_inst],
-            data_s4[l_inst],
-            data_s5[l_inst],
-            data_s6[l_inst],
-            data_s7[l_inst]}),        // 8-bit registered output
-       .CLK (clk),                    // 1-bit input: High-speed clock
-       .CLKDIV (div_clk),             // 1-bit input: Divided Clock
-       .CLK_B (~clk),                 // 1-bit input: Inversion of High-speed clock CLK
-       .D (data_in_idelay_s[l_inst]), // 1-bit input: Serial Data Input
-       .FIFO_RD_CLK (div_clk),        // 1-bit input: FIFO read clock
-       .FIFO_RD_EN (1'b1),            // 1-bit input: Enables reading the FIFO when asserted
-       .RST (serdes_rst)             // 1-bit input: Asynchronous Reset
-    );
+      .DATA_WIDTH (8),            // Parallel data width (4,8)
+      .FIFO_ENABLE ("FALSE"),     // Enables the use of the FIFO
+      .FIFO_SYNC_MODE ("FALSE"),  // Enables the use of internal 2-stage synchronizers on the FIFO
+      .IS_CLK_B_INVERTED (1'b0),  // Optional inversion for CLK_B
+      .IS_CLK_INVERTED (1'b0),    // Optional inversion for CLK
+      .IS_RST_INVERTED (1'b0),    // Optional inversion for RST
+      .SIM_DEVICE (SIM_DEVICE)    // Set the device version (ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1,
+                                  // ULTRASCALE_PLUS_ES2)
+    ) i_iserdes(
+      .FIFO_EMPTY (),                // 1-bit output: FIFO empty flag
+      .INTERNAL_DIVCLK (),           // 1-bit output: Internally divided down clock used when FIFO is
+                                     // disabled (do not connect)
+      .Q ({data_s0[l_inst],
+           data_s1[l_inst],
+           data_s2[l_inst],
+           data_s3[l_inst],
+           data_s4[l_inst],
+           data_s5[l_inst],
+           data_s6[l_inst],
+           data_s7[l_inst]}),        // 8-bit registered output
+      .CLK (clk),                    // 1-bit input: High-speed clock
+      .CLKDIV (div_clk),             // 1-bit input: Divided Clock
+      .CLK_B (~clk),                 // 1-bit input: Inversion of High-speed clock CLK
+      .D (data_in_idelay_s[l_inst]), // 1-bit input: Serial Data Input
+      .FIFO_RD_CLK (div_clk),        // 1-bit input: FIFO read clock
+      .FIFO_RD_EN (1'b1),            // 1-bit input: Enables reading the FIFO when asserted
+      .RST (serdes_rst));            // 1-bit input: Asynchronous Reset
    end
   end
   endgenerate
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
diff --git a/library/xilinx/common/ad_serdes_out.v b/library/xilinx/common/ad_serdes_out.v
index adb3b51dd..4322b5d1e 100644
--- a/library/xilinx/common/ad_serdes_out.v
+++ b/library/xilinx/common/ad_serdes_out.v
@@ -42,7 +42,8 @@ module ad_serdes_out #(
   parameter   CMOS_LVDS_N = 0,
   parameter   DDR_OR_SDR_N = 1,
   parameter   SERDES_FACTOR = 8,
-  parameter   DATA_WIDTH = 16) (
+  parameter   DATA_WIDTH = 16
+) (
 
   // reset and clocks
 
@@ -63,7 +64,8 @@ module ad_serdes_out #(
   input   [(DATA_WIDTH-1):0]  data_s7,   // last bit to be transmitted
   output  [(DATA_WIDTH-1):0]  data_out_se,
   output  [(DATA_WIDTH-1):0]  data_out_p,
-  output  [(DATA_WIDTH-1):0]  data_out_n);
+  output  [(DATA_WIDTH-1):0]  data_out_n
+);
 
   localparam  SEVEN_SERIES  = 1;
   localparam  ULTRASCALE  = 2;
@@ -75,7 +77,6 @@ module ad_serdes_out #(
                           FPGA_TECHNOLOGY == ULTRASCALE_PLUS ? "ULTRASCALE_PLUS" :
                           "UNSUPPORTED";
 
-
   // internal signals
 
   wire    [(DATA_WIDTH-1):0]  data_out_s;
@@ -108,8 +109,8 @@ module ad_serdes_out #(
         .DATA_RATE_TQ ("SDR"),
         .DATA_WIDTH (SERDES_FACTOR),
         .TRISTATE_WIDTH (1),
-        .SERDES_MODE ("MASTER"))
-      i_serdes (
+        .SERDES_MODE ("MASTER")
+      ) i_serdes (
         .D1 (data_s0[l_inst]),
         .D2 (data_s1[l_inst]),
         .D3 (data_s2[l_inst]),
@@ -142,8 +143,8 @@ module ad_serdes_out #(
     if (FPGA_TECHNOLOGY == ULTRASCALE || FPGA_TECHNOLOGY == ULTRASCALE_PLUS) begin
       OSERDESE3  #(
         .DATA_WIDTH (SERDES_FACTOR),
-        .SIM_DEVICE (SIM_DEVICE))
-      i_serdes (
+        .SIM_DEVICE (SIM_DEVICE)
+      ) i_serdes (
         .D ({data_s7[l_inst],
              data_s6[l_inst],
              data_s5[l_inst],
@@ -181,7 +182,3 @@ module ad_serdes_out #(
   endgenerate
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
-
diff --git a/library/xilinx/util_adxcvr/util_adxcvr.v b/library/xilinx/util_adxcvr/util_adxcvr.v
index e95a90dbe..b99e32d54 100644
--- a/library/xilinx/util_adxcvr/util_adxcvr.v
+++ b/library/xilinx/util_adxcvr/util_adxcvr.v
@@ -121,8 +121,8 @@ module util_adxcvr #(
   parameter   [15:0]  TXPI_CFG0 = 16'b0000001100000000,
   parameter   [15:0]  TXPI_CFG1 = 16'b0001000000000000,
   parameter   integer TXSWBST_EN = 0,
-  parameter   integer RX_LANE_INVERT = 0) (
-
+  parameter   integer RX_LANE_INVERT = 0
+) (
   input           up_rstn,
   input           up_clk,
 
@@ -1356,7 +1356,8 @@ module util_adxcvr #(
   input           up_tx_wr_15,
   input   [15:0]  up_tx_wdata_15,
   output  [15:0]  up_tx_rdata_15,
-  output          up_tx_ready_15);
+  output          up_tx_ready_15
+);
 
   // parameters
 
@@ -1433,8 +1434,8 @@ module util_adxcvr #(
     .QPLL_CP_G3 (QPLL_CP_G3),
     .QPLL_LPF (QPLL_LPF),
     .QPLL_CP (QPLL_CP),
-    .QPLL_CFG4 (QPLL_CFG4))
-  i_xcm_0 (
+    .QPLL_CFG4 (QPLL_CFG4)
+  ) i_xcm_0 (
     .qpll_ref_clk (qpll_ref_clk_0),
     .qpll_sel (qpll_sel_0),
     .qpll2ch_clk (qpll2ch_clk_0),
@@ -1512,8 +1513,8 @@ module util_adxcvr #(
     .PREIQ_FREQ_BST (PREIQ_FREQ_BST),
     .RXPI_CFG0 (RXPI_CFG0),
     .RXPI_CFG1 (RXPI_CFG1),
-    .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL))
-  i_xch_0 (
+    .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL)
+  ) i_xch_0 (
     .qpll2ch_clk (qpll2ch_clk_0),
     .qpll2ch_ref_clk (qpll2ch_ref_clk_0),
     .qpll2ch_locked (qpll2ch_locked_0),
@@ -1615,7 +1616,6 @@ module util_adxcvr #(
   end
   endgenerate
 
-
   generate
   if (NUM_OF_LANES >= 2) begin
   util_adxcvr_xch #(
@@ -1664,8 +1664,8 @@ module util_adxcvr #(
     .PREIQ_FREQ_BST (PREIQ_FREQ_BST),
     .RXPI_CFG0 (RXPI_CFG0),
     .RXPI_CFG1 (RXPI_CFG1),
-    .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL))
-  i_xch_1 (
+    .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL)
+  ) i_xch_1 (
     .qpll2ch_clk (qpll2ch_clk_0),
     .qpll2ch_ref_clk (qpll2ch_ref_clk_0),
     .qpll2ch_locked (qpll2ch_locked_0),
@@ -1767,7 +1767,6 @@ module util_adxcvr #(
   end
   endgenerate
 
-
   generate
   if (NUM_OF_LANES >= 3) begin
   util_adxcvr_xch #(
@@ -1816,8 +1815,8 @@ module util_adxcvr #(
     .PREIQ_FREQ_BST (PREIQ_FREQ_BST),
     .RXPI_CFG0 (RXPI_CFG0),
     .RXPI_CFG1 (RXPI_CFG1),
-    .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL))
-  i_xch_2 (
+    .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL)
+  ) i_xch_2 (
     .qpll2ch_clk (qpll2ch_clk_0),
     .qpll2ch_ref_clk (qpll2ch_ref_clk_0),
     .qpll2ch_locked (qpll2ch_locked_0),
@@ -1919,7 +1918,6 @@ module util_adxcvr #(
   end
   endgenerate
 
-
   generate
   if (NUM_OF_LANES >= 4) begin
   util_adxcvr_xch #(
@@ -1968,8 +1966,8 @@ module util_adxcvr #(
     .PREIQ_FREQ_BST (PREIQ_FREQ_BST),
     .RXPI_CFG0 (RXPI_CFG0),
     .RXPI_CFG1 (RXPI_CFG1),
-    .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL))
-  i_xch_3 (
+    .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL)
+  ) i_xch_3 (
     .qpll2ch_clk (qpll2ch_clk_0),
     .qpll2ch_ref_clk (qpll2ch_ref_clk_0),
     .qpll2ch_locked (qpll2ch_locked_0),
@@ -2091,8 +2089,8 @@ module util_adxcvr #(
     .QPLL_CP_G3 (QPLL_CP_G3),
     .QPLL_LPF (QPLL_LPF),
     .QPLL_CP (QPLL_CP),
-    .QPLL_CFG4 (QPLL_CFG4))
-  i_xcm_4 (
+    .QPLL_CFG4 (QPLL_CFG4)
+  ) i_xcm_4 (
     .qpll_ref_clk (qpll_ref_clk_4),
     .qpll_sel (qpll_sel_4),
     .qpll2ch_clk (qpll2ch_clk_4),
@@ -2170,8 +2168,8 @@ module util_adxcvr #(
     .PREIQ_FREQ_BST (PREIQ_FREQ_BST),
     .RXPI_CFG0 (RXPI_CFG0),
     .RXPI_CFG1 (RXPI_CFG1),
-    .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL))
-  i_xch_4 (
+    .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL)
+  ) i_xch_4 (
     .qpll2ch_clk (qpll2ch_clk_4),
     .qpll2ch_ref_clk (qpll2ch_ref_clk_4),
     .qpll2ch_locked (qpll2ch_locked_4),
@@ -2273,7 +2271,6 @@ module util_adxcvr #(
   end
   endgenerate
 
-
   generate
   if (NUM_OF_LANES >= 6) begin
   util_adxcvr_xch #(
@@ -2322,8 +2319,8 @@ module util_adxcvr #(
     .PREIQ_FREQ_BST (PREIQ_FREQ_BST),
     .RXPI_CFG0 (RXPI_CFG0),
     .RXPI_CFG1 (RXPI_CFG1),
-    .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL))
-  i_xch_5 (
+    .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL)
+  ) i_xch_5 (
     .qpll2ch_clk (qpll2ch_clk_4),
     .qpll2ch_ref_clk (qpll2ch_ref_clk_4),
     .qpll2ch_locked (qpll2ch_locked_4),
@@ -2425,7 +2422,6 @@ module util_adxcvr #(
   end
   endgenerate
 
-
   generate
   if (NUM_OF_LANES >= 7) begin
   util_adxcvr_xch #(
@@ -2474,8 +2470,8 @@ module util_adxcvr #(
     .PREIQ_FREQ_BST (PREIQ_FREQ_BST),
     .RXPI_CFG0 (RXPI_CFG0),
     .RXPI_CFG1 (RXPI_CFG1),
-    .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL))
-  i_xch_6 (
+    .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL)
+  ) i_xch_6 (
     .qpll2ch_clk (qpll2ch_clk_4),
     .qpll2ch_ref_clk (qpll2ch_ref_clk_4),
     .qpll2ch_locked (qpll2ch_locked_4),
@@ -2577,7 +2573,6 @@ module util_adxcvr #(
   end
   endgenerate
 
-
   generate
   if (NUM_OF_LANES >= 8) begin
   util_adxcvr_xch #(
@@ -2626,8 +2621,8 @@ module util_adxcvr #(
     .PREIQ_FREQ_BST (PREIQ_FREQ_BST),
     .RXPI_CFG0 (RXPI_CFG0),
     .RXPI_CFG1 (RXPI_CFG1),
-    .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL))
-  i_xch_7 (
+    .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL)
+  ) i_xch_7 (
     .qpll2ch_clk (qpll2ch_clk_4),
     .qpll2ch_ref_clk (qpll2ch_ref_clk_4),
     .qpll2ch_locked (qpll2ch_locked_4),
@@ -2749,8 +2744,8 @@ module util_adxcvr #(
     .QPLL_CP_G3 (QPLL_CP_G3),
     .QPLL_LPF (QPLL_LPF),
     .QPLL_CP (QPLL_CP),
-    .QPLL_CFG4 (QPLL_CFG4))
-  i_xcm_8 (
+    .QPLL_CFG4 (QPLL_CFG4)
+  ) i_xcm_8 (
     .qpll_ref_clk (qpll_ref_clk_8),
     .qpll_sel (qpll_sel_8),
     .qpll2ch_clk (qpll2ch_clk_8),
@@ -2828,8 +2823,8 @@ module util_adxcvr #(
     .PREIQ_FREQ_BST (PREIQ_FREQ_BST),
     .RXPI_CFG0 (RXPI_CFG0),
     .RXPI_CFG1 (RXPI_CFG1),
-    .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL))
-  i_xch_8 (
+    .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL)
+  ) i_xch_8 (
     .qpll2ch_clk (qpll2ch_clk_8),
     .qpll2ch_ref_clk (qpll2ch_ref_clk_8),
     .qpll2ch_locked (qpll2ch_locked_8),
@@ -2931,7 +2926,6 @@ module util_adxcvr #(
   end
   endgenerate
 
-
   generate
   if (NUM_OF_LANES >= 10) begin
   util_adxcvr_xch #(
@@ -2980,8 +2974,8 @@ module util_adxcvr #(
     .PREIQ_FREQ_BST (PREIQ_FREQ_BST),
     .RXPI_CFG0 (RXPI_CFG0),
     .RXPI_CFG1 (RXPI_CFG1),
-    .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL))
-  i_xch_9 (
+    .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL)
+  ) i_xch_9 (
     .qpll2ch_clk (qpll2ch_clk_8),
     .qpll2ch_ref_clk (qpll2ch_ref_clk_8),
     .qpll2ch_locked (qpll2ch_locked_8),
@@ -3083,7 +3077,6 @@ module util_adxcvr #(
   end
   endgenerate
 
-
   generate
   if (NUM_OF_LANES >= 11) begin
   util_adxcvr_xch #(
@@ -3132,8 +3125,8 @@ module util_adxcvr #(
     .PREIQ_FREQ_BST (PREIQ_FREQ_BST),
     .RXPI_CFG0 (RXPI_CFG0),
     .RXPI_CFG1 (RXPI_CFG1),
-    .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL))
-  i_xch_10 (
+    .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL)
+  ) i_xch_10 (
     .qpll2ch_clk (qpll2ch_clk_8),
     .qpll2ch_ref_clk (qpll2ch_ref_clk_8),
     .qpll2ch_locked (qpll2ch_locked_8),
@@ -3235,7 +3228,6 @@ module util_adxcvr #(
   end
   endgenerate
 
-
   generate
   if (NUM_OF_LANES >= 12) begin
   util_adxcvr_xch #(
@@ -3284,8 +3276,8 @@ module util_adxcvr #(
     .PREIQ_FREQ_BST (PREIQ_FREQ_BST),
     .RXPI_CFG0 (RXPI_CFG0),
     .RXPI_CFG1 (RXPI_CFG1),
-    .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL))
-  i_xch_11 (
+    .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL)
+  ) i_xch_11 (
     .qpll2ch_clk (qpll2ch_clk_8),
     .qpll2ch_ref_clk (qpll2ch_ref_clk_8),
     .qpll2ch_locked (qpll2ch_locked_8),
@@ -3407,8 +3399,8 @@ module util_adxcvr #(
     .QPLL_CP_G3 (QPLL_CP_G3),
     .QPLL_LPF (QPLL_LPF),
     .QPLL_CP (QPLL_CP),
-    .QPLL_CFG4 (QPLL_CFG4))
-  i_xcm_12 (
+    .QPLL_CFG4 (QPLL_CFG4)
+  ) i_xcm_12 (
     .qpll_ref_clk (qpll_ref_clk_12),
     .qpll_sel (qpll_sel_12),
     .qpll2ch_clk (qpll2ch_clk_12),
@@ -3486,8 +3478,8 @@ module util_adxcvr #(
     .PREIQ_FREQ_BST (PREIQ_FREQ_BST),
     .RXPI_CFG0 (RXPI_CFG0),
     .RXPI_CFG1 (RXPI_CFG1),
-    .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL))
-  i_xch_12 (
+    .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL)
+  ) i_xch_12 (
     .qpll2ch_clk (qpll2ch_clk_12),
     .qpll2ch_ref_clk (qpll2ch_ref_clk_12),
     .qpll2ch_locked (qpll2ch_locked_12),
@@ -3589,7 +3581,6 @@ module util_adxcvr #(
   end
   endgenerate
 
-
   generate
   if (NUM_OF_LANES >= 14) begin
   util_adxcvr_xch #(
@@ -3638,8 +3629,8 @@ module util_adxcvr #(
     .PREIQ_FREQ_BST (PREIQ_FREQ_BST),
     .RXPI_CFG0 (RXPI_CFG0),
     .RXPI_CFG1 (RXPI_CFG1),
-    .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL))
-  i_xch_13 (
+    .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL)
+  ) i_xch_13 (
     .qpll2ch_clk (qpll2ch_clk_12),
     .qpll2ch_ref_clk (qpll2ch_ref_clk_12),
     .qpll2ch_locked (qpll2ch_locked_12),
@@ -3741,7 +3732,6 @@ module util_adxcvr #(
   end
   endgenerate
 
-
   generate
   if (NUM_OF_LANES >= 15) begin
   util_adxcvr_xch #(
@@ -3790,8 +3780,8 @@ module util_adxcvr #(
     .PREIQ_FREQ_BST (PREIQ_FREQ_BST),
     .RXPI_CFG0 (RXPI_CFG0),
     .RXPI_CFG1 (RXPI_CFG1),
-    .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL))
-  i_xch_14 (
+    .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL)
+  ) i_xch_14 (
     .qpll2ch_clk (qpll2ch_clk_12),
     .qpll2ch_ref_clk (qpll2ch_ref_clk_12),
     .qpll2ch_locked (qpll2ch_locked_12),
@@ -3893,7 +3883,6 @@ module util_adxcvr #(
   end
   endgenerate
 
-
   generate
   if (NUM_OF_LANES >= 16) begin
   util_adxcvr_xch #(
@@ -3942,8 +3931,8 @@ module util_adxcvr #(
     .PREIQ_FREQ_BST (PREIQ_FREQ_BST),
     .RXPI_CFG0 (RXPI_CFG0),
     .RXPI_CFG1 (RXPI_CFG1),
-    .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL))
-  i_xch_15 (
+    .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL)
+  ) i_xch_15 (
     .qpll2ch_clk (qpll2ch_clk_12),
     .qpll2ch_ref_clk (qpll2ch_ref_clk_12),
     .qpll2ch_locked (qpll2ch_locked_12),
@@ -4046,7 +4035,3 @@ module util_adxcvr #(
   endgenerate
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
-
diff --git a/library/xilinx/util_adxcvr/util_adxcvr_xch.v b/library/xilinx/util_adxcvr/util_adxcvr_xch.v
index 64b0d2552..f05c05361 100644
--- a/library/xilinx/util_adxcvr/util_adxcvr_xch.v
+++ b/library/xilinx/util_adxcvr/util_adxcvr_xch.v
@@ -91,7 +91,8 @@ module util_adxcvr_xch #(
   parameter   [15:0]  TXPI_CFG0 = 16'b0000001100000000,
   parameter   [15:0]  TXPI_CFG1 = 16'b0001000000000000,
   parameter   integer TXSWBST_EN = 0,
-  parameter   integer RX_POLARITY = 0) (
+  parameter   integer RX_POLARITY = 0
+) (
 
   // pll interface
 
@@ -355,14 +356,15 @@ module util_adxcvr_xch #(
   wire [ 3:0] rx_prbssel;
   reg         rx_prbserr_sticky = 1'b0;
 
-  sync_bits #(.NUM_OF_BITS(5)) i_sync_bits_rx_prbs_in (
+  sync_bits #(
+    .NUM_OF_BITS(5)
+  ) i_sync_bits_rx_prbs_in (
     .in_bits ({up_rx_prbssel,
                up_rx_prbscntreset}),
     .out_resetn (1'b1),
     .out_clk (rx_clk),
     .out_bits ({rx_prbssel,
-                rx_prbscntreset})
-  );
+                rx_prbscntreset}));
 
   always @(posedge rx_clk) begin
     if (rx_prbscntreset) begin
@@ -372,44 +374,47 @@ module util_adxcvr_xch #(
     end
   end
 
-  sync_bits #(.NUM_OF_BITS(2)) i_sync_bits_rx_prbs_out (
+  sync_bits #(
+    .NUM_OF_BITS(2)
+  ) i_sync_bits_rx_prbs_out (
     .in_bits ({rx_prbslocked,
                rx_prbserr_sticky}),
     .out_resetn (up_rstn),
     .out_clk (up_clk),
     .out_bits ({up_rx_prbslocked,
-                up_rx_prbserr})
-  );
+                up_rx_prbserr}));
 
   // Tx PRBS interface logic
   wire        tx_prbsforceerr;
   wire [ 3:0] tx_prbssel;
 
-  sync_bits #(.NUM_OF_BITS(5)) i_sync_bits_tx_prbs_in (
+  sync_bits #(
+    .NUM_OF_BITS(5)
+  ) i_sync_bits_tx_prbs_in (
     .in_bits ({up_tx_prbssel,
                up_tx_prbsforceerr}),
     .out_resetn (1'b1),
     .out_clk (tx_clk),
     .out_bits ({tx_prbssel,
-                tx_prbsforceerr})
-  );
-  
-  // Bufstatus 
+                tx_prbsforceerr}));
+
+  // Bufstatus
   reg         rx_bufstatus_sticky_0 = 1'b0;
   reg         rx_bufstatus_sticky_1 = 1'b0;
-  
+
   wire        rx_bufstatus_rst;
   wire [ 1:0] rx_bufstatus;
   wire [ 1:0] rx_bufstatus_s;
   wire [ 1:0] tx_bufstatus;
   wire [ 1:0] tx_bufstatus_s;
-  
-  sync_bits #(.NUM_OF_BITS(1)) i_sync_bits_rx_bufstatus_in (
+
+  sync_bits #(
+    .NUM_OF_BITS(1)
+  ) i_sync_bits_rx_bufstatus_in (
     .in_bits (up_rx_bufstatus_rst),
     .out_resetn (1'b1),
     .out_clk (rx_clk),
-    .out_bits (rx_bufstatus_rst)
-  );
+    .out_bits (rx_bufstatus_rst));
 
   always @(posedge rx_clk) begin
     if (rx_bufstatus_rst) begin
@@ -418,7 +423,7 @@ module util_adxcvr_xch #(
       rx_bufstatus_sticky_0 <= 1'b1;
     end
   end
-  
+
   always @(posedge rx_clk) begin
     if (rx_bufstatus_rst) begin
       rx_bufstatus_sticky_1 <= 1'b0;
@@ -426,16 +431,17 @@ module util_adxcvr_xch #(
       rx_bufstatus_sticky_1 <= 1'b1;
     end
   end
-  
-  sync_bits #(.NUM_OF_BITS(4)) i_sync_bits_bufstatus_out (
-      .in_bits ({rx_bufstatus,
-                 tx_bufstatus}),
-      .out_resetn (up_rstn),
-      .out_clk (up_clk),
-      .out_bits ({up_rx_bufstatus,
-                  up_tx_bufstatus})
-    );
-  
+
+  sync_bits #(
+    .NUM_OF_BITS(4)
+  ) i_sync_bits_bufstatus_out (
+    .in_bits ({rx_bufstatus,
+               tx_bufstatus}),
+    .out_resetn (up_rstn),
+    .out_clk (up_clk),
+    .out_bits ({up_rx_bufstatus,
+                up_tx_bufstatus}));
+
   // 204C specific logic
   localparam ALIGN_COMMA_ENABLE  = LINK_MODE[1] ? 10'b0000000000 : 10'b1111111111;
   localparam ALIGN_MCOMMA_DET = LINK_MODE[1] ? "FALSE" : "TRUE";
@@ -485,20 +491,20 @@ module util_adxcvr_xch #(
         .i_slip_done(rx_bitslip_d[3]),
         .o_data(rx_data),
         .o_header(rx_header),
-        .o_block_sync(rx_block_sync)
-      );
+        .o_block_sync(rx_block_sync));
+
       assign tx_data_s = {64'd0, tx_data};
 
       assign rx_usrclk = (XCVR_TYPE==GTHE3_TRANSCEIVERS) ||
                          (XCVR_TYPE==GTHE4_TRANSCEIVERS) ? rx_clk_2x : rx_clk;
       assign tx_usrclk = (XCVR_TYPE==GTHE3_TRANSCEIVERS) ||
                          (XCVR_TYPE==GTHE4_TRANSCEIVERS) ? tx_clk_2x : tx_clk;
-						 
+
       assign rx_bufstatus[0] = rx_bufstatus_sticky_0;
       assign rx_bufstatus[1] = rx_bufstatus_sticky_1;
-	  
+
       assign tx_bufstatus = tx_bufstatus_s;
-	  
+
     end else begin
 
       assign {rx_data_open_s, rx_data} = rx_data_s;
@@ -507,10 +513,10 @@ module util_adxcvr_xch #(
 
       assign rx_usrclk = rx_clk;
       assign tx_usrclk = tx_clk;
-	  
+
       assign rx_bufstatus[0] = rx_bufstatus_sticky_1;
       assign rx_bufstatus[1] = rx_bufstatus_sticky_1;
-	  
+
       assign tx_bufstatus[0] = tx_bufstatus_s[1];
       assign tx_bufstatus[1] = tx_bufstatus_s[1];
     end
@@ -520,8 +526,13 @@ module util_adxcvr_xch #(
 
   generate
   if (XCVR_TYPE == GTXE2_TRANSCEIVERS) begin
-  BUFG i_rx_bufg (.I (rx_out_clk_s), .O (rx_out_clk));
-  BUFG i_tx_bufg (.I (tx_out_clk_s), .O (tx_out_clk));
+    BUFG i_rx_bufg (
+      .I (rx_out_clk_s),
+      .O (rx_out_clk));
+
+    BUFG i_tx_bufg (
+      .I (tx_out_clk_s),
+      .O (tx_out_clk));
   end
   endgenerate
 
@@ -743,8 +754,8 @@ module util_adxcvr_xch #(
     .TX_RXDETECT_CFG (14'h1832),
     .TX_RXDETECT_REF (3'b100),
     .TX_XCLK_SEL ("TXOUT"),
-    .UCODEER_CLR (1'b0))
-  i_gtxe2_channel (
+    .UCODEER_CLR (1'b0)
+  ) i_gtxe2_channel (
     .RXOUTCLKPCS (),
     .RXPHSLIPMONITOR (),
     .PHYSTATUS (),
@@ -1009,7 +1020,7 @@ module util_adxcvr_xch #(
     .I (rx_out_clk_s),
     .O (rx_out_clk_div2));
 
-    BUFG_GT i_tx_div2_bufg (
+  BUFG_GT i_tx_div2_bufg (
     .CE (1'b1),
     .CEMASK (1'b0),
     .CLR (1'b0),
@@ -1419,8 +1430,8 @@ module util_adxcvr_xch #(
     .TX_SARC_LPBK_ENB (1'b0),
     .TX_XCLK_SEL ("TXOUT"),
     .USE_PCS_CLK_PHASE_SEL (1'b0),
-    .WB_MODE (2'b00))
-  i_gthe3_channel (
+    .WB_MODE (2'b00)
+  ) i_gthe3_channel (
     .BUFGTCE (),
     .BUFGTCEMASK (),
     .BUFGTDIV (),
@@ -1782,7 +1793,7 @@ module util_adxcvr_xch #(
     .I (rx_out_clk_s),
     .O (rx_out_clk_div2));
 
-    BUFG_GT i_tx_div2_bufg (
+  BUFG_GT i_tx_div2_bufg (
     .CE (1'b1),
     .CEMASK (1'b0),
     .CLR (1'b0),
@@ -2307,8 +2318,8 @@ module util_adxcvr_xch #(
     .USB_U2_SAS_MAX_COM (64),
     .USB_U2_SAS_MIN_COM (36),
     .USE_PCS_CLK_PHASE_SEL (1'b0),
-    .Y_ALL_MODE (1'b0))
-  i_gthe4_channel (
+    .Y_ALL_MODE (1'b0)
+  ) i_gthe4_channel (
     .BUFGTCE (),
     .BUFGTCEMASK (),
     .BUFGTDIV (),
@@ -3178,8 +3189,8 @@ module util_adxcvr_xch #(
       .USB_U2_SAS_MAX_COM (64),
       .USB_U2_SAS_MIN_COM (36),
       .USE_PCS_CLK_PHASE_SEL (1'b0),
-      .Y_ALL_MODE (1'b0))
-    i_gtye4_channel (
+      .Y_ALL_MODE (1'b0)
+    ) i_gtye4_channel (
       .CDRSTEPDIR (1'b0),
       .CDRSTEPSQ (1'b0),
       .CDRSTEPSX (1'b0),
@@ -3511,13 +3522,7 @@ module util_adxcvr_xch #(
       .TXRATEDONE (),
       .TXRESETDONE (tx_rst_done_s),
       .TXSYNCDONE (),
-      .TXSYNCOUT ()
-    );
-
+      .TXSYNCOUT ());
   end
   endgenerate
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
-
diff --git a/library/xilinx/util_adxcvr/util_adxcvr_xcm.v b/library/xilinx/util_adxcvr/util_adxcvr_xcm.v
index 6a1c22832..ece8276ad 100644
--- a/library/xilinx/util_adxcvr/util_adxcvr_xcm.v
+++ b/library/xilinx/util_adxcvr/util_adxcvr_xcm.v
@@ -57,7 +57,6 @@ module util_adxcvr_xcm #(
   parameter   [15:0]  QPLL_CP_G3 = 10'b0000011111,
   parameter   [15:0]  QPLL_LPF = 10'b0100110111,
   parameter   [15:0]  QPLL_CP = 10'b0001111111
-
 ) (
 
   // reset and clocks
@@ -82,7 +81,8 @@ module util_adxcvr_xcm #(
   input           up_cm_wr,
   input   [15:0]  up_cm_wdata,
   output  [15:0]  up_cm_rdata,
-  output          up_cm_ready);
+  output          up_cm_ready
+);
 
   localparam GTXE2_TRANSCEIVERS = 2;
   localparam GTHE3_TRANSCEIVERS = 5;
@@ -738,7 +738,3 @@ module util_adxcvr_xcm #(
   endgenerate
 
 endmodule
-
-// ***************************************************************************
-// ***************************************************************************
-
diff --git a/library/xilinx/util_clkdiv/util_clkdiv.v b/library/xilinx/util_clkdiv/util_clkdiv.v
index 0a6c78bdb..4864ef0fc 100644
--- a/library/xilinx/util_clkdiv/util_clkdiv.v
+++ b/library/xilinx/util_clkdiv/util_clkdiv.v
@@ -39,54 +39,54 @@ module util_clkdiv (
   input   clk,
   input   clk_sel,
   output  clk_out
- );
+);
 
-parameter SIM_DEVICE = "7SERIES";
-parameter SEL_0_DIV = "4";
-parameter SEL_1_DIV = "2";
+  parameter SIM_DEVICE = "7SERIES";
+  parameter SEL_0_DIV = "4";
+  parameter SEL_1_DIV = "2";
 
   wire clk_div_sel_0_s;
   wire clk_div_sel_1_s;
 
-generate if (SIM_DEVICE == "7SERIES") begin
+  generate if (SIM_DEVICE == "7SERIES") begin
 
-  BUFR #(
-    .BUFR_DIVIDE(SEL_0_DIV),
-    .SIM_DEVICE("7SERIES")
-  ) clk_divide_sel_0 (
-    .I(clk),
-    .CE(1),
-    .CLR(0),
-    .O(clk_div_sel_0_s));
+    BUFR #(
+      .BUFR_DIVIDE(SEL_0_DIV),
+      .SIM_DEVICE("7SERIES")
+    ) clk_divide_sel_0 (
+      .I(clk),
+      .CE(1),
+      .CLR(0),
+      .O(clk_div_sel_0_s));
 
-  BUFR #(
-    .BUFR_DIVIDE(SEL_1_DIV),
-    .SIM_DEVICE("7SERIES")
-  ) clk_divide_sel_1 (
-    .I(clk),
-    .CE(1),
-    .CLR(0),
-    .O(clk_div_sel_1_s));
+    BUFR #(
+      .BUFR_DIVIDE(SEL_1_DIV),
+      .SIM_DEVICE("7SERIES")
+    ) clk_divide_sel_1 (
+      .I(clk),
+      .CE(1),
+      .CLR(0),
+      .O(clk_div_sel_1_s));
 
-end else if (SIM_DEVICE == "ULTRASCALE") begin
+  end else if (SIM_DEVICE == "ULTRASCALE") begin
 
-  BUFGCE_DIV #(
-    .BUFGCE_DIVIDE(SEL_0_DIV)
-  ) clk_divide_sel_0 (
-    .I(clk),
-    .CE(1),
-    .CLR(0),
-    .O(clk_div_sel_0_s));
+    BUFGCE_DIV #(
+      .BUFGCE_DIVIDE(SEL_0_DIV)
+    ) clk_divide_sel_0 (
+      .I(clk),
+      .CE(1),
+      .CLR(0),
+      .O(clk_div_sel_0_s));
 
-  BUFGCE_DIV #(
-    .BUFGCE_DIVIDE(SEL_1_DIV)
-  ) clk_divide_sel_1 (
-    .I(clk),
-    .CE(1),
-    .CLR(0),
-    .O(clk_div_sel_1_s));
+    BUFGCE_DIV #(
+      .BUFGCE_DIVIDE(SEL_1_DIV)
+    ) clk_divide_sel_1 (
+      .I(clk),
+      .CE(1),
+      .CLR(0),
+      .O(clk_div_sel_1_s));
 
-end endgenerate
+  end endgenerate
 
   BUFGMUX_CTRL i_div_clk_gbuf (
     .I0(clk_div_sel_0_s), // 1-bit input: Clock input (S=0)
@@ -94,5 +94,4 @@ end endgenerate
     .S(clk_sel),
     .O (clk_out));
 
-endmodule  // util_clkdiv
-
+endmodule