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libraries: Update modules according to guideline 

* Added header license for the files that didn't have
* Modified parentheses
* Removed extra spaces at the end of lines
* Fixed parameters list to be each parameter on its line
* Deleted lines after endmodule and consecutive empty lines
* Fixed indentation

Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
main
Iulia Moldovan 2022-04-08 11:21:52 +01:00 committed by imoldovan
parent 521476a8d4
commit 0c0617d49e
397 changed files with 16299 additions and 16791 deletions
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117
library/ad463x_data_capture/ad463x_data_capture.v
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@ -44,7 +44,6 @@ module ad463x_data_capture #(
parameter NUM_OF_LANES = 2, parameter NUM_OF_LANES = 2,
parameter DATA_WIDTH = 32 parameter DATA_WIDTH = 32
) ( ) (
input clk, // core clock of the SPIE input clk, // core clock of the SPIE
input csn, // CSN (chip select) input csn, // CSN (chip select)
input echo_sclk, // BUSY/SCLKOUT input echo_sclk, // BUSY/SCLKOUT
@ -53,82 +52,80 @@ module ad463x_data_capture #(
output [(NUM_OF_LANES * DATA_WIDTH)-1:0] m_axis_data, // parallel data lines output [(NUM_OF_LANES * DATA_WIDTH)-1:0] m_axis_data, // parallel data lines
output m_axis_valid, // data validation output m_axis_valid, // data validation
input m_axis_ready // NOTE: back pressure is ignored input m_axis_ready // NOTE: back pressure is ignored
); );
reg csn_d; reg csn_d;
wire reset; wire reset;
always @(posedge clk) begin always @(posedge clk) begin
csn_d <= csn; csn_d <= csn;
end end
// negative edge resets the shift registers // negative edge resets the shift registers
assign reset = ~csn & csn_d; assign reset = ~csn & csn_d;
// CSN positive edge validates the output data // CSN positive edge validates the output data
// WARNING: there isn't any buffering for data, if the sink module is not // WARNING: there isn't any buffering for data, if the sink module is not
// ready, the data will be discarded // ready, the data will be discarded
assign m_axis_valid = csn & ~csn_d & m_axis_ready; assign m_axis_valid = csn & ~csn_d & m_axis_ready;
genvar i, j; genvar i, j;
generate generate
if (DDR_EN) // Double Data Rate mode if (DDR_EN) // Double Data Rate mode
begin begin
for (i=0; i<NUM_OF_LANES; i=i+1) begin for (i=0; i<NUM_OF_LANES; i=i+1) begin
reg [DATA_WIDTH-1:0] data_shift_p; reg [DATA_WIDTH-1:0] data_shift_p;
reg [DATA_WIDTH-1:0] data_shift_n; reg [DATA_WIDTH-1:0] data_shift_n;
// shift register for positive edge // shift register for positive edge
always @(negedge echo_sclk or posedge reset) begin always @(negedge echo_sclk or posedge reset) begin
if (reset) begin if (reset) begin
data_shift_n <= 0; data_shift_n <= 0;
end else begin end else begin
data_shift_n <= {data_shift_n, data_in[i]}; data_shift_n <= {data_shift_n, data_in[i]};
end
end end
end
// shift register for positive edge // shift register for positive edge
always @(posedge echo_sclk or posedge reset) begin always @(posedge echo_sclk or posedge reset) begin
if (reset) begin if (reset) begin
data_shift_p <= 0; data_shift_p <= 0;
end else begin end else begin
data_shift_p <= {data_shift_p, data_in[i]}; data_shift_p <= {data_shift_p, data_in[i]};
end
end end
end
// DDR output logic - only the first 16 bits are forwarded // DDR output logic - only the first 16 bits are forwarded
for (j=0; j<DATA_WIDTH/2; j=j+1) begin for (j=0; j<DATA_WIDTH/2; j=j+1) begin
assign m_axis_data[DATA_WIDTH*i+(j*2)+:2] = {data_shift_p[j], data_shift_n[j]}; assign m_axis_data[DATA_WIDTH*i+(j*2)+:2] = {data_shift_p[j], data_shift_n[j]};
end
end /* for loop */
end else begin // Single Data Rate mode
for (i=0; i<NUM_OF_LANES; i=i+1) begin
reg [DATA_WIDTH-1:0] data_shift_n;
// shift register for positive edge
always @(negedge echo_sclk or posedge reset) begin
if (reset) begin
data_shift_n <= 0;
end else begin
data_shift_n <= {data_shift_n, data_in[i]};
end end
end
// SDR output logic end /* for loop */
assign m_axis_data[DATA_WIDTH*i+:DATA_WIDTH] = data_shift_n;
end /* for loop */ end else begin // Single Data Rate mode
end for (i=0; i<NUM_OF_LANES; i=i+1) begin
endgenerate
reg [DATA_WIDTH-1:0] data_shift_n;
// shift register for positive edge
always @(negedge echo_sclk or posedge reset) begin
if (reset) begin
data_shift_n <= 0;
end else begin
data_shift_n <= {data_shift_n, data_in[i]};
end
end
// SDR output logic
assign m_axis_data[DATA_WIDTH*i+:DATA_WIDTH] = data_shift_n;
end /* for loop */
end
endgenerate
endmodule endmodule

63
library/axi_ad5766/axi_ad5766.v
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@ -43,7 +43,8 @@ module axi_ad5766 #(
parameter DEV_PACKAGE = 0, parameter DEV_PACKAGE = 0,
parameter ASYNC_SPI_CLK = 0, parameter ASYNC_SPI_CLK = 0,
parameter CMD_MEM_ADDRESS_WIDTH = 4, parameter CMD_MEM_ADDRESS_WIDTH = 4,
parameter SDO_MEM_ADDRESS_WIDTH = 4)( parameter SDO_MEM_ADDRESS_WIDTH = 4
) (
// Slave AXI interface // Slave AXI interface
@ -107,7 +108,8 @@ module axi_ad5766 #(
input ctrl_enable, input ctrl_enable,
output ctrl_enabled, output ctrl_enabled,
input ctrl_mem_reset); input ctrl_mem_reset
);
// internal wires // internal wires
@ -192,35 +194,32 @@ module axi_ad5766 #(
spi_enabled <= spi_enable_s | spi_active; spi_enabled <= spi_enable_s | spi_active;
end end
sync_bits # ( sync_bits #(
.NUM_OF_BITS(1), .NUM_OF_BITS(1),
.ASYNC_CLK(1) .ASYNC_CLK(1)
) i_sync_enable ( ) i_sync_enable (
.in_bits(ctrl_do_enable), .in_bits(ctrl_do_enable),
.out_clk(spi_clk), .out_clk(spi_clk),
.out_resetn(1'b1), .out_resetn(1'b1),
.out_bits(spi_enable_s) .out_bits(spi_enable_s));
);
sync_bits # ( sync_bits #(
.NUM_OF_BITS(1), .NUM_OF_BITS(1),
.ASYNC_CLK(1) .ASYNC_CLK(1)
) i_sync_enabled ( ) i_sync_enabled (
.in_bits(spi_enabled), .in_bits(spi_enabled),
.out_clk(ctrl_clk), .out_clk(ctrl_clk),
.out_resetn(1'b1), .out_resetn(1'b1),
.out_bits(ctrl_is_enabled) .out_bits(ctrl_is_enabled));
);
sync_bits # ( sync_bits #(
.NUM_OF_BITS(1), .NUM_OF_BITS(1),
.ASYNC_CLK(1) .ASYNC_CLK(1)
) i_sync_mem_reset ( ) i_sync_mem_reset (
.in_bits(ctrl_mem_reset), .in_bits(ctrl_mem_reset),
.out_clk(spi_clk), .out_clk(spi_clk),
.out_resetn(1'b1), .out_resetn(1'b1),
.out_bits(spi_mem_reset_s) .out_bits(spi_mem_reset_s));
);
end else begin end else begin
assign spi_enable_s = ctrl_enable; assign spi_enable_s = ctrl_enable;
@ -299,14 +298,15 @@ module axi_ad5766 #(
// rate controller // rate controller
assign dac_rstn_s = ~dac_rst_s; assign dac_rstn_s = ~dac_rst_s;
util_pulse_gen #(.PULSE_WIDTH(1)) i_trigger_gen ( util_pulse_gen #(
.PULSE_WIDTH(1)
) i_trigger_gen (
.clk (spi_clk), .clk (spi_clk),
.rstn (dac_rstn_s), .rstn (dac_rstn_s),
.pulse_width (1'b1), .pulse_width (1'b1),
.pulse_period (pulse_period_s), .pulse_period (pulse_period_s),
.load_config (1'b1), .load_config (1'b1),
.pulse (trigger_s) .pulse (trigger_s));
);
// offset of the sequencer registers are 8'h40 // offset of the sequencer registers are 8'h40
@ -327,8 +327,8 @@ module axi_ad5766 #(
assign pulse_period_s = {16'h0, dac_datarate_s}; assign pulse_period_s = {16'h0, dac_datarate_s};
up_ad5766_sequencer #( up_ad5766_sequencer #(
.SEQ_ID(4)) .SEQ_ID(4)
i_sequencer ( ) i_sequencer (
.sequence_clk (spi_clk), .sequence_clk (spi_clk),
.sequence_rst (spi_mem_reset_s), .sequence_rst (spi_mem_reset_s),
.sequence_req (dma_valid), .sequence_req (dma_valid),
@ -397,7 +397,6 @@ module axi_ad5766 #(
.up_rdata (up_rdata_s[0]), .up_rdata (up_rdata_s[0]),
.up_rack (up_rack_s[0])); .up_rack (up_rack_s[0]));
// AXI wrapper // AXI wrapper
up_axi #( up_axi #(

12
library/axi_ad5766/up_ad5766_sequencer.v
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@ -37,8 +37,8 @@
module up_ad5766_sequencer #( module up_ad5766_sequencer #(
parameter SEQ_ID = 0)( parameter SEQ_ID = 0
) (
input sequence_clk, input sequence_clk,
input sequence_rst, input sequence_rst,
input sequence_req, input sequence_req,
@ -54,8 +54,8 @@ module up_ad5766_sequencer #(
input up_rreq, input up_rreq,
input [13:0] up_raddr, input [13:0] up_raddr,
output reg [31:0] up_rdata, output reg [31:0] up_rdata,
output reg up_rack); output reg up_rack
);
// registers // registers
@ -214,7 +214,9 @@ module up_ad5766_sequencer #(
// CDC // CDC
up_xfer_cntrl #(.DATA_WIDTH(132)) i_xfer_cntrl ( up_xfer_cntrl #(
.DATA_WIDTH(132)
) i_xfer_cntrl (
.up_rstn (up_rstn), .up_rstn (up_rstn),
.up_clk (up_clk), .up_clk (up_clk),
.up_data_cntrl ({up_endof_seq, .up_data_cntrl ({up_endof_seq,

16
library/axi_ad7616/axi_ad7616.v
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@ -38,7 +38,8 @@
module axi_ad7616 #( module axi_ad7616 #(
parameter ID = 0, parameter ID = 0,
parameter IF_TYPE = 1) ( parameter IF_TYPE = 1
) (
// physical data interface // physical data interface
@ -88,8 +89,8 @@ module axi_ad7616 #(
output [15:0] adc_data, output [15:0] adc_data,
output adc_sync, output adc_sync,
output irq); output irq
);
localparam NUM_OF_SDI = 2; localparam NUM_OF_SDI = 2;
localparam SERIAL = 0; localparam SERIAL = 0;
@ -368,8 +369,7 @@ module axi_ad7616 #(
.fifo_wr_en(adc_valid), .fifo_wr_en(adc_valid),
.fifo_wr_data(adc_data), .fifo_wr_data(adc_data),
.fifo_wr_sync(adc_sync), .fifo_wr_sync(adc_sync),
.fifo_wr_xfer_req(1'b1) .fifo_wr_xfer_req(1'b1));
);
end end
endgenerate endgenerate
@ -402,8 +402,7 @@ module axi_ad7616 #(
.wr_req (wr_req_s), .wr_req (wr_req_s),
.wr_data (wr_data_s), .wr_data (wr_data_s),
.rd_data (rd_data_s), .rd_data (rd_data_s),
.rd_valid (rd_valid_s) .rd_valid (rd_valid_s));
);
end end
endgenerate endgenerate
@ -466,6 +465,3 @@ module axi_ad7616 #(
.up_rack (up_rack)); .up_rack (up_rack));
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

8
library/axi_ad7616/axi_ad7616_control.v
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@ -38,7 +38,8 @@
module axi_ad7616_control #( module axi_ad7616_control #(
parameter ID = 0, parameter ID = 0,
parameter IF_TYPE = 0) ( parameter IF_TYPE = 0
) (
// control signals // control signals
@ -68,7 +69,6 @@ module axi_ad7616_control #(
output reg up_rack output reg up_rack
); );
localparam PCORE_VERSION = 'h00001002; localparam PCORE_VERSION = 'h00001002;
localparam POS_EDGE = 0; localparam POS_EDGE = 0;
localparam NEG_EDGE = 1; localparam NEG_EDGE = 1;
@ -170,8 +170,7 @@ module axi_ad7616_control #(
.clk (up_clk), .clk (up_clk),
.rst (up_rst), .rst (up_rst),
.signal_in (busy), .signal_in (busy),
.signal_out (end_of_conv) .signal_out (end_of_conv));
);
// convertion start generator // convertion start generator
// NOTE: + The minimum convertion cycle is 1 us // NOTE: + The minimum convertion cycle is 1 us
@ -208,4 +207,3 @@ module axi_ad7616_control #(
assign cnvst = (up_cnvst_en == 1'b1) ? cnvst_buf : 1'b0; assign cnvst = (up_cnvst_en == 1'b1) ? cnvst_buf : 1'b0;
endmodule endmodule

5
library/axi_ad7616/axi_ad7616_maxis2wrfifo.v
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@ -37,8 +37,8 @@
module axi_ad7616_maxis2wrfifo #( module axi_ad7616_maxis2wrfifo #(
parameter DATA_WIDTH = 16) ( parameter DATA_WIDTH = 16
) (
input clk, input clk,
input rstn, input rstn,
input sync_in, input sync_in,
@ -58,7 +58,6 @@ module axi_ad7616_maxis2wrfifo #(
input fifo_wr_xfer_req input fifo_wr_xfer_req
); );
always @(posedge clk) begin always @(posedge clk) begin
if (rstn == 1'b0) begin if (rstn == 1'b0) begin
m_axis_ready <= 1'b0; m_axis_ready <= 1'b0;

8
library/axi_ad7616/axi_ad7616_pif.v
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@ -37,7 +37,8 @@
module axi_ad7616_pif #( module axi_ad7616_pif #(
parameter UP_ADDRESS_WIDTH = 14) ( parameter UP_ADDRESS_WIDTH = 14
) (
// physical interface // physical interface
@ -67,8 +68,8 @@ module axi_ad7616_pif #(
input wr_req, input wr_req,
input [15:0] wr_data, input [15:0] wr_data,
output reg [15:0] rd_data, output reg [15:0] rd_data,
output reg rd_valid); output reg rd_valid
);
// state registers // state registers
@ -212,4 +213,3 @@ module axi_ad7616_pif #(
end end
endmodule endmodule

18
library/axi_ad9122/axi_ad9122.v
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@ -53,7 +53,8 @@ module axi_ad9122 #(
parameter DAC_DDS_TYPE = 1, parameter DAC_DDS_TYPE = 1,
parameter DAC_DDS_CORDIC_DW = 20, parameter DAC_DDS_CORDIC_DW = 20,
parameter DAC_DDS_CORDIC_PHASE_DW = 18, parameter DAC_DDS_CORDIC_PHASE_DW = 18,
parameter IO_DELAY_GROUP = "dev_if_delay_group") ( parameter IO_DELAY_GROUP = "dev_if_delay_group"
) (
// dac interface // dac interface
@ -104,8 +105,8 @@ module axi_ad9122 #(
output [ 1:0] s_axi_rresp, output [ 1:0] s_axi_rresp,
input s_axi_rready, input s_axi_rready,
input [ 2:0] s_axi_awprot, input [ 2:0] s_axi_awprot,
input [ 2:0] s_axi_arprot); input [ 2:0] s_axi_arprot
);
// internal clocks and resets // internal clocks and resets
@ -164,8 +165,8 @@ module axi_ad9122 #(
.MMCM_VCO_DIV (MMCM_VCO_DIV), .MMCM_VCO_DIV (MMCM_VCO_DIV),
.MMCM_VCO_MUL (MMCM_VCO_MUL), .MMCM_VCO_MUL (MMCM_VCO_MUL),
.MMCM_CLK0_DIV (MMCM_CLK0_DIV), .MMCM_CLK0_DIV (MMCM_CLK0_DIV),
.MMCM_CLK1_DIV (MMCM_CLK1_DIV)) .MMCM_CLK1_DIV (MMCM_CLK1_DIV)
i_if ( ) i_if (
.dac_clk_in_p (dac_clk_in_p), .dac_clk_in_p (dac_clk_in_p),
.dac_clk_in_n (dac_clk_in_n), .dac_clk_in_n (dac_clk_in_n),
.dac_clk_out_p (dac_clk_out_p), .dac_clk_out_p (dac_clk_out_p),
@ -216,8 +217,8 @@ module axi_ad9122 #(
.DAC_DDS_TYPE (DAC_DDS_TYPE), .DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.DATAPATH_DISABLE(DAC_DATAPATH_DISABLE)) .DATAPATH_DISABLE(DAC_DATAPATH_DISABLE)
i_core ( ) i_core (
.dac_div_clk (dac_div_clk), .dac_div_clk (dac_div_clk),
.dac_rst (dac_rst), .dac_rst (dac_rst),
.dac_frame_i0 (dac_frame_i0_s), .dac_frame_i0 (dac_frame_i0_s),
@ -297,6 +298,3 @@ module axi_ad9122 #(
.up_rack (up_rack_s)); .up_rack (up_rack_s));
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

17
library/axi_ad9122/axi_ad9122_channel.v
View File

@ -41,7 +41,8 @@ module axi_ad9122_channel #(
parameter DAC_DDS_TYPE = 1, parameter DAC_DDS_TYPE = 1,
parameter DAC_DDS_CORDIC_DW = 16, parameter DAC_DDS_CORDIC_DW = 16,
parameter DAC_DDS_CORDIC_PHASE_DW = 16, parameter DAC_DDS_CORDIC_PHASE_DW = 16,
parameter DATAPATH_DISABLE = 0) ( parameter DATAPATH_DISABLE = 0
) (
// dac interface // dac interface
@ -69,7 +70,8 @@ module axi_ad9122_channel #(
input up_rreq, input up_rreq,
input [13:0] up_raddr, input [13:0] up_raddr,
output [31:0] up_rdata, output [31:0] up_rdata,
output up_rack); output up_rack
);
// internal signals // internal signals
@ -110,8 +112,8 @@ module axi_ad9122_channel #(
.DDS_TYPE (DAC_DDS_TYPE), .DDS_TYPE (DAC_DDS_TYPE),
.CORDIC_DW (DAC_DDS_CORDIC_DW), .CORDIC_DW (DAC_DDS_CORDIC_DW),
.CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), .CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.CLK_RATIO (4)) .CLK_RATIO (4)
i_dds ( ) i_dds (
.clk (dac_clk), .clk (dac_clk),
.dac_dds_format (dac_dds_format), .dac_dds_format (dac_dds_format),
.dac_data_sync (dac_data_sync), .dac_data_sync (dac_data_sync),
@ -131,8 +133,8 @@ module axi_ad9122_channel #(
.CHANNEL_ID(CHANNEL_ID), .CHANNEL_ID(CHANNEL_ID),
.DDS_DISABLE (0), .DDS_DISABLE (0),
.USERPORTS_DISABLE (0), .USERPORTS_DISABLE (0),
.IQCORRECTION_DISABLE (0)) .IQCORRECTION_DISABLE (0)
i_up_dac_channel ( ) i_up_dac_channel (
.dac_clk (dac_div_clk), .dac_clk (dac_div_clk),
.dac_rst (dac_rst), .dac_rst (dac_rst),
.dac_dds_scale_1 (dac_dds_scale_1_s), .dac_dds_scale_1 (dac_dds_scale_1_s),
@ -174,6 +176,3 @@ module axi_ad9122_channel #(
.up_rack (up_rack)); .up_rack (up_rack));
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

22
library/axi_ad9122/axi_ad9122_core.v
View File

@ -45,7 +45,8 @@ module axi_ad9122_core #(
parameter DAC_DDS_TYPE = 1, parameter DAC_DDS_TYPE = 1,
parameter DAC_DDS_CORDIC_DW = 16, parameter DAC_DDS_CORDIC_DW = 16,
parameter DAC_DDS_CORDIC_PHASE_DW = 16, parameter DAC_DDS_CORDIC_PHASE_DW = 16,
parameter DATAPATH_DISABLE = 0) ( parameter DATAPATH_DISABLE = 0
) (
// dac interface // dac interface
@ -109,8 +110,8 @@ module axi_ad9122_core #(
input up_rreq, input up_rreq,
input [13:0] up_raddr, input [13:0] up_raddr,
output reg [31:0] up_rdata, output reg [31:0] up_rdata,
output reg up_rack); output reg up_rack
);
// internal registers // internal registers
@ -159,8 +160,8 @@ module axi_ad9122_core #(
.DAC_DDS_TYPE (DAC_DDS_TYPE), .DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.DATAPATH_DISABLE(DATAPATH_DISABLE)) .DATAPATH_DISABLE(DATAPATH_DISABLE)
i_channel_0 ( ) i_channel_0 (
.dac_div_clk (dac_div_clk), .dac_div_clk (dac_div_clk),
.dac_rst (dac_rst), .dac_rst (dac_rst),
.dac_enable (dac_enable_0), .dac_enable (dac_enable_0),
@ -188,8 +189,8 @@ module axi_ad9122_core #(
.DAC_DDS_TYPE (DAC_DDS_TYPE), .DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.DATAPATH_DISABLE(DATAPATH_DISABLE)) .DATAPATH_DISABLE(DATAPATH_DISABLE)
i_channel_1 ( ) i_channel_1 (
.dac_div_clk (dac_div_clk), .dac_div_clk (dac_div_clk),
.dac_rst (dac_rst), .dac_rst (dac_rst),
.dac_enable (dac_enable_1), .dac_enable (dac_enable_1),
@ -223,8 +224,8 @@ module axi_ad9122_core #(
.COMMON_ID (6'h10), .COMMON_ID (6'h10),
.DRP_DISABLE (6'h00), .DRP_DISABLE (6'h00),
.USERPORTS_DISABLE (0), .USERPORTS_DISABLE (0),
.GPIO_DISABLE (0)) .GPIO_DISABLE (0)
i_up_dac_common ( ) i_up_dac_common (
.mmcm_rst (mmcm_rst), .mmcm_rst (mmcm_rst),
.dac_clk (dac_div_clk), .dac_clk (dac_div_clk),
.dac_rst (dac_rst), .dac_rst (dac_rst),
@ -266,6 +267,3 @@ module axi_ad9122_core #(
.up_rack (up_rack_s)); .up_rack (up_rack_s));
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

26
library/axi_ad9122/axi_ad9122_if.v
View File

@ -47,7 +47,8 @@ module axi_ad9122_if #(
parameter MMCM_VCO_MUL = 12, parameter MMCM_VCO_MUL = 12,
parameter MMCM_CLK0_DIV = 2, parameter MMCM_CLK0_DIV = 2,
parameter MMCM_CLK1_DIV = 8, parameter MMCM_CLK1_DIV = 8,
parameter IO_DELAY_GROUP = "dac_if_delay_group") ( parameter IO_DELAY_GROUP = "dac_if_delay_group"
) (
// dac interface // dac interface
@ -101,8 +102,8 @@ module axi_ad9122_if #(
input [31:0] up_drp_wdata, input [31:0] up_drp_wdata,
output [31:0] up_drp_rdata, output [31:0] up_drp_rdata,
output up_drp_ready, output up_drp_ready,
output up_drp_locked); output up_drp_locked
);
// internal registers // internal registers
@ -130,8 +131,8 @@ module axi_ad9122_if #(
ad_serdes_out #( ad_serdes_out #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.DDR_OR_SDR_N (SERDES_OR_DDR_N), .DDR_OR_SDR_N (SERDES_OR_DDR_N),
.DATA_WIDTH (16)) .DATA_WIDTH (16)
i_serdes_out_data ( ) i_serdes_out_data (
.rst (dac_rst), .rst (dac_rst),
.clk (dac_clk), .clk (dac_clk),
.div_clk (dac_div_clk), .div_clk (dac_div_clk),
@ -154,8 +155,8 @@ module axi_ad9122_if #(
ad_serdes_out #( ad_serdes_out #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.DDR_OR_SDR_N (SERDES_OR_DDR_N), .DDR_OR_SDR_N (SERDES_OR_DDR_N),
.DATA_WIDTH (1)) .DATA_WIDTH (1)
i_serdes_out_frame ( ) i_serdes_out_frame (
.rst (dac_rst), .rst (dac_rst),
.clk (dac_clk), .clk (dac_clk),
.div_clk (dac_div_clk), .div_clk (dac_div_clk),
@ -178,8 +179,8 @@ module axi_ad9122_if #(
ad_serdes_out #( ad_serdes_out #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.DDR_OR_SDR_N (SERDES_OR_DDR_N), .DDR_OR_SDR_N (SERDES_OR_DDR_N),
.DATA_WIDTH (1)) .DATA_WIDTH (1)
i_serdes_out_clk ( ) i_serdes_out_clk (
.rst (dac_rst), .rst (dac_rst),
.clk (dac_clk), .clk (dac_clk),
.div_clk (dac_div_clk), .div_clk (dac_div_clk),
@ -207,8 +208,8 @@ module axi_ad9122_if #(
.MMCM_VCO_DIV (MMCM_VCO_DIV), .MMCM_VCO_DIV (MMCM_VCO_DIV),
.MMCM_VCO_MUL (MMCM_VCO_MUL), .MMCM_VCO_MUL (MMCM_VCO_MUL),
.MMCM_CLK0_DIV (MMCM_CLK0_DIV), .MMCM_CLK0_DIV (MMCM_CLK0_DIV),
.MMCM_CLK1_DIV (MMCM_CLK1_DIV)) .MMCM_CLK1_DIV (MMCM_CLK1_DIV)
i_serdes_clk ( ) i_serdes_clk (
.rst (mmcm_rst), .rst (mmcm_rst),
.clk_in_p (dac_clk_in_p), .clk_in_p (dac_clk_in_p),
.clk_in_n (dac_clk_in_n), .clk_in_n (dac_clk_in_n),
@ -228,6 +229,3 @@ module axi_ad9122_if #(
.up_drp_locked (up_drp_locked)); .up_drp_locked (up_drp_locked));
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

6
library/axi_ad9250/axi_ad9250.v
View File

@ -85,7 +85,8 @@ module axi_ad9250 #(
output s_axi_rvalid, output s_axi_rvalid,
output [31:0] s_axi_rdata, output [31:0] s_axi_rdata,
output [ 1:0] s_axi_rresp, output [ 1:0] s_axi_rresp,
input s_axi_rready); input s_axi_rready
);
assign adc_clk = rx_clk; assign adc_clk = rx_clk;
@ -135,7 +136,6 @@ module axi_ad9250 #(
.s_axi_rvalid (s_axi_rvalid), .s_axi_rvalid (s_axi_rvalid),
.s_axi_rready (s_axi_rready), .s_axi_rready (s_axi_rready),
.s_axi_rresp (s_axi_rresp), .s_axi_rresp (s_axi_rresp),
.s_axi_rdata (s_axi_rdata) .s_axi_rdata (s_axi_rdata));
);
endmodule endmodule

28
library/axi_ad9265/axi_ad9265.v
View File

@ -43,7 +43,8 @@ module axi_ad9265 #(
parameter SPEED_GRADE = 0, parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0, parameter DEV_PACKAGE = 0,
parameter ADC_DATAPATH_DISABLE = 0, parameter ADC_DATAPATH_DISABLE = 0,
parameter IO_DELAY_GROUP = "adc_if_delay_group") ( parameter IO_DELAY_GROUP = "adc_if_delay_group"
) (
// adc interface (clk, data, over-range) // adc interface (clk, data, over-range)
@ -89,8 +90,8 @@ module axi_ad9265 #(
output [31:0] s_axi_rdata, output [31:0] s_axi_rdata,
input s_axi_rready, input s_axi_rready,
input [ 2:0] s_axi_awprot, input [ 2:0] s_axi_awprot,
input [ 2:0] s_axi_arprot); input [ 2:0] s_axi_arprot
);
// internal registers // internal registers
@ -157,8 +158,8 @@ module axi_ad9265 #(
axi_ad9265_channel #( axi_ad9265_channel #(
.CHANNEL_ID(0), .CHANNEL_ID(0),
.DATAPATH_DISABLE (ADC_DATAPATH_DISABLE)) .DATAPATH_DISABLE (ADC_DATAPATH_DISABLE)
i_channel ( ) i_channel (
.adc_clk (adc_clk), .adc_clk (adc_clk),
.adc_rst (adc_rst), .adc_rst (adc_rst),
.adc_data (adc_data_s), .adc_data (adc_data_s),
@ -184,8 +185,8 @@ module axi_ad9265 #(
axi_ad9265_if #( axi_ad9265_if #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IO_DELAY_GROUP (IO_DELAY_GROUP)) .IO_DELAY_GROUP (IO_DELAY_GROUP)
i_if ( ) i_if (
.adc_clk_in_p (adc_clk_in_p), .adc_clk_in_p (adc_clk_in_p),
.adc_clk_in_n (adc_clk_in_n), .adc_clk_in_n (adc_clk_in_n),
.adc_data_in_p (adc_data_in_p), .adc_data_in_p (adc_data_in_p),
@ -206,7 +207,10 @@ module axi_ad9265 #(
// adc delay control // adc delay control
up_delay_cntrl #(.DATA_WIDTH(9), .BASE_ADDRESS(6'h02)) i_delay_cntrl ( up_delay_cntrl #(
.DATA_WIDTH(9),
.BASE_ADDRESS(6'h02)
) i_delay_cntrl (
.delay_clk (delay_clk), .delay_clk (delay_clk),
.delay_rst (delay_rst), .delay_rst (delay_rst),
.delay_locked (delay_locked_s), .delay_locked (delay_locked_s),
@ -237,8 +241,8 @@ module axi_ad9265 #(
.DRP_DISABLE (6'h00), .DRP_DISABLE (6'h00),
.USERPORTS_DISABLE (0), .USERPORTS_DISABLE (0),
.GPIO_DISABLE (0), .GPIO_DISABLE (0),
.START_CODE_DISABLE(0)) .START_CODE_DISABLE(0)
i_up_adc_common ( ) i_up_adc_common (
.mmcm_rst (), .mmcm_rst (),
.adc_clk (adc_clk), .adc_clk (adc_clk),
.adc_rst (adc_rst), .adc_rst (adc_rst),
@ -313,7 +317,3 @@ module axi_ad9265 #(
.up_rack (up_rack)); .up_rack (up_rack));
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

18
library/axi_ad9265/axi_ad9265_channel.v
View File

@ -39,7 +39,8 @@
module axi_ad9265_channel #( module axi_ad9265_channel #(
parameter CHANNEL_ID = 0, parameter CHANNEL_ID = 0,
parameter DATAPATH_DISABLE = 0) ( parameter DATAPATH_DISABLE = 0
) (
// adc interface // adc interface
@ -68,8 +69,8 @@ module axi_ad9265_channel #(
input up_rreq, input up_rreq,
input [13:0] up_raddr, input [13:0] up_raddr,
output [31:0] up_rdata, output [31:0] up_rdata,
output up_rack); output up_rack
);
// internal signals // internal signals
@ -97,7 +98,9 @@ module axi_ad9265_channel #(
if (DATAPATH_DISABLE == 1) begin if (DATAPATH_DISABLE == 1) begin
assign adc_dfmt_data_s = adc_data; assign adc_dfmt_data_s = adc_data;
end else begin end else begin
ad_datafmt #(.DATA_WIDTH(16)) i_ad_datafmt ( ad_datafmt #(
.DATA_WIDTH(16)
) i_ad_datafmt (
.clk (adc_clk), .clk (adc_clk),
.valid (1'b1), .valid (1'b1),
.data (adc_data), .data (adc_data),
@ -131,8 +134,8 @@ module axi_ad9265_channel #(
.USERPORTS_DISABLE (0), .USERPORTS_DISABLE (0),
.DATAFORMAT_DISABLE (0), .DATAFORMAT_DISABLE (0),
.DCFILTER_DISABLE (0), .DCFILTER_DISABLE (0),
.IQCORRECTION_DISABLE (0)) .IQCORRECTION_DISABLE (0)
i_up_adc_channel ( ) i_up_adc_channel (
.adc_clk (adc_clk), .adc_clk (adc_clk),
.adc_rst (adc_rst), .adc_rst (adc_rst),
.adc_enable (adc_enable), .adc_enable (adc_enable),
@ -179,6 +182,3 @@ module axi_ad9265_channel #(
.up_rack (up_rack)); .up_rack (up_rack));
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

21
library/axi_ad9265/axi_ad9265_if.v
View File

@ -41,7 +41,8 @@ module axi_ad9265_if #(
parameter FPGA_TECHNOLOGY = 0, parameter FPGA_TECHNOLOGY = 0,
parameter IO_DELAY_GROUP = "adc_if_delay_group", parameter IO_DELAY_GROUP = "adc_if_delay_group",
parameter DELAY_REFCLK_FREQUENCY = 200) ( parameter DELAY_REFCLK_FREQUENCY = 200
) (
// adc interface (clk, data, over-range) // adc interface (clk, data, over-range)
// nominal clock 125 MHz, up to 300 MHz // nominal clock 125 MHz, up to 300 MHz
@ -68,8 +69,8 @@ module axi_ad9265_if #(
output [44:0] up_drdata, output [44:0] up_drdata,
input delay_clk, input delay_clk,
input delay_rst, input delay_rst,
output delay_locked); output delay_locked
);
// internal registers // internal registers
@ -102,8 +103,8 @@ module axi_ad9265_if #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_CTRL (0), .IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP), .IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)) .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
i_adc_data ( ) i_adc_data (
.rx_clk (adc_clk), .rx_clk (adc_clk),
.rx_data_in_p (adc_data_in_p[l_inst]), .rx_data_in_p (adc_data_in_p[l_inst]),
.rx_data_in_n (adc_data_in_n[l_inst]), .rx_data_in_n (adc_data_in_n[l_inst]),
@ -125,8 +126,8 @@ module axi_ad9265_if #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_CTRL (1), .IODELAY_CTRL (1),
.IODELAY_GROUP (IO_DELAY_GROUP), .IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)) .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
i_adc_or ( ) i_adc_or (
.rx_clk (adc_clk), .rx_clk (adc_clk),
.rx_data_in_p (adc_or_in_p), .rx_data_in_p (adc_or_in_p),
.rx_data_in_n (adc_or_in_n), .rx_data_in_n (adc_or_in_n),
@ -142,8 +143,7 @@ module axi_ad9265_if #(
// clock // clock
ad_data_clk ad_data_clk i_adc_clk (
i_adc_clk (
.rst (1'b0), .rst (1'b0),
.locked (), .locked (),
.clk_in_p (adc_clk_in_p), .clk_in_p (adc_clk_in_p),
@ -151,6 +151,3 @@ module axi_ad9265_if #(
.clk (adc_clk)); .clk (adc_clk));
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

11
library/axi_ad9265/axi_ad9265_pnmon.v
View File

@ -47,7 +47,8 @@ module axi_ad9265_pnmon (
output adc_pn_oos, output adc_pn_oos,
output adc_pn_err, output adc_pn_err,
input [ 3:0] adc_pnseq_sel); input [ 3:0] adc_pnseq_sel
);
// internal registers // internal registers
@ -161,7 +162,9 @@ module axi_ad9265_pnmon (
// pn oos & pn err // pn oos & pn err
ad_pnmon #(.DATA_WIDTH(32)) i_pnmon ( ad_pnmon #(
.DATA_WIDTH(32)
) i_pnmon (
.adc_clk (adc_clk), .adc_clk (adc_clk),
.adc_valid_in (adc_valid_in), .adc_valid_in (adc_valid_in),
.adc_data_in (adc_pn_data_in), .adc_data_in (adc_pn_data_in),
@ -170,7 +173,3 @@ module axi_ad9265_pnmon (
.adc_pn_err (adc_pn_err)); .adc_pn_err (adc_pn_err));
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

29
library/axi_ad9361/axi_ad9361.v
View File

@ -69,7 +69,8 @@ module axi_ad9361 #(
parameter MIMO_ENABLE = 0, parameter MIMO_ENABLE = 0,
parameter USE_SSI_CLK = 1, parameter USE_SSI_CLK = 1,
parameter DELAY_REFCLK_FREQUENCY = 200, parameter DELAY_REFCLK_FREQUENCY = 200,
parameter RX_NODPA = 0) ( parameter RX_NODPA = 0
) (
// physical interface (receive-lvds) // physical interface (receive-lvds)
@ -192,7 +193,8 @@ module axi_ad9361 #(
input [31:0] up_dac_gpio_in, input [31:0] up_dac_gpio_in,
output [31:0] up_dac_gpio_out, output [31:0] up_dac_gpio_out,
input [31:0] up_adc_gpio_in, input [31:0] up_adc_gpio_in,
output [31:0] up_adc_gpio_out); output [31:0] up_adc_gpio_out
);
// derived parameters // derived parameters
@ -339,8 +341,8 @@ module axi_ad9361 #(
.IODELAY_CTRL (IODELAY_CTRL), .IODELAY_CTRL (IODELAY_CTRL),
.CLK_DESKEW (MIMO_ENABLE), .CLK_DESKEW (MIMO_ENABLE),
.USE_SSI_CLK (USE_SSI_CLK), .USE_SSI_CLK (USE_SSI_CLK),
.DELAY_REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)) .DELAY_REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
i_dev_if ( ) i_dev_if (
.rx_clk_in (rx_clk_in), .rx_clk_in (rx_clk_in),
.rx_frame_in (rx_frame_in), .rx_frame_in (rx_frame_in),
.rx_data_in (rx_data_in), .rx_data_in (rx_data_in),
@ -405,8 +407,8 @@ module axi_ad9361 #(
.CLK_DESKEW (MIMO_ENABLE), .CLK_DESKEW (MIMO_ENABLE),
.USE_SSI_CLK (USE_SSI_CLK), .USE_SSI_CLK (USE_SSI_CLK),
.DELAY_REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY), .DELAY_REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY),
.RX_NODPA (RX_NODPA)) .RX_NODPA (RX_NODPA)
i_dev_if ( ) i_dev_if (
.rx_clk_in_p (rx_clk_in_p), .rx_clk_in_p (rx_clk_in_p),
.rx_clk_in_n (rx_clk_in_n), .rx_clk_in_n (rx_clk_in_n),
.rx_frame_in_p (rx_frame_in_p), .rx_frame_in_p (rx_frame_in_p),
@ -521,7 +523,9 @@ module axi_ad9361 #(
generate generate
if (TDD_DISABLE == 0) begin if (TDD_DISABLE == 0) begin
axi_ad9361_tdd_if #(.LEVEL_OR_PULSE_N(1)) i_tdd_if ( axi_ad9361_tdd_if #(
.LEVEL_OR_PULSE_N(1)
) i_tdd_if (
.clk (clk), .clk (clk),
.rst (rst), .rst (rst),
.tdd_rx_vco_en (tdd_rx_vco_en_s), .tdd_rx_vco_en (tdd_rx_vco_en_s),
@ -599,8 +603,8 @@ module axi_ad9361 #(
.USERPORTS_DISABLE (ADC_USERPORTS_DISABLE_INT), .USERPORTS_DISABLE (ADC_USERPORTS_DISABLE_INT),
.DATAFORMAT_DISABLE (ADC_DATAFORMAT_DISABLE_INT), .DATAFORMAT_DISABLE (ADC_DATAFORMAT_DISABLE_INT),
.DCFILTER_DISABLE (ADC_DCFILTER_DISABLE_INT), .DCFILTER_DISABLE (ADC_DCFILTER_DISABLE_INT),
.IQCORRECTION_DISABLE (ADC_IQCORRECTION_DISABLE_INT)) .IQCORRECTION_DISABLE (ADC_IQCORRECTION_DISABLE_INT)
i_rx ( ) i_rx (
.mmcm_rst (mmcm_rst), .mmcm_rst (mmcm_rst),
.adc_rst (rst), .adc_rst (rst),
.adc_clk (clk), .adc_clk (clk),
@ -672,8 +676,8 @@ module axi_ad9361 #(
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.USERPORTS_DISABLE (DAC_USERPORTS_DISABLE_INT), .USERPORTS_DISABLE (DAC_USERPORTS_DISABLE_INT),
.DELAYCNTRL_DISABLE (DAC_DELAYCNTRL_DISABLE_INT), .DELAYCNTRL_DISABLE (DAC_DELAYCNTRL_DISABLE_INT),
.IQCORRECTION_DISABLE (DAC_IQCORRECTION_DISABLE_INT)) .IQCORRECTION_DISABLE (DAC_IQCORRECTION_DISABLE_INT)
i_tx ( ) i_tx (
.dac_clk (clk), .dac_clk (clk),
.dac_valid (dac_valid_s), .dac_valid (dac_valid_s),
.dac_data (dac_data_s), .dac_data (dac_data_s),
@ -750,6 +754,3 @@ module axi_ad9361 #(
.up_rack (up_rack)); .up_rack (up_rack));
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

34
library/axi_ad9361/axi_ad9361_rx.v
View File

@ -52,7 +52,8 @@ module axi_ad9361_rx #(
parameter USERPORTS_DISABLE = 0, parameter USERPORTS_DISABLE = 0,
parameter DATAFORMAT_DISABLE = 0, parameter DATAFORMAT_DISABLE = 0,
parameter DCFILTER_DISABLE = 0, parameter DCFILTER_DISABLE = 0,
parameter IQCORRECTION_DISABLE = 0) ( parameter IQCORRECTION_DISABLE = 0
) (
// common // common
@ -126,7 +127,8 @@ module axi_ad9361_rx #(
output [31:0] up_drp_wdata, output [31:0] up_drp_wdata,
input [31:0] up_drp_rdata, input [31:0] up_drp_rdata,
input up_drp_ready, input up_drp_ready,
input up_drp_locked); input up_drp_locked
);
// configuration settings // configuration settings
@ -194,8 +196,8 @@ module axi_ad9361_rx #(
.USERPORTS_DISABLE (USERPORTS_DISABLE), .USERPORTS_DISABLE (USERPORTS_DISABLE),
.DATAFORMAT_DISABLE (DATAFORMAT_DISABLE), .DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
.DCFILTER_DISABLE (DCFILTER_DISABLE), .DCFILTER_DISABLE (DCFILTER_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)) .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)
i_rx_channel_0 ( ) i_rx_channel_0 (
.adc_clk (adc_clk), .adc_clk (adc_clk),
.adc_rst (adc_rst), .adc_rst (adc_rst),
.adc_valid (adc_valid), .adc_valid (adc_valid),
@ -231,8 +233,8 @@ module axi_ad9361_rx #(
.USERPORTS_DISABLE (USERPORTS_DISABLE), .USERPORTS_DISABLE (USERPORTS_DISABLE),
.DATAFORMAT_DISABLE (DATAFORMAT_DISABLE), .DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
.DCFILTER_DISABLE (DCFILTER_DISABLE), .DCFILTER_DISABLE (DCFILTER_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)) .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)
i_rx_channel_1 ( ) i_rx_channel_1 (
.adc_clk (adc_clk), .adc_clk (adc_clk),
.adc_rst (adc_rst), .adc_rst (adc_rst),
.adc_valid (adc_valid), .adc_valid (adc_valid),
@ -268,8 +270,8 @@ module axi_ad9361_rx #(
.USERPORTS_DISABLE (USERPORTS_DISABLE), .USERPORTS_DISABLE (USERPORTS_DISABLE),
.DATAFORMAT_DISABLE (DATAFORMAT_DISABLE), .DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
.DCFILTER_DISABLE (DCFILTER_DISABLE), .DCFILTER_DISABLE (DCFILTER_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)) .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)
i_rx_channel_2 ( ) i_rx_channel_2 (
.adc_clk (adc_clk), .adc_clk (adc_clk),
.adc_rst (adc_rst), .adc_rst (adc_rst),
.adc_valid (adc_valid), .adc_valid (adc_valid),
@ -305,8 +307,8 @@ module axi_ad9361_rx #(
.USERPORTS_DISABLE (USERPORTS_DISABLE), .USERPORTS_DISABLE (USERPORTS_DISABLE),
.DATAFORMAT_DISABLE (DATAFORMAT_DISABLE), .DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
.DCFILTER_DISABLE (DCFILTER_DISABLE), .DCFILTER_DISABLE (DCFILTER_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)) .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)
i_rx_channel_3 ( ) i_rx_channel_3 (
.adc_clk (adc_clk), .adc_clk (adc_clk),
.adc_rst (adc_rst), .adc_rst (adc_rst),
.adc_valid (adc_valid), .adc_valid (adc_valid),
@ -345,8 +347,8 @@ module axi_ad9361_rx #(
.DRP_DISABLE (1), .DRP_DISABLE (1),
.USERPORTS_DISABLE (USERPORTS_DISABLE), .USERPORTS_DISABLE (USERPORTS_DISABLE),
.GPIO_DISABLE (0), .GPIO_DISABLE (0),
.START_CODE_DISABLE (0)) .START_CODE_DISABLE (0)
i_up_adc_common ( ) i_up_adc_common (
.mmcm_rst (mmcm_rst), .mmcm_rst (mmcm_rst),
.adc_clk (adc_clk), .adc_clk (adc_clk),
.adc_rst (adc_rst), .adc_rst (adc_rst),
@ -397,8 +399,8 @@ module axi_ad9361_rx #(
up_delay_cntrl #( up_delay_cntrl #(
.INIT_DELAY (INIT_DELAY), .INIT_DELAY (INIT_DELAY),
.DATA_WIDTH (13), .DATA_WIDTH (13),
.BASE_ADDRESS (6'h02)) .BASE_ADDRESS (6'h02)
i_delay_cntrl ( ) i_delay_cntrl (
.delay_clk (delay_clk), .delay_clk (delay_clk),
.delay_rst (delay_rst), .delay_rst (delay_rst),
.delay_locked (delay_locked), .delay_locked (delay_locked),
@ -417,7 +419,3 @@ module axi_ad9361_rx #(
.up_rack (up_rack_s[5])); .up_rack (up_rack_s[5]));
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

31
library/axi_ad9361/axi_ad9361_rx_channel.v
View File

@ -45,7 +45,8 @@ module axi_ad9361_rx_channel #(
parameter USERPORTS_DISABLE = 0, parameter USERPORTS_DISABLE = 0,
parameter DATAFORMAT_DISABLE = 0, parameter DATAFORMAT_DISABLE = 0,
parameter DCFILTER_DISABLE = 0, parameter DCFILTER_DISABLE = 0,
parameter IQCORRECTION_DISABLE = 0) ( parameter IQCORRECTION_DISABLE = 0
) (
// adc interface // adc interface
@ -79,7 +80,8 @@ module axi_ad9361_rx_channel #(
input up_rreq, input up_rreq,
input [13:0] up_raddr, input [13:0] up_raddr,
output [31:0] up_rdata, output [31:0] up_rdata,
output up_rack); output up_rack
);
// internal signals // internal signals
@ -129,8 +131,8 @@ module axi_ad9361_rx_channel #(
axi_ad9361_rx_pnmon #( axi_ad9361_rx_pnmon #(
.Q_OR_I_N (Q_OR_I_N), .Q_OR_I_N (Q_OR_I_N),
.PRBS_SEL (CHANNEL_ID)) .PRBS_SEL (CHANNEL_ID)
i_rx_pnmon ( ) i_rx_pnmon (
.adc_clk (adc_clk), .adc_clk (adc_clk),
.adc_valid (adc_valid), .adc_valid (adc_valid),
.adc_data_i (adc_data), .adc_data_i (adc_data),
@ -141,8 +143,8 @@ module axi_ad9361_rx_channel #(
ad_datafmt #( ad_datafmt #(
.DATA_WIDTH (12), .DATA_WIDTH (12),
.DISABLE (DATAFORMAT_DISABLE)) .DISABLE (DATAFORMAT_DISABLE)
i_ad_datafmt ( ) i_ad_datafmt (
.clk (adc_clk), .clk (adc_clk),
.valid (adc_valid), .valid (adc_valid),
.data (adc_data_s), .data (adc_data_s),
@ -153,8 +155,8 @@ module axi_ad9361_rx_channel #(
.dfmt_se (adc_dfmt_se_s)); .dfmt_se (adc_dfmt_se_s));
ad_dcfilter #( ad_dcfilter #(
.DISABLE (DCFILTER_DISABLE)) .DISABLE (DCFILTER_DISABLE)
i_ad_dcfilter ( ) i_ad_dcfilter (
.clk (adc_clk), .clk (adc_clk),
.valid (adc_dfmt_valid_s), .valid (adc_dfmt_valid_s),
.data (adc_dfmt_data_s), .data (adc_dfmt_data_s),
@ -166,8 +168,8 @@ module axi_ad9361_rx_channel #(
ad_iqcor #( ad_iqcor #(
.Q_OR_I_N (Q_OR_I_N), .Q_OR_I_N (Q_OR_I_N),
.DISABLE (IQCORRECTION_DISABLE)) .DISABLE (IQCORRECTION_DISABLE)
i_ad_iqcor ( ) i_ad_iqcor (
.clk (adc_clk), .clk (adc_clk),
.valid (adc_dcfilter_valid_s), .valid (adc_dcfilter_valid_s),
.data_in (adc_dcfilter_data_s), .data_in (adc_dcfilter_data_s),
@ -183,8 +185,8 @@ module axi_ad9361_rx_channel #(
.USERPORTS_DISABLE (USERPORTS_DISABLE), .USERPORTS_DISABLE (USERPORTS_DISABLE),
.DATAFORMAT_DISABLE (DATAFORMAT_DISABLE), .DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
.DCFILTER_DISABLE (DCFILTER_DISABLE), .DCFILTER_DISABLE (DCFILTER_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)) .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)
i_up_adc_channel ( ) i_up_adc_channel (
.adc_clk (adc_clk), .adc_clk (adc_clk),
.adc_rst (adc_rst), .adc_rst (adc_rst),
.adc_enable (adc_enable), .adc_enable (adc_enable),
@ -232,9 +234,4 @@ module axi_ad9361_rx_channel #(
end end
endgenerate endgenerate
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

14
library/axi_ad9361/axi_ad9361_rx_pnmon.v
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@ -39,7 +39,8 @@
module axi_ad9361_rx_pnmon #( module axi_ad9361_rx_pnmon #(
parameter Q_OR_I_N = 0, parameter Q_OR_I_N = 0,
parameter PRBS_SEL = 0) ( parameter PRBS_SEL = 0
) (
// adc interface // adc interface
@ -52,7 +53,8 @@ module axi_ad9361_rx_pnmon #(
input [ 3:0] adc_pnseq_sel, input [ 3:0] adc_pnseq_sel,
output adc_pn_oos, output adc_pn_oos,
output adc_pn_err); output adc_pn_err
);
localparam PRBS_P09 = 0; localparam PRBS_P09 = 0;
localparam PRBS_P11 = 1; localparam PRBS_P11 = 1;
@ -287,7 +289,9 @@ module axi_ad9361_rx_pnmon #(
// pn oos & pn err // pn oos & pn err
ad_pnmon #(.DATA_WIDTH(24)) i_pnmon ( ad_pnmon #(
.DATA_WIDTH(24)
) i_pnmon (
.adc_clk (adc_clk), .adc_clk (adc_clk),
.adc_valid_in (adc_pn_valid_in), .adc_valid_in (adc_pn_valid_in),
.adc_data_in (adc_pn_data_in), .adc_data_in (adc_pn_data_in),
@ -297,7 +301,3 @@ module axi_ad9361_rx_pnmon #(
.adc_pn_err (adc_pn_err)); .adc_pn_err (adc_pn_err));
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

9
library/axi_ad9361/axi_ad9361_tdd.v
View File

@ -75,7 +75,8 @@ module axi_ad9361_tdd (
input up_rreq, input up_rreq,
input [13:0] up_raddr, input [13:0] up_raddr,
output [31:0] up_rdata, output [31:0] up_rdata,
output up_rack); output up_rack
);
// internal signals // internal signals
@ -152,7 +153,7 @@ module axi_ad9361_tdd (
// instantiations // instantiations
up_tdd_cntrl i_up_tdd_cntrl( up_tdd_cntrl i_up_tdd_cntrl (
.clk(clk), .clk(clk),
.rst(rst), .rst(rst),
.tdd_enable(tdd_enable_s), .tdd_enable(tdd_enable_s),
@ -206,8 +207,8 @@ module axi_ad9361_tdd (
ad_tdd_control #( ad_tdd_control #(
.TX_DATA_PATH_DELAY(), .TX_DATA_PATH_DELAY(),
.CONTROL_PATH_DELAY()) .CONTROL_PATH_DELAY()
i_tdd_control( ) i_tdd_control(
.clk(clk), .clk(clk),
.rst(rst), .rst(rst),
.tdd_enable(tdd_enable_s), .tdd_enable(tdd_enable_s),

17
library/axi_ad9361/axi_ad9361_tdd_if.v
View File

@ -35,12 +35,9 @@
`timescale 1ns/1ps `timescale 1ns/1ps
module axi_ad9361_tdd_if#( module axi_ad9361_tdd_if #(
parameter LEVEL_OR_PULSE_N = 0
parameter LEVEL_OR_PULSE_N = 0) ( ) (
// clock
input clk, input clk,
input rst, input rst,
@ -58,15 +55,14 @@ module axi_ad9361_tdd_if#(
// interface status // interface status
output [ 7:0] ad9361_tdd_status); output [ 7:0] ad9361_tdd_status
);
localparam PULSE_MODE = 0; localparam PULSE_MODE = 0;
localparam LEVEL_MODE = 1; localparam LEVEL_MODE = 1;
// internal registers // internal registers
reg tdd_vco_overlap = 1'b0; reg tdd_vco_overlap = 1'b0;
reg tdd_rf_overlap = 1'b0; reg tdd_rf_overlap = 1'b0;
@ -91,7 +87,7 @@ module axi_ad9361_tdd_if#(
endgenerate endgenerate
always @(posedge clk) begin always @(posedge clk) begin
if(rst == 1'b1) begin if (rst == 1'b1) begin
tdd_vco_overlap <= 1'b0; tdd_vco_overlap <= 1'b0;
tdd_rf_overlap <= 1'b0; tdd_rf_overlap <= 1'b0;
end else begin end else begin
@ -106,4 +102,3 @@ module axi_ad9361_tdd_if#(
assign ad9361_enable = ad9361_enable_s; assign ad9361_enable = ad9361_enable_s;
endmodule endmodule

33
library/axi_ad9361/axi_ad9361_tx.v
View File

@ -55,7 +55,8 @@ module axi_ad9361_tx #(
parameter DAC_DDS_CORDIC_PHASE_DW = 13, parameter DAC_DDS_CORDIC_PHASE_DW = 13,
parameter USERPORTS_DISABLE = 0, parameter USERPORTS_DISABLE = 0,
parameter DELAYCNTRL_DISABLE = 0, parameter DELAYCNTRL_DISABLE = 0,
parameter IQCORRECTION_DISABLE = 0) ( parameter IQCORRECTION_DISABLE = 0
) (
// dac interface // dac interface
@ -119,7 +120,8 @@ module axi_ad9361_tx #(
input up_rreq, input up_rreq,
input [13:0] up_raddr, input [13:0] up_raddr,
output [31:0] up_rdata, output [31:0] up_rdata,
output up_rack); output up_rack
);
// configuration settings // configuration settings
@ -227,8 +229,8 @@ module axi_ad9361_tx #(
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.USERPORTS_DISABLE (USERPORTS_DISABLE), .USERPORTS_DISABLE (USERPORTS_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)) .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)
i_tx_channel_0 ( ) i_tx_channel_0 (
.dac_clk (dac_clk), .dac_clk (dac_clk),
.dac_rst (dac_rst), .dac_rst (dac_rst),
.dac_valid (dac_valid_int), .dac_valid (dac_valid_int),
@ -262,8 +264,8 @@ module axi_ad9361_tx #(
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.USERPORTS_DISABLE (USERPORTS_DISABLE), .USERPORTS_DISABLE (USERPORTS_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)) .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)
i_tx_channel_1 ( ) i_tx_channel_1 (
.dac_clk (dac_clk), .dac_clk (dac_clk),
.dac_rst (dac_rst), .dac_rst (dac_rst),
.dac_valid (dac_valid_int), .dac_valid (dac_valid_int),
@ -297,8 +299,8 @@ module axi_ad9361_tx #(
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.USERPORTS_DISABLE (USERPORTS_DISABLE), .USERPORTS_DISABLE (USERPORTS_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)) .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)
i_tx_channel_2 ( ) i_tx_channel_2 (
.dac_clk (dac_clk), .dac_clk (dac_clk),
.dac_rst (dac_rst), .dac_rst (dac_rst),
.dac_valid (dac_valid_int), .dac_valid (dac_valid_int),
@ -332,8 +334,8 @@ module axi_ad9361_tx #(
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.USERPORTS_DISABLE (USERPORTS_DISABLE), .USERPORTS_DISABLE (USERPORTS_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)) .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)
i_tx_channel_3 ( ) i_tx_channel_3 (
.dac_clk (dac_clk), .dac_clk (dac_clk),
.dac_rst (dac_rst), .dac_rst (dac_rst),
.dac_valid (dac_valid_int), .dac_valid (dac_valid_int),
@ -368,8 +370,8 @@ module axi_ad9361_tx #(
.CLK_EDGE_SEL (CLK_EDGE_SEL), .CLK_EDGE_SEL (CLK_EDGE_SEL),
.DRP_DISABLE (1), .DRP_DISABLE (1),
.USERPORTS_DISABLE (USERPORTS_DISABLE), .USERPORTS_DISABLE (USERPORTS_DISABLE),
.GPIO_DISABLE (0)) .GPIO_DISABLE (0)
i_up_dac_common ( ) i_up_dac_common (
.mmcm_rst (), .mmcm_rst (),
.dac_clk (dac_clk), .dac_clk (dac_clk),
.dac_rst (dac_rst), .dac_rst (dac_rst),
@ -419,8 +421,8 @@ module axi_ad9361_tx #(
.DISABLE (DELAYCNTRL_DISABLE), .DISABLE (DELAYCNTRL_DISABLE),
.INIT_DELAY (INIT_DELAY), .INIT_DELAY (INIT_DELAY),
.DATA_WIDTH(16), .DATA_WIDTH(16),
.BASE_ADDRESS(6'h12)) .BASE_ADDRESS(6'h12)
i_delay_cntrl ( ) i_delay_cntrl (
.delay_clk (delay_clk), .delay_clk (delay_clk),
.delay_rst (delay_rst), .delay_rst (delay_rst),
.delay_locked (delay_locked), .delay_locked (delay_locked),
@ -439,6 +441,3 @@ module axi_ad9361_tx #(
.up_rack (up_rack_s[5])); .up_rack (up_rack_s[5]));
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

21
library/axi_ad9361/axi_ad9361_tx_channel.v
View File

@ -47,7 +47,8 @@ module axi_ad9361_tx_channel #(
parameter DAC_DDS_CORDIC_DW = 14, parameter DAC_DDS_CORDIC_DW = 14,
parameter DAC_DDS_CORDIC_PHASE_DW = 13, parameter DAC_DDS_CORDIC_PHASE_DW = 13,
parameter USERPORTS_DISABLE = 0, parameter USERPORTS_DISABLE = 0,
parameter IQCORRECTION_DISABLE = 0) ( parameter IQCORRECTION_DISABLE = 0
) (
// dac interface // dac interface
@ -77,7 +78,8 @@ module axi_ad9361_tx_channel #(
input up_rreq, input up_rreq,
input [13:0] up_raddr, input [13:0] up_raddr,
output [31:0] up_rdata, output [31:0] up_rdata,
output up_rack); output up_rack
);
// parameters // parameters
@ -258,8 +260,8 @@ module axi_ad9361_tx_channel #(
ad_iqcor #( ad_iqcor #(
.Q_OR_I_N (Q_OR_I_N), .Q_OR_I_N (Q_OR_I_N),
.DISABLE (IQCORRECTION_DISABLE)) .DISABLE (IQCORRECTION_DISABLE)
i_ad_iqcor ( ) i_ad_iqcor (
.clk (dac_clk), .clk (dac_clk),
.valid (dac_valid), .valid (dac_valid),
.data_in ({dac_data_out_int, 4'd0}), .data_in ({dac_data_out_int, 4'd0}),
@ -323,8 +325,8 @@ module axi_ad9361_tx_channel #(
.DDS_TYPE (DAC_DDS_TYPE), .DDS_TYPE (DAC_DDS_TYPE),
.CORDIC_DW (DAC_DDS_CORDIC_DW), .CORDIC_DW (DAC_DDS_CORDIC_DW),
.CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), .CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.CLK_RATIO (1)) .CLK_RATIO (1)
i_dds ( ) i_dds (
.clk (dac_clk), .clk (dac_clk),
.dac_dds_format (dac_dds_format), .dac_dds_format (dac_dds_format),
.dac_data_sync (dac_data_sync), .dac_data_sync (dac_data_sync),
@ -348,8 +350,8 @@ module axi_ad9361_tx_channel #(
.CHANNEL_ID (CHANNEL_ID), .CHANNEL_ID (CHANNEL_ID),
.DDS_DISABLE (DAC_DDS_DISABLE), .DDS_DISABLE (DAC_DDS_DISABLE),
.USERPORTS_DISABLE (USERPORTS_DISABLE), .USERPORTS_DISABLE (USERPORTS_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)) .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)
i_up_dac_channel ( ) i_up_dac_channel (
.dac_clk (dac_clk), .dac_clk (dac_clk),
.dac_rst (dac_rst), .dac_rst (dac_rst),
.dac_dds_scale_1 (dac_dds_scale_1_s), .dac_dds_scale_1 (dac_dds_scale_1_s),
@ -391,6 +393,3 @@ module axi_ad9361_tx_channel #(
.up_rack (up_rack_s)); .up_rack (up_rack_s));
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

3
library/axi_ad9361/intel/axi_ad9361_alt_lvds_rx.v
View File

@ -54,7 +54,8 @@ module axi_ad9361_alt_lvds_rx (
output [ 5:0] rx_data_1, output [ 5:0] rx_data_1,
output [ 5:0] rx_data_2, output [ 5:0] rx_data_2,
output [ 5:0] rx_data_3, output [ 5:0] rx_data_3,
output rx_locked); output rx_locked
);
// internal signals // internal signals

3
library/axi_ad9361/intel/axi_ad9361_alt_lvds_tx.v
View File

@ -55,7 +55,8 @@ module axi_ad9361_alt_lvds_tx (
input [ 5:0] tx_data_1, input [ 5:0] tx_data_1,
input [ 5:0] tx_data_2, input [ 5:0] tx_data_2,
input [ 5:0] tx_data_3, input [ 5:0] tx_data_3,
output tx_locked); output tx_locked
);
// internal registers // internal registers

9
library/axi_ad9361/intel/axi_ad9361_cmos_if.v
View File

@ -45,7 +45,8 @@ module axi_ad9361_cmos_if #(
// Dummy parameters, required keep the code consistency(used on Xilinx) // Dummy parameters, required keep the code consistency(used on Xilinx)
parameter IO_DELAY_GROUP = "dev_if_delay_group", parameter IO_DELAY_GROUP = "dev_if_delay_group",
parameter IODELAY_CTRL = 1, parameter IODELAY_CTRL = 1,
parameter DELAY_REFCLK_FREQUENCY = 0) ( parameter DELAY_REFCLK_FREQUENCY = 0
) (
// physical interface (receive) // physical interface (receive)
@ -116,7 +117,8 @@ module axi_ad9361_cmos_if #(
input [31:0] up_drp_wdata, input [31:0] up_drp_wdata,
output [31:0] up_drp_rdata, output [31:0] up_drp_rdata,
output up_drp_ready, output up_drp_ready,
output up_drp_locked); output up_drp_locked
);
// cmos is not supported on intel platforms yet. // cmos is not supported on intel platforms yet.
@ -137,6 +139,3 @@ module axi_ad9361_cmos_if #(
assign up_drp_locked = 1'd0; assign up_drp_locked = 1'd0;
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

15
library/axi_ad9361/intel/axi_ad9361_lvds_if.v
View File

@ -46,7 +46,8 @@ module axi_ad9361_lvds_if #(
parameter IO_DELAY_GROUP = "dev_if_delay_group", parameter IO_DELAY_GROUP = "dev_if_delay_group",
parameter IODELAY_CTRL = 1, parameter IODELAY_CTRL = 1,
parameter DELAY_REFCLK_FREQUENCY = 0, parameter DELAY_REFCLK_FREQUENCY = 0,
parameter RX_NODPA = 0) ( parameter RX_NODPA = 0
) (
// physical interface (receive) // physical interface (receive)
@ -123,7 +124,8 @@ module axi_ad9361_lvds_if #(
input [31:0] up_drp_wdata, input [31:0] up_drp_wdata,
output [31:0] up_drp_rdata, output [31:0] up_drp_rdata,
output up_drp_ready, output up_drp_ready,
output up_drp_locked); output up_drp_locked
);
// internal registers // internal registers
@ -218,7 +220,7 @@ module axi_ad9361_lvds_if #(
end end
end end
endgenerate endgenerate
// frame check // frame check
@ -531,8 +533,8 @@ endgenerate
generate generate
if (FPGA_TECHNOLOGY == ARRIA10) begin if (FPGA_TECHNOLOGY == ARRIA10) begin
axi_ad9361_lvds_if_10 #( axi_ad9361_lvds_if_10 #(
.RX_NODPA (RX_NODPA)) .RX_NODPA (RX_NODPA)
i_axi_ad9361_lvds_if_10 ( ) i_axi_ad9361_lvds_if_10 (
.rx_clk_in_p (rx_clk_in_p), .rx_clk_in_p (rx_clk_in_p),
.rx_clk_in_n (rx_clk_in_n), .rx_clk_in_n (rx_clk_in_n),
.rx_frame_in_p (rx_frame_in_p), .rx_frame_in_p (rx_frame_in_p),
@ -567,6 +569,3 @@ endgenerate
endgenerate endgenerate
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

11
library/axi_ad9361/intel/axi_ad9361_lvds_if_10.v
View File

@ -37,7 +37,8 @@
module axi_ad9361_lvds_if_10 #( module axi_ad9361_lvds_if_10 #(
parameter RX_NODPA = 0) ( parameter RX_NODPA = 0
) (
// physical interface (receive) // physical interface (receive)
@ -91,7 +92,8 @@ module axi_ad9361_lvds_if_10 #(
// delay interface // delay interface
input up_clk, input up_clk,
input up_rstn); input up_rstn
);
// internal registers // internal registers
@ -236,7 +238,7 @@ module axi_ad9361_lvds_if_10 #(
.data_s_export (rx_data_s[27:24]), .data_s_export (rx_data_s[27:24]),
.delay_locked_export (rx_delay_locked_s[6])); .delay_locked_export (rx_delay_locked_s[6]));
assign rx_clk = rx_clk_in_p; assign rx_clk = rx_clk_in_p;
end else begin end else begin
@ -302,6 +304,3 @@ module axi_ad9361_lvds_if_10 #(
.ls_clk_clk (clk)); .ls_clk_clk (clk));
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

6
library/axi_ad9361/intel/axi_ad9361_lvds_if_c5.v
View File

@ -89,7 +89,8 @@ module axi_ad9361_lvds_if_c5 (
// delay interface // delay interface
input up_clk, input up_clk,
input up_rstn); input up_rstn
);
// internal registers // internal registers
@ -392,6 +393,3 @@ module axi_ad9361_lvds_if_c5 (
.sset (1'b0)); .sset (1'b0));
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

41
library/axi_ad9361/xilinx/axi_ad9361_cmos_if.v
View File

@ -43,7 +43,8 @@ module axi_ad9361_cmos_if #(
parameter IODELAY_CTRL = 1, parameter IODELAY_CTRL = 1,
parameter CLK_DESKEW = 0, parameter CLK_DESKEW = 0,
parameter USE_SSI_CLK = 1, parameter USE_SSI_CLK = 1,
parameter DELAY_REFCLK_FREQUENCY = 200) ( parameter DELAY_REFCLK_FREQUENCY = 200
) (
// physical interface (receive) // physical interface (receive)
@ -114,7 +115,8 @@ module axi_ad9361_cmos_if #(
input [31:0] up_drp_wdata, input [31:0] up_drp_wdata,
output [31:0] up_drp_rdata, output [31:0] up_drp_rdata,
output up_drp_ready, output up_drp_ready,
output up_drp_locked); output up_drp_locked
);
// internal registers // internal registers
@ -439,8 +441,8 @@ module axi_ad9361_cmos_if #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_CTRL (0), .IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP), .IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)) .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
i_rx_data ( ) i_rx_data (
.rx_clk (l_clk), .rx_clk (l_clk),
.rx_data_in_p (rx_data_in[i]), .rx_data_in_p (rx_data_in[i]),
.rx_data_in_n (1'd0), .rx_data_in_n (1'd0),
@ -463,8 +465,8 @@ module axi_ad9361_cmos_if #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_CTRL (IODELAY_CTRL), .IODELAY_CTRL (IODELAY_CTRL),
.IODELAY_GROUP (IO_DELAY_GROUP), .IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)) .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
i_rx_frame ( ) i_rx_frame (
.rx_clk (l_clk), .rx_clk (l_clk),
.rx_data_in_p (rx_frame_in), .rx_data_in_p (rx_frame_in),
.rx_data_in_n (1'd0), .rx_data_in_n (1'd0),
@ -488,8 +490,8 @@ module axi_ad9361_cmos_if #(
.IODELAY_ENABLE (DAC_IODELAY_ENABLE), .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0), .IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP), .IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)) .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
i_tx_data ( ) i_tx_data (
.tx_clk (l_clk), .tx_clk (l_clk),
.tx_data_p (tx_data_1[i]), .tx_data_p (tx_data_1[i]),
.tx_data_n (tx_data_0[i]), .tx_data_n (tx_data_0[i]),
@ -513,8 +515,8 @@ module axi_ad9361_cmos_if #(
.IODELAY_ENABLE (DAC_IODELAY_ENABLE), .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0), .IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP), .IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)) .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
i_tx_frame ( ) i_tx_frame (
.tx_clk (l_clk), .tx_clk (l_clk),
.tx_data_p (tx_frame[1]), .tx_data_p (tx_frame[1]),
.tx_data_n (tx_frame[0]), .tx_data_n (tx_frame[0]),
@ -536,8 +538,8 @@ module axi_ad9361_cmos_if #(
.IODELAY_ENABLE (DAC_IODELAY_ENABLE), .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0), .IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP), .IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)) .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
i_tx_clk ( ) i_tx_clk (
.tx_clk (l_clk), .tx_clk (l_clk),
.tx_data_p (tx_clk[1]), .tx_data_p (tx_clk[1]),
.tx_data_n (tx_clk[0]), .tx_data_n (tx_clk[0]),
@ -559,8 +561,8 @@ module axi_ad9361_cmos_if #(
.IODELAY_ENABLE (DAC_IODELAY_ENABLE), .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0), .IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP), .IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)) .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
i_enable ( ) i_enable (
.tx_clk (l_clk), .tx_clk (l_clk),
.tx_data_p (enable_int_p), .tx_data_p (enable_int_p),
.tx_data_n (enable_int_p), .tx_data_n (enable_int_p),
@ -582,8 +584,8 @@ module axi_ad9361_cmos_if #(
.IODELAY_ENABLE (DAC_IODELAY_ENABLE), .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0), .IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP), .IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)) .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
i_txnrx ( ) i_txnrx (
.tx_clk (l_clk), .tx_clk (l_clk),
.tx_data_p (txnrx_int_p), .tx_data_p (txnrx_int_p),
.tx_data_n (txnrx_int_p), .tx_data_n (txnrx_int_p),
@ -601,8 +603,8 @@ module axi_ad9361_cmos_if #(
generate if (USE_SSI_CLK == 1) begin generate if (USE_SSI_CLK == 1) begin
ad_data_clk #( ad_data_clk #(
.SINGLE_ENDED (1)) .SINGLE_ENDED (1)
i_clk ( ) i_clk (
.rst (1'd0), .rst (1'd0),
.locked (), .locked (),
.clk_in_p (rx_clk_in), .clk_in_p (rx_clk_in),
@ -614,6 +616,3 @@ module axi_ad9361_cmos_if #(
endgenerate endgenerate
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

41
library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v
View File

@ -44,7 +44,8 @@ module axi_ad9361_lvds_if #(
parameter CLK_DESKEW = 0, parameter CLK_DESKEW = 0,
parameter USE_SSI_CLK = 1, parameter USE_SSI_CLK = 1,
parameter DELAY_REFCLK_FREQUENCY = 200, parameter DELAY_REFCLK_FREQUENCY = 200,
parameter RX_NODPA = 0) ( parameter RX_NODPA = 0
) (
// physical interface (receive) // physical interface (receive)
@ -121,7 +122,8 @@ module axi_ad9361_lvds_if #(
input [31:0] up_drp_wdata, input [31:0] up_drp_wdata,
output [31:0] up_drp_rdata, output [31:0] up_drp_rdata,
output up_drp_ready, output up_drp_ready,
output up_drp_locked); output up_drp_locked
);
// internal registers // internal registers
@ -213,7 +215,6 @@ module axi_ad9361_lvds_if #(
// frame check // frame check
// delineation // delineation
reg rx_error_r1 = 'd0; reg rx_error_r1 = 'd0;
reg rx_error_r2 = 'd0; reg rx_error_r2 = 'd0;
@ -454,8 +455,8 @@ module axi_ad9361_lvds_if #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_CTRL (0), .IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP), .IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)) .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
i_rx_data ( ) i_rx_data (
.rx_clk (l_clk), .rx_clk (l_clk),
.rx_data_in_p (rx_data_in_p[i]), .rx_data_in_p (rx_data_in_p[i]),
.rx_data_in_n (rx_data_in_n[i]), .rx_data_in_n (rx_data_in_n[i]),
@ -477,8 +478,8 @@ module axi_ad9361_lvds_if #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_CTRL (IODELAY_CTRL), .IODELAY_CTRL (IODELAY_CTRL),
.IODELAY_GROUP (IO_DELAY_GROUP), .IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)) .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
i_rx_frame ( ) i_rx_frame (
.rx_clk (l_clk), .rx_clk (l_clk),
.rx_data_in_p (rx_frame_in_p), .rx_data_in_p (rx_frame_in_p),
.rx_data_in_n (rx_frame_in_n), .rx_data_in_n (rx_frame_in_n),
@ -501,8 +502,8 @@ module axi_ad9361_lvds_if #(
.IODELAY_ENABLE (DAC_IODELAY_ENABLE), .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0), .IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP), .IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)) .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
i_tx_data ( ) i_tx_data (
.tx_clk (l_clk), .tx_clk (l_clk),
.tx_data_p (tx_data_1[i]), .tx_data_p (tx_data_1[i]),
.tx_data_n (tx_data_0[i]), .tx_data_n (tx_data_0[i]),
@ -525,8 +526,8 @@ module axi_ad9361_lvds_if #(
.IODELAY_ENABLE (DAC_IODELAY_ENABLE), .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0), .IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP), .IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)) .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
i_tx_frame ( ) i_tx_frame (
.tx_clk (l_clk), .tx_clk (l_clk),
.tx_data_p (tx_frame), .tx_data_p (tx_frame),
.tx_data_n (tx_frame), .tx_data_n (tx_frame),
@ -547,8 +548,8 @@ module axi_ad9361_lvds_if #(
.IODELAY_ENABLE (DAC_IODELAY_ENABLE), .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0), .IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP), .IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)) .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
i_tx_clk ( ) i_tx_clk (
.tx_clk (l_clk), .tx_clk (l_clk),
.tx_data_p (tx_clk[1]), .tx_data_p (tx_clk[1]),
.tx_data_n (tx_clk[0]), .tx_data_n (tx_clk[0]),
@ -570,8 +571,8 @@ module axi_ad9361_lvds_if #(
.IODELAY_ENABLE (DAC_IODELAY_ENABLE), .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0), .IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP), .IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)) .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
i_enable ( ) i_enable (
.tx_clk (l_clk), .tx_clk (l_clk),
.tx_data_p (enable_int_p), .tx_data_p (enable_int_p),
.tx_data_n (enable_int_p), .tx_data_n (enable_int_p),
@ -593,8 +594,8 @@ module axi_ad9361_lvds_if #(
.IODELAY_ENABLE (DAC_IODELAY_ENABLE), .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0), .IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP), .IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)) .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
i_txnrx ( ) i_txnrx (
.tx_clk (l_clk), .tx_clk (l_clk),
.tx_data_p (txnrx_int_p), .tx_data_p (txnrx_int_p),
.tx_data_n (txnrx_int_p), .tx_data_n (txnrx_int_p),
@ -610,8 +611,7 @@ module axi_ad9361_lvds_if #(
// device clock interface (receive clock) // device clock interface (receive clock)
generate if (USE_SSI_CLK == 1) begin generate if (USE_SSI_CLK == 1) begin
ad_data_clk ad_data_clk i_clk (
i_clk (
.rst (1'd0), .rst (1'd0),
.locked (), .locked (),
.clk_in_p (rx_clk_in_p), .clk_in_p (rx_clk_in_p),
@ -623,6 +623,3 @@ module axi_ad9361_lvds_if #(
endgenerate endgenerate
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

10
library/axi_ad9434/axi_ad9434.v
View File

@ -43,7 +43,8 @@ module axi_ad9434 #(
parameter FPGA_FAMILY = 0, parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0, parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0, parameter DEV_PACKAGE = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group") ( parameter IO_DELAY_GROUP = "dev_if_delay_group"
) (
// physical interface // physical interface
input adc_clk_in_p, input adc_clk_in_p,
@ -84,7 +85,8 @@ module axi_ad9434 #(
output [31:0] s_axi_rdata, output [31:0] s_axi_rdata,
input s_axi_rready, input s_axi_rready,
input [ 2:0] s_axi_awprot, input [ 2:0] s_axi_awprot,
input [ 2:0] s_axi_arprot); input [ 2:0] s_axi_arprot
);
// internal clocks & resets // internal clocks & resets
wire adc_rst; wire adc_rst;
@ -131,8 +133,8 @@ module axi_ad9434 #(
axi_ad9434_if #( axi_ad9434_if #(
.FPGA_TECHNOLOGY(FPGA_TECHNOLOGY), .FPGA_TECHNOLOGY(FPGA_TECHNOLOGY),
.IO_DELAY_GROUP(IO_DELAY_GROUP)) .IO_DELAY_GROUP(IO_DELAY_GROUP)
i_if( ) i_if (
.adc_clk_in_p(adc_clk_in_p), .adc_clk_in_p(adc_clk_in_p),
.adc_clk_in_n(adc_clk_in_n), .adc_clk_in_n(adc_clk_in_n),
.adc_data_in_p(adc_data_in_p), .adc_data_in_p(adc_data_in_p),

41
library/axi_ad9434/axi_ad9434_core.v
View File

@ -41,7 +41,8 @@ module axi_ad9434_core #(
parameter FPGA_TECHNOLOGY = 0, parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0, parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0, parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0) ( parameter DEV_PACKAGE = 0
) (
// device interface // device interface
@ -92,7 +93,8 @@ module axi_ad9434_core #(
output mmcm_rst, output mmcm_rst,
output adc_rst, output adc_rst,
output adc_enable, output adc_enable,
input adc_status); input adc_status
);
// internal signals // internal signals
wire up_status_pn_err_s; wire up_status_pn_err_s;
@ -122,17 +124,17 @@ module axi_ad9434_core #(
genvar n; genvar n;
generate generate
for (n = 0; n < 4; n = n + 1) begin: g_ad_dfmt for (n = 0; n < 4; n = n + 1) begin: g_ad_dfmt
ad_datafmt # ( ad_datafmt #(
.DATA_WIDTH(12)) .DATA_WIDTH(12)
i_datafmt ( ) i_datafmt (
.clk (adc_clk), .clk (adc_clk),
.valid (1'b1), .valid (1'b1),
.data (adc_data[n*12+11:n*12]), .data (adc_data[n*12+11:n*12]),
.valid_out (dma_dvalid), .valid_out (dma_dvalid),
.data_out (dma_data[n*16+15:n*16]), .data_out (dma_data[n*16+15:n*16]),
.dfmt_enable (adc_dfmt_enable_s), .dfmt_enable (adc_dfmt_enable_s),
.dfmt_type (adc_dfmt_type_s), .dfmt_type (adc_dfmt_type_s),
.dfmt_se (adc_dfmt_se_s)); .dfmt_se (adc_dfmt_se_s));
end end
endgenerate endgenerate
@ -161,8 +163,8 @@ module axi_ad9434_core #(
.DRP_DISABLE(0), .DRP_DISABLE(0),
.USERPORTS_DISABLE(1), .USERPORTS_DISABLE(1),
.GPIO_DISABLE(1), .GPIO_DISABLE(1),
.START_CODE_DISABLE(1)) .START_CODE_DISABLE(1)
i_adc_common( ) i_adc_common(
.mmcm_rst (mmcm_rst), .mmcm_rst (mmcm_rst),
.adc_clk (adc_clk), .adc_clk (adc_clk),
@ -216,8 +218,8 @@ module axi_ad9434_core #(
.USERPORTS_DISABLE(1), .USERPORTS_DISABLE(1),
.DATAFORMAT_DISABLE(0), .DATAFORMAT_DISABLE(0),
.DCFILTER_DISABLE(1), .DCFILTER_DISABLE(1),
.IQCORRECTION_DISABLE(1)) .IQCORRECTION_DISABLE(1)
i_adc_channel( ) i_adc_channel(
.adc_clk (adc_clk), .adc_clk (adc_clk),
.adc_rst (adc_rst), .adc_rst (adc_rst),
.adc_enable (adc_enable), .adc_enable (adc_enable),
@ -265,7 +267,10 @@ module axi_ad9434_core #(
// adc delay control // adc delay control
up_delay_cntrl #(.DATA_WIDTH(13), .BASE_ADDRESS(6'h02)) i_delay_cntrl ( up_delay_cntrl #(
.DATA_WIDTH(13),
.BASE_ADDRESS(6'h02)
) i_delay_cntrl (
.delay_clk (delay_clk), .delay_clk (delay_clk),
.delay_rst (delay_rst), .delay_rst (delay_rst),
.delay_locked (delay_locked), .delay_locked (delay_locked),

19
library/axi_ad9434/axi_ad9434_if.v
View File

@ -38,7 +38,8 @@
module axi_ad9434_if #( module axi_ad9434_if #(
parameter FPGA_TECHNOLOGY = 0, parameter FPGA_TECHNOLOGY = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group") ( parameter IO_DELAY_GROUP = "dev_if_delay_group"
) (
// device interface // device interface
input adc_clk_in_p, input adc_clk_in_p,
@ -77,8 +78,8 @@ module axi_ad9434_if #(
input [31:0] up_drp_wdata, input [31:0] up_drp_wdata,
output [31:0] up_drp_rdata, output [31:0] up_drp_rdata,
output up_drp_ready, output up_drp_ready,
output up_drp_locked); output up_drp_locked
);
localparam SDR = 0; localparam SDR = 0;
@ -105,8 +106,8 @@ module axi_ad9434_if #(
.IODELAY_GROUP(IO_DELAY_GROUP), .IODELAY_GROUP(IO_DELAY_GROUP),
.DDR_OR_SDR_N(SDR), .DDR_OR_SDR_N(SDR),
.DATA_WIDTH(12), .DATA_WIDTH(12),
.SERDES_FACTOR(4)) .SERDES_FACTOR(4)
i_adc_data ( ) i_adc_data (
.rst(adc_rst), .rst(adc_rst),
.clk(adc_clk_in), .clk(adc_clk_in),
.div_clk(adc_div_clk), .div_clk(adc_div_clk),
@ -138,8 +139,8 @@ module axi_ad9434_if #(
.IODELAY_GROUP(IO_DELAY_GROUP), .IODELAY_GROUP(IO_DELAY_GROUP),
.DDR_OR_SDR_N(SDR), .DDR_OR_SDR_N(SDR),
.DATA_WIDTH(1), .DATA_WIDTH(1),
.SERDES_FACTOR(4)) .SERDES_FACTOR(4)
i_adc_or ( ) i_adc_or (
.rst(adc_rst), .rst(adc_rst),
.clk(adc_clk_in), .clk(adc_clk_in),
.div_clk(adc_div_clk), .div_clk(adc_div_clk),
@ -174,8 +175,8 @@ module axi_ad9434_if #(
.MMCM_VCO_MUL (12), .MMCM_VCO_MUL (12),
.MMCM_CLK0_DIV (2), .MMCM_CLK0_DIV (2),
.MMCM_CLK1_DIV (8), .MMCM_CLK1_DIV (8),
.SERDES_FACTOR(4)) .SERDES_FACTOR(4)
i_serdes_clk ( ) i_serdes_clk (
.rst (mmcm_rst), .rst (mmcm_rst),
.clk_in_p (adc_clk_in_p), .clk_in_p (adc_clk_in_p),
.clk_in_n (adc_clk_in_n), .clk_in_n (adc_clk_in_n),

7
library/axi_ad9434/axi_ad9434_pnmon.v
View File

@ -44,7 +44,8 @@ module axi_ad9434_pnmon (
// pn interface // pn interface
input [ 3:0] adc_pnseq_sel, input [ 3:0] adc_pnseq_sel,
output adc_pn_err, output adc_pn_err,
output adc_pn_oos); output adc_pn_oos
);
// internal registers // internal registers
reg [47:0] adc_pn_data_pn = 'd0; reg [47:0] adc_pn_data_pn = 'd0;
@ -181,7 +182,9 @@ module axi_ad9434_pnmon (
end end
// pn oos & pn err // pn oos & pn err
ad_pnmon #(.DATA_WIDTH(48)) i_pnmon ( ad_pnmon #(
.DATA_WIDTH(48)
) i_pnmon (
.adc_clk (adc_clk), .adc_clk (adc_clk),
.adc_valid_in (1'b1), .adc_valid_in (1'b1),
.adc_data_in (adc_data_inv_s), .adc_data_in (adc_data_inv_s),

27
library/axi_ad9467/axi_ad9467.v
View File

@ -43,7 +43,8 @@ module axi_ad9467#(
parameter SPEED_GRADE = 0, parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0, parameter DEV_PACKAGE = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group", parameter IO_DELAY_GROUP = "dev_if_delay_group",
parameter DELAY_REFCLK_FREQUENCY = 200) ( parameter DELAY_REFCLK_FREQUENCY = 200
) (
// physical interface // physical interface
@ -88,8 +89,8 @@ module axi_ad9467#(
output s_axi_rvalid, output s_axi_rvalid,
output [ 1:0] s_axi_rresp, output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata, output [31:0] s_axi_rdata,
input s_axi_rready); input s_axi_rready
);
// internal registers // internal registers
@ -150,8 +151,8 @@ module axi_ad9467#(
axi_ad9467_if #( axi_ad9467_if #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IO_DELAY_GROUP (IO_DELAY_GROUP), .IO_DELAY_GROUP (IO_DELAY_GROUP),
.DELAY_REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)) .DELAY_REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
i_if ( ) i_if (
.adc_clk_in_p (adc_clk_in_p), .adc_clk_in_p (adc_clk_in_p),
.adc_clk_in_n (adc_clk_in_n), .adc_clk_in_n (adc_clk_in_n),
.adc_data_in_p (adc_data_in_p), .adc_data_in_p (adc_data_in_p),
@ -172,7 +173,9 @@ module axi_ad9467#(
// channel // channel
axi_ad9467_channel #(.CHANNEL_ID(0)) i_channel ( axi_ad9467_channel #(
.CHANNEL_ID(0)
) i_channel (
.adc_clk (adc_clk), .adc_clk (adc_clk),
.adc_rst (adc_rst), .adc_rst (adc_rst),
.adc_data (adc_data_s), .adc_data (adc_data_s),
@ -195,7 +198,10 @@ module axi_ad9467#(
// adc delay control // adc delay control
up_delay_cntrl #(.DATA_WIDTH(9), .BASE_ADDRESS(6'h02)) i_delay_cntrl ( up_delay_cntrl #(
.DATA_WIDTH(9),
.BASE_ADDRESS(6'h02)
) i_delay_cntrl (
.delay_clk (delay_clk), .delay_clk (delay_clk),
.delay_rst (delay_rst), .delay_rst (delay_rst),
.delay_locked (delay_locked_s), .delay_locked (delay_locked_s),
@ -226,8 +232,8 @@ module axi_ad9467#(
.DRP_DISABLE (6'h00), .DRP_DISABLE (6'h00),
.USERPORTS_DISABLE (0), .USERPORTS_DISABLE (0),
.GPIO_DISABLE (0), .GPIO_DISABLE (0),
.START_CODE_DISABLE(0)) .START_CODE_DISABLE(0)
i_up_adc_common ( ) i_up_adc_common (
.mmcm_rst (), .mmcm_rst (),
.adc_clk (adc_clk), .adc_clk (adc_clk),
.adc_rst (adc_rst), .adc_rst (adc_rst),
@ -305,6 +311,3 @@ module axi_ad9467#(
.up_rack (up_rack)); .up_rack (up_rack));
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

18
library/axi_ad9467/axi_ad9467_channel.v
View File

@ -37,7 +37,8 @@
module axi_ad9467_channel#( module axi_ad9467_channel#(
parameter CHANNEL_ID = 0) ( parameter CHANNEL_ID = 0
) (
// adc interface // adc interface
@ -65,8 +66,8 @@ module axi_ad9467_channel#(
input up_rreq, input up_rreq,
input [13:0] up_raddr, input [13:0] up_raddr,
output [31:0] up_rdata, output [31:0] up_rdata,
output up_rack); output up_rack
);
// internal signals // internal signals
@ -86,7 +87,9 @@ module axi_ad9467_channel#(
.adc_pn_err (adc_pn_err_s), .adc_pn_err (adc_pn_err_s),
.adc_pnseq_sel (adc_pnseq_sel_s)); .adc_pnseq_sel (adc_pnseq_sel_s));
ad_datafmt #(.DATA_WIDTH(16)) i_datafmt ( ad_datafmt #(
.DATA_WIDTH(16)
) i_datafmt (
.clk(adc_clk), .clk(adc_clk),
.valid(1'b1), .valid(1'b1),
.data(adc_data), .data(adc_data),
@ -102,8 +105,8 @@ module axi_ad9467_channel#(
.USERPORTS_DISABLE (0), .USERPORTS_DISABLE (0),
.DATAFORMAT_DISABLE (0), .DATAFORMAT_DISABLE (0),
.DCFILTER_DISABLE (0), .DCFILTER_DISABLE (0),
.IQCORRECTION_DISABLE (0)) .IQCORRECTION_DISABLE (0)
i_up_adc_channel ( ) i_up_adc_channel (
.adc_clk (adc_clk), .adc_clk (adc_clk),
.adc_rst (adc_rst), .adc_rst (adc_rst),
.adc_enable (adc_enable), .adc_enable (adc_enable),
@ -150,6 +153,3 @@ module axi_ad9467_channel#(
.up_rack (up_rack)); .up_rack (up_rack));
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

21
library/axi_ad9467/axi_ad9467_if.v
View File

@ -40,7 +40,8 @@ module axi_ad9467_if #(
parameter FPGA_TECHNOLOGY = 0, parameter FPGA_TECHNOLOGY = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group", parameter IO_DELAY_GROUP = "dev_if_delay_group",
parameter DELAY_REFCLK_FREQUENCY = 200) ( parameter DELAY_REFCLK_FREQUENCY = 200
) (
// adc interface (clk, data, over-range) // adc interface (clk, data, over-range)
@ -69,8 +70,8 @@ module axi_ad9467_if #(
output [44:0] up_drdata, output [44:0] up_drdata,
input delay_clk, input delay_clk,
input delay_rst, input delay_rst,
output delay_locked); output delay_locked
);
// internal registers // internal registers
@ -132,8 +133,8 @@ module axi_ad9467_if #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_CTRL (0), .IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP), .IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)) .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
i_adc_data ( ) i_adc_data (
.rx_clk (adc_clk), .rx_clk (adc_clk),
.rx_data_in_p (adc_data_in_p[l_inst]), .rx_data_in_p (adc_data_in_p[l_inst]),
.rx_data_in_n (adc_data_in_n[l_inst]), .rx_data_in_n (adc_data_in_n[l_inst]),
@ -155,8 +156,8 @@ module axi_ad9467_if #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_CTRL (1), .IODELAY_CTRL (1),
.IODELAY_GROUP (IO_DELAY_GROUP), .IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)) .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
i_adc_or ( ) i_adc_or (
.rx_clk (adc_clk), .rx_clk (adc_clk),
.rx_data_in_p (adc_or_in_p), .rx_data_in_p (adc_or_in_p),
.rx_data_in_n (adc_or_in_n), .rx_data_in_n (adc_or_in_n),
@ -172,8 +173,7 @@ module axi_ad9467_if #(
// clock // clock
ad_data_clk ad_data_clk i_adc_clk (
i_adc_clk (
.rst (1'b0), .rst (1'b0),
.locked (), .locked (),
.clk_in_p (adc_clk_in_p), .clk_in_p (adc_clk_in_p),
@ -181,6 +181,3 @@ module axi_ad9467_if #(
.clk (adc_clk)); .clk (adc_clk));
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

11
library/axi_ad9467/axi_ad9467_pnmon.v
View File

@ -47,7 +47,8 @@ module axi_ad9467_pnmon (
output adc_pn_oos, output adc_pn_oos,
output adc_pn_err, output adc_pn_err,
input [ 3:0] adc_pnseq_sel); input [ 3:0] adc_pnseq_sel
);
// internal registers // internal registers
@ -161,7 +162,9 @@ module axi_ad9467_pnmon (
// pn oos & pn err // pn oos & pn err
ad_pnmon #(.DATA_WIDTH(32)) i_pnmon ( ad_pnmon #(
.DATA_WIDTH(32)
) i_pnmon (
.adc_clk (adc_clk), .adc_clk (adc_clk),
.adc_valid_in (adc_valid_in), .adc_valid_in (adc_valid_in),
.adc_data_in (adc_pn_data_in), .adc_data_in (adc_pn_data_in),
@ -171,7 +174,3 @@ module axi_ad9467_pnmon (
.adc_pn_err (adc_pn_err)); .adc_pn_err (adc_pn_err));
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

18
library/axi_ad9625/axi_ad9625.v
View File

@ -42,7 +42,8 @@ module axi_ad9625 #(
parameter FPGA_FAMILY = 0, parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0, parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0, parameter DEV_PACKAGE = 0,
parameter DELAY_REFCLK_FREQUENCY = 200) ( parameter DELAY_REFCLK_FREQUENCY = 200
) (
// jesd interface // jesd interface
// rx_clk is (line-rate/40) // rx_clk is (line-rate/40)
@ -87,7 +88,8 @@ module axi_ad9625 #(
output [ 31:0] s_axi_rdata, output [ 31:0] s_axi_rdata,
input s_axi_rready, input s_axi_rready,
input [ 2:0] s_axi_awprot, input [ 2:0] s_axi_awprot,
input [ 2:0] s_axi_arprot); input [ 2:0] s_axi_arprot
);
// internal registers // internal registers
@ -143,8 +145,8 @@ module axi_ad9625 #(
assign adc_valid = 1'b1; assign adc_valid = 1'b1;
axi_ad9625_if #( axi_ad9625_if #(
.ID (ID)) .ID (ID)
i_if ( ) i_if (
.rx_clk (rx_clk), .rx_clk (rx_clk),
.rx_sof (rx_sof), .rx_sof (rx_sof),
.rx_data (rx_data), .rx_data (rx_data),
@ -194,8 +196,8 @@ module axi_ad9625 #(
.DRP_DISABLE(1), .DRP_DISABLE(1),
.USERPORTS_DISABLE(1), .USERPORTS_DISABLE(1),
.GPIO_DISABLE(1), .GPIO_DISABLE(1),
.START_CODE_DISABLE(1)) .START_CODE_DISABLE(1)
i_up_adc_common ( ) i_up_adc_common (
.mmcm_rst (), .mmcm_rst (),
.adc_clk (adc_clk), .adc_clk (adc_clk),
.adc_rst (adc_rst), .adc_rst (adc_rst),
@ -270,7 +272,3 @@ module axi_ad9625 #(
.up_rack (up_rack)); .up_rack (up_rack));
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

15
library/axi_ad9625/axi_ad9625_channel.v
View File

@ -63,7 +63,8 @@ module axi_ad9625_channel (
input up_rreq, input up_rreq,
input [ 13:0] up_raddr, input [ 13:0] up_raddr,
output [ 31:0] up_rdata, output [ 31:0] up_rdata,
output up_rack); output up_rack
);
// internal signals // internal signals
@ -86,7 +87,9 @@ module axi_ad9625_channel (
genvar n; genvar n;
generate generate
for (n = 0; n < 16; n = n + 1) begin: g_ad_datafmt_1 for (n = 0; n < 16; n = n + 1) begin: g_ad_datafmt_1
ad_datafmt #(.DATA_WIDTH(12)) i_ad_datafmt ( ad_datafmt #(
.DATA_WIDTH(12)
) i_ad_datafmt (
.clk (adc_clk), .clk (adc_clk),
.valid (1'b1), .valid (1'b1),
.data (adc_data[n*12+11:n*12]), .data (adc_data[n*12+11:n*12]),
@ -104,8 +107,8 @@ module axi_ad9625_channel (
.USERPORTS_DISABLE(1), .USERPORTS_DISABLE(1),
.DATAFORMAT_DISABLE(0), .DATAFORMAT_DISABLE(0),
.DCFILTER_DISABLE(1), .DCFILTER_DISABLE(1),
.IQCORRECTION_DISABLE(1)) .IQCORRECTION_DISABLE(1)
i_up_adc_channel ( ) i_up_adc_channel (
.adc_clk (adc_clk), .adc_clk (adc_clk),
.adc_rst (adc_rst), .adc_rst (adc_rst),
.adc_enable (adc_enable), .adc_enable (adc_enable),
@ -152,7 +155,3 @@ module axi_ad9625_channel (
.up_rack (up_rack)); .up_rack (up_rack));
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

16
library/axi_ad9625/axi_ad9625_if.v
View File

@ -37,7 +37,9 @@
module axi_ad9625_if #( module axi_ad9625_if #(
parameter ID = 0) ( parameter ID = 0
) (
// jesd interface // jesd interface
// rx_clk is (line-rate/40) // rx_clk is (line-rate/40)
@ -55,7 +57,8 @@ module axi_ad9625_if #(
output [ 15:0] adc_sref, output [ 15:0] adc_sref,
input adc_sref_sync, input adc_sref_sync,
input [ 3:0] adc_raddr_in, input [ 3:0] adc_raddr_in,
output [ 3:0] adc_raddr_out); output [ 3:0] adc_raddr_out
);
// internal registers // internal registers
@ -207,7 +210,10 @@ module axi_ad9625_if #(
// alignment fifo // alignment fifo
ad_mem #(.ADDRESS_WIDTH(4), .DATA_WIDTH(192)) i_mem ( ad_mem #(
.ADDRESS_WIDTH(4),
.DATA_WIDTH(192)
) i_mem (
.clka (rx_clk), .clka (rx_clk),
.wea (1'b1), .wea (1'b1),
.addra (adc_waddr), .addra (adc_waddr),
@ -232,7 +238,3 @@ module axi_ad9625_if #(
endgenerate endgenerate
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

11
library/axi_ad9625/axi_ad9625_pnmon.v
View File

@ -49,7 +49,8 @@ module axi_ad9625_pnmon (
// processor interface PN9 (0x0), PN23 (0x1) // processor interface PN9 (0x0), PN23 (0x1)
input [ 3:0] adc_pnseq_sel); input [ 3:0] adc_pnseq_sel
);
// internal registers // internal registers
@ -494,7 +495,9 @@ module axi_ad9625_pnmon (
// pn oos & pn error // pn oos & pn error
ad_pnmon #(.DATA_WIDTH(192)) i_pnmon ( ad_pnmon #(
.DATA_WIDTH(192)
) i_pnmon (
.adc_clk (adc_clk), .adc_clk (adc_clk),
.adc_valid_in (1'b1), .adc_valid_in (1'b1),
.adc_data_in (adc_pn_data_in), .adc_data_in (adc_pn_data_in),
@ -503,7 +506,3 @@ module axi_ad9625_pnmon (
.adc_pn_err (adc_pn_err)); .adc_pn_err (adc_pn_err));
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

18
library/axi_ad9671/axi_ad9671.v
View File

@ -42,7 +42,8 @@ module axi_ad9671 #(
parameter FPGA_FAMILY = 0, parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0, parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0, parameter DEV_PACKAGE = 0,
parameter QUAD_OR_DUAL_N = 1) ( parameter QUAD_OR_DUAL_N = 1
) (
// jesd interface // jesd interface
// rx_clk is (line-rate/40) // rx_clk is (line-rate/40)
@ -87,8 +88,8 @@ module axi_ad9671 #(
output s_axi_rvalid, output s_axi_rvalid,
output [ 1:0] s_axi_rresp, output [ 1:0] s_axi_rresp,
output [ 31:0] s_axi_rdata, output [ 31:0] s_axi_rdata,
input s_axi_rready); input s_axi_rready
);
// internal registers // internal registers
@ -159,8 +160,8 @@ module axi_ad9671 #(
axi_ad9671_if #( axi_ad9671_if #(
.QUAD_OR_DUAL_N (QUAD_OR_DUAL_N), .QUAD_OR_DUAL_N (QUAD_OR_DUAL_N),
.ID (ID)) .ID (ID)
i_if ( ) i_if (
.rx_clk (rx_clk), .rx_clk (rx_clk),
.rx_data (rx_data), .rx_data (rx_data),
.rx_sof (rx_sof), .rx_sof (rx_sof),
@ -197,7 +198,9 @@ module axi_ad9671 #(
genvar n; genvar n;
generate generate
for (n = 0; n < 8; n = n + 1) begin: g_channel for (n = 0; n < 8; n = n + 1) begin: g_channel
axi_ad9671_channel #(.CHANNEL_ID(n)) i_channel ( axi_ad9671_channel #(
.CHANNEL_ID(n)
) i_channel (
.adc_clk (adc_clk), .adc_clk (adc_clk),
.adc_rst (adc_rst), .adc_rst (adc_rst),
.adc_valid (adc_valid_s), .adc_valid (adc_valid_s),
@ -302,6 +305,3 @@ module axi_ad9671 #(
.up_rack (up_rack)); .up_rack (up_rack));
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

19
library/axi_ad9671/axi_ad9671_channel.v
View File

@ -38,7 +38,8 @@
module axi_ad9671_channel #( module axi_ad9671_channel #(
parameter CHANNEL_ID = 0) ( parameter CHANNEL_ID = 0
) (
// adc interface // adc interface
@ -68,8 +69,8 @@ module axi_ad9671_channel #(
input up_rreq, input up_rreq,
input [13:0] up_raddr, input [13:0] up_raddr,
output [31:0] up_rdata, output [31:0] up_rdata,
output up_rack); output up_rack
);
// internal signals // internal signals
@ -90,7 +91,9 @@ module axi_ad9671_channel #(
.adc_pn_err (adc_pn_err_s), .adc_pn_err (adc_pn_err_s),
.adc_pnseq_sel (adc_pnseq_sel_s)); .adc_pnseq_sel (adc_pnseq_sel_s));
ad_datafmt #(.DATA_WIDTH(16)) i_ad_datafmt ( ad_datafmt #(
.DATA_WIDTH(16)
) i_ad_datafmt (
.clk (adc_clk), .clk (adc_clk),
.valid (adc_valid), .valid (adc_valid),
.data (adc_data), .data (adc_data),
@ -100,7 +103,9 @@ module axi_ad9671_channel #(
.dfmt_type (adc_dfmt_type_s), .dfmt_type (adc_dfmt_type_s),
.dfmt_se (adc_dfmt_se_s)); .dfmt_se (adc_dfmt_se_s));
up_adc_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel ( up_adc_channel #(
.CHANNEL_ID(CHANNEL_ID)
) i_up_adc_channel (
.adc_clk (adc_clk), .adc_clk (adc_clk),
.adc_rst (adc_rst), .adc_rst (adc_rst),
.adc_enable (adc_enable), .adc_enable (adc_enable),
@ -147,7 +152,3 @@ module axi_ad9671_channel #(
.up_rack (up_rack)); .up_rack (up_rack));
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

16
library/axi_ad9671/axi_ad9671_if.v
View File

@ -38,7 +38,8 @@
module axi_ad9671_if #( module axi_ad9671_if #(
parameter QUAD_OR_DUAL_N = 1, parameter QUAD_OR_DUAL_N = 1,
parameter ID = 0) ( parameter ID = 0
) (
// jesd interface // jesd interface
// rx_clk is (line-rate/40) // rx_clk is (line-rate/40)
@ -75,8 +76,8 @@ module axi_ad9671_if #(
output reg adc_sync_status, output reg adc_sync_status,
output reg adc_status, output reg adc_status,
input [ 3:0] adc_raddr_in, input [ 3:0] adc_raddr_in,
output reg [ 3:0] adc_raddr_out); output reg [ 3:0] adc_raddr_out
);
// internal wires // internal wires
@ -184,7 +185,10 @@ module axi_ad9671_if #(
end end
end end
ad_mem #(.ADDRESS_WIDTH(4), .DATA_WIDTH(128)) i_mem ( ad_mem #(
.ADDRESS_WIDTH(4),
.DATA_WIDTH(128)
) i_mem (
.clka(rx_clk), .clka(rx_clk),
.wea(int_valid), .wea(int_valid),
.addra(adc_waddr), .addra(adc_waddr),
@ -210,7 +214,3 @@ module axi_ad9671_if #(
endgenerate endgenerate
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

11
library/axi_ad9671/axi_ad9671_pnmon.v
View File

@ -48,7 +48,8 @@ module axi_ad9671_pnmon (
output adc_pn_oos, output adc_pn_oos,
output adc_pn_err, output adc_pn_err,
input [ 3:0] adc_pnseq_sel); input [ 3:0] adc_pnseq_sel
);
// internal registers // internal registers
@ -166,7 +167,9 @@ module axi_ad9671_pnmon (
// pn oos & pn err // pn oos & pn err
ad_pnmon #(.DATA_WIDTH(32)) i_pnmon ( ad_pnmon #(
.DATA_WIDTH(32)
) i_pnmon (
.adc_clk (adc_clk), .adc_clk (adc_clk),
.adc_valid_in (adc_pn_valid_s), .adc_valid_in (adc_pn_valid_s),
.adc_data_in (adc_pn_data_in), .adc_data_in (adc_pn_data_in),
@ -175,7 +178,3 @@ module axi_ad9671_pnmon (
.adc_pn_err (adc_pn_err)); .adc_pn_err (adc_pn_err));
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

27
library/axi_ad9684/axi_ad9684.v
View File

@ -43,7 +43,8 @@ module axi_ad9684 #(
parameter SPEED_GRADE = 0, parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0, parameter DEV_PACKAGE = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group", parameter IO_DELAY_GROUP = "dev_if_delay_group",
parameter OR_STATUS = 1) ( parameter OR_STATUS = 1
) (
// device interface ports // device interface ports
@ -92,8 +93,8 @@ module axi_ad9684 #(
output s_axi_rvalid, output s_axi_rvalid,
output [ 1:0] s_axi_rresp, output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata, output [31:0] s_axi_rdata,
input s_axi_rready); input s_axi_rready
);
// internal registers // internal registers
@ -168,8 +169,8 @@ module axi_ad9684 #(
axi_ad9684_if #( axi_ad9684_if #(
.FPGA_TECHNOLOGY(FPGA_TECHNOLOGY), .FPGA_TECHNOLOGY(FPGA_TECHNOLOGY),
.IO_DELAY_GROUP(IO_DELAY_GROUP), .IO_DELAY_GROUP(IO_DELAY_GROUP),
.OR_STATUS (OR_STATUS)) .OR_STATUS (OR_STATUS)
i_ad9684_if ( ) i_ad9684_if (
.adc_clk_in_p (adc_clk_in_p), .adc_clk_in_p (adc_clk_in_p),
.adc_clk_in_n (adc_clk_in_n), .adc_clk_in_n (adc_clk_in_n),
.adc_data_in_p (adc_data_in_p), .adc_data_in_p (adc_data_in_p),
@ -217,8 +218,8 @@ module axi_ad9684 #(
.DRP_DISABLE (6'h00), .DRP_DISABLE (6'h00),
.USERPORTS_DISABLE (0), .USERPORTS_DISABLE (0),
.GPIO_DISABLE (0), .GPIO_DISABLE (0),
.START_CODE_DISABLE(0)) .START_CODE_DISABLE(0)
i_up_adc_common ( ) i_up_adc_common (
.mmcm_rst (rst_s), .mmcm_rst (rst_s),
.adc_clk (adc_clk), .adc_clk (adc_clk),
.adc_rst (adc_rst), .adc_rst (adc_rst),
@ -265,8 +266,8 @@ module axi_ad9684 #(
axi_ad9684_channel #( axi_ad9684_channel #(
.CHANNEL_ID (0), .CHANNEL_ID (0),
.Q_OR_I_N (0)) .Q_OR_I_N (0)
i_channel_0 ( ) i_channel_0 (
.adc_clk (adc_clk), .adc_clk (adc_clk),
.adc_rst (adc_rst), .adc_rst (adc_rst),
.adc_data (adc_rawdata_0_s), .adc_data (adc_rawdata_0_s),
@ -293,8 +294,8 @@ module axi_ad9684 #(
axi_ad9684_channel #( axi_ad9684_channel #(
.CHANNEL_ID (1), .CHANNEL_ID (1),
.Q_OR_I_N (1)) .Q_OR_I_N (1)
i_channel_1 ( ) i_channel_1 (
.adc_clk (adc_clk), .adc_clk (adc_clk),
.adc_rst (adc_rst), .adc_rst (adc_rst),
.adc_data (adc_rawdata_1_s), .adc_data (adc_rawdata_1_s),
@ -320,8 +321,8 @@ module axi_ad9684 #(
// adc delay control instance // adc delay control instance
up_delay_cntrl #( up_delay_cntrl #(
.DATA_WIDTH(15)) .DATA_WIDTH(15)
i_delay_cntrl ( ) i_delay_cntrl (
.delay_clk (delay_clk), .delay_clk (delay_clk),
.delay_rst (delay_rst), .delay_rst (delay_rst),
.delay_locked (delay_locked_s), .delay_locked (delay_locked_s),

16
library/axi_ad9684/axi_ad9684_channel.v
View File

@ -39,7 +39,8 @@ module axi_ad9684_channel #(
parameter Q_OR_I_N = 0, parameter Q_OR_I_N = 0,
parameter CHANNEL_ID = 0, parameter CHANNEL_ID = 0,
parameter DATAPATH_DISABLE = 0) ( parameter DATAPATH_DISABLE = 0
) (
// adc data interface // adc data interface
@ -69,8 +70,8 @@ module axi_ad9684_channel #(
input up_rreq, input up_rreq,
input [13:0] up_raddr, input [13:0] up_raddr,
output [31:0] up_rdata, output [31:0] up_rdata,
output up_rack); output up_rack
);
// internal signals // internal signals
@ -94,7 +95,9 @@ module axi_ad9684_channel #(
genvar n; genvar n;
generate generate
for (n = 0; n < 2; n = n + 1) begin: g_ad_datafmt_1 for (n = 0; n < 2; n = n + 1) begin: g_ad_datafmt_1
ad_datafmt #(.DATA_WIDTH(14)) i_ad_datafmt ( ad_datafmt #(
.DATA_WIDTH(14)
) i_ad_datafmt (
.clk (adc_clk), .clk (adc_clk),
.valid (1'b1), .valid (1'b1),
.data (adc_data[n*14+13:n*14]), .data (adc_data[n*14+13:n*14]),
@ -114,8 +117,8 @@ module axi_ad9684_channel #(
.USERPORTS_DISABLE (0), .USERPORTS_DISABLE (0),
.DATAFORMAT_DISABLE (0), .DATAFORMAT_DISABLE (0),
.DCFILTER_DISABLE (0), .DCFILTER_DISABLE (0),
.IQCORRECTION_DISABLE (0)) .IQCORRECTION_DISABLE (0)
i_up_adc_channel ( ) i_up_adc_channel (
.adc_clk (adc_clk), .adc_clk (adc_clk),
.adc_rst (adc_rst), .adc_rst (adc_rst),
.adc_enable (adc_enable), .adc_enable (adc_enable),
@ -162,4 +165,3 @@ module axi_ad9684_channel #(
.up_rack (up_rack)); .up_rack (up_rack));
endmodule endmodule

19
library/axi_ad9684/axi_ad9684_if.v
View File

@ -39,7 +39,8 @@ module axi_ad9684_if #(
parameter FPGA_TECHNOLOGY = 0, parameter FPGA_TECHNOLOGY = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group", parameter IO_DELAY_GROUP = "dev_if_delay_group",
parameter OR_STATUS = 0) ( parameter OR_STATUS = 0
) (
// device interface // device interface
input adc_clk_in_p, input adc_clk_in_p,
@ -78,8 +79,8 @@ module axi_ad9684_if #(
input [31:0] up_drp_wdata, input [31:0] up_drp_wdata,
output [31:0] up_drp_rdata, output [31:0] up_drp_rdata,
output up_drp_ready, output up_drp_ready,
output up_drp_locked); output up_drp_locked
);
localparam DDR_OR_SDR_N = 1; localparam DDR_OR_SDR_N = 1;
@ -110,8 +111,8 @@ module axi_ad9684_if #(
.IODELAY_CTRL(1), .IODELAY_CTRL(1),
.IODELAY_GROUP(IO_DELAY_GROUP), .IODELAY_GROUP(IO_DELAY_GROUP),
.DDR_OR_SDR_N(DDR_OR_SDR_N), .DDR_OR_SDR_N(DDR_OR_SDR_N),
.DATA_WIDTH(14)) .DATA_WIDTH(14)
i_adc_data ( ) i_adc_data (
.rst(adc_rst), .rst(adc_rst),
.clk(adc_clk_in), .clk(adc_clk_in),
.div_clk(adc_div_clk), .div_clk(adc_div_clk),
@ -143,8 +144,8 @@ module axi_ad9684_if #(
.IODELAY_CTRL(0), .IODELAY_CTRL(0),
.IODELAY_GROUP(IO_DELAY_GROUP), .IODELAY_GROUP(IO_DELAY_GROUP),
.DDR_OR_SDR_N(DDR_OR_SDR_N), .DDR_OR_SDR_N(DDR_OR_SDR_N),
.DATA_WIDTH(1)) .DATA_WIDTH(1)
i_adc_or ( ) i_adc_or (
.rst(adc_rst), .rst(adc_rst),
.clk(adc_clk_in), .clk(adc_clk_in),
.div_clk(adc_div_clk), .div_clk(adc_div_clk),
@ -188,8 +189,8 @@ module axi_ad9684_if #(
.MMCM_VCO_DIV (6), .MMCM_VCO_DIV (6),
.MMCM_VCO_MUL (12), .MMCM_VCO_MUL (12),
.MMCM_CLK0_DIV (2), .MMCM_CLK0_DIV (2),
.MMCM_CLK1_DIV (4)) .MMCM_CLK1_DIV (4)
i_serdes_clk ( ) i_serdes_clk (
.rst (rst), .rst (rst),
.clk_in_p (adc_clk_in_p), .clk_in_p (adc_clk_in_p),
.clk_in_n (adc_clk_in_n), .clk_in_n (adc_clk_in_n),

11
library/axi_ad9684/axi_ad9684_pnmon.v
View File

@ -50,7 +50,8 @@ module axi_ad9684_pnmon (
// processor interface PN9 (0x0), PN23 (0x1) // processor interface PN9 (0x0), PN23 (0x1)
input [ 3:0] adc_pnseq_sel); input [ 3:0] adc_pnseq_sel
);
// internal registers // internal registers
@ -159,7 +160,9 @@ module axi_ad9684_pnmon (
// pn oos & pn err // pn oos & pn err
ad_pnmon #(.DATA_WIDTH(28)) i_pnmon ( ad_pnmon #(
.DATA_WIDTH(28)
) i_pnmon (
.adc_clk (adc_clk), .adc_clk (adc_clk),
.adc_valid_in (1'b1), .adc_valid_in (1'b1),
.adc_data_in (adc_pn_data_in), .adc_data_in (adc_pn_data_in),
@ -168,7 +171,3 @@ module axi_ad9684_pnmon (
.adc_pn_err (adc_pn_err)); .adc_pn_err (adc_pn_err));
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

18
library/axi_ad9739a/axi_ad9739a.v
View File

@ -48,7 +48,8 @@ module axi_ad9739a #(
parameter DAC_DDS_CORDIC_DW = 16, parameter DAC_DDS_CORDIC_DW = 16,
parameter DAC_DDS_CORDIC_PHASE_DW = 16, parameter DAC_DDS_CORDIC_PHASE_DW = 16,
parameter DAC_DATAPATH_DISABLE = 0, parameter DAC_DATAPATH_DISABLE = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group") ( parameter IO_DELAY_GROUP = "dev_if_delay_group"
) (
// dac interface // dac interface
@ -91,8 +92,8 @@ module axi_ad9739a #(
output [ 1:0] s_axi_rresp, output [ 1:0] s_axi_rresp,
input s_axi_rready, input s_axi_rready,
input [ 2:0] s_axi_awprot, input [ 2:0] s_axi_awprot,
input [ 2:0] s_axi_arprot); input [ 2:0] s_axi_arprot
);
// internal clocks and resets // internal clocks and resets
@ -135,7 +136,9 @@ module axi_ad9739a #(
// device interface // device interface
axi_ad9739a_if #(.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY)) i_if ( axi_ad9739a_if #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY)
) i_if (
.dac_clk_in_p (dac_clk_in_p), .dac_clk_in_p (dac_clk_in_p),
.dac_clk_in_n (dac_clk_in_n), .dac_clk_in_n (dac_clk_in_n),
.dac_clk_out_p (dac_clk_out_p), .dac_clk_out_p (dac_clk_out_p),
@ -176,8 +179,8 @@ module axi_ad9739a #(
.DAC_DDS_TYPE (DAC_DDS_TYPE), .DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.DATAPATH_DISABLE(DAC_DATAPATH_DISABLE)) .DATAPATH_DISABLE(DAC_DATAPATH_DISABLE)
i_core ( ) i_core (
.dac_div_clk (dac_div_clk), .dac_div_clk (dac_div_clk),
.dac_rst (dac_rst), .dac_rst (dac_rst),
.dac_data_00 (dac_data_00_s), .dac_data_00 (dac_data_00_s),
@ -244,6 +247,3 @@ module axi_ad9739a #(
.up_rack (up_rack_s)); .up_rack (up_rack_s));
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

18
library/axi_ad9739a/axi_ad9739a_channel.v
View File

@ -41,7 +41,8 @@ module axi_ad9739a_channel #(
parameter DAC_DDS_TYPE = 1, parameter DAC_DDS_TYPE = 1,
parameter DAC_DDS_CORDIC_DW = 16, parameter DAC_DDS_CORDIC_DW = 16,
parameter DAC_DDS_CORDIC_PHASE_DW = 16, parameter DAC_DDS_CORDIC_PHASE_DW = 16,
parameter DATAPATH_DISABLE = 0) ( parameter DATAPATH_DISABLE = 0
) (
// dac interface // dac interface
@ -82,8 +83,8 @@ module axi_ad9739a_channel #(
input up_rreq, input up_rreq,
input [ 13:0] up_raddr, input [ 13:0] up_raddr,
output [ 31:0] up_rdata, output [ 31:0] up_rdata,
output up_rack); output up_rack
);
// internal signals // internal signals
@ -169,8 +170,8 @@ module axi_ad9739a_channel #(
.DDS_TYPE (DAC_DDS_TYPE), .DDS_TYPE (DAC_DDS_TYPE),
.CORDIC_DW (DAC_DDS_CORDIC_DW), .CORDIC_DW (DAC_DDS_CORDIC_DW),
.CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), .CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.CLK_RATIO (16)) .CLK_RATIO (16)
i_dds ( ) i_dds (
.clk (dac_div_clk), .clk (dac_div_clk),
.dac_dds_format (dac_dds_format), .dac_dds_format (dac_dds_format),
.dac_data_sync (dac_data_sync), .dac_data_sync (dac_data_sync),
@ -185,7 +186,9 @@ module axi_ad9739a_channel #(
// single channel processor // single channel processor
up_dac_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel ( up_dac_channel #(
.CHANNEL_ID(CHANNEL_ID)
) i_up_dac_channel (
.dac_clk (dac_div_clk), .dac_clk (dac_div_clk),
.dac_rst (dac_rst), .dac_rst (dac_rst),
.dac_dds_scale_1 (dac_dds_scale_1_s), .dac_dds_scale_1 (dac_dds_scale_1_s),
@ -227,6 +230,3 @@ module axi_ad9739a_channel #(
.up_rack (up_rack)); .up_rack (up_rack));
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

14
library/axi_ad9739a/axi_ad9739a_core.v
View File

@ -45,7 +45,8 @@ module axi_ad9739a_core #(
parameter DAC_DDS_TYPE = 1, parameter DAC_DDS_TYPE = 1,
parameter DAC_DDS_CORDIC_DW = 16, parameter DAC_DDS_CORDIC_DW = 16,
parameter DAC_DDS_CORDIC_PHASE_DW = 16, parameter DAC_DDS_CORDIC_PHASE_DW = 16,
parameter DATAPATH_DISABLE = 0) ( parameter DATAPATH_DISABLE = 0
) (
// dac interface // dac interface
@ -87,8 +88,8 @@ module axi_ad9739a_core #(
input up_rreq, input up_rreq,
input [ 13:0] up_raddr, input [ 13:0] up_raddr,
output reg [ 31:0] up_rdata, output reg [ 31:0] up_rdata,
output reg up_rack); output reg up_rack
);
// internal registers // internal registers
@ -128,8 +129,8 @@ module axi_ad9739a_core #(
.DAC_DDS_TYPE (DAC_DDS_TYPE), .DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.DATAPATH_DISABLE(DATAPATH_DISABLE)) .DATAPATH_DISABLE(DATAPATH_DISABLE)
i_channel_0 ( ) i_channel_0 (
.dac_div_clk (dac_div_clk), .dac_div_clk (dac_div_clk),
.dac_rst (dac_rst), .dac_rst (dac_rst),
.dac_enable (dac_enable), .dac_enable (dac_enable),
@ -213,6 +214,3 @@ module axi_ad9739a_core #(
.up_rack (up_rack_s)); .up_rack (up_rack_s));
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

26
library/axi_ad9739a/axi_ad9739a_if.v
View File

@ -39,7 +39,8 @@
module axi_ad9739a_if #( module axi_ad9739a_if #(
parameter FPGA_TECHNOLOGY = 0) ( parameter FPGA_TECHNOLOGY = 0
) (
// dac interface // dac interface
@ -76,8 +77,8 @@ module axi_ad9739a_if #(
input [15:0] dac_data_12, input [15:0] dac_data_12,
input [15:0] dac_data_13, input [15:0] dac_data_13,
input [15:0] dac_data_14, input [15:0] dac_data_14,
input [15:0] dac_data_15); input [15:0] dac_data_15
);
// internal registers // internal registers
@ -102,8 +103,8 @@ module axi_ad9739a_if #(
.DDR_OR_SDR_N(1), .DDR_OR_SDR_N(1),
.DATA_WIDTH(14), .DATA_WIDTH(14),
.SERDES_FACTOR(8), .SERDES_FACTOR(8),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY)) .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY)
i_serdes_out_data_a ( ) i_serdes_out_data_a (
.rst (dac_rst), .rst (dac_rst),
.clk (dac_clk), .clk (dac_clk),
.div_clk (dac_div_clk), .div_clk (dac_div_clk),
@ -127,8 +128,8 @@ module axi_ad9739a_if #(
.DDR_OR_SDR_N(1), .DDR_OR_SDR_N(1),
.DATA_WIDTH(14), .DATA_WIDTH(14),
.SERDES_FACTOR(8), .SERDES_FACTOR(8),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY)) .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY)
i_serdes_out_data_b ( ) i_serdes_out_data_b (
.rst (dac_rst), .rst (dac_rst),
.clk (dac_clk), .clk (dac_clk),
.div_clk (dac_div_clk), .div_clk (dac_div_clk),
@ -152,8 +153,8 @@ module axi_ad9739a_if #(
.DDR_OR_SDR_N(1), .DDR_OR_SDR_N(1),
.DATA_WIDTH(1), .DATA_WIDTH(1),
.SERDES_FACTOR(8), .SERDES_FACTOR(8),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY)) .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY)
i_serdes_out_clk ( ) i_serdes_out_clk (
.rst (dac_rst), .rst (dac_rst),
.clk (dac_clk), .clk (dac_clk),
.div_clk (dac_div_clk), .div_clk (dac_div_clk),
@ -182,7 +183,9 @@ module axi_ad9739a_if #(
.I (dac_clk_in_s), .I (dac_clk_in_s),
.O (dac_clk)); .O (dac_clk));
BUFR #(.BUFR_DIVIDE("4")) i_dac_div_clk_rbuf ( BUFR #(
.BUFR_DIVIDE("4")
) i_dac_div_clk_rbuf (
.CLR (1'b0), .CLR (1'b0),
.CE (1'b1), .CE (1'b1),
.I (dac_clk_in_s), .I (dac_clk_in_s),
@ -193,6 +196,3 @@ module axi_ad9739a_if #(
.O (dac_div_clk)); .O (dac_div_clk));
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

18
library/axi_ad9783/axi_ad9783.v
View File

@ -45,7 +45,8 @@ module axi_ad9783 #(
parameter DAC_DDS_TYPE = 2, parameter DAC_DDS_TYPE = 2,
parameter DAC_DDS_CORDIC_DW = 16, parameter DAC_DDS_CORDIC_DW = 16,
parameter DAC_DDS_CORDIC_PHASE_DW = 16, parameter DAC_DDS_CORDIC_PHASE_DW = 16,
parameter DAC_DATAPATH_DISABLE = 0) ( parameter DAC_DATAPATH_DISABLE = 0
) (
// dac interface // dac interface
// from dco1_p // from dco1_p
@ -92,8 +93,8 @@ module axi_ad9783 #(
output [ 1:0] s_axi_rresp, output [ 1:0] s_axi_rresp,
input s_axi_rready, input s_axi_rready,
input [ 2:0] s_axi_awprot, input [ 2:0] s_axi_awprot,
input [ 2:0] s_axi_arprot); input [ 2:0] s_axi_arprot
);
// internal clocks and resets // internal clocks and resets
@ -130,8 +131,8 @@ module axi_ad9783 #(
// device interface // device interface
axi_ad9783_if #( axi_ad9783_if #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY)) .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY)
i_if ( ) i_if (
.dac_clk_in_p (dac_clk_in_p), .dac_clk_in_p (dac_clk_in_p),
.dac_clk_in_n (dac_clk_in_n), .dac_clk_in_n (dac_clk_in_n),
.dac_clk_out_p (dac_clk_out_p), .dac_clk_out_p (dac_clk_out_p),
@ -161,8 +162,8 @@ module axi_ad9783 #(
.DAC_DDS_TYPE (DAC_DDS_TYPE), .DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.DATAPATH_DISABLE(DAC_DATAPATH_DISABLE)) .DATAPATH_DISABLE(DAC_DATAPATH_DISABLE)
i_core ( ) i_core (
.dac_div_clk (dac_div_clk), .dac_div_clk (dac_div_clk),
.dac_rst (dac_rst_s), .dac_rst (dac_rst_s),
.dac_data_a0 (dac_data_a0_s), .dac_data_a0 (dac_data_a0_s),
@ -223,6 +224,3 @@ module axi_ad9783 #(
.up_rack (up_rack_s)); .up_rack (up_rack_s));
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

19
library/axi_ad9783/axi_ad9783_channel.v
View File

@ -41,7 +41,8 @@ module axi_ad9783_channel #(
parameter DAC_DDS_TYPE = 1, parameter DAC_DDS_TYPE = 1,
parameter DAC_DDS_CORDIC_DW = 16, parameter DAC_DDS_CORDIC_DW = 16,
parameter DAC_DDS_CORDIC_PHASE_DW = 16, parameter DAC_DDS_CORDIC_PHASE_DW = 16,
parameter DATAPATH_DISABLE = 0) ( parameter DATAPATH_DISABLE = 0
) (
// dac interface // dac interface
@ -70,8 +71,8 @@ module axi_ad9783_channel #(
input up_rreq, input up_rreq,
input [13:0] up_raddr, input [13:0] up_raddr,
output [31:0] up_rdata, output [31:0] up_rdata,
output up_rack); output up_rack
);
// internal signals // internal signals
@ -89,7 +90,6 @@ module axi_ad9783_channel #(
reg [23:0] dac_prbs_data = 'd0; reg [23:0] dac_prbs_data = 'd0;
reg [15:0] dac_prbs_counter = 'd0; reg [15:0] dac_prbs_counter = 'd0;
// pn23 function // pn23 function
function [23:0] pn23; function [23:0] pn23;
input [23:0] din; input [23:0] din;
@ -155,8 +155,8 @@ module axi_ad9783_channel #(
.DDS_TYPE (DAC_DDS_TYPE), .DDS_TYPE (DAC_DDS_TYPE),
.CORDIC_DW (DAC_DDS_CORDIC_DW), .CORDIC_DW (DAC_DDS_CORDIC_DW),
.CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), .CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.CLK_RATIO (4)) .CLK_RATIO (4)
i_dds ( ) i_dds (
.clk (dac_div_clk), .clk (dac_div_clk),
.dac_dds_format (dac_dds_format), .dac_dds_format (dac_dds_format),
.dac_data_sync (dac_data_sync), .dac_data_sync (dac_data_sync),
@ -172,8 +172,8 @@ module axi_ad9783_channel #(
// single channel processor // single channel processor
up_dac_channel #( up_dac_channel #(
.CHANNEL_ID(CHANNEL_ID)) .CHANNEL_ID(CHANNEL_ID)
i_up_dac_channel ( ) i_up_dac_channel (
.dac_clk (dac_div_clk), .dac_clk (dac_div_clk),
.dac_rst (dac_rst), .dac_rst (dac_rst),
.dac_dds_scale_1 (dac_dds_scale_1_s), .dac_dds_scale_1 (dac_dds_scale_1_s),
@ -215,6 +215,3 @@ module axi_ad9783_channel #(
.up_rack (up_rack)); .up_rack (up_rack));
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

22
library/axi_ad9783/axi_ad9783_core.v
View File

@ -45,7 +45,8 @@ module axi_ad9783_core #(
parameter DAC_DDS_TYPE = 1, parameter DAC_DDS_TYPE = 1,
parameter DAC_DDS_CORDIC_DW = 16, parameter DAC_DDS_CORDIC_DW = 16,
parameter DAC_DDS_CORDIC_PHASE_DW = 16, parameter DAC_DDS_CORDIC_PHASE_DW = 16,
parameter DATAPATH_DISABLE = 0) ( parameter DATAPATH_DISABLE = 0
) (
// dac interface // dac interface
@ -81,8 +82,8 @@ module axi_ad9783_core #(
input up_rreq, input up_rreq,
input [ 13:0] up_raddr, input [ 13:0] up_raddr,
output reg [ 31:0] up_rdata, output reg [ 31:0] up_rdata,
output reg up_rack); output reg up_rack
);
// internal registers // internal registers
@ -129,8 +130,8 @@ module axi_ad9783_core #(
.DAC_DDS_TYPE (DAC_DDS_TYPE), .DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.DATAPATH_DISABLE(DATAPATH_DISABLE)) .DATAPATH_DISABLE(DATAPATH_DISABLE)
i_channel_0 ( ) i_channel_0 (
.dac_div_clk (dac_div_clk), .dac_div_clk (dac_div_clk),
.dac_rst (dac_rst), .dac_rst (dac_rst),
.dac_enable (dac_enable_0_reg), .dac_enable (dac_enable_0_reg),
@ -157,8 +158,8 @@ module axi_ad9783_core #(
.DAC_DDS_TYPE (DAC_DDS_TYPE), .DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.DATAPATH_DISABLE(DATAPATH_DISABLE)) .DATAPATH_DISABLE(DATAPATH_DISABLE)
i_channel_1 ( ) i_channel_1 (
.dac_div_clk (dac_div_clk), .dac_div_clk (dac_div_clk),
.dac_rst (dac_rst), .dac_rst (dac_rst),
.dac_enable (dac_enable_1_reg), .dac_enable (dac_enable_1_reg),
@ -187,8 +188,8 @@ module axi_ad9783_core #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY), .FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE), .SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE)) .DEV_PACKAGE (DEV_PACKAGE)
i_up_dac_common ( ) i_up_dac_common (
.mmcm_rst (), .mmcm_rst (),
.dac_clk (dac_div_clk), .dac_clk (dac_div_clk),
.dac_rst (dac_rst), .dac_rst (dac_rst),
@ -230,6 +231,3 @@ module axi_ad9783_core #(
.up_rack (up_rack_s)); .up_rack (up_rack_s));
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

22
library/axi_ad9783/axi_ad9783_if.v
View File

@ -39,7 +39,8 @@
module axi_ad9783_if #( module axi_ad9783_if #(
parameter FPGA_TECHNOLOGY = 0) ( parameter FPGA_TECHNOLOGY = 0
) (
// dac interface // dac interface
@ -65,8 +66,8 @@ module axi_ad9783_if #(
input [15:0] dac_data_b0, input [15:0] dac_data_b0,
input [15:0] dac_data_b1, input [15:0] dac_data_b1,
input [15:0] dac_data_b2, input [15:0] dac_data_b2,
input [15:0] dac_data_b3); input [15:0] dac_data_b3
);
// internal registers // internal registers
@ -92,8 +93,8 @@ module axi_ad9783_if #(
.DDR_OR_SDR_N(1), .DDR_OR_SDR_N(1),
.DATA_WIDTH(16), .DATA_WIDTH(16),
.SERDES_FACTOR(8), .SERDES_FACTOR(8),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY)) .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY)
i_serdes_out_data ( ) i_serdes_out_data (
.rst (dac_rst), .rst (dac_rst),
.clk (dac_clk_s), .clk (dac_clk_s),
.div_clk (dac_div_clk), .div_clk (dac_div_clk),
@ -117,8 +118,8 @@ module axi_ad9783_if #(
.DDR_OR_SDR_N(1), .DDR_OR_SDR_N(1),
.DATA_WIDTH(1), .DATA_WIDTH(1),
.SERDES_FACTOR(8), .SERDES_FACTOR(8),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY)) .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY)
i_serdes_out_clk ( ) i_serdes_out_clk (
.rst (dac_rst), .rst (dac_rst),
.clk (dac_clk_s), .clk (dac_clk_s),
.div_clk (dac_div_clk), .div_clk (dac_div_clk),
@ -147,8 +148,8 @@ module axi_ad9783_if #(
.BUFGCE_DIVIDE (4), .BUFGCE_DIVIDE (4),
.IS_CE_INVERTED (1'b0), .IS_CE_INVERTED (1'b0),
.IS_CLR_INVERTED (1'b0), .IS_CLR_INVERTED (1'b0),
.IS_I_INVERTED (1'b0)) .IS_I_INVERTED (1'b0)
i_dac_div_clk_rbuf ( ) i_dac_div_clk_rbuf (
.O (dac_div_clk_s), .O (dac_div_clk_s),
.CE (1'b1), .CE (1'b1),
.CLR (1'b0), .CLR (1'b0),
@ -159,6 +160,3 @@ module axi_ad9783_if #(
.O (dac_div_clk)); .O (dac_div_clk));
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

17
library/axi_ad9963/axi_ad9963.v
View File

@ -56,7 +56,8 @@ module axi_ad9963 #(
parameter ADC_DCFILTER_DISABLE = 0, parameter ADC_DCFILTER_DISABLE = 0,
parameter ADC_IQCORRECTION_DISABLE = 0, parameter ADC_IQCORRECTION_DISABLE = 0,
parameter ADC_SCALECORRECTION_ONLY = 1, parameter ADC_SCALECORRECTION_ONLY = 1,
parameter DELAY_REFCLK_FREQUENCY = 200) ( parameter DELAY_REFCLK_FREQUENCY = 200
) (
// physical interface (receive) // physical interface (receive)
@ -130,7 +131,8 @@ module axi_ad9963 #(
output s_axi_rvalid, output s_axi_rvalid,
output [31:0] s_axi_rdata, output [31:0] s_axi_rdata,
output [ 1:0] s_axi_rresp, output [ 1:0] s_axi_rresp,
input s_axi_rready); input s_axi_rready
);
// internal registers // internal registers
@ -189,8 +191,8 @@ module axi_ad9963 #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.ADC_IODELAY_ENABLE (ADC_IODELAY_ENABLE), .ADC_IODELAY_ENABLE (ADC_IODELAY_ENABLE),
.IO_DELAY_GROUP (IO_DELAY_GROUP), .IO_DELAY_GROUP (IO_DELAY_GROUP),
.DELAY_REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)) .DELAY_REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
i_dev_if ( ) i_dev_if (
.trx_clk (trx_clk), .trx_clk (trx_clk),
.trx_iq (trx_iq), .trx_iq (trx_iq),
.trx_data (trx_data), .trx_data (trx_data),
@ -274,8 +276,8 @@ module axi_ad9963 #(
.DAC_DDS_TYPE (DAC_DDS_TYPE), .DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.DATAPATH_DISABLE (DAC_DATAPATH_DISABLE)) .DATAPATH_DISABLE (DAC_DATAPATH_DISABLE)
i_tx ( ) i_tx (
.dac_clk (dac_clk), .dac_clk (dac_clk),
.dac_rst (dac_rst), .dac_rst (dac_rst),
.dac_data (dac_data_s), .dac_data (dac_data_s),
@ -337,6 +339,3 @@ module axi_ad9963 #(
.up_rack (up_rack)); .up_rack (up_rack));
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

63
library/axi_ad9963/axi_ad9963_if.v
View File

@ -42,7 +42,8 @@ module axi_ad9963_if #(
parameter FPGA_TECHNOLOGY = 0, parameter FPGA_TECHNOLOGY = 0,
parameter ADC_IODELAY_ENABLE = 0, parameter ADC_IODELAY_ENABLE = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group", parameter IO_DELAY_GROUP = "dev_if_delay_group",
parameter DELAY_REFCLK_FREQUENCY = 200) ( parameter DELAY_REFCLK_FREQUENCY = 200
) (
// physical interface (receive) // physical interface (receive)
@ -86,7 +87,8 @@ module axi_ad9963_if #(
output [64:0] up_adc_drdata, output [64:0] up_adc_drdata,
input delay_clk, input delay_clk,
input delay_rst, input delay_rst,
output delay_locked); output delay_locked
);
// internal registers // internal registers
@ -149,21 +151,19 @@ module axi_ad9963_if #(
// device clock interface (receive clock) // device clock interface (receive clock)
BUFGCTRL #( BUFGCTRL #(
.INIT_OUT(0), .INIT_OUT(0),
.PRESELECT_I0("FALSE"), .PRESELECT_I0("FALSE"),
.PRESELECT_I1("FALSE") .PRESELECT_I1("FALSE")
) ) bufgctrl_adc (
bufgctrl_adc ( .O(adc_clk),
.O(adc_clk), .CE0(1'b1),
.CE0(1'b1), .CE1(1'b0),
.CE1(1'b0), .I0(trx_clk),
.I0(trx_clk), .I1(1'b0),
.I1(1'b0), .IGNORE0(1'b0),
.IGNORE0(1'b0), .IGNORE1(1'b0),
.IGNORE1(1'b0), .S0(up_adc_ce),
.S0(up_adc_ce), .S1(1'b0));
.S1(1'b0)
);
// receive data interface, ibuf -> idelay -> iddr // receive data interface, ibuf -> idelay -> iddr
@ -175,8 +175,8 @@ module axi_ad9963_if #(
.IODELAY_ENABLE (ADC_IODELAY_ENABLE), .IODELAY_ENABLE (ADC_IODELAY_ENABLE),
.IODELAY_CTRL (0), .IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP), .IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)) .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
i_rx_data ( ) i_rx_data (
.rx_clk (adc_clk), .rx_clk (adc_clk),
.rx_data_in_p (trx_data[l_inst]), .rx_data_in_p (trx_data[l_inst]),
.rx_data_in_n (1'b0), .rx_data_in_n (1'b0),
@ -199,8 +199,8 @@ module axi_ad9963_if #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_ENABLE (ADC_IODELAY_ENABLE), .IODELAY_ENABLE (ADC_IODELAY_ENABLE),
.IODELAY_CTRL (1), .IODELAY_CTRL (1),
.IODELAY_GROUP (IO_DELAY_GROUP)) .IODELAY_GROUP (IO_DELAY_GROUP)
i_rx_iq ( ) i_rx_iq (
.rx_clk (adc_clk), .rx_clk (adc_clk),
.rx_data_in_p (trx_iq), .rx_data_in_p (trx_iq),
.rx_data_in_n (1'b0), .rx_data_in_n (1'b0),
@ -216,7 +216,9 @@ module axi_ad9963_if #(
// transmit data interface // transmit data interface
BUFR #(.BUFR_DIVIDE(2)) i_div_clk_buf ( BUFR #(
.BUFR_DIVIDE(2)
) i_div_clk_buf (
.CLR (1'b0), .CLR (1'b0),
.CE (1'b1), .CE (1'b1),
.I (tx_clk), .I (tx_clk),
@ -226,8 +228,7 @@ module axi_ad9963_if #(
.INIT_OUT(0), .INIT_OUT(0),
.PRESELECT_I0("FALSE"), .PRESELECT_I0("FALSE"),
.PRESELECT_I1("FALSE") .PRESELECT_I1("FALSE")
) ) bufgctrl_dac (
bufgctrl_dac (
.O(dac_clk), .O(dac_clk),
.CE0(1'b1), .CE0(1'b1),
.CE1(1'b0), .CE1(1'b0),
@ -236,16 +237,15 @@ module axi_ad9963_if #(
.IGNORE0(1'b0), .IGNORE0(1'b0),
.IGNORE1(1'b0), .IGNORE1(1'b0),
.S0(up_dac_ce), .S0(up_dac_ce),
.S1(1'b0) .S1(1'b0));
);
generate generate
for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin: g_tx_data for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin: g_tx_data
ODDR #( ODDR #(
.DDR_CLK_EDGE ("SAME_EDGE"), .DDR_CLK_EDGE ("SAME_EDGE"),
.INIT (1'b0), .INIT (1'b0),
.SRTYPE ("SYNC")) .SRTYPE ("SYNC")
i_tx_data_oddr ( ) i_tx_data_oddr (
.CE (1'b1), .CE (1'b1),
.R (dac_rst), .R (dac_rst),
.S (1'b0), .S (1'b0),
@ -259,8 +259,8 @@ module axi_ad9963_if #(
ODDR #( ODDR #(
.DDR_CLK_EDGE ("SAME_EDGE"), .DDR_CLK_EDGE ("SAME_EDGE"),
.INIT (1'b0), .INIT (1'b0),
.SRTYPE ("SYNC")) .SRTYPE ("SYNC")
i_tx_data_oddr ( ) i_tx_data_oddr (
.CE (1'b1), .CE (1'b1),
.R (dac_rst), .R (dac_rst),
.S (1'b0), .S (1'b0),
@ -270,6 +270,3 @@ module axi_ad9963_if #(
.Q (tx_iq)); .Q (tx_iq));
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

23
library/axi_ad9963/axi_ad9963_rx.v
View File

@ -49,7 +49,8 @@ module axi_ad9963_rx #(
parameter FPGA_TECHNOLOGY = 0, parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0, parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0, parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0) ( parameter DEV_PACKAGE = 0
) (
// adc interface // adc interface
@ -91,7 +92,8 @@ module axi_ad9963_rx #(
input up_rreq, input up_rreq,
input [13:0] up_raddr, input [13:0] up_raddr,
output reg [31:0] up_rdata, output reg [31:0] up_rdata,
output reg up_rack); output reg up_rack
);
// configuration settings // configuration settings
@ -148,8 +150,8 @@ module axi_ad9963_rx #(
.DATAFORMAT_DISABLE (DATAFORMAT_DISABLE), .DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
.DCFILTER_DISABLE (DCFILTER_DISABLE), .DCFILTER_DISABLE (DCFILTER_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE), .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
.SCALECORRECTION_ONLY (SCALECORRECTION_ONLY)) .SCALECORRECTION_ONLY (SCALECORRECTION_ONLY)
i_rx_channel_0 ( ) i_rx_channel_0 (
.adc_clk (adc_clk), .adc_clk (adc_clk),
.adc_rst (adc_rst), .adc_rst (adc_rst),
.adc_valid (adc_valid), .adc_valid (adc_valid),
@ -183,8 +185,8 @@ module axi_ad9963_rx #(
.DATAFORMAT_DISABLE (DATAFORMAT_DISABLE), .DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
.DCFILTER_DISABLE (DCFILTER_DISABLE), .DCFILTER_DISABLE (DCFILTER_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE), .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
.SCALECORRECTION_ONLY (SCALECORRECTION_ONLY)) .SCALECORRECTION_ONLY (SCALECORRECTION_ONLY)
i_rx_channel_1 ( ) i_rx_channel_1 (
.adc_clk (adc_clk), .adc_clk (adc_clk),
.adc_rst (adc_rst), .adc_rst (adc_rst),
.adc_valid (adc_valid), .adc_valid (adc_valid),
@ -273,7 +275,10 @@ module axi_ad9963_rx #(
generate if (IODELAY_ENABLE == 1) begin generate if (IODELAY_ENABLE == 1) begin
up_delay_cntrl #(.DATA_WIDTH(13), .BASE_ADDRESS(6'h02)) i_delay_cntrl ( up_delay_cntrl #(
.DATA_WIDTH(13),
.BASE_ADDRESS(6'h02)
) i_delay_cntrl (
.delay_clk (delay_clk), .delay_clk (delay_clk),
.delay_rst (delay_rst), .delay_rst (delay_rst),
.delay_locked (delay_locked), .delay_locked (delay_locked),
@ -302,7 +307,3 @@ module axi_ad9963_rx #(
endgenerate endgenerate
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

23
library/axi_ad9963/axi_ad9963_rx_channel.v
View File

@ -45,7 +45,8 @@ module axi_ad9963_rx_channel #(
parameter DATAFORMAT_DISABLE = 0, parameter DATAFORMAT_DISABLE = 0,
parameter DCFILTER_DISABLE = 0, parameter DCFILTER_DISABLE = 0,
parameter IQCORRECTION_DISABLE = 0, parameter IQCORRECTION_DISABLE = 0,
parameter SCALECORRECTION_ONLY = 1) ( parameter SCALECORRECTION_ONLY = 1
) (
// adc interface // adc interface
@ -77,7 +78,8 @@ module axi_ad9963_rx_channel #(
input up_rreq, input up_rreq,
input [13:0] up_raddr, input [13:0] up_raddr,
output [31:0] up_rdata, output [31:0] up_rdata,
output up_rack); output up_rack
);
// internal signals // internal signals
@ -116,7 +118,9 @@ module axi_ad9963_rx_channel #(
assign adc_dfmt_valid_s = adc_valid; assign adc_dfmt_valid_s = adc_valid;
assign adc_dfmt_data_s = {{4{adc_data[11]}}, adc_data}; assign adc_dfmt_data_s = {{4{adc_data[11]}}, adc_data};
end else begin end else begin
ad_datafmt #(.DATA_WIDTH (12)) i_ad_datafmt ( ad_datafmt #(
.DATA_WIDTH (12)
) i_ad_datafmt (
.clk (adc_clk), .clk (adc_clk),
.valid (adc_valid), .valid (adc_valid),
.data (adc_data), .data (adc_data),
@ -145,10 +149,11 @@ module axi_ad9963_rx_channel #(
end end
endgenerate endgenerate
ad_iqcor #(.Q_OR_I_N (Q_OR_I_N), ad_iqcor #(
.DISABLE(IQCORRECTION_DISABLE == 1), .Q_OR_I_N (Q_OR_I_N),
.SCALE_ONLY(SCALECORRECTION_ONLY)) .DISABLE(IQCORRECTION_DISABLE == 1),
i_ad_iqcor ( .SCALE_ONLY(SCALECORRECTION_ONLY)
) i_ad_iqcor (
.clk (adc_clk), .clk (adc_clk),
.valid (adc_dcfilter_valid_s), .valid (adc_dcfilter_valid_s),
.data_in (adc_dcfilter_data_s), .data_in (adc_dcfilter_data_s),
@ -213,7 +218,3 @@ module axi_ad9963_rx_channel #(
.up_rack (up_rack)); .up_rack (up_rack));
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

24
library/axi_ad9963/axi_ad9963_rx_pnmon.v
View File

@ -48,7 +48,8 @@ module axi_ad9963_rx_pnmon (
input [ 3:0] adc_pnseq_sel, input [ 3:0] adc_pnseq_sel,
output adc_pn_oos, output adc_pn_oos,
output adc_pn_err); output adc_pn_err
);
// internal registers // internal registers
@ -83,7 +84,7 @@ module axi_ad9963_rx_pnmon (
// standard prbs functions // standard prbs functions
function [23:0] pn23; function [23:0] pn23;
input [23:0] din; input [23:0] din;
reg [23:0] dout; reg [23:0] dout;
begin begin
@ -96,16 +97,18 @@ module axi_ad9963_rx_pnmon (
assign adc_pn_data_pn_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in : adc_pn_data_pn; assign adc_pn_data_pn_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in : adc_pn_data_pn;
always @(posedge adc_clk) begin always @(posedge adc_clk) begin
if(adc_valid == 1'b1) begin if(adc_valid == 1'b1) begin
adc_pn_data_in <= {adc_pn_data_in[22:11], adc_data}; adc_pn_data_in <= {adc_pn_data_in[22:11], adc_data};
adc_pn_data_pn <= pn23(adc_pn_data_pn_s); adc_pn_data_pn <= pn23(adc_pn_data_pn_s);
end end
end end
// pn oos & pn err // pn oos & pn err
ad_pnmon #(.DATA_WIDTH(24)) i_pnmon ( ad_pnmon #(
.DATA_WIDTH(24)
) i_pnmon (
.adc_clk (adc_clk), .adc_clk (adc_clk),
.adc_valid_in (adc_valid), .adc_valid_in (adc_valid),
.adc_data_in (adc_pn_data_in), .adc_data_in (adc_pn_data_in),
@ -115,6 +118,3 @@ module axi_ad9963_rx_pnmon (
.adc_pn_err (adc_pn_err)); .adc_pn_err (adc_pn_err));
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

17
library/axi_ad9963/axi_ad9963_tx.v
View File

@ -47,7 +47,8 @@ module axi_ad9963_tx #(
parameter DAC_DDS_TYPE = 1, parameter DAC_DDS_TYPE = 1,
parameter DAC_DDS_CORDIC_DW = 14, parameter DAC_DDS_CORDIC_DW = 14,
parameter DAC_DDS_CORDIC_PHASE_DW = 13, parameter DAC_DDS_CORDIC_PHASE_DW = 13,
parameter DATAPATH_DISABLE = 0) ( parameter DATAPATH_DISABLE = 0
) (
// dac interface // dac interface
@ -88,7 +89,8 @@ module axi_ad9963_tx #(
input up_rreq, input up_rreq,
input [13:0] up_raddr, input [13:0] up_raddr,
output reg [31:0] up_rdata, output reg [31:0] up_rdata,
output reg up_rack); output reg up_rack
);
// internal signals // internal signals
@ -131,8 +133,8 @@ module axi_ad9963_tx #(
.DAC_DDS_TYPE (DAC_DDS_TYPE), .DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.DATAPATH_DISABLE (DATAPATH_DISABLE)) .DATAPATH_DISABLE (DATAPATH_DISABLE)
i_tx_channel_0 ( ) i_tx_channel_0 (
.dac_clk (dac_clk), .dac_clk (dac_clk),
.dac_rst (dac_rst), .dac_rst (dac_rst),
.dac_valid (dac_valid_i), .dac_valid (dac_valid_i),
@ -165,8 +167,8 @@ module axi_ad9963_tx #(
.DAC_DDS_TYPE (DAC_DDS_TYPE), .DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.DATAPATH_DISABLE (DATAPATH_DISABLE)) .DATAPATH_DISABLE (DATAPATH_DISABLE)
i_tx_channel_1 ( ) i_tx_channel_1 (
.dac_clk (dac_clk), .dac_clk (dac_clk),
.dac_rst (dac_rst), .dac_rst (dac_rst),
.dac_valid (dac_valid_q), .dac_valid (dac_valid_q),
@ -250,6 +252,3 @@ module axi_ad9963_tx #(
.up_rack (up_rack_s[2])); .up_rack (up_rack_s[2]));
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

19
library/axi_ad9963/axi_ad9963_tx_channel.v
View File

@ -44,7 +44,8 @@ module axi_ad9963_tx_channel #(
parameter DAC_DDS_TYPE = 1, parameter DAC_DDS_TYPE = 1,
parameter DAC_DDS_CORDIC_DW = 14, parameter DAC_DDS_CORDIC_DW = 14,
parameter DAC_DDS_CORDIC_PHASE_DW = 13, parameter DAC_DDS_CORDIC_PHASE_DW = 13,
parameter DATAPATH_DISABLE = 0) ( parameter DATAPATH_DISABLE = 0
) (
// dac interface // dac interface
@ -76,7 +77,8 @@ module axi_ad9963_tx_channel #(
input up_rreq, input up_rreq,
input [13:0] up_raddr, input [13:0] up_raddr,
output [31:0] up_rdata, output [31:0] up_rdata,
output up_rack); output up_rack
);
localparam PRBS_SEL = CHANNEL_ID; localparam PRBS_SEL = CHANNEL_ID;
localparam PRBS_P09 = 0; localparam PRBS_P09 = 0;
@ -128,7 +130,9 @@ module axi_ad9963_tx_channel #(
assign dac_iqcor_valid_s = data_source_valid; assign dac_iqcor_valid_s = data_source_valid;
assign dac_iqcor_data_s = {dac_data_out, 4'd0}; assign dac_iqcor_data_s = {dac_data_out, 4'd0};
end else begin end else begin
ad_iqcor #(.Q_OR_I_N (Q_OR_I_N)) i_ad_iqcor ( ad_iqcor #(
.Q_OR_I_N (Q_OR_I_N)
) i_ad_iqcor (
.clk (dac_clk), .clk (dac_clk),
.valid (data_source_valid), .valid (data_source_valid),
.data_in ({dac_data_out, 4'd0}), .data_in ({dac_data_out, 4'd0}),
@ -156,7 +160,7 @@ module axi_ad9963_tx_channel #(
dma_valid_m <= dma_valid; dma_valid_m <= dma_valid;
end end
function [23:0] pn23; function [23:0] pn23;
input [23:0] din; input [23:0] din;
reg [23:0] dout; reg [23:0] dout;
begin begin
@ -205,8 +209,8 @@ module axi_ad9963_tx_channel #(
.DDS_TYPE (DAC_DDS_TYPE), .DDS_TYPE (DAC_DDS_TYPE),
.CORDIC_DW (DAC_DDS_CORDIC_DW), .CORDIC_DW (DAC_DDS_CORDIC_DW),
.CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), .CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.CLK_RATIO (1)) .CLK_RATIO (1)
i_dds ( ) i_dds (
.clk (dac_clk), .clk (dac_clk),
.dac_dds_format (dac_dds_format), .dac_dds_format (dac_dds_format),
.dac_data_sync (dac_data_sync), .dac_data_sync (dac_data_sync),
@ -269,6 +273,3 @@ module axi_ad9963_tx_channel #(
.up_rack (up_rack)); .up_rack (up_rack));
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

38
library/axi_adaq8092/axi_adaq8092.v
View File

@ -45,7 +45,8 @@ module axi_adaq8092 #(
parameter ADC_DATAPATH_DISABLE = 0, parameter ADC_DATAPATH_DISABLE = 0,
parameter IO_DELAY_GROUP = "adc_if_delay_group", parameter IO_DELAY_GROUP = "adc_if_delay_group",
parameter OUTPUT_MODE = 0, parameter OUTPUT_MODE = 0,
parameter [27:0] POLARITY_MASK ='hfffffff) ( parameter [27:0] POLARITY_MASK ='hfffffff
) (
// adc interface (clk, data, over-range) // adc interface (clk, data, over-range)
@ -99,10 +100,11 @@ module axi_adaq8092 #(
output [31:0] s_axi_rdata, output [31:0] s_axi_rdata,
input s_axi_rready, input s_axi_rready,
input [ 2:0] s_axi_awprot, input [ 2:0] s_axi_awprot,
input [ 2:0] s_axi_arprot); input [ 2:0] s_axi_arprot
);
// configuration settings // configuration settings
localparam CONFIG = (OUTPUT_MODE * 128); localparam CONFIG = (OUTPUT_MODE * 128);
// internal registers // internal registers
@ -111,7 +113,7 @@ module axi_adaq8092 #(
reg [31:0] up_rdata = 'd0; reg [31:0] up_rdata = 'd0;
reg up_wack = 'd0; reg up_wack = 'd0;
reg up_rack = 'd0; reg up_rack = 'd0;
// internal clocks & resets // internal clocks & resets
wire up_rstn; wire up_rstn;
@ -122,16 +124,16 @@ module axi_adaq8092 #(
wire adc_or_s; wire adc_or_s;
wire [27:0] adc_data_s; wire [27:0] adc_data_s;
wire [1:0] up_status_or_s; wire [1:0] up_status_or_s;
wire adc_status_s; wire adc_status_s;
wire [29:0] up_dld_s; wire [29:0] up_dld_s;
wire [149:0] up_dwdata_s; wire [149:0] up_dwdata_s;
wire [149:0] up_drdata_s; wire [149:0] up_drdata_s;
wire delay_locked_s; wire delay_locked_s;
wire [13:0] up_raddr_s; wire [13:0] up_raddr_s;
wire [31:0] up_rdata_s[0:3]; wire [31:0] up_rdata_s[0:3];
wire [3:0] up_rack_s ; wire [3:0] up_rack_s;
wire [3:0] up_wack_s; wire [3:0] up_wack_s;
wire up_wreq_s; wire up_wreq_s;
wire [13:0] up_waddr_s; wire [13:0] up_waddr_s;
wire [31:0] up_wdata_s; wire [31:0] up_wdata_s;
@ -147,7 +149,7 @@ module axi_adaq8092 #(
assign up_clk = s_axi_aclk; assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn; assign up_rstn = s_axi_aresetn;
assign adc_valid = 1'b1; assign adc_valid = 1'b1;
// processor read interface // processor read interface
always @(negedge up_rstn or posedge up_clk) begin always @(negedge up_rstn or posedge up_clk) begin
@ -159,12 +161,12 @@ module axi_adaq8092 #(
end else begin end else begin
up_status_or <= up_status_or_s[0] | up_status_or_s[1]; up_status_or <= up_status_or_s[0] | up_status_or_s[1];
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | up_rdata_s[3]; up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | up_rdata_s[3];
up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2] | up_rack_s[3]; up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2] | up_rack_s[3];
up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2] | up_wack_s[3]; up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2] | up_wack_s[3];
end end
end end
// ADC channel 1 // ADC channel 1
axi_adaq8092_channel #( axi_adaq8092_channel #(
.CHANNEL_ID(0), .CHANNEL_ID(0),
@ -189,7 +191,7 @@ module axi_adaq8092 #(
.up_rdata (up_rdata_s[0]), .up_rdata (up_rdata_s[0]),
.up_rack (up_rack_s[0])); .up_rack (up_rack_s[0]));
// ADC channel 2 // ADC channel 2
axi_adaq8092_channel #( axi_adaq8092_channel #(
.CHANNEL_ID(1), .CHANNEL_ID(1),
@ -215,19 +217,19 @@ module axi_adaq8092 #(
.up_rack (up_rack_s[1])); .up_rack (up_rack_s[1]));
// ADC interface // ADC interface
axi_adaq8092_rand_decode i_rand ( axi_adaq8092_rand_decode i_rand (
.adc_data(adc_data_s), .adc_data(adc_data_s),
.adc_clk(adc_clk), .adc_clk(adc_clk),
.adc_rand_enb(adc_custom_control_s[0]), .adc_rand_enb(adc_custom_control_s[0]),
.adc_data_decoded(adc_part_decoded_data_s)); .adc_data_decoded(adc_part_decoded_data_s));
axi_adaq8092_apb_decode i_apb ( axi_adaq8092_apb_decode i_apb (
.adc_data(adc_part_decoded_data_s), .adc_data(adc_part_decoded_data_s),
.adc_clk(adc_clk), .adc_clk(adc_clk),
.adc_abp_enb(adc_custom_control_s[1]), .adc_abp_enb(adc_custom_control_s[1]),
.adc_data_decoded({adc_decoded_data_s_2,adc_decoded_data_s_1})); .adc_data_decoded({adc_decoded_data_s_2,adc_decoded_data_s_1}));
axi_adaq8092_if #( axi_adaq8092_if #(
.OUTPUT_MODE(OUTPUT_MODE), .OUTPUT_MODE(OUTPUT_MODE),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
@ -259,7 +261,7 @@ module axi_adaq8092 #(
// adc delay control // adc delay control
up_delay_cntrl #( up_delay_cntrl #(
.DATA_WIDTH(30), .DATA_WIDTH(30),
.BASE_ADDRESS(6'h02) .BASE_ADDRESS(6'h02)
) i_delay_cntrl ( ) i_delay_cntrl (
.delay_clk (delay_clk), .delay_clk (delay_clk),

15
library/axi_adaq8092/axi_adaq8092_apb_decode.v
View File

@ -32,7 +32,7 @@
// //
// *************************************************************************** // ***************************************************************************
// *************************************************************************** // ***************************************************************************
// ADC ALTERNATE BIT POLARITY DECODE // ADC ALTERNATE BIT POLARITY DECODE
`timescale 1ns/100ps `timescale 1ns/100ps
@ -41,23 +41,24 @@ module axi_adaq8092_apb_decode (
input [27:0] adc_data, input [27:0] adc_data,
input adc_clk, input adc_clk,
input adc_abp_enb, input adc_abp_enb,
output [27:0] adc_data_decoded); output [27:0] adc_data_decoded
);
// internal registers
// internal registers
reg [27:0] adc_data_decoded_s; reg [27:0] adc_data_decoded_s;
// internal variable // internal variable
integer i; integer i;
assign adc_data_decoded = adc_abp_enb ? adc_data_decoded_s : adc_data ; assign adc_data_decoded = adc_abp_enb ? adc_data_decoded_s : adc_data ;
always @(posedge adc_clk) begin always @(posedge adc_clk) begin
for (i = 0; i <= 13; i = i + 1) begin for (i = 0; i <= 13; i = i + 1) begin
adc_data_decoded_s[2*i+1] = ~adc_data[2*i+1]; adc_data_decoded_s[2*i+1] = ~adc_data[2*i+1];
adc_data_decoded_s[2*i] = adc_data[2*i]; adc_data_decoded_s[2*i] = adc_data[2*i];
end end
end end
endmodule endmodule

12
library/axi_adaq8092/axi_adaq8092_channel.v
View File

@ -39,7 +39,8 @@
module axi_adaq8092_channel #( module axi_adaq8092_channel #(
parameter CHANNEL_ID = 0, parameter CHANNEL_ID = 0,
parameter DATAPATH_DISABLE = 0) ( parameter DATAPATH_DISABLE = 0
) (
// adc interface // adc interface
@ -66,7 +67,8 @@ module axi_adaq8092_channel #(
input up_rreq, input up_rreq,
input [13:0] up_raddr, input [13:0] up_raddr,
output [31:0] up_rdata, output [31:0] up_rdata,
output up_rack); output up_rack
);
// internal signals // internal signals
@ -77,7 +79,7 @@ module axi_adaq8092_channel #(
wire adc_dfmt_enable_s; wire adc_dfmt_enable_s;
wire [15:0] adc_dcfilt_offset_s; wire [15:0] adc_dcfilt_offset_s;
wire [15:0] adc_dcfilt_coeff_s; wire [15:0] adc_dcfilt_coeff_s;
generate generate
if (DATAPATH_DISABLE == 1) begin if (DATAPATH_DISABLE == 1) begin
assign adc_dfmt_data_s = {2'b0 , adc_data}; assign adc_dfmt_data_s = {2'b0 , adc_data};
@ -110,8 +112,8 @@ module axi_adaq8092_channel #(
.dcfilt_coeff (adc_dcfilt_coeff_s), .dcfilt_coeff (adc_dcfilt_coeff_s),
.dcfilt_offset (adc_dcfilt_offset_s)); .dcfilt_offset (adc_dcfilt_offset_s));
end end
endgenerate endgenerate
up_adc_channel #( up_adc_channel #(
.COMMON_ID (6'h01), .COMMON_ID (6'h01),
.CHANNEL_ID(CHANNEL_ID), .CHANNEL_ID(CHANNEL_ID),

124
library/axi_adaq8092/axi_adaq8092_if.v
View File

@ -43,7 +43,8 @@ module axi_adaq8092_if #(
parameter IO_DELAY_GROUP = "adc_if_delay_group", parameter IO_DELAY_GROUP = "adc_if_delay_group",
parameter DELAY_REFCLK_FREQUENCY = 200, parameter DELAY_REFCLK_FREQUENCY = 200,
parameter [27:0] POLARITY_MASK ='hfffffff, parameter [27:0] POLARITY_MASK ='hfffffff,
parameter OUTPUT_MODE = 0) ( parameter OUTPUT_MODE = 0
) (
// adc interface (clk, data, over-range) // adc interface (clk, data, over-range)
// nominal clock 80 MHz, up to 105 MHz // nominal clock 80 MHz, up to 105 MHz
@ -60,14 +61,14 @@ module axi_adaq8092_if #(
input cmos_adc_data_or_1, input cmos_adc_data_or_1,
input cmos_adc_data_or_2, input cmos_adc_data_or_2,
// up control SDR or DDR // up control SDR or DDR
input sdr_or_ddr, input sdr_or_ddr,
// interface outputs // interface outputs
output adc_clk, output adc_clk,
output reg [27:0] adc_data, output reg [27:0] adc_data,
output reg adc_or, output reg adc_or,
output reg adc_status, output reg adc_status,
@ -79,7 +80,8 @@ module axi_adaq8092_if #(
output [149:0] up_drdata, output [149:0] up_drdata,
input delay_clk, input delay_clk,
input delay_rst, input delay_rst,
output delay_locked); output delay_locked
);
// internal registers // internal registers
@ -105,73 +107,73 @@ module axi_adaq8092_if #(
localparam LVDS = 0; localparam LVDS = 0;
localparam CMOS = 1; localparam CMOS = 1;
always @(posedge adc_clk) begin always @(posedge adc_clk) begin
adc_status <= 1'b1; adc_status <= 1'b1;
if (OUTPUT_MODE == LVDS) begin if (OUTPUT_MODE == LVDS) begin
adc_or <= adc_or_s_1 | adc_or_s_2; adc_or <= adc_or_s_1 | adc_or_s_2;
adc_data <= POLARITY_MASK ^ adc_data_s; adc_data <= POLARITY_MASK ^ adc_data_s;
adc_data_s <= { lvds_adc_data_n_s[13], lvds_adc_data_p_s[13], adc_data_s <= { lvds_adc_data_n_s[13], lvds_adc_data_p_s[13],
lvds_adc_data_n_s[12], lvds_adc_data_p_s[12], lvds_adc_data_n_s[12], lvds_adc_data_p_s[12],
lvds_adc_data_n_s[11], lvds_adc_data_p_s[11], lvds_adc_data_n_s[11], lvds_adc_data_p_s[11],
lvds_adc_data_n_s[10], lvds_adc_data_p_s[10], lvds_adc_data_n_s[10], lvds_adc_data_p_s[10],
lvds_adc_data_n_s[9], lvds_adc_data_p_s[9], lvds_adc_data_n_s[9], lvds_adc_data_p_s[9],
lvds_adc_data_n_s[8], lvds_adc_data_p_s[8], lvds_adc_data_n_s[8], lvds_adc_data_p_s[8],
lvds_adc_data_n_s[7], lvds_adc_data_p_s[7], lvds_adc_data_n_s[7], lvds_adc_data_p_s[7],
lvds_adc_data_n_s[6], lvds_adc_data_p_s[6], lvds_adc_data_n_s[6], lvds_adc_data_p_s[6],
lvds_adc_data_n_s[5], lvds_adc_data_p_s[5], lvds_adc_data_n_s[5], lvds_adc_data_p_s[5],
lvds_adc_data_n_s[4], lvds_adc_data_p_s[4], lvds_adc_data_n_s[4], lvds_adc_data_p_s[4],
lvds_adc_data_n_s[3], lvds_adc_data_p_s[3], lvds_adc_data_n_s[3], lvds_adc_data_p_s[3],
lvds_adc_data_n_s[2], lvds_adc_data_p_s[2], lvds_adc_data_n_s[2], lvds_adc_data_p_s[2],
lvds_adc_data_n_s[1], lvds_adc_data_p_s[1], lvds_adc_data_n_s[1], lvds_adc_data_p_s[1],
lvds_adc_data_n_s[0], lvds_adc_data_p_s[0]}; lvds_adc_data_n_s[0], lvds_adc_data_p_s[0]};
end else if (OUTPUT_MODE == CMOS) begin end else if (OUTPUT_MODE == CMOS) begin
adc_data <= adc_data_s; adc_data <= adc_data_s;
if (sdr_or_ddr == 0) begin //DDR_CMOS if (sdr_or_ddr == 0) begin //DDR_CMOS
adc_or <= adc_or_s_1_p | adc_or_s_1_n; adc_or <= adc_or_s_1_p | adc_or_s_1_n;
adc_data_s <= { cmos_adc_data_n_s[27], cmos_adc_data_p_s[27], adc_data_s <= { cmos_adc_data_n_s[27], cmos_adc_data_p_s[27],
cmos_adc_data_n_s[25], cmos_adc_data_p_s[25], cmos_adc_data_n_s[25], cmos_adc_data_p_s[25],
cmos_adc_data_n_s[23], cmos_adc_data_p_s[23], cmos_adc_data_n_s[23], cmos_adc_data_p_s[23],
cmos_adc_data_n_s[21], cmos_adc_data_p_s[21], cmos_adc_data_n_s[21], cmos_adc_data_p_s[21],
cmos_adc_data_n_s[19], cmos_adc_data_p_s[19], cmos_adc_data_n_s[19], cmos_adc_data_p_s[19],
cmos_adc_data_n_s[17], cmos_adc_data_p_s[17], cmos_adc_data_n_s[17], cmos_adc_data_p_s[17],
cmos_adc_data_n_s[15], cmos_adc_data_p_s[15], cmos_adc_data_n_s[15], cmos_adc_data_p_s[15],
cmos_adc_data_n_s[13], cmos_adc_data_p_s[13], cmos_adc_data_n_s[13], cmos_adc_data_p_s[13],
cmos_adc_data_n_s[11], cmos_adc_data_p_s[11], cmos_adc_data_n_s[11], cmos_adc_data_p_s[11],
cmos_adc_data_n_s[9], cmos_adc_data_p_s[9], cmos_adc_data_n_s[9], cmos_adc_data_p_s[9],
cmos_adc_data_n_s[7], cmos_adc_data_p_s[7], cmos_adc_data_n_s[7], cmos_adc_data_p_s[7],
cmos_adc_data_n_s[5], cmos_adc_data_p_s[5], cmos_adc_data_n_s[5], cmos_adc_data_p_s[5],
cmos_adc_data_n_s[3], cmos_adc_data_p_s[3], cmos_adc_data_n_s[3], cmos_adc_data_p_s[3],
cmos_adc_data_n_s[1], cmos_adc_data_p_s[1]}; cmos_adc_data_n_s[1], cmos_adc_data_p_s[1]};
end else if (sdr_or_ddr == 1) begin //SDR_CMOS end else if (sdr_or_ddr == 1) begin //SDR_CMOS
adc_or <= adc_or_s_1_p | adc_or_s_2_p; adc_or <= adc_or_s_1_p | adc_or_s_2_p;
adc_data_s <= { cmos_adc_data_p_s[27], cmos_adc_data_p_s[26], adc_data_s <= { cmos_adc_data_p_s[27], cmos_adc_data_p_s[26],
cmos_adc_data_p_s[25], cmos_adc_data_p_s[24], cmos_adc_data_p_s[25], cmos_adc_data_p_s[24],
cmos_adc_data_p_s[23], cmos_adc_data_p_s[22], cmos_adc_data_p_s[23], cmos_adc_data_p_s[22],
cmos_adc_data_p_s[21], cmos_adc_data_p_s[20], cmos_adc_data_p_s[21], cmos_adc_data_p_s[20],
cmos_adc_data_p_s[19], cmos_adc_data_p_s[18], cmos_adc_data_p_s[19], cmos_adc_data_p_s[18],
cmos_adc_data_p_s[17], cmos_adc_data_p_s[16], cmos_adc_data_p_s[17], cmos_adc_data_p_s[16],
cmos_adc_data_p_s[15], cmos_adc_data_p_s[14], cmos_adc_data_p_s[15], cmos_adc_data_p_s[14],
cmos_adc_data_p_s[13], cmos_adc_data_p_s[12], cmos_adc_data_p_s[13], cmos_adc_data_p_s[12],
cmos_adc_data_p_s[11], cmos_adc_data_p_s[10], cmos_adc_data_p_s[11], cmos_adc_data_p_s[10],
cmos_adc_data_p_s[9], cmos_adc_data_p_s[8], cmos_adc_data_p_s[9], cmos_adc_data_p_s[8],
cmos_adc_data_p_s[7], cmos_adc_data_p_s[6], cmos_adc_data_p_s[7], cmos_adc_data_p_s[6],
cmos_adc_data_p_s[5], cmos_adc_data_p_s[4], cmos_adc_data_p_s[5], cmos_adc_data_p_s[4],
cmos_adc_data_p_s[3], cmos_adc_data_p_s[2], cmos_adc_data_p_s[3], cmos_adc_data_p_s[2],
cmos_adc_data_p_s[1], cmos_adc_data_p_s[0]}; cmos_adc_data_p_s[1], cmos_adc_data_p_s[0]};
end end
end end
end end
// data interface // data interface
generate generate
if (OUTPUT_MODE == LVDS) begin if (OUTPUT_MODE == LVDS) begin
for (l_inst = 0; l_inst <= 13; l_inst = l_inst + 1) begin : lvds_adc_if // DDR LVDS INTERFACE for (l_inst = 0; l_inst <= 13; l_inst = l_inst + 1) begin : lvds_adc_if // DDR LVDS INTERFACE
ad_data_in #( ad_data_in #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_CTRL (0), .IODELAY_CTRL (0),
@ -191,10 +193,10 @@ module axi_adaq8092_if #(
.delay_clk (delay_clk), .delay_clk (delay_clk),
.delay_rst (delay_rst), .delay_rst (delay_rst),
.delay_locked ()); .delay_locked ());
end end
end else if (OUTPUT_MODE == CMOS) begin end else if (OUTPUT_MODE == CMOS) begin
for (l_inst = 0; l_inst <= 27; l_inst = l_inst + 1) begin : cmos_adc_if // CMOS INTERFACE for (l_inst = 0; l_inst <= 27; l_inst = l_inst + 1) begin : cmos_adc_if // CMOS INTERFACE
ad_data_in #( ad_data_in #(
.SINGLE_ENDED(1), .SINGLE_ENDED(1),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
@ -215,8 +217,8 @@ module axi_adaq8092_if #(
.delay_clk (delay_clk), .delay_clk (delay_clk),
.delay_rst (delay_rst), .delay_rst (delay_rst),
.delay_locked ()); .delay_locked ());
end end
end end
endgenerate endgenerate
// over-range interface // over-range interface
@ -262,7 +264,7 @@ module axi_adaq8092_if #(
.delay_clk (delay_clk), .delay_clk (delay_clk),
.delay_rst (delay_rst), .delay_rst (delay_rst),
.delay_locked ()); .delay_locked ());
ad_data_in #( ad_data_in #(
.SINGLE_ENDED(1), .SINGLE_ENDED(1),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
@ -284,7 +286,7 @@ module axi_adaq8092_if #(
.delay_rst (delay_rst), .delay_rst (delay_rst),
.delay_locked ()); .delay_locked ());
end end
// clock // clock
ad_data_clk i_adc_clk ( ad_data_clk i_adc_clk (
@ -293,5 +295,5 @@ module axi_adaq8092_if #(
.clk_in_p (adc_clk_in_p), .clk_in_p (adc_clk_in_p),
.clk_in_n (adc_clk_in_n), .clk_in_n (adc_clk_in_n),
.clk (adc_clk)); .clk (adc_clk));
endmodule endmodule

17
library/axi_adaq8092/axi_adaq8092_rand_decode.v
View File

@ -32,20 +32,21 @@
// //
// *************************************************************************** // ***************************************************************************
// *************************************************************************** // ***************************************************************************
// ADC DIGITAL OUTPUT RANDOMIZE DECODE // ADC DIGITAL OUTPUT RANDOMIZE DECODE
`timescale 1ns/100ps `timescale 1ns/100ps
module axi_adaq8092_rand_decode ( module axi_adaq8092_rand_decode (
// data interface // data interface
input [27:0] adc_data, input [27:0] adc_data,
input adc_clk, input adc_clk,
input adc_rand_enb, input adc_rand_enb,
output [27:0] adc_data_decoded); output [27:0] adc_data_decoded
);
// internal register
// internal register
reg [27:0] adc_data_decoded_s; reg [27:0] adc_data_decoded_s;
@ -55,7 +56,7 @@ module axi_adaq8092_rand_decode (
// DATA DECODING // DATA DECODING
always @(posedge adc_clk) begin always @(posedge adc_clk) begin
for (i = 1; i <= 13; i = i + 1) begin for (i = 1; i <= 13; i = i + 1) begin
adc_data_decoded_s[i] = adc_data[i] ^ adc_data[0]; adc_data_decoded_s[i] = adc_data[i] ^ adc_data[0];
end end
@ -63,8 +64,8 @@ module axi_adaq8092_rand_decode (
adc_data_decoded_s[i] = adc_data[i] ^ adc_data[14]; adc_data_decoded_s[i] = adc_data[i] ^ adc_data[14];
end end
adc_data_decoded_s[0] = adc_data[0]; adc_data_decoded_s[0] = adc_data[0];
adc_data_decoded_s[14] = adc_data[14]; adc_data_decoded_s[14] = adc_data[14];
end end
endmodule endmodule

15
library/axi_adc_decimate/axi_adc_decimate.v
View File

@ -37,8 +37,8 @@
module axi_adc_decimate #( module axi_adc_decimate #(
parameter CORRECTION_DISABLE = 1) ( parameter CORRECTION_DISABLE = 1
) (
input adc_clk, input adc_clk,
input adc_rst, input adc_rst,
@ -76,7 +76,8 @@ module axi_adc_decimate #(
output s_axi_rvalid, output s_axi_rvalid,
output [31:0] s_axi_rdata, output [31:0] s_axi_rdata,
output [ 1:0] s_axi_rresp, output [ 1:0] s_axi_rresp,
input s_axi_rready); input s_axi_rready
);
// internal signals // internal signals
@ -130,7 +131,6 @@ module axi_adc_decimate #(
.adc_dec_valid_b(adc_dec_valid_b)); .adc_dec_valid_b(adc_dec_valid_b));
axi_adc_decimate_reg axi_adc_decimate_reg ( axi_adc_decimate_reg axi_adc_decimate_reg (
.clk (adc_clk), .clk (adc_clk),
.adc_decimation_ratio (decimation_ratio), .adc_decimation_ratio (decimation_ratio),
@ -152,9 +152,9 @@ module axi_adc_decimate #(
.up_rdata (up_rdata), .up_rdata (up_rdata),
.up_rack (up_rack)); .up_rack (up_rack));
up_axi #( up_axi #(
.AXI_ADDRESS_WIDTH(7) .AXI_ADDRESS_WIDTH(7)
) i_up_axi ( ) i_up_axi (
.up_rstn (up_rstn), .up_rstn (up_rstn),
.up_clk (up_clk), .up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid), .up_axi_awvalid (s_axi_awvalid),
@ -184,6 +184,3 @@ module axi_adc_decimate #(
.up_rack (up_rack)); .up_rack (up_rack));
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

13
library/axi_adc_decimate/axi_adc_decimate_filter.v
View File

@ -35,11 +35,10 @@
`timescale 1ns/100ps `timescale 1ns/100ps
module axi_adc_decimate_filter #( module axi_adc_decimate_filter #(
parameter CORRECTION_DISABLE = 1) ( parameter CORRECTION_DISABLE = 1
) (
input adc_clk, input adc_clk,
input adc_rst, input adc_rst,
@ -122,7 +121,8 @@ module axi_adc_decimate_filter #(
.filter_out(adc_fir_data_b), .filter_out(adc_fir_data_b),
.ce_out(adc_fir_valid_b)); .ce_out(adc_fir_valid_b));
ad_iqcor #(.Q_OR_I_N (0), ad_iqcor #(
.Q_OR_I_N (0),
.DISABLE(CORRECTION_DISABLE), .DISABLE(CORRECTION_DISABLE),
.SCALE_ONLY(1) .SCALE_ONLY(1)
) i_scale_correction_a ( ) i_scale_correction_a (
@ -136,7 +136,8 @@ module axi_adc_decimate_filter #(
.iqcor_coeff_1 (adc_correction_coefficient_a), .iqcor_coeff_1 (adc_correction_coefficient_a),
.iqcor_coeff_2 (16'h0)); .iqcor_coeff_2 (16'h0));
ad_iqcor #(.Q_OR_I_N (0), ad_iqcor #(
.Q_OR_I_N (0),
.DISABLE(CORRECTION_DISABLE), .DISABLE(CORRECTION_DISABLE),
.SCALE_ONLY(1) .SCALE_ONLY(1)
) i_scale_correction_b ( ) i_scale_correction_b (
@ -172,7 +173,7 @@ module axi_adc_decimate_filter #(
default: adc_dec_valid_a_filter = adc_fir_valid_a; default: adc_dec_valid_a_filter = adc_fir_valid_a;
endcase endcase
case (filter_enable[0]) case (filter_enable[0])
1'b0: adc_dec_data_b_r = {{4{adc_data_b[11]}},adc_data_b}; 1'b0: adc_dec_data_b_r = {{4{adc_data_b[11]}},adc_data_b};
default adc_dec_data_b_r = {adc_fir_data_b[25], adc_fir_data_b[25:11]}; default adc_dec_data_b_r = {adc_fir_data_b[25], adc_fir_data_b[25:11]};
endcase endcase

11
library/axi_adc_decimate/axi_adc_decimate_reg.v
View File

@ -58,7 +58,8 @@ module axi_adc_decimate_reg(
input up_rreq, input up_rreq,
input [ 4:0] up_raddr, input [ 4:0] up_raddr,
output reg [31:0] up_rdata, output reg [31:0] up_rdata,
output reg up_rack); output reg up_rack
);
// internal registers // internal registers
@ -129,7 +130,9 @@ module axi_adc_decimate_reg(
end end
end end
up_xfer_cntrl #(.DATA_WIDTH(69)) i_xfer_cntrl ( up_xfer_cntrl #(
.DATA_WIDTH (69)
) i_xfer_cntrl (
.up_rstn (up_rstn), .up_rstn (up_rstn),
.up_clk (up_clk), .up_clk (up_clk),
.up_data_cntrl ({ up_config[1], // 1 .up_data_cntrl ({ up_config[1], // 1
@ -150,7 +153,3 @@ module axi_adc_decimate_reg(
adc_filter_mask})); // 3 adc_filter_mask})); // 3
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

11
library/axi_adc_decimate/cic_decim.v
View File

@ -44,7 +44,7 @@ module cic_decim (
input [2:0] rate_sel, input [2:0] rate_sel,
output [11:0] filter_out, output [11:0] filter_out,
output ce_out output ce_out
); );
localparam NUM_STAGES = 6; localparam NUM_STAGES = 6;
localparam DATA_WIDTH = 106; localparam DATA_WIDTH = 106;
@ -110,8 +110,7 @@ module cic_decim (
.clk(clk), .clk(clk),
.ce(enable), .ce(enable),
.data_in(data_stage[i]), .data_in(data_stage[i]),
.data_out(data_stage[i+1]) .data_out(data_stage[i+1]));
);
end end
endgenerate endgenerate
@ -125,8 +124,7 @@ module cic_decim (
.ce(ce_comb), .ce(ce_comb),
.enable(filter_enable), .enable(filter_enable),
.data_in(data_stage[6]), .data_in(data_stage[6]),
.data_out(data_stage[11]) .data_out(data_stage[11]));
);
cic_comb #( cic_comb #(
.DATA_WIDTH(DATA_WIDTH), .DATA_WIDTH(DATA_WIDTH),
@ -138,8 +136,7 @@ module cic_decim (
.ce(ce_comb), .ce(ce_comb),
.enable(filter_enable), .enable(filter_enable),
.data_in(data_stage[11]), .data_in(data_stage[11]),
.data_out(data_stage[12]) .data_out(data_stage[12]));
);
assign data_final_stage = data_stage[2*NUM_STAGES]; assign data_final_stage = data_stage[2*NUM_STAGES];

88
library/axi_adc_trigger/axi_adc_trigger.v
View File

@ -40,7 +40,8 @@ module axi_adc_trigger #(
// parameters // parameters
parameter SIGN_BITS = 2, parameter SIGN_BITS = 2,
parameter OUT_PIN_HOLD_N = 100000) ( parameter OUT_PIN_HOLD_N = 100000
) (
// interface // interface
@ -89,8 +90,8 @@ module axi_adc_trigger #(
output s_axi_rvalid, output s_axi_rvalid,
output [31:0] s_axi_rdata, output [31:0] s_axi_rdata,
output [ 1:0] s_axi_rresp, output [ 1:0] s_axi_rresp,
input s_axi_rready); input s_axi_rready
);
localparam DW = 15 - SIGN_BITS; localparam DW = 15 - SIGN_BITS;
@ -211,7 +212,6 @@ module axi_adc_trigger #(
reg trigger_out_hold; reg trigger_out_hold;
reg trigger_out_ack; reg trigger_out_ack;
// signal name changes // signal name changes
assign up_clk = s_axi_aclk; assign up_clk = s_axi_aclk;
@ -278,7 +278,6 @@ module axi_adc_trigger #(
trigger_o[1] <= (trig_o_hold_cnt_1 == 'd0) ? trigger_o_m[1] : trig_o_hold_1; trigger_o[1] <= (trig_o_hold_cnt_1 == 'd0) ? trigger_o_m[1] : trig_o_hold_1;
end end
// 1. keep data in sync with the trigger. The trigger bypasses the variable // 1. keep data in sync with the trigger. The trigger bypasses the variable
// fifo. The data goes through and it is delayed with 4 clock cycles) // fifo. The data goes through and it is delayed with 4 clock cycles)
// 2. For non max sample rate of the ADC, the trigger signal that originates // 2. For non max sample rate of the ADC, the trigger signal that originates
@ -344,7 +343,6 @@ module axi_adc_trigger #(
end end
end end
always @(posedge clk) begin always @(posedge clk) begin
if (trigger_delay == 0) begin if (trigger_delay == 0) begin
if (streaming == 1'b1 && data_valid_a == 1'b1 && trigger_out_holdoff == 1'b1) begin if (streaming == 1'b1 && data_valid_a == 1'b1 && trigger_out_holdoff == 1'b1) begin
@ -470,7 +468,7 @@ module axi_adc_trigger #(
(trigger_b_any_edge & any_edge[1])); (trigger_b_any_edge & any_edge[1]));
end end
always @(*) begin always @(*) begin
case(trigger_out_control[3:0]) case(trigger_out_control[3:0])
4'h0: trigger_out_mixed = trigger_a; 4'h0: trigger_out_mixed = trigger_a;
4'h1: trigger_out_mixed = trigger_b; 4'h1: trigger_out_mixed = trigger_b;
@ -569,54 +567,53 @@ module axi_adc_trigger #(
assign comp_low_b_s = !comp_high_b; assign comp_low_b_s = !comp_high_b;
axi_adc_trigger_reg adc_trigger_registers ( axi_adc_trigger_reg adc_trigger_registers (
.clk(clk),
.clk(clk), .io_selection(io_selection),
.trigger_o(trigger_up_o_s),
.triggered(up_triggered),
.io_selection(io_selection), .low_level(low_level),
.trigger_o(trigger_up_o_s), .high_level(high_level),
.triggered(up_triggered), .any_edge(any_edge),
.rise_edge(rise_edge),
.fall_edge(fall_edge),
.low_level(low_level), .limit_a(limit_a),
.high_level(high_level), .function_a(function_a),
.any_edge(any_edge), .hysteresis_a(hysteresis_a),
.rise_edge(rise_edge), .trigger_l_mix_a(trigger_l_mix_a),
.fall_edge(fall_edge),
.limit_a(limit_a), .limit_b(limit_b),
.function_a(function_a), .function_b(function_b),
.hysteresis_a(hysteresis_a), .hysteresis_b(hysteresis_b),
.trigger_l_mix_a(trigger_l_mix_a), .trigger_l_mix_b(trigger_l_mix_b),
.limit_b(limit_b), .trigger_out_control(trigger_out_control),
.function_b(function_b), .trigger_delay(trigger_delay),
.hysteresis_b(hysteresis_b), .trigger_holdoff (trigger_holdoff),
.trigger_l_mix_b(trigger_l_mix_b), .trigger_out_hold_pins (trigger_out_hold_pins),
.trigger_out_control(trigger_out_control), .fifo_depth(fifo_depth),
.trigger_delay(trigger_delay),
.trigger_holdoff (trigger_holdoff),
.trigger_out_hold_pins (trigger_out_hold_pins),
.fifo_depth(fifo_depth), .streaming(streaming),
.streaming(streaming), // bus interface
// bus interface .up_rstn(up_rstn),
.up_clk(up_clk),
.up_wreq(up_wreq),
.up_waddr(up_waddr),
.up_wdata(up_wdata),
.up_wack(up_wack),
.up_rreq(up_rreq),
.up_raddr(up_raddr),
.up_rdata(up_rdata),
.up_rack(up_rack));
.up_rstn(up_rstn), up_axi #(
.up_clk(up_clk),
.up_wreq(up_wreq),
.up_waddr(up_waddr),
.up_wdata(up_wdata),
.up_wack(up_wack),
.up_rreq(up_rreq),
.up_raddr(up_raddr),
.up_rdata(up_rdata),
.up_rack(up_rack));
up_axi #(
.AXI_ADDRESS_WIDTH(7) .AXI_ADDRESS_WIDTH(7)
) i_up_axi ( ) i_up_axi (
.up_rstn (up_rstn), .up_rstn (up_rstn),
.up_clk (up_clk), .up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid), .up_axi_awvalid (s_axi_awvalid),
@ -646,6 +643,3 @@ module axi_adc_trigger #(
.up_rack (up_rack)); .up_rack (up_rack));
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

14
library/axi_adc_trigger/axi_adc_trigger_reg.v
View File

@ -67,7 +67,7 @@ module axi_adc_trigger_reg (
output streaming, output streaming,
// bus interface // bus interface
input up_rstn, input up_rstn,
input up_clk, input up_clk,
@ -78,7 +78,8 @@ module axi_adc_trigger_reg (
input up_rreq, input up_rreq,
input [ 4:0] up_raddr, input [ 4:0] up_raddr,
output reg [31:0] up_rdata, output reg [31:0] up_rdata,
output reg up_rack); output reg up_rack
);
localparam DEFAULT_OUT_HOLD = 100000; // 1ms localparam DEFAULT_OUT_HOLD = 100000; // 1ms
@ -239,7 +240,9 @@ module axi_adc_trigger_reg (
end end
end end
up_xfer_cntrl #(.DATA_WIDTH(262)) i_xfer_cntrl ( up_xfer_cntrl #(
.DATA_WIDTH(262)
) i_xfer_cntrl (
.up_rstn (up_rstn), .up_rstn (up_rstn),
.up_clk (up_clk), .up_clk (up_clk),
.up_data_cntrl ({ up_streaming, // 1 .up_data_cntrl ({ up_streaming, // 1
@ -259,7 +262,6 @@ module axi_adc_trigger_reg (
up_trigger_holdoff, // 32 up_trigger_holdoff, // 32
up_trigger_out_hold_pins, // 20 up_trigger_out_hold_pins, // 20
up_trigger_delay}), // 32 up_trigger_delay}), // 32
.up_xfer_done (), .up_xfer_done (),
.d_rst (1'b0), .d_rst (1'b0),
.d_clk (clk), .d_clk (clk),
@ -282,7 +284,3 @@ module axi_adc_trigger_reg (
trigger_delay})); // 32 trigger_delay})); // 32
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

2
library/axi_adrv9001/adrv9001_pack.v
View File

@ -51,7 +51,7 @@
module adrv9001_pack #( module adrv9001_pack #(
parameter WIDTH = 8 parameter WIDTH = 8
)( ) (
input clk, // Input clock input clk, // Input clock
input rst, input rst,
input sof, // Start of frame indicator marking the MS Beat input sof, // Start of frame indicator marking the MS Beat

62
library/axi_adrv9001/adrv9001_rx.v
View File

@ -44,6 +44,7 @@ module adrv9001_rx #(
parameter USE_BUFG = 0, parameter USE_BUFG = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group" parameter IO_DELAY_GROUP = "dev_if_delay_group"
) ( ) (
// device interface // device interface
input rx_dclk_in_n_NC, input rx_dclk_in_n_NC,
input rx_dclk_in_p_dclk_in, input rx_dclk_in_p_dclk_in,
@ -114,8 +115,8 @@ module adrv9001_rx #(
.DDR_OR_SDR_N (DDR_OR_SDR_N), .DDR_OR_SDR_N (DDR_OR_SDR_N),
.DATA_WIDTH (NUM_LANES), .DATA_WIDTH (NUM_LANES),
.DRP_WIDTH (DRP_WIDTH), .DRP_WIDTH (DRP_WIDTH),
.SERDES_FACTOR (8)) .SERDES_FACTOR (8)
i_serdes ( ) i_serdes (
.rst (adc_rst|ssi_rst), .rst (adc_rst|ssi_rst),
.clk (adc_clk_in_fast), .clk (adc_clk_in_fast),
.div_clk (adc_clk_div), .div_clk (adc_clk_div),
@ -196,7 +197,9 @@ module adrv9001_rx #(
.I (clk_in_s), .I (clk_in_s),
.O (adc_clk_in_fast)); .O (adc_clk_in_fast));
BUFR #(.BUFR_DIVIDE("4")) i_div_clk_buf ( BUFR #(
.BUFR_DIVIDE("4")
) i_div_clk_buf (
.CLR (mssi_sync), .CLR (mssi_sync),
.CE (1'b1), .CE (1'b1),
.I (clk_in_s), .I (clk_in_s),
@ -205,24 +208,19 @@ module adrv9001_rx #(
if (USE_BUFG == 1) begin if (USE_BUFG == 1) begin
BUFG I_bufg ( BUFG I_bufg (
.I (adc_clk_div_s), .I (adc_clk_div_s),
.O (adc_clk_div) .O (adc_clk_div));
);
end else begin end else begin
assign adc_clk_div = adc_clk_div_s; assign adc_clk_div = adc_clk_div_s;
end end
xpm_cdc_async_rst xpm_cdc_async_rst #(
# ( .DEST_SYNC_FF (10), // DECIMAL; range: 2-10
.DEST_SYNC_FF (10), // DECIMAL; range: 2-10 .INIT_SYNC_FF ( 0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
.INIT_SYNC_FF ( 0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values .RST_ACTIVE_HIGH ( 1) // DECIMAL; 0=active low reset, 1=active high reset
.RST_ACTIVE_HIGH ( 1) // DECIMAL; 0=active low reset, 1=active high reset ) rst_syncro (
) .src_arst (mssi_sync),
rst_syncro .dest_clk (adc_clk_div),
( .dest_arst(ssi_rst));
.src_arst (mssi_sync ),
.dest_clk (adc_clk_div),
.dest_arst(ssi_rst )
);
end else begin end else begin
wire adc_clk_in; wire adc_clk_in;
@ -248,26 +246,24 @@ module adrv9001_rx #(
assign adc_clk_in = clk_in_s; assign adc_clk_in = clk_in_s;
BUFGCE #( BUFGCE #(
.CE_TYPE ("SYNC"), .CE_TYPE ("SYNC"),
.IS_CE_INVERTED (1'b0), .IS_CE_INVERTED (1'b0),
.IS_I_INVERTED (1'b0) .IS_I_INVERTED (1'b0)
) i_clk_buf_fast ( ) i_clk_buf_fast (
.O (adc_clk_in_fast), .O (adc_clk_in_fast),
.CE (1'b1), .CE (1'b1),
.I (adc_clk_in) .I (adc_clk_in));
);
BUFGCE_DIV #( BUFGCE_DIV #(
.BUFGCE_DIVIDE (4), .BUFGCE_DIVIDE (4),
.IS_CE_INVERTED (1'b0), .IS_CE_INVERTED (1'b0),
.IS_CLR_INVERTED (1'b0), .IS_CLR_INVERTED (1'b0),
.IS_I_INVERTED (1'b0) .IS_I_INVERTED (1'b0)
) i_div_clk_buf ( ) i_div_clk_buf (
.O (adc_clk_div), .O (adc_clk_div),
.CE (1'b1), .CE (1'b1),
.CLR (ssi_rst), .CLR (ssi_rst),
.I (adc_clk_in) .I (adc_clk_in));
);
assign ssi_rst = ssi_rst_pos; assign ssi_rst = ssi_rst_pos;

67
library/axi_adrv9001/adrv9001_rx_link.v
View File

@ -38,7 +38,6 @@
module adrv9001_rx_link #( module adrv9001_rx_link #(
parameter CMOS_LVDS_N = 0 parameter CMOS_LVDS_N = 0
) ( ) (
input adc_rst, input adc_rst,
input adc_clk_div, input adc_clk_div,
input [7:0] adc_data_0, input [7:0] adc_data_0,
@ -107,8 +106,7 @@ module adrv9001_rx_link #(
.idata (sdr_data_0), .idata (sdr_data_0),
.ivalid (adc_valid), .ivalid (adc_valid),
.strobe (sdr_data_strobe), .strobe (sdr_data_strobe),
.odata (sdr_data_0_aligned) .odata (sdr_data_0_aligned));
);
adrv9001_aligner4 i_rx_aligner4_1 ( adrv9001_aligner4 i_rx_aligner4_1 (
.clk (adc_clk_div), .clk (adc_clk_div),
@ -116,8 +114,7 @@ module adrv9001_rx_link #(
.idata (sdr_data_1), .idata (sdr_data_1),
.ivalid (adc_valid), .ivalid (adc_valid),
.strobe (sdr_data_strobe), .strobe (sdr_data_strobe),
.odata (sdr_data_1_aligned) .odata (sdr_data_1_aligned));
);
adrv9001_aligner4 i_rx_aligner4_2 ( adrv9001_aligner4 i_rx_aligner4_2 (
.clk (adc_clk_div), .clk (adc_clk_div),
@ -125,8 +122,7 @@ module adrv9001_rx_link #(
.idata (sdr_data_2), .idata (sdr_data_2),
.ivalid (adc_valid), .ivalid (adc_valid),
.strobe (sdr_data_strobe), .strobe (sdr_data_strobe),
.odata (sdr_data_2_aligned) .odata (sdr_data_2_aligned));
);
adrv9001_aligner4 i_rx_aligner4_3 ( adrv9001_aligner4 i_rx_aligner4_3 (
.clk (adc_clk_div), .clk (adc_clk_div),
@ -134,8 +130,7 @@ module adrv9001_rx_link #(
.idata (sdr_data_3), .idata (sdr_data_3),
.ivalid (adc_valid), .ivalid (adc_valid),
.strobe (sdr_data_strobe), .strobe (sdr_data_strobe),
.odata (sdr_data_3_aligned) .odata (sdr_data_3_aligned));
);
adrv9001_aligner4 i_rx_aligner4_strobe ( adrv9001_aligner4 i_rx_aligner4_strobe (
.clk (adc_clk_div), .clk (adc_clk_div),
@ -144,8 +139,7 @@ module adrv9001_rx_link #(
.ivalid (adc_valid), .ivalid (adc_valid),
.strobe (sdr_data_strobe), .strobe (sdr_data_strobe),
.ovalid (aligner4_ovalid), .ovalid (aligner4_ovalid),
.odata (sdr_data_strobe_aligned) .odata (sdr_data_strobe_aligned));
);
adrv9001_pack #( adrv9001_pack #(
.WIDTH(4) .WIDTH(4)
@ -156,8 +150,7 @@ module adrv9001_rx_link #(
.ivalid (aligner4_ovalid), .ivalid (aligner4_ovalid),
.sof (sdr_data_strobe_aligned[3]), .sof (sdr_data_strobe_aligned[3]),
.odata (sdr_data_0_packed), .odata (sdr_data_0_packed),
.ovalid (sdr_data_valid) .ovalid (sdr_data_valid));
);
adrv9001_pack #( adrv9001_pack #(
.WIDTH(4) .WIDTH(4)
@ -168,8 +161,7 @@ module adrv9001_rx_link #(
.ivalid (aligner4_ovalid), .ivalid (aligner4_ovalid),
.sof (sdr_data_strobe_aligned[3]), .sof (sdr_data_strobe_aligned[3]),
.odata (sdr_data_1_packed), .odata (sdr_data_1_packed),
.ovalid () .ovalid ());
);
adrv9001_pack #( adrv9001_pack #(
.WIDTH(4) .WIDTH(4)
@ -179,8 +171,7 @@ module adrv9001_rx_link #(
.ivalid (aligner4_ovalid), .ivalid (aligner4_ovalid),
.sof (sdr_data_strobe_aligned[3]), .sof (sdr_data_strobe_aligned[3]),
.odata (sdr_data_2_packed), .odata (sdr_data_2_packed),
.ovalid () .ovalid ());
);
adrv9001_pack #( adrv9001_pack #(
.WIDTH(4) .WIDTH(4)
@ -191,8 +182,7 @@ module adrv9001_rx_link #(
.ivalid (aligner4_ovalid), .ivalid (aligner4_ovalid),
.sof (sdr_data_strobe_aligned[3]), .sof (sdr_data_strobe_aligned[3]),
.odata (sdr_data_3_packed), .odata (sdr_data_3_packed),
.ovalid () .ovalid ());
);
adrv9001_pack #( adrv9001_pack #(
.WIDTH(4) .WIDTH(4)
@ -203,8 +193,8 @@ module adrv9001_rx_link #(
.ivalid (aligner4_ovalid), .ivalid (aligner4_ovalid),
.sof (sdr_data_strobe_aligned[3]), .sof (sdr_data_strobe_aligned[3]),
.odata (sdr_data_strobe_packed), .odata (sdr_data_strobe_packed),
.ovalid () .ovalid ());
);
assign data_0 = rx_sdr_ddr_n ? sdr_data_0_packed : adc_data_0; assign data_0 = rx_sdr_ddr_n ? sdr_data_0_packed : adc_data_0;
assign data_1 = rx_sdr_ddr_n ? sdr_data_1_packed : adc_data_1; assign data_1 = rx_sdr_ddr_n ? sdr_data_1_packed : adc_data_1;
assign data_2 = rx_sdr_ddr_n ? sdr_data_2_packed : adc_data_2; assign data_2 = rx_sdr_ddr_n ? sdr_data_2_packed : adc_data_2;
@ -241,54 +231,50 @@ module adrv9001_rx_link #(
wire [31:0] rx_data32_0_packed; wire [31:0] rx_data32_0_packed;
wire rx_data32_0_packed_valid; wire rx_data32_0_packed_valid;
adrv9001_aligner8 i_rx_aligner8_0( adrv9001_aligner8 i_rx_aligner8_0 (
.clk (adc_clk_div), .clk (adc_clk_div),
.rst (adc_rst), .rst (adc_rst),
.idata (data_0), .idata (data_0),
.ivalid (data_valid), .ivalid (data_valid),
.strobe (data_strobe), .strobe (data_strobe),
.odata (rx_data8_0_aligned), .odata (rx_data8_0_aligned),
.ovalid (rx_data8_0_aligned_valid) .ovalid (rx_data8_0_aligned_valid));
);
adrv9001_aligner8 i_rx_aligner8_1( adrv9001_aligner8 i_rx_aligner8_1 (
.clk (adc_clk_div), .clk (adc_clk_div),
.rst (adc_rst), .rst (adc_rst),
.ivalid (data_valid), .ivalid (data_valid),
.idata (data_1), .idata (data_1),
.strobe (data_strobe), .strobe (data_strobe),
.odata (rx_data8_1_aligned), .odata (rx_data8_1_aligned),
.ovalid (rx_data8_1_aligned_valid) .ovalid (rx_data8_1_aligned_valid));
);
generate if (CMOS_LVDS_N) begin : cmos_aligner8 generate if (CMOS_LVDS_N) begin : cmos_aligner8
adrv9001_aligner8 i_rx_aligner8_2( adrv9001_aligner8 i_rx_aligner8_2 (
.clk (adc_clk_div), .clk (adc_clk_div),
.rst (adc_rst), .rst (adc_rst),
.idata (data_2), .idata (data_2),
.ivalid (data_valid), .ivalid (data_valid),
.strobe (data_strobe), .strobe (data_strobe),
.odata (rx_data8_2_aligned) .odata (rx_data8_2_aligned));
);
adrv9001_aligner8 i_rx_aligner8_3( adrv9001_aligner8 i_rx_aligner8_3(
.clk (adc_clk_div), .clk (adc_clk_div),
.rst (adc_rst), .rst (adc_rst),
.idata (data_3), .idata (data_3),
.ivalid (data_valid), .ivalid (data_valid),
.strobe (data_strobe), .strobe (data_strobe),
.odata (rx_data8_3_aligned) .odata (rx_data8_3_aligned));
);
end end
endgenerate endgenerate
adrv9001_aligner8 i_rx_strobe_aligner( adrv9001_aligner8 i_rx_strobe_aligner (
.clk (adc_clk_div), .clk (adc_clk_div),
.rst (adc_rst), .rst (adc_rst),
.idata (data_strobe), .idata (data_strobe),
.ivalid (data_valid), .ivalid (data_valid),
.strobe (data_strobe), .strobe (data_strobe),
.odata (rx_data8_strobe_aligned) .odata (rx_data8_strobe_aligned));
);
adrv9001_pack #( adrv9001_pack #(
.WIDTH (8) .WIDTH (8)
@ -300,8 +286,7 @@ module adrv9001_rx_link #(
.sof (rx_data8_strobe_aligned[7]), .sof (rx_data8_strobe_aligned[7]),
.odata (rx_data16_0_packed), .odata (rx_data16_0_packed),
.ovalid (rx_data16_0_packed_valid), .ovalid (rx_data16_0_packed_valid),
.osof (rx_data16_0_packed_osof) .osof (rx_data16_0_packed_osof));
);
adrv9001_pack #( adrv9001_pack #(
.WIDTH (8) .WIDTH (8)
@ -313,8 +298,7 @@ module adrv9001_rx_link #(
.sof (rx_data8_strobe_aligned[7]), .sof (rx_data8_strobe_aligned[7]),
.odata (rx_data16_1_packed), .odata (rx_data16_1_packed),
.ovalid (rx_data16_1_paked_valid), .ovalid (rx_data16_1_paked_valid),
.osof (rx_data16_1_packed_osof) .osof (rx_data16_1_packed_osof));
);
adrv9001_pack #( adrv9001_pack #(
.WIDTH (16) .WIDTH (16)
@ -326,15 +310,14 @@ module adrv9001_rx_link #(
.sof (rx_data16_0_packed_osof), .sof (rx_data16_0_packed_osof),
.odata (rx_data32_0_packed), .odata (rx_data32_0_packed),
.ovalid (rx_data32_0_packed_valid), .ovalid (rx_data32_0_packed_valid),
.osof (rx_data32_0_packed_osof) .osof (rx_data32_0_packed_osof));
);
generate if (CMOS_LVDS_N) begin generate if (CMOS_LVDS_N) begin
assign rx_data_i = ~rx_single_lane ? {rx_data8_1_aligned,rx_data8_0_aligned} : assign rx_data_i = ~rx_single_lane ? {rx_data8_1_aligned,rx_data8_0_aligned} :
(rx_symb_op ? rx_data16_0_packed : rx_data32_0_packed[31:16]); (rx_symb_op ? rx_data16_0_packed : rx_data32_0_packed[31:16]);
assign rx_data_q = ~rx_single_lane ? {rx_data8_3_aligned,rx_data8_2_aligned} : assign rx_data_q = ~rx_single_lane ? {rx_data8_3_aligned,rx_data8_2_aligned} :
(rx_symb_op ? 'b0 : rx_data32_0_packed[15:0]); (rx_symb_op ? 'b0 : rx_data32_0_packed[15:0]);
assign rx_data_valid = ~rx_single_lane ? rx_data8_0_aligned_valid : assign rx_data_valid = ~rx_single_lane ? rx_data8_0_aligned_valid :
(rx_symb_op ? (rx_symb_8_16b ? rx_data8_0_aligned_valid : rx_data16_0_packed_valid) : rx_data32_0_packed_valid); (rx_symb_op ? (rx_symb_8_16b ? rx_data8_0_aligned_valid : rx_data16_0_packed_valid) : rx_data32_0_packed_valid);
end else begin end else begin
assign rx_data_i = ~rx_single_lane ? rx_data16_0_packed : assign rx_data_i = ~rx_single_lane ? rx_data16_0_packed :

63
library/axi_adrv9001/adrv9001_tx.v
View File

@ -103,8 +103,8 @@ module adrv9001_tx #(
.DDR_OR_SDR_N(1), .DDR_OR_SDR_N(1),
.DATA_WIDTH(NUM_LANES), .DATA_WIDTH(NUM_LANES),
.SERDES_FACTOR(8), .SERDES_FACTOR(8),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY)) .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY)
i_serdes ( ) i_serdes (
.rst (dac_rst|ssi_rst), .rst (dac_rst|ssi_rst),
.clk (dac_fast_clk), .clk (dac_fast_clk),
.div_clk (dac_clk_div), .div_clk (dac_clk_div),
@ -184,7 +184,9 @@ module adrv9001_tx #(
.O (dac_fast_clk)); .O (dac_fast_clk));
// SERDES slow clock // SERDES slow clock
BUFR #(.BUFR_DIVIDE("4")) i_dac_div_clk_rbuf ( BUFR #(
.BUFR_DIVIDE("4")
) i_dac_div_clk_rbuf (
.CLR (mssi_sync), .CLR (mssi_sync),
.CE (1'b1), .CE (1'b1),
.I (tx_dclk_in_s), .I (tx_dclk_in_s),
@ -192,25 +194,20 @@ module adrv9001_tx #(
if (USE_BUFG == 1) begin if (USE_BUFG == 1) begin
BUFG I_bufg ( BUFG I_bufg (
.I (dac_clk_div_s), .I (dac_clk_div_s),
.O (dac_clk_div) .O (dac_clk_div));
);
end else begin end else begin
assign dac_clk_div = dac_clk_div_s; assign dac_clk_div = dac_clk_div_s;
end end
xpm_cdc_async_rst xpm_cdc_async_rst #(
# ( .DEST_SYNC_FF (10), // DECIMAL; range: 2-10
.DEST_SYNC_FF (10), // DECIMAL; range: 2-10 .INIT_SYNC_FF ( 0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
.INIT_SYNC_FF ( 0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values .RST_ACTIVE_HIGH ( 1) // DECIMAL; 0=active low reset, 1=active high reset
.RST_ACTIVE_HIGH ( 1) // DECIMAL; 0=active low reset, 1=active high reset ) rst_syncro (
) .src_arst (mssi_sync),
rst_syncro .dest_clk (dac_clk_div),
( .dest_arst(ssi_rst));
.src_arst (mssi_sync ),
.dest_clk (dac_clk_div),
.dest_arst(ssi_rst )
);
end else begin end else begin
@ -222,26 +219,24 @@ module adrv9001_tx #(
end end
BUFGCE #( BUFGCE #(
.CE_TYPE ("SYNC"), .CE_TYPE ("SYNC"),
.IS_CE_INVERTED (1'b0), .IS_CE_INVERTED (1'b0),
.IS_I_INVERTED (1'b0) .IS_I_INVERTED (1'b0)
) i_dac_clk_in_gbuf ( ) i_dac_clk_in_gbuf (
.O (dac_fast_clk), .O (dac_fast_clk),
.CE (1'b1), .CE (1'b1),
.I (tx_dclk_in_s) .I (tx_dclk_in_s));
);
BUFGCE_DIV #( BUFGCE_DIV #(
.BUFGCE_DIVIDE (4), .BUFGCE_DIVIDE (4),
.IS_CE_INVERTED (1'b0), .IS_CE_INVERTED (1'b0),
.IS_CLR_INVERTED (1'b0), .IS_CLR_INVERTED (1'b0),
.IS_I_INVERTED (1'b0) .IS_I_INVERTED (1'b0)
) i_dac_div_clk_rbuf ( ) i_dac_div_clk_rbuf (
.O (dac_clk_div), .O (dac_clk_div),
.CE (1'b1), .CE (1'b1),
.CLR (mssi_sync_2d), .CLR (mssi_sync_2d),
.I (tx_dclk_in_s) .I (tx_dclk_in_s));
);
assign ssi_rst = mssi_sync_2d; assign ssi_rst = mssi_sync_2d;

32
library/axi_adrv9001/adrv9001_tx_link.v
View File

@ -58,9 +58,9 @@ module adrv9001_tx_link #(
// Config interface // Config interface
input tx_sdr_ddr_n, input tx_sdr_ddr_n,
input tx_single_lane, input tx_single_lane,
input tx_symb_op, input tx_symb_op,
input tx_symb_8_16b input tx_symb_8_16b
); );
assign tx_clk = dac_clk_div; assign tx_clk = dac_clk_div;
@ -74,7 +74,7 @@ module adrv9001_tx_link #(
wire [7:0] data8sdr_2; wire [7:0] data8sdr_2;
wire [7:0] data8sdr_3; wire [7:0] data8sdr_3;
wire [7:0] strobe8sdr; wire [7:0] strobe8sdr;
wire ld_next; wire ld_next;
reg [31:0] data32 = 32'b0; reg [31:0] data32 = 32'b0;
@ -122,15 +122,15 @@ module adrv9001_tx_link #(
data16_1 <= tx_data_q; data16_1 <= tx_data_q;
strobe16 <= {1'b1,15'b0}; strobe16 <= {1'b1,15'b0};
end else if (ld_next) begin end else if (ld_next) begin
if(tx_sdr_ddr_n) begin if(tx_sdr_ddr_n) begin
data16_0 <= {data16_0,4'b0}; data16_0 <= {data16_0,4'b0};
data16_1 <= {data16_1,4'b0}; data16_1 <= {data16_1,4'b0};
strobe16 <= {strobe16,4'b0}; strobe16 <= {strobe16,4'b0};
end else begin end else begin
data16_0 <= {data16_0,8'b0}; data16_0 <= {data16_0,8'b0};
data16_1 <= {data16_1,8'b0}; data16_1 <= {data16_1,8'b0};
strobe16 <= {strobe16,8'b0}; strobe16 <= {strobe16,8'b0};
end end
end end
end end
@ -138,7 +138,7 @@ module adrv9001_tx_link #(
assign data16sdr_0 = {data16_0[15],data16_0[15], assign data16sdr_0 = {data16_0[15],data16_0[15],
data16_0[14],data16_0[14], data16_0[14],data16_0[14],
data16_0[13],data16_0[13], data16_0[13],data16_0[13],
data16_0[12],data16_0[12]}; data16_0[12],data16_0[12]};
assign strobe16sdr = {strobe16[15],strobe16[15], assign strobe16sdr = {strobe16[15],strobe16[15],
strobe16[14],strobe16[14], strobe16[14],strobe16[14],
strobe16[13],strobe16[13], strobe16[13],strobe16[13],
@ -198,7 +198,7 @@ module adrv9001_tx_link #(
assign dac_data_3 = tx_single_lane ? 'b0 : assign dac_data_3 = tx_single_lane ? 'b0 :
(CMOS_LVDS_N ? (tx_sdr_ddr_n ? data8sdr_3 : data8_3) : (CMOS_LVDS_N ? (tx_sdr_ddr_n ? data8sdr_3 : data8_3) :
1'b0); 1'b0);
assign dac_data_strobe = tx_single_lane ? (tx_symb_op ? (tx_symb_8_16b ? (tx_sdr_ddr_n ? strobe8sdr : strobe8) : assign dac_data_strobe = tx_single_lane ? (tx_symb_op ? (tx_symb_8_16b ? (tx_sdr_ddr_n ? strobe8sdr : strobe8) :
(tx_sdr_ddr_n ? strobe16sdr : strobe16[15-:8])): (tx_sdr_ddr_n ? strobe16sdr : strobe16[15-:8])):
(tx_sdr_ddr_n ? strobe32sdr : strobe32[31-:8])) : (tx_sdr_ddr_n ? strobe32sdr : strobe32[31-:8])) :
@ -215,6 +215,6 @@ module adrv9001_tx_link #(
valid_gen <= {valid_gen[2:0],valid_gen[3]}; valid_gen <= {valid_gen[2:0],valid_gen[3]};
end end
end end
assign ld_next = (CLK_DIV_IS_FAST_CLK == 0) ? 1'b1 : valid_gen[2]; assign ld_next = (CLK_DIV_IS_FAST_CLK == 0) ? 1'b1 : valid_gen[2];
endmodule endmodule

13
library/axi_adrv9001/axi_adrv9001.v
View File

@ -286,7 +286,7 @@ module axi_adrv9001 #(
.DISABLE_RX2_SSI (DISABLE_RX2_SSI), .DISABLE_RX2_SSI (DISABLE_RX2_SSI),
.DISABLE_TX2_SSI (DISABLE_TX2_SSI), .DISABLE_TX2_SSI (DISABLE_TX2_SSI),
.USE_RX_CLK_FOR_TX (USE_RX_CLK_FOR_TX) .USE_RX_CLK_FOR_TX (USE_RX_CLK_FOR_TX)
) i_if( ) i_if (
// //
// Physical interface // Physical interface
@ -404,8 +404,7 @@ module axi_adrv9001 #(
.tx2_single_lane (tx2_single_lane), .tx2_single_lane (tx2_single_lane),
.tx2_sdr_ddr_n (tx2_sdr_ddr_n), .tx2_sdr_ddr_n (tx2_sdr_ddr_n),
.tx2_symb_op (tx2_symb_op), .tx2_symb_op (tx2_symb_op),
.tx2_symb_8_16b (tx2_symb_8_16b) .tx2_symb_8_16b (tx2_symb_8_16b));
);
// common processor control // common processor control
axi_adrv9001_core #( axi_adrv9001_core #(
@ -551,8 +550,7 @@ module axi_adrv9001 #(
.up_rreq (up_rreq_s), .up_rreq (up_rreq_s),
.up_raddr (up_raddr_s), .up_raddr (up_raddr_s),
.up_rdata (up_rdata_s), .up_rdata (up_rdata_s),
.up_rack (up_rack_s) .up_rack (up_rack_s));
);
assign adc_1_valid_i0 = adc_1_valid; assign adc_1_valid_i0 = adc_1_valid;
assign adc_1_valid_q0 = adc_1_valid; assign adc_1_valid_q0 = adc_1_valid;
@ -576,7 +574,7 @@ module axi_adrv9001 #(
// up bus interface // up bus interface
up_axi #( up_axi #(
.AXI_ADDRESS_WIDTH(15) .AXI_ADDRESS_WIDTH(15)
) i_up_axi ( ) i_up_axi (
.up_rstn (up_rstn), .up_rstn (up_rstn),
.up_clk (up_clk), .up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid), .up_axi_awvalid (s_axi_awvalid),
@ -603,8 +601,7 @@ module axi_adrv9001 #(
.up_wack (up_wack_s), .up_wack (up_wack_s),
.up_raddr (up_raddr_s[12:0]), .up_raddr (up_raddr_s[12:0]),
.up_rreq (up_rreq_s), .up_rreq (up_rreq_s),
.up_rack (up_rack_s) .up_rack (up_rack_s));
);
// Alias Rx/Tx peripherals @ 0x8000 // Alias Rx/Tx peripherals @ 0x8000
assign up_raddr_s[13] = 1'b0; assign up_raddr_s[13] = 1'b0;

42
library/axi_adrv9001/axi_adrv9001_core.v
View File

@ -57,6 +57,7 @@ module axi_adrv9001_core #(
parameter DAC_DDS_CORDIC_DW = 20, parameter DAC_DDS_CORDIC_DW = 20,
parameter DAC_DDS_CORDIC_PHASE_DW = 18 parameter DAC_DDS_CORDIC_PHASE_DW = 18
) ( ) (
// ADC interface // ADC interface
input rx1_clk, input rx1_clk,
output rx1_rst, output rx1_rst,
@ -245,8 +246,8 @@ module axi_adrv9001_core #(
sync_bits #( sync_bits #(
.NUM_OF_BITS (6), .NUM_OF_BITS (6),
.ASYNC_CLK (1)) .ASYNC_CLK (1)
i_rx1_ctrl_sync ( ) i_rx1_ctrl_sync (
.in_bits ({up_rx1_r1_mode,rx1_symb_op,rx1_symb_8_16b,rx1_sdr_ddr_n,rx1_single_lane,rx1_rst}), .in_bits ({up_rx1_r1_mode,rx1_symb_op,rx1_symb_8_16b,rx1_sdr_ddr_n,rx1_single_lane,rx1_rst}),
.out_clk (rx2_clk), .out_clk (rx2_clk),
.out_resetn (1'b1), .out_resetn (1'b1),
@ -254,8 +255,8 @@ module axi_adrv9001_core #(
sync_bits #( sync_bits #(
.NUM_OF_BITS (6), .NUM_OF_BITS (6),
.ASYNC_CLK (1)) .ASYNC_CLK (1)
i_tx1_ctrl_sync ( ) i_tx1_ctrl_sync (
.in_bits ({up_tx1_r1_mode,tx1_symb_op,tx1_symb_8_16b,tx1_sdr_ddr_n,tx1_single_lane,tx1_rst}), .in_bits ({up_tx1_r1_mode,tx1_symb_op,tx1_symb_8_16b,tx1_sdr_ddr_n,tx1_single_lane,tx1_rst}),
.out_clk (tx2_clk), .out_clk (tx2_clk),
.out_resetn (1'b1), .out_resetn (1'b1),
@ -324,8 +325,8 @@ module axi_adrv9001_core #(
sync_event #( sync_event #(
.NUM_OF_EVENTS (1), .NUM_OF_EVENTS (1),
.ASYNC_CLK (1)) .ASYNC_CLK (1)
i_rx_external_sync ( ) i_rx_external_sync (
.in_clk (ref_clk), .in_clk (ref_clk),
.in_event (adc_sync_in), .in_event (adc_sync_in),
.out_clk (rx1_clk), .out_clk (rx1_clk),
@ -352,8 +353,8 @@ module axi_adrv9001_core #(
sync_event #( sync_event #(
.NUM_OF_EVENTS (1), .NUM_OF_EVENTS (1),
.ASYNC_CLK (1)) .ASYNC_CLK (1)
i_tx_external_sync ( ) i_tx_external_sync (
.in_clk (ref_clk), .in_clk (ref_clk),
.in_event (dac_sync_in), .in_event (dac_sync_in),
.out_clk (tx1_clk), .out_clk (tx1_clk),
@ -388,8 +389,8 @@ module axi_adrv9001_core #(
.DEV_PACKAGE (DEV_PACKAGE), .DEV_PACKAGE (DEV_PACKAGE),
.DATAFORMAT_DISABLE (0), .DATAFORMAT_DISABLE (0),
.DCFILTER_DISABLE (1), .DCFILTER_DISABLE (1),
.IQCORRECTION_DISABLE (1)) .IQCORRECTION_DISABLE (1)
i_rx1 ( ) i_rx1 (
.adc_rst (rx1_rst), .adc_rst (rx1_rst),
.adc_clk (rx1_clk), .adc_clk (rx1_clk),
.adc_valid_A (rx1_data_valid & tdd_rx1_valid & sync_adc_valid), .adc_valid_A (rx1_data_valid & tdd_rx1_valid & sync_adc_valid),
@ -453,8 +454,8 @@ module axi_adrv9001_core #(
.DEV_PACKAGE (DEV_PACKAGE), .DEV_PACKAGE (DEV_PACKAGE),
.DATAFORMAT_DISABLE (0), .DATAFORMAT_DISABLE (0),
.DCFILTER_DISABLE (1), .DCFILTER_DISABLE (1),
.IQCORRECTION_DISABLE (1)) .IQCORRECTION_DISABLE (1)
i_rx2 ( ) i_rx2 (
.adc_rst (rx2_rst_loc), .adc_rst (rx2_rst_loc),
.adc_clk (rx2_clk), .adc_clk (rx2_clk),
.adc_valid_A (rx2_data_valid & tdd_rx2_valid & sync_adc_valid), .adc_valid_A (rx2_data_valid & tdd_rx2_valid & sync_adc_valid),
@ -515,8 +516,8 @@ module axi_adrv9001_core #(
.IQCORRECTION_DISABLE (1), .IQCORRECTION_DISABLE (1),
.DAC_DDS_TYPE (DAC_DDS_TYPE), .DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW)) .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW)
i_tx1 ( ) i_tx1 (
.dac_rst (tx1_rst), .dac_rst (tx1_rst),
.dac_clk (tx1_clk), .dac_clk (tx1_clk),
.dac_data_valid_A (tx1_data_valid_A), .dac_data_valid_A (tx1_data_valid_A),
@ -573,8 +574,8 @@ module axi_adrv9001_core #(
.IQCORRECTION_DISABLE (1), .IQCORRECTION_DISABLE (1),
.DAC_DDS_TYPE (DAC_DDS_TYPE), .DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW)) .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW)
i_tx2 ( ) i_tx2 (
.dac_rst (tx2_rst_loc), .dac_rst (tx2_rst_loc),
.dac_clk (tx2_clk), .dac_clk (tx2_clk),
.dac_data_valid_A (tx2_data_valid_A), .dac_data_valid_A (tx2_data_valid_A),
@ -616,8 +617,8 @@ module axi_adrv9001_core #(
up_delay_cntrl #( up_delay_cntrl #(
.DATA_WIDTH(NUM_LANES), .DATA_WIDTH(NUM_LANES),
.DRP_WIDTH(DRP_WIDTH), .DRP_WIDTH(DRP_WIDTH),
.BASE_ADDRESS(6'h02)) .BASE_ADDRESS(6'h02)
i_delay_cntrl_rx1 ( ) i_delay_cntrl_rx1 (
.delay_clk (delay_clk), .delay_clk (delay_clk),
.delay_rst (delay_rx1_rst), .delay_rst (delay_rx1_rst),
.delay_locked (delay_rx1_locked), .delay_locked (delay_rx1_locked),
@ -639,8 +640,8 @@ module axi_adrv9001_core #(
.DATA_WIDTH(NUM_LANES), .DATA_WIDTH(NUM_LANES),
.DRP_WIDTH(DRP_WIDTH), .DRP_WIDTH(DRP_WIDTH),
.DISABLE(DISABLE_RX2_SSI), .DISABLE(DISABLE_RX2_SSI),
.BASE_ADDRESS(6'h06)) .BASE_ADDRESS(6'h06)
i_delay_cntrl_rx2 ( ) i_delay_cntrl_rx2 (
.delay_clk (delay_clk), .delay_clk (delay_clk),
.delay_rst (delay_rx2_rst), .delay_rst (delay_rx2_rst),
.delay_locked (delay_rx2_locked), .delay_locked (delay_rx2_locked),
@ -723,4 +724,3 @@ module axi_adrv9001_core #(
assign tdd_sync_cntr = tdd_sync_cntr1 | tdd_sync_cntr2; assign tdd_sync_cntr = tdd_sync_cntr1 | tdd_sync_cntr2;
endmodule endmodule

143
library/axi_adrv9001/axi_adrv9001_if.v
View File

@ -267,8 +267,7 @@ module axi_adrv9001_if #(
.rx_single_lane (rx1_single_lane), .rx_single_lane (rx1_single_lane),
.rx_sdr_ddr_n (rx1_sdr_ddr_n), .rx_sdr_ddr_n (rx1_sdr_ddr_n),
.rx_symb_op (rx1_symb_op), .rx_symb_op (rx1_symb_op),
.rx_symb_8_16b (rx1_symb_8_16b) .rx_symb_8_16b (rx1_symb_8_16b));
);
generate if (DISABLE_RX2_SSI == 0) begin generate if (DISABLE_RX2_SSI == 0) begin
adrv9001_rx adrv9001_rx
@ -332,8 +331,7 @@ module axi_adrv9001_if #(
.rx_single_lane (rx2_single_lane), .rx_single_lane (rx2_single_lane),
.rx_sdr_ddr_n (rx2_sdr_ddr_n), .rx_sdr_ddr_n (rx2_sdr_ddr_n),
.rx_symb_op (rx2_symb_op), .rx_symb_op (rx2_symb_op),
.rx_symb_8_16b (rx2_symb_8_16b) .rx_symb_8_16b (rx2_symb_8_16b));
);
end else begin end else begin
assign delay_rx2_locked = 1'b1; assign delay_rx2_locked = 1'b1;
assign up_rx2_drdata = 'h0; assign up_rx2_drdata = 'h0;
@ -345,48 +343,46 @@ module axi_adrv9001_if #(
endgenerate endgenerate
adrv9001_tx #( adrv9001_tx #(
.CMOS_LVDS_N (CMOS_LVDS_N), .CMOS_LVDS_N (CMOS_LVDS_N),
.NUM_LANES (TX_NUM_LANES), .NUM_LANES (TX_NUM_LANES),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.USE_BUFG (TX_USE_BUFG), .USE_BUFG (TX_USE_BUFG),
.USE_RX_CLK_FOR_TX (USE_RX_CLK_FOR_TX) .USE_RX_CLK_FOR_TX (USE_RX_CLK_FOR_TX)
) i_tx_1_phy ( ) i_tx_1_phy (
.ref_clk (ref_clk),
.up_clk (up_clk),
.ref_clk (ref_clk), .tx_output_enable(tx_output_enable),
.up_clk (up_clk),
.tx_output_enable(tx_output_enable), .tx_dclk_out_n_NC (tx1_dclk_out_n_NC),
.tx_dclk_out_p_dclk_out (tx1_dclk_out_p_dclk_out),
.tx_dclk_in_n_NC (tx1_dclk_in_n_NC),
.tx_dclk_in_p_dclk_in (tx1_dclk_in_p_dclk_in),
.tx_idata_out_n_idata0 (tx1_idata_out_n_idata0),
.tx_idata_out_p_idata1 (tx1_idata_out_p_idata1),
.tx_qdata_out_n_qdata2 (tx1_qdata_out_n_qdata2),
.tx_qdata_out_p_qdata3 (tx1_qdata_out_p_qdata3),
.tx_strobe_out_n_NC (tx1_strobe_out_n_NC),
.tx_strobe_out_p_strobe_out (tx1_strobe_out_p_strobe_out),
.tx_dclk_out_n_NC (tx1_dclk_out_n_NC), .rx_clk_div (adc_1_clk_div),
.tx_dclk_out_p_dclk_out (tx1_dclk_out_p_dclk_out), .rx_clk (adc_1_clk),
.tx_dclk_in_n_NC (tx1_dclk_in_n_NC), .rx_ssi_rst (adc_1_ssi_rst),
.tx_dclk_in_p_dclk_in (tx1_dclk_in_p_dclk_in),
.tx_idata_out_n_idata0 (tx1_idata_out_n_idata0),
.tx_idata_out_p_idata1 (tx1_idata_out_p_idata1),
.tx_qdata_out_n_qdata2 (tx1_qdata_out_n_qdata2),
.tx_qdata_out_p_qdata3 (tx1_qdata_out_p_qdata3),
.tx_strobe_out_n_NC (tx1_strobe_out_n_NC),
.tx_strobe_out_p_strobe_out (tx1_strobe_out_p_strobe_out),
.rx_clk_div (adc_1_clk_div), .dac_rst (tx1_rst),
.rx_clk (adc_1_clk), .dac_clk_div (dac_1_clk_div),
.rx_ssi_rst (adc_1_ssi_rst),
.dac_rst (tx1_rst), .dac_data_0 (dac_1_data_0),
.dac_clk_div (dac_1_clk_div), .dac_data_1 (dac_1_data_1),
.dac_data_2 (dac_1_data_2),
.dac_data_3 (dac_1_data_3),
.dac_data_strb (dac_1_data_strobe),
.dac_data_clk (dac_1_data_clk),
.dac_data_valid (dac_1_data_valid),
.dac_data_0 (dac_1_data_0), .dac_clk_ratio (dac_clk_ratio),
.dac_data_1 (dac_1_data_1),
.dac_data_2 (dac_1_data_2),
.dac_data_3 (dac_1_data_3),
.dac_data_strb (dac_1_data_strobe),
.dac_data_clk (dac_1_data_clk),
.dac_data_valid (dac_1_data_valid),
.dac_clk_ratio (dac_clk_ratio), .mssi_sync (mssi_sync));
.mssi_sync (mssi_sync)
);
adrv9001_tx_link #( adrv9001_tx_link #(
.CMOS_LVDS_N (CMOS_LVDS_N), .CMOS_LVDS_N (CMOS_LVDS_N),
@ -409,51 +405,48 @@ module axi_adrv9001_if #(
.tx_sdr_ddr_n (tx1_sdr_ddr_n), .tx_sdr_ddr_n (tx1_sdr_ddr_n),
.tx_single_lane (tx1_single_lane), .tx_single_lane (tx1_single_lane),
.tx_symb_op (tx1_symb_op), .tx_symb_op (tx1_symb_op),
.tx_symb_8_16b (tx1_symb_8_16b) .tx_symb_8_16b (tx1_symb_8_16b));
);
generate if (DISABLE_TX2_SSI == 0) begin generate if (DISABLE_TX2_SSI == 0) begin
adrv9001_tx #( adrv9001_tx #(
.CMOS_LVDS_N (CMOS_LVDS_N), .CMOS_LVDS_N (CMOS_LVDS_N),
.NUM_LANES (TX_NUM_LANES), .NUM_LANES (TX_NUM_LANES),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.USE_BUFG (TX_USE_BUFG), .USE_BUFG (TX_USE_BUFG),
.USE_RX_CLK_FOR_TX (USE_RX_CLK_FOR_TX) .USE_RX_CLK_FOR_TX (USE_RX_CLK_FOR_TX)
) i_tx_2_phy ( ) i_tx_2_phy (
.ref_clk (ref_clk),
.up_clk (up_clk),
.ref_clk (ref_clk), .tx_output_enable(tx_output_enable),
.up_clk (up_clk),
.tx_output_enable(tx_output_enable), .tx_dclk_out_n_NC (tx2_dclk_out_n_NC),
.tx_dclk_out_p_dclk_out (tx2_dclk_out_p_dclk_out),
.tx_dclk_in_n_NC (tx2_dclk_in_n_NC),
.tx_dclk_in_p_dclk_in (tx2_dclk_in_p_dclk_in),
.tx_idata_out_n_idata0 (tx2_idata_out_n_idata0),
.tx_idata_out_p_idata1 (tx2_idata_out_p_idata1),
.tx_qdata_out_n_qdata2 (tx2_qdata_out_n_qdata2),
.tx_qdata_out_p_qdata3 (tx2_qdata_out_p_qdata3),
.tx_strobe_out_n_NC (tx2_strobe_out_n_NC),
.tx_strobe_out_p_strobe_out (tx2_strobe_out_p_strobe_out),
.tx_dclk_out_n_NC (tx2_dclk_out_n_NC), .rx_clk_div (adc_2_clk_div),
.tx_dclk_out_p_dclk_out (tx2_dclk_out_p_dclk_out), .rx_clk (adc_2_clk),
.tx_dclk_in_n_NC (tx2_dclk_in_n_NC), .rx_ssi_rst (adc_2_ssi_rst),
.tx_dclk_in_p_dclk_in (tx2_dclk_in_p_dclk_in),
.tx_idata_out_n_idata0 (tx2_idata_out_n_idata0),
.tx_idata_out_p_idata1 (tx2_idata_out_p_idata1),
.tx_qdata_out_n_qdata2 (tx2_qdata_out_n_qdata2),
.tx_qdata_out_p_qdata3 (tx2_qdata_out_p_qdata3),
.tx_strobe_out_n_NC (tx2_strobe_out_n_NC),
.tx_strobe_out_p_strobe_out (tx2_strobe_out_p_strobe_out),
.rx_clk_div (adc_2_clk_div), .dac_rst (tx2_rst),
.rx_clk (adc_2_clk), .dac_clk_div (dac_2_clk_div),
.rx_ssi_rst (adc_2_ssi_rst),
.dac_rst (tx2_rst), .dac_data_0 (dac_2_data_0),
.dac_clk_div (dac_2_clk_div), .dac_data_1 (dac_2_data_1),
.dac_data_2 (dac_2_data_2),
.dac_data_3 (dac_2_data_3),
.dac_data_strb (dac_2_data_strobe),
.dac_data_clk (dac_2_data_clk),
.dac_data_valid (dac_2_data_valid),
.dac_data_0 (dac_2_data_0), .mssi_sync (mssi_sync));
.dac_data_1 (dac_2_data_1),
.dac_data_2 (dac_2_data_2),
.dac_data_3 (dac_2_data_3),
.dac_data_strb (dac_2_data_strobe),
.dac_data_clk (dac_2_data_clk),
.dac_data_valid (dac_2_data_valid),
.mssi_sync (mssi_sync)
);
adrv9001_tx_link #( adrv9001_tx_link #(
.CMOS_LVDS_N (CMOS_LVDS_N), .CMOS_LVDS_N (CMOS_LVDS_N),
@ -476,8 +469,7 @@ module axi_adrv9001_if #(
.tx_sdr_ddr_n (tx2_sdr_ddr_n), .tx_sdr_ddr_n (tx2_sdr_ddr_n),
.tx_single_lane (tx2_single_lane), .tx_single_lane (tx2_single_lane),
.tx_symb_op (tx2_symb_op), .tx_symb_op (tx2_symb_op),
.tx_symb_8_16b (tx2_symb_8_16b) .tx_symb_8_16b (tx2_symb_8_16b));
);
end else begin end else begin
assign tx2_clk = 1'b0; assign tx2_clk = 1'b0;
assign tx2_dclk_out_n_NC = 1'b0; assign tx2_dclk_out_n_NC = 1'b0;
@ -492,4 +484,3 @@ module axi_adrv9001_if #(
endgenerate endgenerate
endmodule endmodule

586
library/axi_adrv9001/axi_adrv9001_rx.v
View File

@ -50,6 +50,7 @@ module axi_adrv9001_rx #(
parameter DCFILTER_DISABLE = 0, parameter DCFILTER_DISABLE = 0,
parameter IQCORRECTION_DISABLE = 1 parameter IQCORRECTION_DISABLE = 1
) ( ) (
// adc interface // adc interface
output adc_rst, output adc_rst,
input adc_clk, input adc_clk,
@ -108,303 +109,300 @@ module axi_adrv9001_rx #(
output reg up_rack output reg up_rack
); );
generate generate
if (ENABLED == 0) begin : core_disabled if (ENABLED == 0) begin : core_disabled
assign adc_rst = 1'b0; assign adc_rst = 1'b0;
assign adc_single_lane = 1'b0; assign adc_single_lane = 1'b0;
assign adc_sdr_ddr_n = 1'b0; assign adc_sdr_ddr_n = 1'b0;
assign adc_symb_op = 1'b0; assign adc_symb_op = 1'b0;
assign adc_symb_8_16b = 1'b0; assign adc_symb_8_16b = 1'b0;
assign up_adc_r1_mode = 1'b0; assign up_adc_r1_mode = 1'b0;
assign adc_valid = 1'b0; assign adc_valid = 1'b0;
assign adc_enable_i0 = 1'b0; assign adc_enable_i0 = 1'b0;
assign adc_data_i0 = 16'b0; assign adc_data_i0 = 16'b0;
assign adc_enable_q0 = 1'b0; assign adc_enable_q0 = 1'b0;
assign adc_data_q0 = 16'b0; assign adc_data_q0 = 16'b0;
assign adc_enable_i1 = 1'b0; assign adc_enable_i1 = 1'b0;
assign adc_data_i1 = 16'b0; assign adc_data_i1 = 16'b0;
assign adc_enable_q1 = 1'b0; assign adc_enable_q1 = 1'b0;
assign adc_data_q1 = 16'b0; assign adc_data_q1 = 16'b0;
always @(*) begin always @(*) begin
up_wack = 1'b0; up_wack = 1'b0;
up_rdata = 32'b0; up_rdata = 32'b0;
up_rack = 1'b0; up_rack = 1'b0;
end
end else begin : core_enabled
// configuration settings
localparam CONFIG = (CMOS_LVDS_N * 128) +
(MODE_R1 * 16) +
(DATAFORMAT_DISABLE * 4) +
(DCFILTER_DISABLE * 2) +
(IQCORRECTION_DISABLE * 1);
// internal registers
reg up_status_pn_err = 'd0;
reg up_status_pn_oos = 'd0;
reg up_status_or = 'd0;
// internal signals
wire [ 15:0] adc_data_iq_i0_s;
wire [ 15:0] adc_data_iq_q0_s;
wire [ 15:0] adc_data_iq_i1_s;
wire [ 15:0] adc_data_iq_q1_s;
wire [ 4:0] adc_num_lanes;
wire [ 3:0] up_adc_pn_err_s;
wire [ 3:0] up_adc_pn_oos_s;
wire [ 3:0] up_adc_or_s;
wire [ 4:0] up_wack_s;
wire [ 4:0] up_rack_s;
wire [ 31:0] up_rdata_s[0:4];
wire adc_valid_out_i0;
wire adc_valid_out_i1;
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_status_pn_err <= 'd0;
up_status_pn_oos <= 'd0;
up_status_or <= 'd0;
up_wack <= 'd0;
up_rack <= 'd0;
up_rdata <= 'd0;
end else begin
up_status_pn_err <= up_adc_r1_mode ? | up_adc_pn_err_s[1:0] : | up_adc_pn_err_s[3:0];
up_status_pn_oos <= up_adc_r1_mode ? | up_adc_pn_oos_s[1:0] : | up_adc_pn_oos_s[3:0];
up_status_or <= | up_adc_or_s;
up_wack <= | up_wack_s;
up_rack <= | up_rack_s;
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] |
up_rdata_s[3] | up_rdata_s[4];
end end
end else begin : core_enabled
// configuration settings
localparam CONFIG = (CMOS_LVDS_N * 128) +
(MODE_R1 * 16) +
(DATAFORMAT_DISABLE * 4) +
(DCFILTER_DISABLE * 2) +
(IQCORRECTION_DISABLE * 1);
// internal registers
reg up_status_pn_err = 'd0;
reg up_status_pn_oos = 'd0;
reg up_status_or = 'd0;
// internal signals
wire [ 15:0] adc_data_iq_i0_s;
wire [ 15:0] adc_data_iq_q0_s;
wire [ 15:0] adc_data_iq_i1_s;
wire [ 15:0] adc_data_iq_q1_s;
wire [ 4:0] adc_num_lanes;
wire [ 3:0] up_adc_pn_err_s;
wire [ 3:0] up_adc_pn_oos_s;
wire [ 3:0] up_adc_or_s;
wire [ 4:0] up_wack_s;
wire [ 4:0] up_rack_s;
wire [ 31:0] up_rdata_s[0:4];
wire adc_valid_out_i0;
wire adc_valid_out_i1;
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_status_pn_err <= 'd0;
up_status_pn_oos <= 'd0;
up_status_or <= 'd0;
up_wack <= 'd0;
up_rack <= 'd0;
up_rdata <= 'd0;
end else begin
up_status_pn_err <= up_adc_r1_mode ? | up_adc_pn_err_s[1:0] : | up_adc_pn_err_s[3:0];
up_status_pn_oos <= up_adc_r1_mode ? | up_adc_pn_oos_s[1:0] : | up_adc_pn_oos_s[3:0];
up_status_or <= | up_adc_or_s;
up_wack <= | up_wack_s;
up_rack <= | up_rack_s;
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] |
up_rdata_s[3] | up_rdata_s[4];
end
end
// channel width is 32 bits
assign adc_valid = adc_enable_i0 ? adc_valid_out_i0 : adc_valid_out_i1;
// channel 0 (i)
axi_adrv9001_rx_channel #(
.Q_OR_I_N (0),
.COMMON_ID (CHANNEL_BASE_ADDR),
.DISABLE (0),
.DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
.DCFILTER_DISABLE (DCFILTER_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
.DATA_WIDTH (16)
) i_rx_channel_0 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_valid_in (adc_valid_A),
.adc_data_in (adc_data_i_A[15:0]),
.adc_valid_out (adc_valid_out_i0),
.adc_data_out (adc_data_i0),
.adc_data_iq_in (adc_data_iq_q0_s),
.adc_data_iq_out (adc_data_iq_i0_s),
.adc_enable (adc_enable_i0),
.dac_valid_in (dac_data_valid_A),
.dac_data_in (dac_data_i_A),
.up_adc_pn_err (up_adc_pn_err_s[0]),
.up_adc_pn_oos (up_adc_pn_oos_s[0]),
.up_adc_or (up_adc_or_s[0]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[0]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[0]),
.up_rack (up_rack_s[0]));
// channel 1 (q)
axi_adrv9001_rx_channel #(
.Q_OR_I_N (1),
.COMMON_ID (CHANNEL_BASE_ADDR),
.CHANNEL_ID (1),
.DISABLE (0),
.DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
.DCFILTER_DISABLE (DCFILTER_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
.DATA_WIDTH (16)
) i_rx_channel_1 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_valid_in (adc_valid_A),
.adc_data_in (adc_data_q_A[15:0]),
.adc_valid_out (),
.adc_data_out (adc_data_q0),
.adc_data_iq_in (adc_data_iq_i0_s),
.adc_data_iq_out (adc_data_iq_q0_s),
.adc_enable (adc_enable_q0),
.dac_valid_in (dac_data_valid_A),
.dac_data_in (dac_data_q_A),
.up_adc_pn_err (up_adc_pn_err_s[1]),
.up_adc_pn_oos (up_adc_pn_oos_s[1]),
.up_adc_or (up_adc_or_s[1]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[1]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[1]),
.up_rack (up_rack_s[1]));
// channel 2 (i)
axi_adrv9001_rx_channel #(
.Q_OR_I_N (0),
.COMMON_ID (CHANNEL_BASE_ADDR),
.CHANNEL_ID (2),
.DISABLE (MODE_R1),
.DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
.DCFILTER_DISABLE (DCFILTER_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
.DATA_WIDTH (16)
) i_rx_channel_2 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_valid_in (adc_valid_B),
.adc_data_in (adc_data_i_B[15:0]),
.adc_valid_out (adc_valid_out_i1),
.adc_data_out (adc_data_i1),
.adc_data_iq_in (adc_data_iq_q1_s),
.adc_data_iq_out (adc_data_iq_i1_s),
.adc_enable (adc_enable_i1),
.dac_valid_in (dac_data_valid_B),
.dac_data_in (dac_data_i_B),
.up_adc_pn_err (up_adc_pn_err_s[2]),
.up_adc_pn_oos (up_adc_pn_oos_s[2]),
.up_adc_or (up_adc_or_s[2]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[2]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[2]),
.up_rack (up_rack_s[2]));
// channel 3 (q)
axi_adrv9001_rx_channel #(
.Q_OR_I_N (1),
.COMMON_ID (CHANNEL_BASE_ADDR),
.CHANNEL_ID (3),
.DISABLE (MODE_R1),
.DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
.DCFILTER_DISABLE (DCFILTER_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
.DATA_WIDTH (16)
) i_rx_channel_3 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_valid_in (adc_valid_B),
.adc_data_in (adc_data_q_B[15:0]),
.adc_valid_out (),
.adc_data_out (adc_data_q1),
.adc_data_iq_in (adc_data_iq_i1_s),
.adc_data_iq_out (adc_data_iq_q1_s),
.adc_enable (adc_enable_q1),
.dac_valid_in (dac_data_valid_B),
.dac_data_in (dac_data_q_B),
.up_adc_pn_err (up_adc_pn_err_s[3]),
.up_adc_pn_oos (up_adc_pn_oos_s[3]),
.up_adc_or (up_adc_or_s[3]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[3]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[3]),
.up_rack (up_rack_s[3]));
// common processor control
up_adc_common #(
.ID (ID),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
.COMMON_ID (COMMON_BASE_ADDR),
.CONFIG(CONFIG),
.DRP_DISABLE(1),
.USERPORTS_DISABLE(1),
.GPIO_DISABLE(1),
.START_CODE_DISABLE(1)
) i_up_adc_common (
.mmcm_rst (),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_r1_mode (),
.adc_ddr_edgesel (),
.adc_pin_mode (),
.adc_status (1'b1),
.adc_sync_status (1'd0),
.adc_status_ovf (adc_dovf),
.adc_clk_ratio (adc_clk_ratio),
.adc_start_code (),
.adc_sref_sync (),
.adc_sync (adc_sync),
.adc_num_lanes (adc_num_lanes),
.adc_sdr_ddr_n (adc_sdr_ddr_n),
.adc_symb_op (adc_symb_op),
.adc_symb_8_16b (adc_symb_8_16b),
.up_pps_rcounter(32'h0),
.up_pps_status(1'b0),
.up_pps_irq_mask(),
.up_adc_r1_mode (up_adc_r1_mode),
.up_adc_ce (),
.up_status_pn_err (up_status_pn_err),
.up_status_pn_oos (up_status_pn_oos),
.up_status_or (up_status_or),
.up_drp_sel (),
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (32'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.up_usr_chanmax_out (),
.up_usr_chanmax_in (8'd3),
.up_adc_gpio_in (32'd0),
.up_adc_gpio_out (),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[4]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[4]),
.up_rack (up_rack_s[4]));
assign adc_single_lane = adc_num_lanes[0];
end end
endgenerate
// channel width is 32 bits
assign adc_valid = adc_enable_i0 ? adc_valid_out_i0 : adc_valid_out_i1;
// channel 0 (i)
axi_adrv9001_rx_channel #(
.Q_OR_I_N (0),
.COMMON_ID (CHANNEL_BASE_ADDR),
.DISABLE (0),
.DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
.DCFILTER_DISABLE (DCFILTER_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
.DATA_WIDTH (16))
i_rx_channel_0 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_valid_in (adc_valid_A),
.adc_data_in (adc_data_i_A[15:0]),
.adc_valid_out (adc_valid_out_i0),
.adc_data_out (adc_data_i0),
.adc_data_iq_in (adc_data_iq_q0_s),
.adc_data_iq_out (adc_data_iq_i0_s),
.adc_enable (adc_enable_i0),
.dac_valid_in (dac_data_valid_A),
.dac_data_in (dac_data_i_A),
.up_adc_pn_err (up_adc_pn_err_s[0]),
.up_adc_pn_oos (up_adc_pn_oos_s[0]),
.up_adc_or (up_adc_or_s[0]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[0]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[0]),
.up_rack (up_rack_s[0]));
// channel 1 (q)
axi_adrv9001_rx_channel #(
.Q_OR_I_N (1),
.COMMON_ID (CHANNEL_BASE_ADDR),
.CHANNEL_ID (1),
.DISABLE (0),
.DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
.DCFILTER_DISABLE (DCFILTER_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
.DATA_WIDTH (16))
i_rx_channel_1 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_valid_in (adc_valid_A),
.adc_data_in (adc_data_q_A[15:0]),
.adc_valid_out (),
.adc_data_out (adc_data_q0),
.adc_data_iq_in (adc_data_iq_i0_s),
.adc_data_iq_out (adc_data_iq_q0_s),
.adc_enable (adc_enable_q0),
.dac_valid_in (dac_data_valid_A),
.dac_data_in (dac_data_q_A),
.up_adc_pn_err (up_adc_pn_err_s[1]),
.up_adc_pn_oos (up_adc_pn_oos_s[1]),
.up_adc_or (up_adc_or_s[1]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[1]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[1]),
.up_rack (up_rack_s[1]));
// channel 2 (i)
axi_adrv9001_rx_channel #(
.Q_OR_I_N (0),
.COMMON_ID (CHANNEL_BASE_ADDR),
.CHANNEL_ID (2),
.DISABLE (MODE_R1),
.DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
.DCFILTER_DISABLE (DCFILTER_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
.DATA_WIDTH (16))
i_rx_channel_2 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_valid_in (adc_valid_B),
.adc_data_in (adc_data_i_B[15:0]),
.adc_valid_out (adc_valid_out_i1),
.adc_data_out (adc_data_i1),
.adc_data_iq_in (adc_data_iq_q1_s),
.adc_data_iq_out (adc_data_iq_i1_s),
.adc_enable (adc_enable_i1),
.dac_valid_in (dac_data_valid_B),
.dac_data_in (dac_data_i_B),
.up_adc_pn_err (up_adc_pn_err_s[2]),
.up_adc_pn_oos (up_adc_pn_oos_s[2]),
.up_adc_or (up_adc_or_s[2]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[2]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[2]),
.up_rack (up_rack_s[2]));
// channel 3 (q)
axi_adrv9001_rx_channel #(
.Q_OR_I_N (1),
.COMMON_ID (CHANNEL_BASE_ADDR),
.CHANNEL_ID (3),
.DISABLE (MODE_R1),
.DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
.DCFILTER_DISABLE (DCFILTER_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
.DATA_WIDTH (16))
i_rx_channel_3 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_valid_in (adc_valid_B),
.adc_data_in (adc_data_q_B[15:0]),
.adc_valid_out (),
.adc_data_out (adc_data_q1),
.adc_data_iq_in (adc_data_iq_i1_s),
.adc_data_iq_out (adc_data_iq_q1_s),
.adc_enable (adc_enable_q1),
.dac_valid_in (dac_data_valid_B),
.dac_data_in (dac_data_q_B),
.up_adc_pn_err (up_adc_pn_err_s[3]),
.up_adc_pn_oos (up_adc_pn_oos_s[3]),
.up_adc_or (up_adc_or_s[3]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[3]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[3]),
.up_rack (up_rack_s[3]));
// common processor control
up_adc_common #(
.ID (ID),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
.COMMON_ID (COMMON_BASE_ADDR),
.CONFIG(CONFIG),
.DRP_DISABLE(1),
.USERPORTS_DISABLE(1),
.GPIO_DISABLE(1),
.START_CODE_DISABLE(1))
i_up_adc_common (
.mmcm_rst (),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_r1_mode (),
.adc_ddr_edgesel (),
.adc_pin_mode (),
.adc_status (1'b1),
.adc_sync_status (1'd0),
.adc_status_ovf (adc_dovf),
.adc_clk_ratio (adc_clk_ratio),
.adc_start_code (),
.adc_sref_sync (),
.adc_sync (adc_sync),
.adc_num_lanes (adc_num_lanes),
.adc_sdr_ddr_n (adc_sdr_ddr_n),
.adc_symb_op (adc_symb_op),
.adc_symb_8_16b (adc_symb_8_16b),
.up_pps_rcounter(32'h0),
.up_pps_status(1'b0),
.up_pps_irq_mask(),
.up_adc_r1_mode (up_adc_r1_mode),
.up_adc_ce (),
.up_status_pn_err (up_status_pn_err),
.up_status_pn_oos (up_status_pn_oos),
.up_status_or (up_status_or),
.up_drp_sel (),
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (32'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.up_usr_chanmax_out (),
.up_usr_chanmax_in (8'd3),
.up_adc_gpio_in (32'd0),
.up_adc_gpio_out (),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[4]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[4]),
.up_rack (up_rack_s[4]));
assign adc_single_lane = adc_num_lanes[0];
end
endgenerate
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

34
library/axi_adrv9001/axi_adrv9001_rx_channel.v
View File

@ -45,6 +45,7 @@ module axi_adrv9001_rx_channel #(
parameter IQCORRECTION_DISABLE = 0, parameter IQCORRECTION_DISABLE = 0,
parameter DATA_WIDTH = 16 parameter DATA_WIDTH = 16
) ( ) (
// adc interface // adc interface
input adc_clk, input adc_clk,
input adc_rst, input adc_rst,
@ -145,7 +146,9 @@ module axi_adrv9001_rx_channel #(
assign adc_dfmt_valid_s[n] = adc_valid_in_s; assign adc_dfmt_valid_s[n] = adc_valid_in_s;
assign adc_dfmt_data_s[((16*n)+15):(16*n)] = adc_data_in_s[((16*n)+15):(16*n)]; assign adc_dfmt_data_s[((16*n)+15):(16*n)] = adc_data_in_s[((16*n)+15):(16*n)];
end else begin end else begin
ad_datafmt #(.DATA_WIDTH (16)) i_ad_datafmt ( ad_datafmt #(
.DATA_WIDTH (16)
) i_ad_datafmt (
.clk (adc_clk), .clk (adc_clk),
.valid (adc_valid_in_s), .valid (adc_valid_in_s),
.data (adc_data_in_s[((16*n)+15):(16*n)]), .data (adc_data_in_s[((16*n)+15):(16*n)]),
@ -182,7 +185,9 @@ module axi_adrv9001_rx_channel #(
assign adc_valid_out_s[n] = adc_dcfilter_valid_s[n]; assign adc_valid_out_s[n] = adc_dcfilter_valid_s[n];
assign adc_data_out[((16*n)+15):(16*n)] = adc_dcfilter_data_s[((16*n)+15):(16*n)]; assign adc_data_out[((16*n)+15):(16*n)] = adc_dcfilter_data_s[((16*n)+15):(16*n)];
end else begin end else begin
ad_iqcor #(.Q_OR_I_N (Q_OR_I_N)) i_ad_iqcor ( ad_iqcor #(
.Q_OR_I_N (Q_OR_I_N)
) i_ad_iqcor (
.clk (adc_clk), .clk (adc_clk),
.valid (adc_dcfilter_valid_s[n]), .valid (adc_dcfilter_valid_s[n]),
.data_in (adc_dcfilter_data_s[((16*n)+15):(16*n)]), .data_in (adc_dcfilter_data_s[((16*n)+15):(16*n)]),
@ -211,31 +216,29 @@ module axi_adrv9001_rx_channel #(
.POL_MASK ( (1<<7) | (1<<6) ), .POL_MASK ( (1<<7) | (1<<6) ),
.POL_W (7), .POL_W (7),
.DW (16) .DW (16)
) PN7_gen ( ) PN7_gen (
.clk (adc_clk), .clk (adc_clk),
.reset (adc_rst), .reset (adc_rst),
.clk_en (adc_valid_in_s), .clk_en (adc_valid_in_s),
.pn_init (adc_pn_oos_s), .pn_init (adc_pn_oos_s),
.pn_data_in (adc_data_in_s), .pn_data_in (adc_data_in_s),
.pn_data_out (pn7_data) .pn_data_out (pn7_data));
);
// PN15 x^15 + x^14 + 1 // PN15 x^15 + x^14 + 1
ad_pngen #( ad_pngen #(
.POL_MASK ( (1<<15) | (1<<14) ), .POL_MASK ( (1<<15) | (1<<14) ),
.POL_W (15), .POL_W (15),
.DW (16) .DW (16)
) PN15_gen ( ) PN15_gen (
.clk (adc_clk), .clk (adc_clk),
.reset (adc_rst), .reset (adc_rst),
.clk_en (adc_valid_in_s), .clk_en (adc_valid_in_s),
.pn_init (adc_pn_oos_s), .pn_init (adc_pn_oos_s),
.pn_data_in (adc_data_in_s), .pn_data_in (adc_data_in_s),
.pn_data_out (pn15_data) .pn_data_out (pn15_data));
);
// reference nibble ramp and full ramp generator // reference nibble ramp and full ramp generator
// next value is always the currently received value incremented // next value is always the currently received value incremented
always @(posedge adc_clk) begin always @(posedge adc_clk) begin
if (adc_valid_in_s) begin if (adc_valid_in_s) begin
full_ramp_counter <= adc_data_in_s + 16'd1; full_ramp_counter <= adc_data_in_s + 16'd1;
@ -246,7 +249,7 @@ module axi_adrv9001_rx_channel #(
adc_pnseq_sel == 4'd5 ? pn15_data : adc_pnseq_sel == 4'd5 ? pn15_data :
adc_pnseq_sel == 4'd10 ? {4{full_ramp_counter[3:0]}} : adc_pnseq_sel == 4'd10 ? {4{full_ramp_counter[3:0]}} :
adc_pnseq_sel == 4'd11 ? full_ramp_counter : 'h0; adc_pnseq_sel == 4'd11 ? full_ramp_counter : 'h0;
assign valid_seq_sel = adc_pnseq_sel == 4'd4 || adc_pnseq_sel == 4'd5 || assign valid_seq_sel = adc_pnseq_sel == 4'd4 || adc_pnseq_sel == 4'd5 ||
adc_pnseq_sel == 4'd10 || adc_pnseq_sel == 4'd11; adc_pnseq_sel == 4'd10 || adc_pnseq_sel == 4'd11;
ad_pnmon #( ad_pnmon #(
@ -260,8 +263,7 @@ module axi_adrv9001_rx_channel #(
.adc_data_pn (adc_data_pn), .adc_data_pn (adc_data_pn),
.adc_pattern_has_zero (adc_pnseq_sel[3]), .adc_pattern_has_zero (adc_pnseq_sel[3]),
.adc_pn_oos (adc_pn_oos_s), .adc_pn_oos (adc_pn_oos_s),
.adc_pn_err (adc_pn_err_s) .adc_pn_err (adc_pn_err_s));
);
up_adc_channel #( up_adc_channel #(
.COMMON_ID (COMMON_ID), .COMMON_ID (COMMON_ID),
@ -269,8 +271,8 @@ module axi_adrv9001_rx_channel #(
.USERPORTS_DISABLE(1), .USERPORTS_DISABLE(1),
.DATAFORMAT_DISABLE(DATAFORMAT_DISABLE), .DATAFORMAT_DISABLE(DATAFORMAT_DISABLE),
.DCFILTER_DISABLE(DCFILTER_DISABLE), .DCFILTER_DISABLE(DCFILTER_DISABLE),
.IQCORRECTION_DISABLE(IQCORRECTION_DISABLE)) .IQCORRECTION_DISABLE(IQCORRECTION_DISABLE)
i_up_adc_channel ( ) i_up_adc_channel (
.adc_clk (adc_clk), .adc_clk (adc_clk),
.adc_rst (adc_rst), .adc_rst (adc_rst),
.adc_enable (adc_enable), .adc_enable (adc_enable),
@ -319,7 +321,3 @@ module axi_adrv9001_rx_channel #(
endgenerate endgenerate
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

7
library/axi_adrv9001/axi_adrv9001_tdd.v
View File

@ -79,7 +79,8 @@ module axi_adrv9001_tdd #(
input up_rreq, input up_rreq,
input [13:0] up_raddr, input [13:0] up_raddr,
output [31:0] up_rdata, output [31:0] up_rdata,
output up_rack); output up_rack
);
generate generate
if (ENABLED == 1) begin if (ENABLED == 1) begin
@ -215,8 +216,8 @@ module axi_adrv9001_tdd #(
ad_tdd_control #( ad_tdd_control #(
.TX_DATA_PATH_DELAY(), .TX_DATA_PATH_DELAY(),
.CONTROL_PATH_DELAY()) .CONTROL_PATH_DELAY()
i_tdd_control( ) i_tdd_control(
.clk(clk), .clk(clk),
.rst(rst), .rst(rst),
.tdd_enable(tdd_enable_s), .tdd_enable(tdd_enable_s),

581
library/axi_adrv9001/axi_adrv9001_tx.v
View File

@ -55,6 +55,7 @@ module axi_adrv9001_tx #(
parameter DAC_DDS_CORDIC_DW = 20, parameter DAC_DDS_CORDIC_DW = 20,
parameter DAC_DDS_CORDIC_PHASE_DW = 18 parameter DAC_DDS_CORDIC_PHASE_DW = 18
) ( ) (
// dac interface // dac interface
output dac_rst, output dac_rst,
input dac_clk, input dac_clk,
@ -108,321 +109,319 @@ module axi_adrv9001_tx #(
output reg [ 31:0] up_rdata, output reg [ 31:0] up_rdata,
output reg up_rack output reg up_rack
); );
generate
if (ENABLED == 0) begin : core_disabled
assign dac_rst = 1'b0; generate
assign dac_data_valid_A = 1'b0; if (ENABLED == 0) begin : core_disabled
assign dac_data_i_A = 16'b0;
assign dac_data_q_A = 16'b0;
assign dac_data_valid_B = 1'b0;
assign dac_data_i_B = 16'b0;
assign dac_data_q_B = 16'b0;
assign dac_single_lane = 1'b0;
assign dac_sdr_ddr_n = 1'b0;
assign dac_symb_op = 1'b0;
assign dac_symb_8_16b = 1'b0;
assign up_dac_r1_mode = 1'b0;
assign dac_sync_out = 1'b0;
assign dac_valid = 1'b0;
assign dac_enable_i0 = 1'b0;
assign dac_enable_q0 = 1'b0;
assign dac_enable_i1 = 1'b0;
assign dac_enable_q1 = 1'b0;
always @(*) begin assign dac_rst = 1'b0;
up_wack = 1'b0; assign dac_data_valid_A = 1'b0;
up_rdata = 32'b0; assign dac_data_i_A = 16'b0;
up_rack = 1'b0; assign dac_data_q_A = 16'b0;
end assign dac_data_valid_B = 1'b0;
assign dac_data_i_B = 16'b0;
assign dac_data_q_B = 16'b0;
assign dac_single_lane = 1'b0;
assign dac_sdr_ddr_n = 1'b0;
assign dac_symb_op = 1'b0;
assign dac_symb_8_16b = 1'b0;
assign up_dac_r1_mode = 1'b0;
assign dac_sync_out = 1'b0;
assign dac_valid = 1'b0;
assign dac_enable_i0 = 1'b0;
assign dac_enable_q0 = 1'b0;
assign dac_enable_i1 = 1'b0;
assign dac_enable_q1 = 1'b0;
end else begin : core_enabled always @(*) begin
up_wack = 1'b0;
up_rdata = 32'b0;
up_rack = 1'b0;
end
// configuration settings end else begin : core_enabled
localparam CONFIG = (USE_RX_CLK_FOR_TX * 1024) + // configuration settings
(CMOS_LVDS_N * 128) +
(MODE_R1 * 16) +
(DDS_DISABLE * 64) +
(IQCORRECTION_DISABLE * 1);
// internal registers localparam CONFIG = (USE_RX_CLK_FOR_TX * 1024) +
(CMOS_LVDS_N * 128) +
(MODE_R1 * 16) +
(DDS_DISABLE * 64) +
(IQCORRECTION_DISABLE * 1);
reg dac_data_sync = 'd0; // internal registers
reg [15:0] dac_rate_cnt = 'd0;
reg dac_valid_int = 'd0;
// internal signals reg dac_data_sync = 'd0;
reg [15:0] dac_rate_cnt = 'd0;
reg dac_valid_int = 'd0;
wire dac_data_sync_s; // internal signals
wire [ 15:0] dac_data_iq_i0_s;
wire [ 15:0] dac_data_iq_q0_s;
wire [ 15:0] dac_data_iq_i1_s;
wire [ 15:0] dac_data_iq_q1_s;
wire dac_dds_format_s;
wire [ 15:0] dac_datarate_s;
wire [4:0] dac_num_lanes;
wire [ 4:0] up_wack_s;
wire [ 4:0] up_rack_s;
wire [ 31:0] up_rdata_s[0:4];
// master/slave wire dac_data_sync_s;
wire [ 15:0] dac_data_iq_i0_s;
wire [ 15:0] dac_data_iq_q0_s;
wire [ 15:0] dac_data_iq_i1_s;
wire [ 15:0] dac_data_iq_q1_s;
wire dac_dds_format_s;
wire [ 15:0] dac_datarate_s;
wire [4:0] dac_num_lanes;
wire [ 4:0] up_wack_s;
wire [ 4:0] up_rack_s;
wire [ 31:0] up_rdata_s[0:4];
assign dac_data_sync_s = (EXT_SYNC == 0) ? dac_sync_out : dac_sync_in; // master/slave
always @(posedge dac_clk) begin assign dac_data_sync_s = (EXT_SYNC == 0) ? dac_sync_out : dac_sync_in;
dac_data_sync <= dac_data_sync_s;
end
// rate counters and data sync signals always @(posedge dac_clk) begin
dac_data_sync <= dac_data_sync_s;
end
always @(posedge dac_clk) begin // rate counters and data sync signals
if (dac_rst == 1'b1) begin
dac_rate_cnt <= 16'b0; always @(posedge dac_clk) begin
end else begin if (dac_rst == 1'b1) begin
if ((dac_data_sync == 1'b1) || (dac_rate_cnt == 16'd0)) begin dac_rate_cnt <= 16'b0;
dac_rate_cnt <= dac_datarate_s;
end else begin end else begin
dac_rate_cnt <= dac_rate_cnt - 1'b1; if ((dac_data_sync == 1'b1) || (dac_rate_cnt == 16'd0)) begin
dac_rate_cnt <= dac_datarate_s;
end else begin
dac_rate_cnt <= dac_rate_cnt - 1'b1;
end
end end
end end
end
// dma interface // dma interface
assign dac_data_valid_A = dac_valid_int; assign dac_data_valid_A = dac_valid_int;
assign dac_data_valid_B = dac_valid_int; assign dac_data_valid_B = dac_valid_int;
always @(posedge dac_clk) begin always @(posedge dac_clk) begin
if (dac_rst == 1'b1) begin if (dac_rst == 1'b1) begin
dac_valid_int <= 1'b0; dac_valid_int <= 1'b0;
end else begin end else begin
dac_valid_int <= (dac_rate_cnt == 16'd0) ? tdd_tx_valid : 1'b0; dac_valid_int <= (dac_rate_cnt == 16'd0) ? tdd_tx_valid : 1'b0;
end
end end
end
// processor read interface // processor read interface
always @(negedge up_rstn or posedge up_clk) begin always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin if (up_rstn == 0) begin
up_wack <= 'd0; up_wack <= 'd0;
up_rack <= 'd0; up_rack <= 'd0;
up_rdata <= 'd0; up_rdata <= 'd0;
end else begin end else begin
up_wack <= | up_wack_s; up_wack <= | up_wack_s;
up_rack <= | up_rack_s; up_rack <= | up_rack_s;
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] |
up_rdata_s[3] | up_rdata_s[4]; up_rdata_s[3] | up_rdata_s[4];
end
end end
// dac channel 0
axi_adrv9001_tx_channel #(
.CHANNEL_ID (0),
.COMMON_ID (CHANNEL_BASE_ADDR),
.Q_OR_I_N (0),
.DISABLE (DISABLE),
.DDS_DISABLE (DDS_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
.DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW)
) i_tx_channel_0 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_data_in_req (dac_valid),
.dac_data_in (dac_data_i0),
.dac_data_out_req (dac_data_valid_A),
.dac_data_out (dac_data_i_A[15:0]),
.dac_data_iq_in (dac_data_iq_q0_s),
.dac_data_iq_out (dac_data_iq_i0_s),
.dac_enable (dac_enable_i0),
.dac_data_sync (dac_data_sync),
.dac_dds_format (dac_dds_format_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[0]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[0]),
.up_rack (up_rack_s[0]));
// dac channel 1
axi_adrv9001_tx_channel #(
.CHANNEL_ID (1),
.COMMON_ID (CHANNEL_BASE_ADDR),
.Q_OR_I_N (1),
.DISABLE (DISABLE),
.DDS_DISABLE (DDS_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
.DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW)
) i_tx_channel_1 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_data_in_req (),
.dac_data_in (dac_data_q0),
.dac_data_out_req (dac_data_valid_A),
.dac_data_out (dac_data_q_A[15:0]),
.dac_data_iq_in (dac_data_iq_i0_s),
.dac_data_iq_out (dac_data_iq_q0_s),
.dac_enable (dac_enable_q0),
.dac_data_sync (dac_data_sync),
.dac_dds_format (dac_dds_format_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[1]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[1]),
.up_rack (up_rack_s[1]));
// dac channel 2 - disabled in 1R1T mode
axi_adrv9001_tx_channel #(
.CHANNEL_ID (2),
.COMMON_ID (CHANNEL_BASE_ADDR),
.Q_OR_I_N (0),
.DISABLE (MODE_R1),
.DDS_DISABLE (DDS_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
.DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW)
) i_tx_channel_2 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_data_in_req (),
.dac_data_in (dac_data_i1),
.dac_data_out_req (dac_data_valid_B),
.dac_data_out (dac_data_i_B[15:0]),
.dac_data_iq_in (dac_data_iq_q1_s),
.dac_data_iq_out (dac_data_iq_i1_s),
.dac_enable (dac_enable_i1),
.dac_data_sync (dac_data_sync),
.dac_dds_format (dac_dds_format_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[2]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[2]),
.up_rack (up_rack_s[2]));
// dac channel 3 - disabled in 1R1T mode
axi_adrv9001_tx_channel #(
.CHANNEL_ID (3),
.COMMON_ID (CHANNEL_BASE_ADDR),
.Q_OR_I_N (1),
.DISABLE (MODE_R1),
.DDS_DISABLE (DDS_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
.DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW)
) i_tx_channel_3 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_data_in_req (),
.dac_data_in (dac_data_q1),
.dac_data_out_req (dac_data_valid_B),
.dac_data_out (dac_data_q_B[15:0]),
.dac_data_iq_in (dac_data_iq_i1_s),
.dac_data_iq_out (dac_data_iq_q1_s),
.dac_enable (dac_enable_q1),
.dac_data_sync (dac_data_sync),
.dac_dds_format (dac_dds_format_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[3]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[3]),
.up_rack (up_rack_s[3]));
// dac common processor interface
up_dac_common #(
.ID (ID),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
.CONFIG(CONFIG),
.CLK_EDGE_SEL(0),
.COMMON_ID(COMMON_BASE_ADDR),
.DRP_DISABLE(1),
.USERPORTS_DISABLE(1),
.GPIO_DISABLE(1)
) i_up_dac_common (
.mmcm_rst (),
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_num_lanes (dac_num_lanes),
.dac_sdr_ddr_n (dac_sdr_ddr_n),
.dac_symb_op (dac_symb_op),
.dac_symb_8_16b (dac_symb_8_16b),
.dac_sync (dac_sync_out),
.dac_ext_sync_arm (dac_ext_sync_arm),
.dac_frame (),
.dac_clksel (),
.dac_par_type (),
.dac_par_enb (),
.dac_r1_mode (),
.up_dac_r1_mode (up_dac_r1_mode),
.dac_datafmt (dac_dds_format_s),
.dac_datarate (dac_datarate_s),
.dac_status (1'b1),
.dac_status_unf (dac_dunf),
.dac_clk_ratio (dac_clk_ratio),
.up_dac_ce (),
.up_pps_rcounter(32'h0),
.up_pps_status(1'b0),
.up_pps_irq_mask(),
.up_drp_sel (),
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (32'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.up_usr_chanmax (),
.dac_usr_chanmax (8'd3),
.up_dac_gpio_in (32'd0),
.up_dac_gpio_out (),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[4]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[4]),
.up_rack (up_rack_s[4]));
assign dac_single_lane = dac_num_lanes[0];
end end
endgenerate
// dac channel 0
axi_adrv9001_tx_channel #(
.CHANNEL_ID (0),
.COMMON_ID (CHANNEL_BASE_ADDR),
.Q_OR_I_N (0),
.DISABLE (DISABLE),
.DDS_DISABLE (DDS_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
.DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
i_tx_channel_0 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_data_in_req (dac_valid),
.dac_data_in (dac_data_i0),
.dac_data_out_req (dac_data_valid_A),
.dac_data_out (dac_data_i_A[15:0]),
.dac_data_iq_in (dac_data_iq_q0_s),
.dac_data_iq_out (dac_data_iq_i0_s),
.dac_enable (dac_enable_i0),
.dac_data_sync (dac_data_sync),
.dac_dds_format (dac_dds_format_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[0]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[0]),
.up_rack (up_rack_s[0]));
// dac channel 1
axi_adrv9001_tx_channel #(
.CHANNEL_ID (1),
.COMMON_ID (CHANNEL_BASE_ADDR),
.Q_OR_I_N (1),
.DISABLE (DISABLE),
.DDS_DISABLE (DDS_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
.DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
i_tx_channel_1 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_data_in_req (),
.dac_data_in (dac_data_q0),
.dac_data_out_req (dac_data_valid_A),
.dac_data_out (dac_data_q_A[15:0]),
.dac_data_iq_in (dac_data_iq_i0_s),
.dac_data_iq_out (dac_data_iq_q0_s),
.dac_enable (dac_enable_q0),
.dac_data_sync (dac_data_sync),
.dac_dds_format (dac_dds_format_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[1]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[1]),
.up_rack (up_rack_s[1]));
// dac channel 2 - disabled in 1R1T mode
axi_adrv9001_tx_channel #(
.CHANNEL_ID (2),
.COMMON_ID (CHANNEL_BASE_ADDR),
.Q_OR_I_N (0),
.DISABLE (MODE_R1),
.DDS_DISABLE (DDS_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
.DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
i_tx_channel_2 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_data_in_req (),
.dac_data_in (dac_data_i1),
.dac_data_out_req (dac_data_valid_B),
.dac_data_out (dac_data_i_B[15:0]),
.dac_data_iq_in (dac_data_iq_q1_s),
.dac_data_iq_out (dac_data_iq_i1_s),
.dac_enable (dac_enable_i1),
.dac_data_sync (dac_data_sync),
.dac_dds_format (dac_dds_format_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[2]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[2]),
.up_rack (up_rack_s[2]));
// dac channel 3 - disabled in 1R1T mode
axi_adrv9001_tx_channel #(
.CHANNEL_ID (3),
.COMMON_ID (CHANNEL_BASE_ADDR),
.Q_OR_I_N (1),
.DISABLE (MODE_R1),
.DDS_DISABLE (DDS_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
.DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
i_tx_channel_3 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_data_in_req (),
.dac_data_in (dac_data_q1),
.dac_data_out_req (dac_data_valid_B),
.dac_data_out (dac_data_q_B[15:0]),
.dac_data_iq_in (dac_data_iq_i1_s),
.dac_data_iq_out (dac_data_iq_q1_s),
.dac_enable (dac_enable_q1),
.dac_data_sync (dac_data_sync),
.dac_dds_format (dac_dds_format_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[3]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[3]),
.up_rack (up_rack_s[3]));
// dac common processor interface
up_dac_common #(
.ID (ID),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
.CONFIG(CONFIG),
.CLK_EDGE_SEL(0),
.COMMON_ID(COMMON_BASE_ADDR),
.DRP_DISABLE(1),
.USERPORTS_DISABLE(1),
.GPIO_DISABLE(1))
i_up_dac_common (
.mmcm_rst (),
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_num_lanes (dac_num_lanes),
.dac_sdr_ddr_n (dac_sdr_ddr_n),
.dac_symb_op (dac_symb_op),
.dac_symb_8_16b (dac_symb_8_16b),
.dac_sync (dac_sync_out),
.dac_ext_sync_arm (dac_ext_sync_arm),
.dac_frame (),
.dac_clksel (),
.dac_par_type (),
.dac_par_enb (),
.dac_r1_mode (),
.up_dac_r1_mode (up_dac_r1_mode),
.dac_datafmt (dac_dds_format_s),
.dac_datarate (dac_datarate_s),
.dac_status (1'b1),
.dac_status_unf (dac_dunf),
.dac_clk_ratio (dac_clk_ratio),
.up_dac_ce (),
.up_pps_rcounter(32'h0),
.up_pps_status(1'b0),
.up_pps_irq_mask(),
.up_drp_sel (),
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (32'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.up_usr_chanmax (),
.dac_usr_chanmax (8'd3),
.up_dac_gpio_in (32'd0),
.up_dac_gpio_out (),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[4]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[4]),
.up_rack (up_rack_s[4]));
assign dac_single_lane = dac_num_lanes[0];
end
endgenerate
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

23
library/axi_adrv9001/axi_adrv9001_tx_channel.v
View File

@ -46,6 +46,7 @@ module axi_adrv9001_tx_channel #(
parameter DAC_DDS_CORDIC_DW = 20, parameter DAC_DDS_CORDIC_DW = 20,
parameter DAC_DDS_CORDIC_PHASE_DW = 18 parameter DAC_DDS_CORDIC_PHASE_DW = 18
) ( ) (
// dac interface // dac interface
input dac_clk, input dac_clk,
input dac_rst, input dac_rst,
@ -105,7 +106,9 @@ module axi_adrv9001_tx_channel #(
assign dac_data_in_req = dac_data_out_req; assign dac_data_in_req = dac_data_out_req;
end else begin end else begin
ad_iqcor #(.Q_OR_I_N (Q_OR_I_N)) i_ad_iqcor_0 ( ad_iqcor #(
.Q_OR_I_N (Q_OR_I_N)
) i_ad_iqcor_0 (
.clk (dac_clk), .clk (dac_clk),
.valid (dac_data_out_req), .valid (dac_data_out_req),
.data_in (dac_data_iq_out[15:0]), .data_in (dac_data_iq_out[15:0]),
@ -128,26 +131,24 @@ module axi_adrv9001_tx_channel #(
.POL_MASK ((1<<7) | (1<<6)), .POL_MASK ((1<<7) | (1<<6)),
.POL_W (7), .POL_W (7),
.DW (16) .DW (16)
) PN7_gen ( ) PN7_gen (
.clk (dac_clk), .clk (dac_clk),
.reset (dac_rst), .reset (dac_rst),
.clk_en (dac_data_in_req), .clk_en (dac_data_in_req),
.pn_init (1'b0), .pn_init (1'b0),
.pn_data_out (pn7_data) .pn_data_out (pn7_data));
);
// PN15 x^15 + x^14 + 1 // PN15 x^15 + x^14 + 1
ad_pngen #( ad_pngen #(
.POL_MASK ((1<<15) | (1<<14)), .POL_MASK ((1<<15) | (1<<14)),
.POL_W (15), .POL_W (15),
.DW (16) .DW (16)
) PN15_gen ( ) PN15_gen (
.clk (dac_clk), .clk (dac_clk),
.reset (dac_rst), .reset (dac_rst),
.clk_en (dac_data_in_req), .clk_en (dac_data_in_req),
.pn_init (1'b0), .pn_init (1'b0),
.pn_data_out (pn15_data) .pn_data_out (pn15_data));
);
// full ramp generator // full ramp generator
always @(posedge dac_clk) begin always @(posedge dac_clk) begin
@ -183,8 +184,8 @@ module axi_adrv9001_tx_channel #(
.DDS_TYPE (DAC_DDS_TYPE), .DDS_TYPE (DAC_DDS_TYPE),
.CORDIC_DW (DAC_DDS_CORDIC_DW), .CORDIC_DW (DAC_DDS_CORDIC_DW),
.CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), .CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.CLK_RATIO (1)) .CLK_RATIO (1)
i_dds ( ) i_dds (
.clk (dac_clk), .clk (dac_clk),
.dac_dds_format (dac_dds_format), .dac_dds_format (dac_dds_format),
.dac_data_sync (dac_data_sync), .dac_data_sync (dac_data_sync),
@ -204,8 +205,8 @@ module axi_adrv9001_tx_channel #(
.CHANNEL_ID (CHANNEL_ID), .CHANNEL_ID (CHANNEL_ID),
.DDS_DISABLE(DDS_DISABLE), .DDS_DISABLE(DDS_DISABLE),
.USERPORTS_DISABLE(1), .USERPORTS_DISABLE(1),
.IQCORRECTION_DISABLE(IQCORRECTION_DISABLE)) .IQCORRECTION_DISABLE(IQCORRECTION_DISABLE)
i_up_dac_channel ( ) i_up_dac_channel (
.dac_clk (dac_clk), .dac_clk (dac_clk),
.dac_rst (dac_rst), .dac_rst (dac_rst),
.dac_dds_scale_1 (dac_dds_scale_1_s), .dac_dds_scale_1 (dac_dds_scale_1_s),

1
library/axi_adrv9001/intel/adrv9001_rx.v
View File

@ -44,6 +44,7 @@ module adrv9001_rx #(
parameter USE_BUFG = 0, parameter USE_BUFG = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group" parameter IO_DELAY_GROUP = "dev_if_delay_group"
) ( ) (
// device interface // device interface
input rx_dclk_in_n_NC, input rx_dclk_in_n_NC,
input rx_dclk_in_p_dclk_in, input rx_dclk_in_p_dclk_in,

14
library/axi_clkgen/axi_clkgen.v
View File

@ -52,7 +52,8 @@ module axi_clkgen #(
parameter real CLK0_DIV = 6.000, parameter real CLK0_DIV = 6.000,
parameter real CLK0_PHASE = 0.000, parameter real CLK0_PHASE = 0.000,
parameter integer CLK1_DIV = 6, parameter integer CLK1_DIV = 6,
parameter real CLK1_PHASE = 0.000) ( parameter real CLK1_PHASE = 0.000
) (
// clocks // clocks
@ -83,8 +84,8 @@ module axi_clkgen #(
output [ 1:0] s_axi_rresp, output [ 1:0] s_axi_rresp,
input s_axi_rready, input s_axi_rready,
input [ 2:0] s_axi_awprot, input [ 2:0] s_axi_awprot,
input [ 2:0] s_axi_arprot); input [ 2:0] s_axi_arprot
);
// reset and clocks // reset and clocks
@ -199,8 +200,8 @@ module axi_clkgen #(
.MMCM_CLK0_DIV (CLK0_DIV), .MMCM_CLK0_DIV (CLK0_DIV),
.MMCM_CLK0_PHASE (CLK0_PHASE), .MMCM_CLK0_PHASE (CLK0_PHASE),
.MMCM_CLK1_DIV (CLK1_DIV), .MMCM_CLK1_DIV (CLK1_DIV),
.MMCM_CLK1_PHASE (CLK1_PHASE)) .MMCM_CLK1_PHASE (CLK1_PHASE)
i_mmcm_drp ( ) i_mmcm_drp (
.clk (clk), .clk (clk),
.clk2 (clk2), .clk2 (clk2),
.clk_sel(clk_sel_s), .clk_sel(clk_sel_s),
@ -219,6 +220,3 @@ module axi_clkgen #(
.up_drp_locked (up_drp_locked_s)); .up_drp_locked (up_drp_locked_s));
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

12
library/axi_clock_monitor/axi_clock_monitor.v
View File

@ -38,7 +38,8 @@
module axi_clock_monitor #( module axi_clock_monitor #(
parameter ID = 0, parameter ID = 0,
parameter NUM_OF_CLOCKS = 1) ( parameter NUM_OF_CLOCKS = 1
) (
// clocks // clocks
@ -83,7 +84,8 @@ module axi_clock_monitor #(
output s_axi_rvalid, output s_axi_rvalid,
output [31:0] s_axi_rdata, output [31:0] s_axi_rdata,
output [ 1:0] s_axi_rresp, output [ 1:0] s_axi_rresp,
input s_axi_rready); input s_axi_rready
);
// local parameters // local parameters
@ -226,8 +228,7 @@ module axi_clock_monitor #(
.up_clk(up_clk), .up_clk(up_clk),
.up_d_count(clk_mon_count[n]), .up_d_count(clk_mon_count[n]),
.d_rst(1'b0), .d_rst(1'b0),
.d_clk(clock[n]) .d_clk(clock[n]));
);
end end
for (n = NUM_OF_CLOCKS; n < 16; n = n + 1) begin: clk_mon_z for (n = NUM_OF_CLOCKS; n < 16; n = n + 1) begin: clk_mon_z
assign clk_mon_count[n] = 21'd0; assign clk_mon_count[n] = 21'd0;
@ -266,6 +267,3 @@ module axi_clock_monitor #(
.up_rack (up_rack_o_s)); .up_rack (up_rack_o_s));
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

49
library/axi_dac_interpolate/axi_dac_interpolate.v
View File

@ -37,8 +37,8 @@
module axi_dac_interpolate #( module axi_dac_interpolate #(
parameter CORRECTION_DISABLE = 1) ( parameter CORRECTION_DISABLE = 1
) (
input dac_clk, input dac_clk,
input dac_rst, input dac_rst,
@ -87,8 +87,8 @@ module axi_dac_interpolate #(
output s_axi_rvalid, output s_axi_rvalid,
output [31:0] s_axi_rdata, output [31:0] s_axi_rdata,
output [ 1:0] s_axi_rresp, output [ 1:0] s_axi_rresp,
input s_axi_rready); input s_axi_rready
);
reg [ 1:0] trigger_i_m1; reg [ 1:0] trigger_i_m1;
reg [ 1:0] trigger_i_m2; reg [ 1:0] trigger_i_m2;
@ -187,23 +187,23 @@ module axi_dac_interpolate #(
// sync // sync
always @(posedge dac_clk) begin always @(posedge dac_clk) begin
trigger_i_m1 <= trigger_i; trigger_i_m1 <= trigger_i;
trigger_i_m2 <= trigger_i_m1; trigger_i_m2 <= trigger_i_m1;
trigger_i_m3 <= trigger_i_m2; trigger_i_m3 <= trigger_i_m2;
trigger_adc_m1 <= trigger_adc; trigger_adc_m1 <= trigger_adc;
trigger_adc_m2 <= trigger_adc_m1; trigger_adc_m2 <= trigger_adc_m1;
trigger_la_m1 <= trigger_la; trigger_la_m1 <= trigger_la;
trigger_la_m2 <= trigger_la_m1; trigger_la_m2 <= trigger_la_m1;
end end
always @(posedge dac_clk) begin always @(posedge dac_clk) begin
any_edge_trigger <= (trigger_i_m3 ^ trigger_i_m2) & any_edge; any_edge_trigger <= (trigger_i_m3 ^ trigger_i_m2) & any_edge;
rise_edge_trigger <= (~trigger_i_m3 & trigger_i_m2) & rise_edge; rise_edge_trigger <= (~trigger_i_m3 & trigger_i_m2) & rise_edge;
fall_edge_trigger <= (trigger_i_m3 & ~trigger_i_m2) & fall_edge; fall_edge_trigger <= (trigger_i_m3 & ~trigger_i_m2) & fall_edge;
high_level_trigger <= trigger_i_m3 & high_level; high_level_trigger <= trigger_i_m3 & high_level;
low_level_trigger <= ~trigger_i_m3 & low_level; low_level_trigger <= ~trigger_i_m3 & low_level;
end end
assign hold_last_sample = lsample_hold_config[0]; assign hold_last_sample = lsample_hold_config[0];
@ -212,8 +212,8 @@ module axi_dac_interpolate #(
assign underflow = underflow_a | underflow_b; assign underflow = underflow_a | underflow_b;
axi_dac_interpolate_filter #( axi_dac_interpolate_filter #(
.CORRECTION_DISABLE(CORRECTION_DISABLE)) .CORRECTION_DISABLE (CORRECTION_DISABLE)
i_filter_a ( ) i_filter_a (
.dac_clk (dac_clk), .dac_clk (dac_clk),
.dac_rst (dac_rst), .dac_rst (dac_rst),
@ -238,12 +238,11 @@ module axi_dac_interpolate #(
.dma_valid (dma_valid_a), .dma_valid (dma_valid_a),
.dma_valid_adjacent (dma_valid_b), .dma_valid_adjacent (dma_valid_b),
.dac_correction_enable(dac_correction_enable_a), .dac_correction_enable(dac_correction_enable_a),
.dac_correction_coefficient(dac_correction_coefficient_a) .dac_correction_coefficient(dac_correction_coefficient_a));
);
axi_dac_interpolate_filter #( axi_dac_interpolate_filter #(
.CORRECTION_DISABLE(CORRECTION_DISABLE)) .CORRECTION_DISABLE(CORRECTION_DISABLE)
i_filter_b ( ) i_filter_b (
.dac_clk (dac_clk), .dac_clk (dac_clk),
.dac_rst (dac_rst), .dac_rst (dac_rst),
@ -268,8 +267,7 @@ module axi_dac_interpolate #(
.dma_valid (dma_valid_b), .dma_valid (dma_valid_b),
.dma_valid_adjacent (dma_valid_a), .dma_valid_adjacent (dma_valid_a),
.dac_correction_enable(dac_correction_enable_b), .dac_correction_enable(dac_correction_enable_b),
.dac_correction_coefficient(dac_correction_coefficient_b) .dac_correction_coefficient(dac_correction_coefficient_b));
);
axi_dac_interpolate_reg axi_dac_interpolate_reg_inst ( axi_dac_interpolate_reg axi_dac_interpolate_reg_inst (
@ -332,6 +330,3 @@ module axi_dac_interpolate #(
.up_rack (up_rack)); .up_rack (up_rack));
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

12
library/axi_dac_interpolate/axi_dac_interpolate_filter.v
View File

@ -35,11 +35,10 @@
`timescale 1ns/100ps `timescale 1ns/100ps
module axi_dac_interpolate_filter #( module axi_dac_interpolate_filter #(
parameter CORRECTION_DISABLE = 1) ( parameter CORRECTION_DISABLE = 1
) (
input dac_clk, input dac_clk,
input dac_rst, input dac_rst,
@ -96,10 +95,11 @@ module axi_dac_interpolate_filter #(
wire dma_valid_ch_sync; wire dma_valid_ch_sync;
wire dma_valid_ch; wire dma_valid_ch;
ad_iqcor #(.Q_OR_I_N (0), ad_iqcor #(
.Q_OR_I_N (0),
.DISABLE(CORRECTION_DISABLE), .DISABLE(CORRECTION_DISABLE),
.SCALE_ONLY(1)) .SCALE_ONLY(1)
i_ad_iqcor ( ) i_ad_iqcor (
.clk (dac_clk), .clk (dac_clk),
.valid (dac_valid), .valid (dac_valid),
.data_in (dac_data), .data_in (dac_data),

11
library/axi_dac_interpolate/axi_dac_interpolate_reg.v
View File

@ -62,7 +62,8 @@ module axi_dac_interpolate_reg(
input up_rreq, input up_rreq,
input [ 4:0] up_raddr, input [ 4:0] up_raddr,
output reg [31:0] up_rdata, output reg [31:0] up_rdata,
output reg up_rack); output reg up_rack
);
// internal registers // internal registers
@ -167,7 +168,9 @@ module axi_dac_interpolate_reg(
end end
end end
up_xfer_cntrl #(.DATA_WIDTH(128)) i_xfer_cntrl ( up_xfer_cntrl #(
.DATA_WIDTH(128)
) i_xfer_cntrl (
.up_rstn (up_rstn), .up_rstn (up_rstn),
.up_clk (up_clk), .up_clk (up_clk),
.up_data_cntrl ({ up_config[1], // 1 .up_data_cntrl ({ up_config[1], // 1
@ -198,7 +201,3 @@ module axi_dac_interpolate_reg(
dac_filter_mask_a})); // 3 dac_filter_mask_a})); // 3
endmodule endmodule
// ***************************************************************************
// ***************************************************************************

32
library/axi_dac_interpolate/cic_interp.v
View File

@ -37,26 +37,16 @@
`timescale 1 ns / 1 ns `timescale 1 ns / 1 ns
module cic_interp module cic_interp (
( input clk,
clk, input clk_enable,
clk_enable, input reset,
reset, input signed [30:0] filter_in, //sfix31_En30
filter_in, input [15:0] rate, //ufix16
rate, input load_rate,
load_rate, output signed [109:0] filter_out, //sfix110_En30
filter_out, output ce_out
ce_out );
);
input clk;
input clk_enable;
input reset;
input signed [30:0] filter_in; //sfix31_En30
input [15:0] rate; //ufix16
input load_rate;
output signed [109:0] filter_out; //sfix110_En30
output ce_out;
//////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////
//Module Architecture: cic_interp //Module Architecture: cic_interp
@ -611,4 +601,4 @@ module cic_interp
// Assignment Statements // Assignment Statements
assign ce_out = phase_0; assign ce_out = phase_0;
assign filter_out = output_register; assign filter_out = output_register;
endmodule // cic_interp endmodule

27
library/axi_dac_interpolate/fir_interp.v
View File

@ -40,22 +40,14 @@
`timescale 1 ns / 1 ns `timescale 1 ns / 1 ns
module fir_interp module fir_interp (
( input clk,
clk, input clk_enable,
clk_enable, input reset,
reset, input signed [15:0] filter_in, //sfix16_En15
filter_in, output signed [35:0] filter_out, //sfix36_En30
filter_out, output ce_out
ce_out );
);
input clk;
input clk_enable;
input reset;
input signed [15:0] filter_in; //sfix16_En15
output signed [35:0] filter_out; //sfix36_En30
output ce_out;
//////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////
//Module Architecture: fir_interp //Module Architecture: fir_interp
@ -214,7 +206,6 @@ module fir_interp
end end
end // Delay_Pipeline_process end // Delay_Pipeline_process
assign product_mux = (cur_count == 2'b00) ? coeffphase1_12 : assign product_mux = (cur_count == 2'b00) ? coeffphase1_12 :
coeffphase2_12; coeffphase2_12;
assign product = delay_pipeline[11] * product_mux; assign product = delay_pipeline[11] * product_mux;
@ -387,4 +378,4 @@ module fir_interp
// Assignment Statements // Assignment Statements
assign ce_out = phase_1; assign ce_out = phase_1;
assign filter_out = output_register; assign filter_out = output_register;
endmodule // fir_interp endmodule

178
library/axi_dmac/address_generator.v
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@ -43,8 +43,8 @@ module address_generator #(
parameter BEATS_PER_BURST_WIDTH = 4, parameter BEATS_PER_BURST_WIDTH = 4,
parameter BYTES_PER_BEAT_WIDTH = $clog2(DMA_DATA_WIDTH/8), parameter BYTES_PER_BEAT_WIDTH = $clog2(DMA_DATA_WIDTH/8),
parameter LENGTH_WIDTH = 8, parameter LENGTH_WIDTH = 8,
parameter CACHE_COHERENT = 0)( parameter CACHE_COHERENT = 0
) (
input clk, input clk,
input resetn, input resetn,
@ -74,114 +74,114 @@ module address_generator #(
output [ 3:0] cache output [ 3:0] cache
); );
localparam MAX_BEATS_PER_BURST = {1'b1,{BEATS_PER_BURST_WIDTH{1'b0}}}; localparam MAX_BEATS_PER_BURST = {1'b1,{BEATS_PER_BURST_WIDTH{1'b0}}};
localparam MAX_LENGTH = {BEATS_PER_BURST_WIDTH{1'b1}}; localparam MAX_LENGTH = {BEATS_PER_BURST_WIDTH{1'b1}};
`include "inc_id.vh" `include "inc_id.vh"
assign burst = 2'b01; assign burst = 2'b01;
assign prot = 3'b000; assign prot = 3'b000;
// If CACHE_COHERENT is set, signal downstream that this transaction must be // If CACHE_COHERENT is set, signal downstream that this transaction must be
// looked up in cache. Otherwise default to "normal non-cachable bufferable". // looked up in cache. Otherwise default to "normal non-cachable bufferable".
assign cache = CACHE_COHERENT ? 4'b1110 : 4'b0011; assign cache = CACHE_COHERENT ? 4'b1110 : 4'b0011;
assign size = DMA_DATA_WIDTH == 1024 ? 3'b111 : assign size = DMA_DATA_WIDTH == 1024 ? 3'b111 :
DMA_DATA_WIDTH == 512 ? 3'b110 : DMA_DATA_WIDTH == 512 ? 3'b110 :
DMA_DATA_WIDTH == 256 ? 3'b101 : DMA_DATA_WIDTH == 256 ? 3'b101 :
DMA_DATA_WIDTH == 128 ? 3'b100 : DMA_DATA_WIDTH == 128 ? 3'b100 :
DMA_DATA_WIDTH == 64 ? 3'b011 : DMA_DATA_WIDTH == 64 ? 3'b011 :
DMA_DATA_WIDTH == 32 ? 3'b010 : DMA_DATA_WIDTH == 32 ? 3'b010 :
DMA_DATA_WIDTH == 16 ? 3'b001 : 3'b000; DMA_DATA_WIDTH == 16 ? 3'b001 : 3'b000;
reg [LENGTH_WIDTH-1:0] length = 'h0; reg [LENGTH_WIDTH-1:0] length = 'h0;
reg [DMA_ADDR_WIDTH-BYTES_PER_BEAT_WIDTH-1:0] address = 'h00; reg [DMA_ADDR_WIDTH-BYTES_PER_BEAT_WIDTH-1:0] address = 'h00;
reg [BEATS_PER_BURST_WIDTH-1:0] last_burst_len = 'h00; reg [BEATS_PER_BURST_WIDTH-1:0] last_burst_len = 'h00;
assign addr = {address, {BYTES_PER_BEAT_WIDTH{1'b0}}}; assign addr = {address, {BYTES_PER_BEAT_WIDTH{1'b0}}};
assign len = length; assign len = length;
reg addr_valid_d1; reg addr_valid_d1;
reg last = 1'b0; reg last = 1'b0;
// If we already asserted addr_valid we have to wait until it is accepted before // If we already asserted addr_valid we have to wait until it is accepted before
// we can disable the address generator. // we can disable the address generator.
always @(posedge clk) begin always @(posedge clk) begin
if (resetn == 1'b0) begin if (resetn == 1'b0) begin
enabled <= 1'b0; enabled <= 1'b0;
end else if (enable == 1'b1) begin end else if (enable == 1'b1) begin
enabled <= 1'b1; enabled <= 1'b1;
end else if (addr_valid == 1'b0) begin end else if (addr_valid == 1'b0) begin
enabled <= 1'b0; enabled <= 1'b0;
end
end
always @(posedge clk) begin
if (bl_valid == 1'b1 && bl_ready == 1'b1) begin
last_burst_len <= measured_last_burst_length;
end
end
always @(posedge clk) begin
if (addr_valid == 1'b0) begin
last <= eot;
if (eot == 1'b1) begin
length <= last_burst_len;
end else begin
length <= MAX_LENGTH;
end end
end end
end
always @(posedge clk) begin always @(posedge clk) begin
if (req_ready == 1'b1) begin if (bl_valid == 1'b1 && bl_ready == 1'b1) begin
address <= req_address; last_burst_len <= measured_last_burst_length;
end else if (addr_valid == 1'b1 && addr_ready == 1'b1) begin end
address <= address + MAX_BEATS_PER_BURST;
end end
end
always @(posedge clk) begin always @(posedge clk) begin
if (resetn == 1'b0) begin if (addr_valid == 1'b0) begin
bl_ready <= 1'b1; last <= eot;
end else begin if (eot == 1'b1) begin
if (bl_ready == 1'b1) begin length <= last_burst_len;
bl_ready <= ~bl_valid; end else begin
end else if (addr_valid == 1'b0 && eot == 1'b1) begin length <= MAX_LENGTH;
// assert bl_ready only when the addr_valid asserts in the next cycle
if (id != request_id && enable == 1'b1) begin
bl_ready <= 1'b1;
end end
end end
end end
end
always @(posedge clk) begin always @(posedge clk) begin
if (resetn == 1'b0) begin
req_ready <= 1'b1;
addr_valid <= 1'b0;
end else begin
if (req_ready == 1'b1) begin if (req_ready == 1'b1) begin
req_ready <= ~req_valid; address <= req_address;
end else if (addr_valid == 1'b1 && addr_ready == 1'b1) begin end else if (addr_valid == 1'b1 && addr_ready == 1'b1) begin
addr_valid <= 1'b0; address <= address + MAX_BEATS_PER_BURST;
req_ready <= last; end
end else if (id != request_id && enable == 1'b1) begin end
// if eot wait until the last_burst_len gets synced over
if (eot == 1'b0 || (eot == 1'b1 && bl_ready == 1'b0)) begin always @(posedge clk) begin
addr_valid <= 1'b1; if (resetn == 1'b0) begin
bl_ready <= 1'b1;
end else begin
if (bl_ready == 1'b1) begin
bl_ready <= ~bl_valid;
end else if (addr_valid == 1'b0 && eot == 1'b1) begin
// assert bl_ready only when the addr_valid asserts in the next cycle
if (id != request_id && enable == 1'b1) begin
bl_ready <= 1'b1;
end
end end
end end
end end
end
always @(posedge clk) begin always @(posedge clk) begin
addr_valid_d1 <= addr_valid; if (resetn == 1'b0) begin
end req_ready <= 1'b1;
addr_valid <= 1'b0;
always @(posedge clk) begin end else begin
if (resetn == 1'b0) begin if (req_ready == 1'b1) begin
id <= 'h0; req_ready <= ~req_valid;
end else if (addr_valid == 1'b1 && addr_valid_d1 == 1'b0) begin end else if (addr_valid == 1'b1 && addr_ready == 1'b1) begin
id <= inc_id(id); addr_valid <= 1'b0;
req_ready <= last;
end else if (id != request_id && enable == 1'b1) begin
// if eot wait until the last_burst_len gets synced over
if (eot == 1'b0 || (eot == 1'b1 && bl_ready == 1'b0)) begin
addr_valid <= 1'b1;
end
end
end
end
always @(posedge clk) begin
addr_valid_d1 <= addr_valid;
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
id <= 'h0;
end else if (addr_valid == 1'b1 && addr_valid_d1 == 1'b0) begin
id <= inc_id(id);
end
end end
end
endmodule endmodule

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