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libraries: Update modules according to guideline 

* Added header license for the files that didn't have
* Modified parentheses
* Removed extra spaces at the end of lines
* Fixed parameters list to be each parameter on its line
* Deleted lines after endmodule and consecutive empty lines
* Fixed indentation

Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
main
Iulia Moldovan 2022-04-08 11:21:52 +01:00 committed by imoldovan
parent 521476a8d4
commit 0c0617d49e
397 changed files with 16299 additions and 16791 deletions
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3
library/ad463x_data_capture/ad463x_data_capture.v
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@ -44,7 +44,6 @@ module ad463x_data_capture #(
parameter NUM_OF_LANES = 2,
parameter DATA_WIDTH = 32
) (
input clk, // core clock of the SPIE
input csn, // CSN (chip select)
input echo_sclk, // BUSY/SCLKOUT
@ -53,7 +52,6 @@ module ad463x_data_capture #(
output [(NUM_OF_LANES * DATA_WIDTH)-1:0] m_axis_data, // parallel data lines
output m_axis_valid, // data validation
input m_axis_ready // NOTE: back pressure is ignored
);
reg csn_d;
@ -131,4 +129,3 @@ end
endgenerate
endmodule

27
library/axi_ad5766/axi_ad5766.v
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@ -43,7 +43,8 @@ module axi_ad5766 #(
parameter DEV_PACKAGE = 0,
parameter ASYNC_SPI_CLK = 0,
parameter CMD_MEM_ADDRESS_WIDTH = 4,
parameter SDO_MEM_ADDRESS_WIDTH = 4)(
parameter SDO_MEM_ADDRESS_WIDTH = 4
) (
// Slave AXI interface
@ -107,7 +108,8 @@ module axi_ad5766 #(
input ctrl_enable,
output ctrl_enabled,
input ctrl_mem_reset);
input ctrl_mem_reset
);
// internal wires
@ -199,8 +201,7 @@ module axi_ad5766 #(
.in_bits(ctrl_do_enable),
.out_clk(spi_clk),
.out_resetn(1'b1),
.out_bits(spi_enable_s)
);
.out_bits(spi_enable_s));
sync_bits #(
.NUM_OF_BITS(1),
@ -209,8 +210,7 @@ module axi_ad5766 #(
.in_bits(spi_enabled),
.out_clk(ctrl_clk),
.out_resetn(1'b1),
.out_bits(ctrl_is_enabled)
);
.out_bits(ctrl_is_enabled));
sync_bits #(
.NUM_OF_BITS(1),
@ -219,8 +219,7 @@ module axi_ad5766 #(
.in_bits(ctrl_mem_reset),
.out_clk(spi_clk),
.out_resetn(1'b1),
.out_bits(spi_mem_reset_s)
);
.out_bits(spi_mem_reset_s));
end else begin
assign spi_enable_s = ctrl_enable;
@ -299,14 +298,15 @@ module axi_ad5766 #(
// rate controller
assign dac_rstn_s = ~dac_rst_s;
util_pulse_gen #(.PULSE_WIDTH(1)) i_trigger_gen (
util_pulse_gen #(
.PULSE_WIDTH(1)
) i_trigger_gen (
.clk (spi_clk),
.rstn (dac_rstn_s),
.pulse_width (1'b1),
.pulse_period (pulse_period_s),
.load_config (1'b1),
.pulse (trigger_s)
);
.pulse (trigger_s));
// offset of the sequencer registers are 8'h40
@ -327,8 +327,8 @@ module axi_ad5766 #(
assign pulse_period_s = {16'h0, dac_datarate_s};
up_ad5766_sequencer #(
.SEQ_ID(4))
i_sequencer (
.SEQ_ID(4)
) i_sequencer (
.sequence_clk (spi_clk),
.sequence_rst (spi_mem_reset_s),
.sequence_req (dma_valid),
@ -397,7 +397,6 @@ module axi_ad5766 #(
.up_rdata (up_rdata_s[0]),
.up_rack (up_rack_s[0]));
// AXI wrapper
up_axi #(

12
library/axi_ad5766/up_ad5766_sequencer.v
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@ -37,8 +37,8 @@
module up_ad5766_sequencer #(
parameter SEQ_ID = 0)(
parameter SEQ_ID = 0
) (
input sequence_clk,
input sequence_rst,
input sequence_req,
@ -54,8 +54,8 @@ module up_ad5766_sequencer #(
input up_rreq,
input [13:0] up_raddr,
output reg [31:0] up_rdata,
output reg up_rack);
output reg up_rack
);
// registers
@ -214,7 +214,9 @@ module up_ad5766_sequencer #(
// CDC
up_xfer_cntrl #(.DATA_WIDTH(132)) i_xfer_cntrl (
up_xfer_cntrl #(
.DATA_WIDTH(132)
) i_xfer_cntrl (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_cntrl ({up_endof_seq,

16
library/axi_ad7616/axi_ad7616.v
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@ -38,7 +38,8 @@
module axi_ad7616 #(
parameter ID = 0,
parameter IF_TYPE = 1) (
parameter IF_TYPE = 1
) (
// physical data interface
@ -88,8 +89,8 @@ module axi_ad7616 #(
output [15:0] adc_data,
output adc_sync,
output irq);
output irq
);
localparam NUM_OF_SDI = 2;
localparam SERIAL = 0;
@ -368,8 +369,7 @@ module axi_ad7616 #(
.fifo_wr_en(adc_valid),
.fifo_wr_data(adc_data),
.fifo_wr_sync(adc_sync),
.fifo_wr_xfer_req(1'b1)
);
.fifo_wr_xfer_req(1'b1));
end
endgenerate
@ -402,8 +402,7 @@ module axi_ad7616 #(
.wr_req (wr_req_s),
.wr_data (wr_data_s),
.rd_data (rd_data_s),
.rd_valid (rd_valid_s)
);
.rd_valid (rd_valid_s));
end
endgenerate
@ -466,6 +465,3 @@ module axi_ad7616 #(
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************

8
library/axi_ad7616/axi_ad7616_control.v
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@ -38,7 +38,8 @@
module axi_ad7616_control #(
parameter ID = 0,
parameter IF_TYPE = 0) (
parameter IF_TYPE = 0
) (
// control signals
@ -68,7 +69,6 @@ module axi_ad7616_control #(
output reg up_rack
);
localparam PCORE_VERSION = 'h00001002;
localparam POS_EDGE = 0;
localparam NEG_EDGE = 1;
@ -170,8 +170,7 @@ module axi_ad7616_control #(
.clk (up_clk),
.rst (up_rst),
.signal_in (busy),
.signal_out (end_of_conv)
);
.signal_out (end_of_conv));
// convertion start generator
// NOTE: + The minimum convertion cycle is 1 us
@ -208,4 +207,3 @@ module axi_ad7616_control #(
assign cnvst = (up_cnvst_en == 1'b1) ? cnvst_buf : 1'b0;
endmodule

5
library/axi_ad7616/axi_ad7616_maxis2wrfifo.v
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@ -37,8 +37,8 @@
module axi_ad7616_maxis2wrfifo #(
parameter DATA_WIDTH = 16) (
parameter DATA_WIDTH = 16
) (
input clk,
input rstn,
input sync_in,
@ -58,7 +58,6 @@ module axi_ad7616_maxis2wrfifo #(
input fifo_wr_xfer_req
);
always @(posedge clk) begin
if (rstn == 1'b0) begin
m_axis_ready <= 1'b0;

8
library/axi_ad7616/axi_ad7616_pif.v
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@ -37,7 +37,8 @@
module axi_ad7616_pif #(
parameter UP_ADDRESS_WIDTH = 14) (
parameter UP_ADDRESS_WIDTH = 14
) (
// physical interface
@ -67,8 +68,8 @@ module axi_ad7616_pif #(
input wr_req,
input [15:0] wr_data,
output reg [15:0] rd_data,
output reg rd_valid);
output reg rd_valid
);
// state registers
@ -212,4 +213,3 @@ module axi_ad7616_pif #(
end
endmodule

18
library/axi_ad9122/axi_ad9122.v
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@ -53,7 +53,8 @@ module axi_ad9122 #(
parameter DAC_DDS_TYPE = 1,
parameter DAC_DDS_CORDIC_DW = 20,
parameter DAC_DDS_CORDIC_PHASE_DW = 18,
parameter IO_DELAY_GROUP = "dev_if_delay_group") (
parameter IO_DELAY_GROUP = "dev_if_delay_group"
) (
// dac interface
@ -104,8 +105,8 @@ module axi_ad9122 #(
output [ 1:0] s_axi_rresp,
input s_axi_rready,
input [ 2:0] s_axi_awprot,
input [ 2:0] s_axi_arprot);
input [ 2:0] s_axi_arprot
);
// internal clocks and resets
@ -164,8 +165,8 @@ module axi_ad9122 #(
.MMCM_VCO_DIV (MMCM_VCO_DIV),
.MMCM_VCO_MUL (MMCM_VCO_MUL),
.MMCM_CLK0_DIV (MMCM_CLK0_DIV),
.MMCM_CLK1_DIV (MMCM_CLK1_DIV))
i_if (
.MMCM_CLK1_DIV (MMCM_CLK1_DIV)
) i_if (
.dac_clk_in_p (dac_clk_in_p),
.dac_clk_in_n (dac_clk_in_n),
.dac_clk_out_p (dac_clk_out_p),
@ -216,8 +217,8 @@ module axi_ad9122 #(
.DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.DATAPATH_DISABLE(DAC_DATAPATH_DISABLE))
i_core (
.DATAPATH_DISABLE(DAC_DATAPATH_DISABLE)
) i_core (
.dac_div_clk (dac_div_clk),
.dac_rst (dac_rst),
.dac_frame_i0 (dac_frame_i0_s),
@ -297,6 +298,3 @@ module axi_ad9122 #(
.up_rack (up_rack_s));
endmodule
// ***************************************************************************
// ***************************************************************************

17
library/axi_ad9122/axi_ad9122_channel.v
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@ -41,7 +41,8 @@ module axi_ad9122_channel #(
parameter DAC_DDS_TYPE = 1,
parameter DAC_DDS_CORDIC_DW = 16,
parameter DAC_DDS_CORDIC_PHASE_DW = 16,
parameter DATAPATH_DISABLE = 0) (
parameter DATAPATH_DISABLE = 0
) (
// dac interface
@ -69,7 +70,8 @@ module axi_ad9122_channel #(
input up_rreq,
input [13:0] up_raddr,
output [31:0] up_rdata,
output up_rack);
output up_rack
);
// internal signals
@ -110,8 +112,8 @@ module axi_ad9122_channel #(
.DDS_TYPE (DAC_DDS_TYPE),
.CORDIC_DW (DAC_DDS_CORDIC_DW),
.CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.CLK_RATIO (4))
i_dds (
.CLK_RATIO (4)
) i_dds (
.clk (dac_clk),
.dac_dds_format (dac_dds_format),
.dac_data_sync (dac_data_sync),
@ -131,8 +133,8 @@ module axi_ad9122_channel #(
.CHANNEL_ID(CHANNEL_ID),
.DDS_DISABLE (0),
.USERPORTS_DISABLE (0),
.IQCORRECTION_DISABLE (0))
i_up_dac_channel (
.IQCORRECTION_DISABLE (0)
) i_up_dac_channel (
.dac_clk (dac_div_clk),
.dac_rst (dac_rst),
.dac_dds_scale_1 (dac_dds_scale_1_s),
@ -174,6 +176,3 @@ module axi_ad9122_channel #(
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************

22
library/axi_ad9122/axi_ad9122_core.v
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@ -45,7 +45,8 @@ module axi_ad9122_core #(
parameter DAC_DDS_TYPE = 1,
parameter DAC_DDS_CORDIC_DW = 16,
parameter DAC_DDS_CORDIC_PHASE_DW = 16,
parameter DATAPATH_DISABLE = 0) (
parameter DATAPATH_DISABLE = 0
) (
// dac interface
@ -109,8 +110,8 @@ module axi_ad9122_core #(
input up_rreq,
input [13:0] up_raddr,
output reg [31:0] up_rdata,
output reg up_rack);
output reg up_rack
);
// internal registers
@ -159,8 +160,8 @@ module axi_ad9122_core #(
.DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.DATAPATH_DISABLE(DATAPATH_DISABLE))
i_channel_0 (
.DATAPATH_DISABLE(DATAPATH_DISABLE)
) i_channel_0 (
.dac_div_clk (dac_div_clk),
.dac_rst (dac_rst),
.dac_enable (dac_enable_0),
@ -188,8 +189,8 @@ module axi_ad9122_core #(
.DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.DATAPATH_DISABLE(DATAPATH_DISABLE))
i_channel_1 (
.DATAPATH_DISABLE(DATAPATH_DISABLE)
) i_channel_1 (
.dac_div_clk (dac_div_clk),
.dac_rst (dac_rst),
.dac_enable (dac_enable_1),
@ -223,8 +224,8 @@ module axi_ad9122_core #(
.COMMON_ID (6'h10),
.DRP_DISABLE (6'h00),
.USERPORTS_DISABLE (0),
.GPIO_DISABLE (0))
i_up_dac_common (
.GPIO_DISABLE (0)
) i_up_dac_common (
.mmcm_rst (mmcm_rst),
.dac_clk (dac_div_clk),
.dac_rst (dac_rst),
@ -266,6 +267,3 @@ module axi_ad9122_core #(
.up_rack (up_rack_s));
endmodule
// ***************************************************************************
// ***************************************************************************

26
library/axi_ad9122/axi_ad9122_if.v
View File

@ -47,7 +47,8 @@ module axi_ad9122_if #(
parameter MMCM_VCO_MUL = 12,
parameter MMCM_CLK0_DIV = 2,
parameter MMCM_CLK1_DIV = 8,
parameter IO_DELAY_GROUP = "dac_if_delay_group") (
parameter IO_DELAY_GROUP = "dac_if_delay_group"
) (
// dac interface
@ -101,8 +102,8 @@ module axi_ad9122_if #(
input [31:0] up_drp_wdata,
output [31:0] up_drp_rdata,
output up_drp_ready,
output up_drp_locked);
output up_drp_locked
);
// internal registers
@ -130,8 +131,8 @@ module axi_ad9122_if #(
ad_serdes_out #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.DDR_OR_SDR_N (SERDES_OR_DDR_N),
.DATA_WIDTH (16))
i_serdes_out_data (
.DATA_WIDTH (16)
) i_serdes_out_data (
.rst (dac_rst),
.clk (dac_clk),
.div_clk (dac_div_clk),
@ -154,8 +155,8 @@ module axi_ad9122_if #(
ad_serdes_out #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.DDR_OR_SDR_N (SERDES_OR_DDR_N),
.DATA_WIDTH (1))
i_serdes_out_frame (
.DATA_WIDTH (1)
) i_serdes_out_frame (
.rst (dac_rst),
.clk (dac_clk),
.div_clk (dac_div_clk),
@ -178,8 +179,8 @@ module axi_ad9122_if #(
ad_serdes_out #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.DDR_OR_SDR_N (SERDES_OR_DDR_N),
.DATA_WIDTH (1))
i_serdes_out_clk (
.DATA_WIDTH (1)
) i_serdes_out_clk (
.rst (dac_rst),
.clk (dac_clk),
.div_clk (dac_div_clk),
@ -207,8 +208,8 @@ module axi_ad9122_if #(
.MMCM_VCO_DIV (MMCM_VCO_DIV),
.MMCM_VCO_MUL (MMCM_VCO_MUL),
.MMCM_CLK0_DIV (MMCM_CLK0_DIV),
.MMCM_CLK1_DIV (MMCM_CLK1_DIV))
i_serdes_clk (
.MMCM_CLK1_DIV (MMCM_CLK1_DIV)
) i_serdes_clk (
.rst (mmcm_rst),
.clk_in_p (dac_clk_in_p),
.clk_in_n (dac_clk_in_n),
@ -228,6 +229,3 @@ module axi_ad9122_if #(
.up_drp_locked (up_drp_locked));
endmodule
// ***************************************************************************
// ***************************************************************************

6
library/axi_ad9250/axi_ad9250.v
View File

@ -85,7 +85,8 @@ module axi_ad9250 #(
output s_axi_rvalid,
output [31:0] s_axi_rdata,
output [ 1:0] s_axi_rresp,
input s_axi_rready);
input s_axi_rready
);
assign adc_clk = rx_clk;
@ -135,7 +136,6 @@ module axi_ad9250 #(
.s_axi_rvalid (s_axi_rvalid),
.s_axi_rready (s_axi_rready),
.s_axi_rresp (s_axi_rresp),
.s_axi_rdata (s_axi_rdata)
);
.s_axi_rdata (s_axi_rdata));
endmodule

28
library/axi_ad9265/axi_ad9265.v
View File

@ -43,7 +43,8 @@ module axi_ad9265 #(
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0,
parameter ADC_DATAPATH_DISABLE = 0,
parameter IO_DELAY_GROUP = "adc_if_delay_group") (
parameter IO_DELAY_GROUP = "adc_if_delay_group"
) (
// adc interface (clk, data, over-range)
@ -89,8 +90,8 @@ module axi_ad9265 #(
output [31:0] s_axi_rdata,
input s_axi_rready,
input [ 2:0] s_axi_awprot,
input [ 2:0] s_axi_arprot);
input [ 2:0] s_axi_arprot
);
// internal registers
@ -157,8 +158,8 @@ module axi_ad9265 #(
axi_ad9265_channel #(
.CHANNEL_ID(0),
.DATAPATH_DISABLE (ADC_DATAPATH_DISABLE))
i_channel (
.DATAPATH_DISABLE (ADC_DATAPATH_DISABLE)
) i_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data (adc_data_s),
@ -184,8 +185,8 @@ module axi_ad9265 #(
axi_ad9265_if #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IO_DELAY_GROUP (IO_DELAY_GROUP))
i_if (
.IO_DELAY_GROUP (IO_DELAY_GROUP)
) i_if (
.adc_clk_in_p (adc_clk_in_p),
.adc_clk_in_n (adc_clk_in_n),
.adc_data_in_p (adc_data_in_p),
@ -206,7 +207,10 @@ module axi_ad9265 #(
// adc delay control
up_delay_cntrl #(.DATA_WIDTH(9), .BASE_ADDRESS(6'h02)) i_delay_cntrl (
up_delay_cntrl #(
.DATA_WIDTH(9),
.BASE_ADDRESS(6'h02)
) i_delay_cntrl (
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked_s),
@ -237,8 +241,8 @@ module axi_ad9265 #(
.DRP_DISABLE (6'h00),
.USERPORTS_DISABLE (0),
.GPIO_DISABLE (0),
.START_CODE_DISABLE(0))
i_up_adc_common (
.START_CODE_DISABLE(0)
) i_up_adc_common (
.mmcm_rst (),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
@ -313,7 +317,3 @@ module axi_ad9265 #(
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************

18
library/axi_ad9265/axi_ad9265_channel.v
View File

@ -39,7 +39,8 @@
module axi_ad9265_channel #(
parameter CHANNEL_ID = 0,
parameter DATAPATH_DISABLE = 0) (
parameter DATAPATH_DISABLE = 0
) (
// adc interface
@ -68,8 +69,8 @@ module axi_ad9265_channel #(
input up_rreq,
input [13:0] up_raddr,
output [31:0] up_rdata,
output up_rack);
output up_rack
);
// internal signals
@ -97,7 +98,9 @@ module axi_ad9265_channel #(
if (DATAPATH_DISABLE == 1) begin
assign adc_dfmt_data_s = adc_data;
end else begin
ad_datafmt #(.DATA_WIDTH(16)) i_ad_datafmt (
ad_datafmt #(
.DATA_WIDTH(16)
) i_ad_datafmt (
.clk (adc_clk),
.valid (1'b1),
.data (adc_data),
@ -131,8 +134,8 @@ module axi_ad9265_channel #(
.USERPORTS_DISABLE (0),
.DATAFORMAT_DISABLE (0),
.DCFILTER_DISABLE (0),
.IQCORRECTION_DISABLE (0))
i_up_adc_channel (
.IQCORRECTION_DISABLE (0)
) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),
@ -179,6 +182,3 @@ module axi_ad9265_channel #(
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************

21
library/axi_ad9265/axi_ad9265_if.v
View File

@ -41,7 +41,8 @@ module axi_ad9265_if #(
parameter FPGA_TECHNOLOGY = 0,
parameter IO_DELAY_GROUP = "adc_if_delay_group",
parameter DELAY_REFCLK_FREQUENCY = 200) (
parameter DELAY_REFCLK_FREQUENCY = 200
) (
// adc interface (clk, data, over-range)
// nominal clock 125 MHz, up to 300 MHz
@ -68,8 +69,8 @@ module axi_ad9265_if #(
output [44:0] up_drdata,
input delay_clk,
input delay_rst,
output delay_locked);
output delay_locked
);
// internal registers
@ -102,8 +103,8 @@ module axi_ad9265_if #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
i_adc_data (
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
) i_adc_data (
.rx_clk (adc_clk),
.rx_data_in_p (adc_data_in_p[l_inst]),
.rx_data_in_n (adc_data_in_n[l_inst]),
@ -125,8 +126,8 @@ module axi_ad9265_if #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_CTRL (1),
.IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
i_adc_or (
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
) i_adc_or (
.rx_clk (adc_clk),
.rx_data_in_p (adc_or_in_p),
.rx_data_in_n (adc_or_in_n),
@ -142,8 +143,7 @@ module axi_ad9265_if #(
// clock
ad_data_clk
i_adc_clk (
ad_data_clk i_adc_clk (
.rst (1'b0),
.locked (),
.clk_in_p (adc_clk_in_p),
@ -151,6 +151,3 @@ module axi_ad9265_if #(
.clk (adc_clk));
endmodule
// ***************************************************************************
// ***************************************************************************

11
library/axi_ad9265/axi_ad9265_pnmon.v
View File

@ -47,7 +47,8 @@ module axi_ad9265_pnmon (
output adc_pn_oos,
output adc_pn_err,
input [ 3:0] adc_pnseq_sel);
input [ 3:0] adc_pnseq_sel
);
// internal registers
@ -161,7 +162,9 @@ module axi_ad9265_pnmon (
// pn oos & pn err
ad_pnmon #(.DATA_WIDTH(32)) i_pnmon (
ad_pnmon #(
.DATA_WIDTH(32)
) i_pnmon (
.adc_clk (adc_clk),
.adc_valid_in (adc_valid_in),
.adc_data_in (adc_pn_data_in),
@ -170,7 +173,3 @@ module axi_ad9265_pnmon (
.adc_pn_err (adc_pn_err));
endmodule
// ***************************************************************************
// ***************************************************************************

29
library/axi_ad9361/axi_ad9361.v
View File

@ -69,7 +69,8 @@ module axi_ad9361 #(
parameter MIMO_ENABLE = 0,
parameter USE_SSI_CLK = 1,
parameter DELAY_REFCLK_FREQUENCY = 200,
parameter RX_NODPA = 0) (
parameter RX_NODPA = 0
) (
// physical interface (receive-lvds)
@ -192,7 +193,8 @@ module axi_ad9361 #(
input [31:0] up_dac_gpio_in,
output [31:0] up_dac_gpio_out,
input [31:0] up_adc_gpio_in,
output [31:0] up_adc_gpio_out);
output [31:0] up_adc_gpio_out
);
// derived parameters
@ -339,8 +341,8 @@ module axi_ad9361 #(
.IODELAY_CTRL (IODELAY_CTRL),
.CLK_DESKEW (MIMO_ENABLE),
.USE_SSI_CLK (USE_SSI_CLK),
.DELAY_REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
i_dev_if (
.DELAY_REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
) i_dev_if (
.rx_clk_in (rx_clk_in),
.rx_frame_in (rx_frame_in),
.rx_data_in (rx_data_in),
@ -405,8 +407,8 @@ module axi_ad9361 #(
.CLK_DESKEW (MIMO_ENABLE),
.USE_SSI_CLK (USE_SSI_CLK),
.DELAY_REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY),
.RX_NODPA (RX_NODPA))
i_dev_if (
.RX_NODPA (RX_NODPA)
) i_dev_if (
.rx_clk_in_p (rx_clk_in_p),
.rx_clk_in_n (rx_clk_in_n),
.rx_frame_in_p (rx_frame_in_p),
@ -521,7 +523,9 @@ module axi_ad9361 #(
generate
if (TDD_DISABLE == 0) begin
axi_ad9361_tdd_if #(.LEVEL_OR_PULSE_N(1)) i_tdd_if (
axi_ad9361_tdd_if #(
.LEVEL_OR_PULSE_N(1)
) i_tdd_if (
.clk (clk),
.rst (rst),
.tdd_rx_vco_en (tdd_rx_vco_en_s),
@ -599,8 +603,8 @@ module axi_ad9361 #(
.USERPORTS_DISABLE (ADC_USERPORTS_DISABLE_INT),
.DATAFORMAT_DISABLE (ADC_DATAFORMAT_DISABLE_INT),
.DCFILTER_DISABLE (ADC_DCFILTER_DISABLE_INT),
.IQCORRECTION_DISABLE (ADC_IQCORRECTION_DISABLE_INT))
i_rx (
.IQCORRECTION_DISABLE (ADC_IQCORRECTION_DISABLE_INT)
) i_rx (
.mmcm_rst (mmcm_rst),
.adc_rst (rst),
.adc_clk (clk),
@ -672,8 +676,8 @@ module axi_ad9361 #(
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.USERPORTS_DISABLE (DAC_USERPORTS_DISABLE_INT),
.DELAYCNTRL_DISABLE (DAC_DELAYCNTRL_DISABLE_INT),
.IQCORRECTION_DISABLE (DAC_IQCORRECTION_DISABLE_INT))
i_tx (
.IQCORRECTION_DISABLE (DAC_IQCORRECTION_DISABLE_INT)
) i_tx (
.dac_clk (clk),
.dac_valid (dac_valid_s),
.dac_data (dac_data_s),
@ -750,6 +754,3 @@ module axi_ad9361 #(
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************

34
library/axi_ad9361/axi_ad9361_rx.v
View File

@ -52,7 +52,8 @@ module axi_ad9361_rx #(
parameter USERPORTS_DISABLE = 0,
parameter DATAFORMAT_DISABLE = 0,
parameter DCFILTER_DISABLE = 0,
parameter IQCORRECTION_DISABLE = 0) (
parameter IQCORRECTION_DISABLE = 0
) (
// common
@ -126,7 +127,8 @@ module axi_ad9361_rx #(
output [31:0] up_drp_wdata,
input [31:0] up_drp_rdata,
input up_drp_ready,
input up_drp_locked);
input up_drp_locked
);
// configuration settings
@ -194,8 +196,8 @@ module axi_ad9361_rx #(
.USERPORTS_DISABLE (USERPORTS_DISABLE),
.DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
.DCFILTER_DISABLE (DCFILTER_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
i_rx_channel_0 (
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)
) i_rx_channel_0 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_valid (adc_valid),
@ -231,8 +233,8 @@ module axi_ad9361_rx #(
.USERPORTS_DISABLE (USERPORTS_DISABLE),
.DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
.DCFILTER_DISABLE (DCFILTER_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
i_rx_channel_1 (
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)
) i_rx_channel_1 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_valid (adc_valid),
@ -268,8 +270,8 @@ module axi_ad9361_rx #(
.USERPORTS_DISABLE (USERPORTS_DISABLE),
.DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
.DCFILTER_DISABLE (DCFILTER_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
i_rx_channel_2 (
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)
) i_rx_channel_2 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_valid (adc_valid),
@ -305,8 +307,8 @@ module axi_ad9361_rx #(
.USERPORTS_DISABLE (USERPORTS_DISABLE),
.DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
.DCFILTER_DISABLE (DCFILTER_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
i_rx_channel_3 (
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)
) i_rx_channel_3 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_valid (adc_valid),
@ -345,8 +347,8 @@ module axi_ad9361_rx #(
.DRP_DISABLE (1),
.USERPORTS_DISABLE (USERPORTS_DISABLE),
.GPIO_DISABLE (0),
.START_CODE_DISABLE (0))
i_up_adc_common (
.START_CODE_DISABLE (0)
) i_up_adc_common (
.mmcm_rst (mmcm_rst),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
@ -397,8 +399,8 @@ module axi_ad9361_rx #(
up_delay_cntrl #(
.INIT_DELAY (INIT_DELAY),
.DATA_WIDTH (13),
.BASE_ADDRESS (6'h02))
i_delay_cntrl (
.BASE_ADDRESS (6'h02)
) i_delay_cntrl (
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked),
@ -417,7 +419,3 @@ module axi_ad9361_rx #(
.up_rack (up_rack_s[5]));
endmodule
// ***************************************************************************
// ***************************************************************************

31
library/axi_ad9361/axi_ad9361_rx_channel.v
View File

@ -45,7 +45,8 @@ module axi_ad9361_rx_channel #(
parameter USERPORTS_DISABLE = 0,
parameter DATAFORMAT_DISABLE = 0,
parameter DCFILTER_DISABLE = 0,
parameter IQCORRECTION_DISABLE = 0) (
parameter IQCORRECTION_DISABLE = 0
) (
// adc interface
@ -79,7 +80,8 @@ module axi_ad9361_rx_channel #(
input up_rreq,
input [13:0] up_raddr,
output [31:0] up_rdata,
output up_rack);
output up_rack
);
// internal signals
@ -129,8 +131,8 @@ module axi_ad9361_rx_channel #(
axi_ad9361_rx_pnmon #(
.Q_OR_I_N (Q_OR_I_N),
.PRBS_SEL (CHANNEL_ID))
i_rx_pnmon (
.PRBS_SEL (CHANNEL_ID)
) i_rx_pnmon (
.adc_clk (adc_clk),
.adc_valid (adc_valid),
.adc_data_i (adc_data),
@ -141,8 +143,8 @@ module axi_ad9361_rx_channel #(
ad_datafmt #(
.DATA_WIDTH (12),
.DISABLE (DATAFORMAT_DISABLE))
i_ad_datafmt (
.DISABLE (DATAFORMAT_DISABLE)
) i_ad_datafmt (
.clk (adc_clk),
.valid (adc_valid),
.data (adc_data_s),
@ -153,8 +155,8 @@ module axi_ad9361_rx_channel #(
.dfmt_se (adc_dfmt_se_s));
ad_dcfilter #(
.DISABLE (DCFILTER_DISABLE))
i_ad_dcfilter (
.DISABLE (DCFILTER_DISABLE)
) i_ad_dcfilter (
.clk (adc_clk),
.valid (adc_dfmt_valid_s),
.data (adc_dfmt_data_s),
@ -166,8 +168,8 @@ module axi_ad9361_rx_channel #(
ad_iqcor #(
.Q_OR_I_N (Q_OR_I_N),
.DISABLE (IQCORRECTION_DISABLE))
i_ad_iqcor (
.DISABLE (IQCORRECTION_DISABLE)
) i_ad_iqcor (
.clk (adc_clk),
.valid (adc_dcfilter_valid_s),
.data_in (adc_dcfilter_data_s),
@ -183,8 +185,8 @@ module axi_ad9361_rx_channel #(
.USERPORTS_DISABLE (USERPORTS_DISABLE),
.DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
.DCFILTER_DISABLE (DCFILTER_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
i_up_adc_channel (
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)
) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),
@ -232,9 +234,4 @@ module axi_ad9361_rx_channel #(
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************

14
library/axi_ad9361/axi_ad9361_rx_pnmon.v
View File

@ -39,7 +39,8 @@
module axi_ad9361_rx_pnmon #(
parameter Q_OR_I_N = 0,
parameter PRBS_SEL = 0) (
parameter PRBS_SEL = 0
) (
// adc interface
@ -52,7 +53,8 @@ module axi_ad9361_rx_pnmon #(
input [ 3:0] adc_pnseq_sel,
output adc_pn_oos,
output adc_pn_err);
output adc_pn_err
);
localparam PRBS_P09 = 0;
localparam PRBS_P11 = 1;
@ -287,7 +289,9 @@ module axi_ad9361_rx_pnmon #(
// pn oos & pn err
ad_pnmon #(.DATA_WIDTH(24)) i_pnmon (
ad_pnmon #(
.DATA_WIDTH(24)
) i_pnmon (
.adc_clk (adc_clk),
.adc_valid_in (adc_pn_valid_in),
.adc_data_in (adc_pn_data_in),
@ -297,7 +301,3 @@ module axi_ad9361_rx_pnmon #(
.adc_pn_err (adc_pn_err));
endmodule
// ***************************************************************************
// ***************************************************************************

7
library/axi_ad9361/axi_ad9361_tdd.v
View File

@ -75,7 +75,8 @@ module axi_ad9361_tdd (
input up_rreq,
input [13:0] up_raddr,
output [31:0] up_rdata,
output up_rack);
output up_rack
);
// internal signals
@ -206,8 +207,8 @@ module axi_ad9361_tdd (
ad_tdd_control #(
.TX_DATA_PATH_DELAY(),
.CONTROL_PATH_DELAY())
i_tdd_control(
.CONTROL_PATH_DELAY()
) i_tdd_control(
.clk(clk),
.rst(rst),
.tdd_enable(tdd_enable_s),

13
library/axi_ad9361/axi_ad9361_tdd_if.v
View File

@ -36,11 +36,8 @@
`timescale 1ns/1ps
module axi_ad9361_tdd_if #(
parameter LEVEL_OR_PULSE_N = 0) (
// clock
parameter LEVEL_OR_PULSE_N = 0
) (
input clk,
input rst,
@ -58,15 +55,14 @@ module axi_ad9361_tdd_if#(
// interface status
output [ 7:0] ad9361_tdd_status);
output [ 7:0] ad9361_tdd_status
);
localparam PULSE_MODE = 0;
localparam LEVEL_MODE = 1;
// internal registers
reg tdd_vco_overlap = 1'b0;
reg tdd_rf_overlap = 1'b0;
@ -106,4 +102,3 @@ module axi_ad9361_tdd_if#(
assign ad9361_enable = ad9361_enable_s;
endmodule

33
library/axi_ad9361/axi_ad9361_tx.v
View File

@ -55,7 +55,8 @@ module axi_ad9361_tx #(
parameter DAC_DDS_CORDIC_PHASE_DW = 13,
parameter USERPORTS_DISABLE = 0,
parameter DELAYCNTRL_DISABLE = 0,
parameter IQCORRECTION_DISABLE = 0) (
parameter IQCORRECTION_DISABLE = 0
) (
// dac interface
@ -119,7 +120,8 @@ module axi_ad9361_tx #(
input up_rreq,
input [13:0] up_raddr,
output [31:0] up_rdata,
output up_rack);
output up_rack
);
// configuration settings
@ -227,8 +229,8 @@ module axi_ad9361_tx #(
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.USERPORTS_DISABLE (USERPORTS_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
i_tx_channel_0 (
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)
) i_tx_channel_0 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_valid (dac_valid_int),
@ -262,8 +264,8 @@ module axi_ad9361_tx #(
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.USERPORTS_DISABLE (USERPORTS_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
i_tx_channel_1 (
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)
) i_tx_channel_1 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_valid (dac_valid_int),
@ -297,8 +299,8 @@ module axi_ad9361_tx #(
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.USERPORTS_DISABLE (USERPORTS_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
i_tx_channel_2 (
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)
) i_tx_channel_2 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_valid (dac_valid_int),
@ -332,8 +334,8 @@ module axi_ad9361_tx #(
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.USERPORTS_DISABLE (USERPORTS_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
i_tx_channel_3 (
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)
) i_tx_channel_3 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_valid (dac_valid_int),
@ -368,8 +370,8 @@ module axi_ad9361_tx #(
.CLK_EDGE_SEL (CLK_EDGE_SEL),
.DRP_DISABLE (1),
.USERPORTS_DISABLE (USERPORTS_DISABLE),
.GPIO_DISABLE (0))
i_up_dac_common (
.GPIO_DISABLE (0)
) i_up_dac_common (
.mmcm_rst (),
.dac_clk (dac_clk),
.dac_rst (dac_rst),
@ -419,8 +421,8 @@ module axi_ad9361_tx #(
.DISABLE (DELAYCNTRL_DISABLE),
.INIT_DELAY (INIT_DELAY),
.DATA_WIDTH(16),
.BASE_ADDRESS(6'h12))
i_delay_cntrl (
.BASE_ADDRESS(6'h12)
) i_delay_cntrl (
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked),
@ -439,6 +441,3 @@ module axi_ad9361_tx #(
.up_rack (up_rack_s[5]));
endmodule
// ***************************************************************************
// ***************************************************************************

21
library/axi_ad9361/axi_ad9361_tx_channel.v
View File

@ -47,7 +47,8 @@ module axi_ad9361_tx_channel #(
parameter DAC_DDS_CORDIC_DW = 14,
parameter DAC_DDS_CORDIC_PHASE_DW = 13,
parameter USERPORTS_DISABLE = 0,
parameter IQCORRECTION_DISABLE = 0) (
parameter IQCORRECTION_DISABLE = 0
) (
// dac interface
@ -77,7 +78,8 @@ module axi_ad9361_tx_channel #(
input up_rreq,
input [13:0] up_raddr,
output [31:0] up_rdata,
output up_rack);
output up_rack
);
// parameters
@ -258,8 +260,8 @@ module axi_ad9361_tx_channel #(
ad_iqcor #(
.Q_OR_I_N (Q_OR_I_N),
.DISABLE (IQCORRECTION_DISABLE))
i_ad_iqcor (
.DISABLE (IQCORRECTION_DISABLE)
) i_ad_iqcor (
.clk (dac_clk),
.valid (dac_valid),
.data_in ({dac_data_out_int, 4'd0}),
@ -323,8 +325,8 @@ module axi_ad9361_tx_channel #(
.DDS_TYPE (DAC_DDS_TYPE),
.CORDIC_DW (DAC_DDS_CORDIC_DW),
.CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.CLK_RATIO (1))
i_dds (
.CLK_RATIO (1)
) i_dds (
.clk (dac_clk),
.dac_dds_format (dac_dds_format),
.dac_data_sync (dac_data_sync),
@ -348,8 +350,8 @@ module axi_ad9361_tx_channel #(
.CHANNEL_ID (CHANNEL_ID),
.DDS_DISABLE (DAC_DDS_DISABLE),
.USERPORTS_DISABLE (USERPORTS_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
i_up_dac_channel (
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)
) i_up_dac_channel (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_dds_scale_1 (dac_dds_scale_1_s),
@ -391,6 +393,3 @@ module axi_ad9361_tx_channel #(
.up_rack (up_rack_s));
endmodule
// ***************************************************************************
// ***************************************************************************

3
library/axi_ad9361/intel/axi_ad9361_alt_lvds_rx.v
View File

@ -54,7 +54,8 @@ module axi_ad9361_alt_lvds_rx (
output [ 5:0] rx_data_1,
output [ 5:0] rx_data_2,
output [ 5:0] rx_data_3,
output rx_locked);
output rx_locked
);
// internal signals

3
library/axi_ad9361/intel/axi_ad9361_alt_lvds_tx.v
View File

@ -55,7 +55,8 @@ module axi_ad9361_alt_lvds_tx (
input [ 5:0] tx_data_1,
input [ 5:0] tx_data_2,
input [ 5:0] tx_data_3,
output tx_locked);
output tx_locked
);
// internal registers

9
library/axi_ad9361/intel/axi_ad9361_cmos_if.v
View File

@ -45,7 +45,8 @@ module axi_ad9361_cmos_if #(
// Dummy parameters, required keep the code consistency(used on Xilinx)
parameter IO_DELAY_GROUP = "dev_if_delay_group",
parameter IODELAY_CTRL = 1,
parameter DELAY_REFCLK_FREQUENCY = 0) (
parameter DELAY_REFCLK_FREQUENCY = 0
) (
// physical interface (receive)
@ -116,7 +117,8 @@ module axi_ad9361_cmos_if #(
input [31:0] up_drp_wdata,
output [31:0] up_drp_rdata,
output up_drp_ready,
output up_drp_locked);
output up_drp_locked
);
// cmos is not supported on intel platforms yet.
@ -137,6 +139,3 @@ module axi_ad9361_cmos_if #(
assign up_drp_locked = 1'd0;
endmodule
// ***************************************************************************
// ***************************************************************************

13
library/axi_ad9361/intel/axi_ad9361_lvds_if.v
View File

@ -46,7 +46,8 @@ module axi_ad9361_lvds_if #(
parameter IO_DELAY_GROUP = "dev_if_delay_group",
parameter IODELAY_CTRL = 1,
parameter DELAY_REFCLK_FREQUENCY = 0,
parameter RX_NODPA = 0) (
parameter RX_NODPA = 0
) (
// physical interface (receive)
@ -123,7 +124,8 @@ module axi_ad9361_lvds_if #(
input [31:0] up_drp_wdata,
output [31:0] up_drp_rdata,
output up_drp_ready,
output up_drp_locked);
output up_drp_locked
);
// internal registers
@ -531,8 +533,8 @@ endgenerate
generate
if (FPGA_TECHNOLOGY == ARRIA10) begin
axi_ad9361_lvds_if_10 #(
.RX_NODPA (RX_NODPA))
i_axi_ad9361_lvds_if_10 (
.RX_NODPA (RX_NODPA)
) i_axi_ad9361_lvds_if_10 (
.rx_clk_in_p (rx_clk_in_p),
.rx_clk_in_n (rx_clk_in_n),
.rx_frame_in_p (rx_frame_in_p),
@ -567,6 +569,3 @@ endgenerate
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************

9
library/axi_ad9361/intel/axi_ad9361_lvds_if_10.v
View File

@ -37,7 +37,8 @@
module axi_ad9361_lvds_if_10 #(
parameter RX_NODPA = 0) (
parameter RX_NODPA = 0
) (
// physical interface (receive)
@ -91,7 +92,8 @@ module axi_ad9361_lvds_if_10 #(
// delay interface
input up_clk,
input up_rstn);
input up_rstn
);
// internal registers
@ -302,6 +304,3 @@ module axi_ad9361_lvds_if_10 #(
.ls_clk_clk (clk));
endmodule
// ***************************************************************************
// ***************************************************************************

6
library/axi_ad9361/intel/axi_ad9361_lvds_if_c5.v
View File

@ -89,7 +89,8 @@ module axi_ad9361_lvds_if_c5 (
// delay interface
input up_clk,
input up_rstn);
input up_rstn
);
// internal registers
@ -392,6 +393,3 @@ module axi_ad9361_lvds_if_c5 (
.sset (1'b0));
endmodule
// ***************************************************************************
// ***************************************************************************

41
library/axi_ad9361/xilinx/axi_ad9361_cmos_if.v
View File

@ -43,7 +43,8 @@ module axi_ad9361_cmos_if #(
parameter IODELAY_CTRL = 1,
parameter CLK_DESKEW = 0,
parameter USE_SSI_CLK = 1,
parameter DELAY_REFCLK_FREQUENCY = 200) (
parameter DELAY_REFCLK_FREQUENCY = 200
) (
// physical interface (receive)
@ -114,7 +115,8 @@ module axi_ad9361_cmos_if #(
input [31:0] up_drp_wdata,
output [31:0] up_drp_rdata,
output up_drp_ready,
output up_drp_locked);
output up_drp_locked
);
// internal registers
@ -439,8 +441,8 @@ module axi_ad9361_cmos_if #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
i_rx_data (
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
) i_rx_data (
.rx_clk (l_clk),
.rx_data_in_p (rx_data_in[i]),
.rx_data_in_n (1'd0),
@ -463,8 +465,8 @@ module axi_ad9361_cmos_if #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_CTRL (IODELAY_CTRL),
.IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
i_rx_frame (
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
) i_rx_frame (
.rx_clk (l_clk),
.rx_data_in_p (rx_frame_in),
.rx_data_in_n (1'd0),
@ -488,8 +490,8 @@ module axi_ad9361_cmos_if #(
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
i_tx_data (
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
) i_tx_data (
.tx_clk (l_clk),
.tx_data_p (tx_data_1[i]),
.tx_data_n (tx_data_0[i]),
@ -513,8 +515,8 @@ module axi_ad9361_cmos_if #(
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
i_tx_frame (
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
) i_tx_frame (
.tx_clk (l_clk),
.tx_data_p (tx_frame[1]),
.tx_data_n (tx_frame[0]),
@ -536,8 +538,8 @@ module axi_ad9361_cmos_if #(
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
i_tx_clk (
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
) i_tx_clk (
.tx_clk (l_clk),
.tx_data_p (tx_clk[1]),
.tx_data_n (tx_clk[0]),
@ -559,8 +561,8 @@ module axi_ad9361_cmos_if #(
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
i_enable (
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
) i_enable (
.tx_clk (l_clk),
.tx_data_p (enable_int_p),
.tx_data_n (enable_int_p),
@ -582,8 +584,8 @@ module axi_ad9361_cmos_if #(
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
i_txnrx (
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
) i_txnrx (
.tx_clk (l_clk),
.tx_data_p (txnrx_int_p),
.tx_data_n (txnrx_int_p),
@ -601,8 +603,8 @@ module axi_ad9361_cmos_if #(
generate if (USE_SSI_CLK == 1) begin
ad_data_clk #(
.SINGLE_ENDED (1))
i_clk (
.SINGLE_ENDED (1)
) i_clk (
.rst (1'd0),
.locked (),
.clk_in_p (rx_clk_in),
@ -614,6 +616,3 @@ module axi_ad9361_cmos_if #(
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************

41
library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v
View File

@ -44,7 +44,8 @@ module axi_ad9361_lvds_if #(
parameter CLK_DESKEW = 0,
parameter USE_SSI_CLK = 1,
parameter DELAY_REFCLK_FREQUENCY = 200,
parameter RX_NODPA = 0) (
parameter RX_NODPA = 0
) (
// physical interface (receive)
@ -121,7 +122,8 @@ module axi_ad9361_lvds_if #(
input [31:0] up_drp_wdata,
output [31:0] up_drp_rdata,
output up_drp_ready,
output up_drp_locked);
output up_drp_locked
);
// internal registers
@ -213,7 +215,6 @@ module axi_ad9361_lvds_if #(
// frame check
// delineation
reg rx_error_r1 = 'd0;
reg rx_error_r2 = 'd0;
@ -454,8 +455,8 @@ module axi_ad9361_lvds_if #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
i_rx_data (
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
) i_rx_data (
.rx_clk (l_clk),
.rx_data_in_p (rx_data_in_p[i]),
.rx_data_in_n (rx_data_in_n[i]),
@ -477,8 +478,8 @@ module axi_ad9361_lvds_if #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_CTRL (IODELAY_CTRL),
.IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
i_rx_frame (
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
) i_rx_frame (
.rx_clk (l_clk),
.rx_data_in_p (rx_frame_in_p),
.rx_data_in_n (rx_frame_in_n),
@ -501,8 +502,8 @@ module axi_ad9361_lvds_if #(
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
i_tx_data (
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
) i_tx_data (
.tx_clk (l_clk),
.tx_data_p (tx_data_1[i]),
.tx_data_n (tx_data_0[i]),
@ -525,8 +526,8 @@ module axi_ad9361_lvds_if #(
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
i_tx_frame (
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
) i_tx_frame (
.tx_clk (l_clk),
.tx_data_p (tx_frame),
.tx_data_n (tx_frame),
@ -547,8 +548,8 @@ module axi_ad9361_lvds_if #(
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
i_tx_clk (
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
) i_tx_clk (
.tx_clk (l_clk),
.tx_data_p (tx_clk[1]),
.tx_data_n (tx_clk[0]),
@ -570,8 +571,8 @@ module axi_ad9361_lvds_if #(
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
i_enable (
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
) i_enable (
.tx_clk (l_clk),
.tx_data_p (enable_int_p),
.tx_data_n (enable_int_p),
@ -593,8 +594,8 @@ module axi_ad9361_lvds_if #(
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
i_txnrx (
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
) i_txnrx (
.tx_clk (l_clk),
.tx_data_p (txnrx_int_p),
.tx_data_n (txnrx_int_p),
@ -610,8 +611,7 @@ module axi_ad9361_lvds_if #(
// device clock interface (receive clock)
generate if (USE_SSI_CLK == 1) begin
ad_data_clk
i_clk (
ad_data_clk i_clk (
.rst (1'd0),
.locked (),
.clk_in_p (rx_clk_in_p),
@ -623,6 +623,3 @@ module axi_ad9361_lvds_if #(
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************

10
library/axi_ad9434/axi_ad9434.v
View File

@ -43,7 +43,8 @@ module axi_ad9434 #(
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group") (
parameter IO_DELAY_GROUP = "dev_if_delay_group"
) (
// physical interface
input adc_clk_in_p,
@ -84,7 +85,8 @@ module axi_ad9434 #(
output [31:0] s_axi_rdata,
input s_axi_rready,
input [ 2:0] s_axi_awprot,
input [ 2:0] s_axi_arprot);
input [ 2:0] s_axi_arprot
);
// internal clocks & resets
wire adc_rst;
@ -131,8 +133,8 @@ module axi_ad9434 #(
axi_ad9434_if #(
.FPGA_TECHNOLOGY(FPGA_TECHNOLOGY),
.IO_DELAY_GROUP(IO_DELAY_GROUP))
i_if(
.IO_DELAY_GROUP(IO_DELAY_GROUP)
) i_if (
.adc_clk_in_p(adc_clk_in_p),
.adc_clk_in_n(adc_clk_in_n),
.adc_data_in_p(adc_data_in_p),

23
library/axi_ad9434/axi_ad9434_core.v
View File

@ -41,7 +41,8 @@ module axi_ad9434_core #(
parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0) (
parameter DEV_PACKAGE = 0
) (
// device interface
@ -92,7 +93,8 @@ module axi_ad9434_core #(
output mmcm_rst,
output adc_rst,
output adc_enable,
input adc_status);
input adc_status
);
// internal signals
wire up_status_pn_err_s;
@ -123,8 +125,8 @@ module axi_ad9434_core #(
generate
for (n = 0; n < 4; n = n + 1) begin: g_ad_dfmt
ad_datafmt #(
.DATA_WIDTH(12))
i_datafmt (
.DATA_WIDTH(12)
) i_datafmt (
.clk (adc_clk),
.valid (1'b1),
.data (adc_data[n*12+11:n*12]),
@ -161,8 +163,8 @@ module axi_ad9434_core #(
.DRP_DISABLE(0),
.USERPORTS_DISABLE(1),
.GPIO_DISABLE(1),
.START_CODE_DISABLE(1))
i_adc_common(
.START_CODE_DISABLE(1)
) i_adc_common(
.mmcm_rst (mmcm_rst),
.adc_clk (adc_clk),
@ -216,8 +218,8 @@ module axi_ad9434_core #(
.USERPORTS_DISABLE(1),
.DATAFORMAT_DISABLE(0),
.DCFILTER_DISABLE(1),
.IQCORRECTION_DISABLE(1))
i_adc_channel(
.IQCORRECTION_DISABLE(1)
) i_adc_channel(
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),
@ -265,7 +267,10 @@ module axi_ad9434_core #(
// adc delay control
up_delay_cntrl #(.DATA_WIDTH(13), .BASE_ADDRESS(6'h02)) i_delay_cntrl (
up_delay_cntrl #(
.DATA_WIDTH(13),
.BASE_ADDRESS(6'h02)
) i_delay_cntrl (
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked),

19
library/axi_ad9434/axi_ad9434_if.v
View File

@ -38,7 +38,8 @@
module axi_ad9434_if #(
parameter FPGA_TECHNOLOGY = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group") (
parameter IO_DELAY_GROUP = "dev_if_delay_group"
) (
// device interface
input adc_clk_in_p,
@ -77,8 +78,8 @@ module axi_ad9434_if #(
input [31:0] up_drp_wdata,
output [31:0] up_drp_rdata,
output up_drp_ready,
output up_drp_locked);
output up_drp_locked
);
localparam SDR = 0;
@ -105,8 +106,8 @@ module axi_ad9434_if #(
.IODELAY_GROUP(IO_DELAY_GROUP),
.DDR_OR_SDR_N(SDR),
.DATA_WIDTH(12),
.SERDES_FACTOR(4))
i_adc_data (
.SERDES_FACTOR(4)
) i_adc_data (
.rst(adc_rst),
.clk(adc_clk_in),
.div_clk(adc_div_clk),
@ -138,8 +139,8 @@ module axi_ad9434_if #(
.IODELAY_GROUP(IO_DELAY_GROUP),
.DDR_OR_SDR_N(SDR),
.DATA_WIDTH(1),
.SERDES_FACTOR(4))
i_adc_or (
.SERDES_FACTOR(4)
) i_adc_or (
.rst(adc_rst),
.clk(adc_clk_in),
.div_clk(adc_div_clk),
@ -174,8 +175,8 @@ module axi_ad9434_if #(
.MMCM_VCO_MUL (12),
.MMCM_CLK0_DIV (2),
.MMCM_CLK1_DIV (8),
.SERDES_FACTOR(4))
i_serdes_clk (
.SERDES_FACTOR(4)
) i_serdes_clk (
.rst (mmcm_rst),
.clk_in_p (adc_clk_in_p),
.clk_in_n (adc_clk_in_n),

7
library/axi_ad9434/axi_ad9434_pnmon.v
View File

@ -44,7 +44,8 @@ module axi_ad9434_pnmon (
// pn interface
input [ 3:0] adc_pnseq_sel,
output adc_pn_err,
output adc_pn_oos);
output adc_pn_oos
);
// internal registers
reg [47:0] adc_pn_data_pn = 'd0;
@ -181,7 +182,9 @@ module axi_ad9434_pnmon (
end
// pn oos & pn err
ad_pnmon #(.DATA_WIDTH(48)) i_pnmon (
ad_pnmon #(
.DATA_WIDTH(48)
) i_pnmon (
.adc_clk (adc_clk),
.adc_valid_in (1'b1),
.adc_data_in (adc_data_inv_s),

27
library/axi_ad9467/axi_ad9467.v
View File

@ -43,7 +43,8 @@ module axi_ad9467#(
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group",
parameter DELAY_REFCLK_FREQUENCY = 200) (
parameter DELAY_REFCLK_FREQUENCY = 200
) (
// physical interface
@ -88,8 +89,8 @@ module axi_ad9467#(
output s_axi_rvalid,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
input s_axi_rready);
input s_axi_rready
);
// internal registers
@ -150,8 +151,8 @@ module axi_ad9467#(
axi_ad9467_if #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IO_DELAY_GROUP (IO_DELAY_GROUP),
.DELAY_REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
i_if (
.DELAY_REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
) i_if (
.adc_clk_in_p (adc_clk_in_p),
.adc_clk_in_n (adc_clk_in_n),
.adc_data_in_p (adc_data_in_p),
@ -172,7 +173,9 @@ module axi_ad9467#(
// channel
axi_ad9467_channel #(.CHANNEL_ID(0)) i_channel (
axi_ad9467_channel #(
.CHANNEL_ID(0)
) i_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data (adc_data_s),
@ -195,7 +198,10 @@ module axi_ad9467#(
// adc delay control
up_delay_cntrl #(.DATA_WIDTH(9), .BASE_ADDRESS(6'h02)) i_delay_cntrl (
up_delay_cntrl #(
.DATA_WIDTH(9),
.BASE_ADDRESS(6'h02)
) i_delay_cntrl (
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked_s),
@ -226,8 +232,8 @@ module axi_ad9467#(
.DRP_DISABLE (6'h00),
.USERPORTS_DISABLE (0),
.GPIO_DISABLE (0),
.START_CODE_DISABLE(0))
i_up_adc_common (
.START_CODE_DISABLE(0)
) i_up_adc_common (
.mmcm_rst (),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
@ -305,6 +311,3 @@ module axi_ad9467#(
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************

18
library/axi_ad9467/axi_ad9467_channel.v
View File

@ -37,7 +37,8 @@
module axi_ad9467_channel#(
parameter CHANNEL_ID = 0) (
parameter CHANNEL_ID = 0
) (
// adc interface
@ -65,8 +66,8 @@ module axi_ad9467_channel#(
input up_rreq,
input [13:0] up_raddr,
output [31:0] up_rdata,
output up_rack);
output up_rack
);
// internal signals
@ -86,7 +87,9 @@ module axi_ad9467_channel#(
.adc_pn_err (adc_pn_err_s),
.adc_pnseq_sel (adc_pnseq_sel_s));
ad_datafmt #(.DATA_WIDTH(16)) i_datafmt (
ad_datafmt #(
.DATA_WIDTH(16)
) i_datafmt (
.clk(adc_clk),
.valid(1'b1),
.data(adc_data),
@ -102,8 +105,8 @@ module axi_ad9467_channel#(
.USERPORTS_DISABLE (0),
.DATAFORMAT_DISABLE (0),
.DCFILTER_DISABLE (0),
.IQCORRECTION_DISABLE (0))
i_up_adc_channel (
.IQCORRECTION_DISABLE (0)
) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),
@ -150,6 +153,3 @@ module axi_ad9467_channel#(
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************

21
library/axi_ad9467/axi_ad9467_if.v
View File

@ -40,7 +40,8 @@ module axi_ad9467_if #(
parameter FPGA_TECHNOLOGY = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group",
parameter DELAY_REFCLK_FREQUENCY = 200) (
parameter DELAY_REFCLK_FREQUENCY = 200
) (
// adc interface (clk, data, over-range)
@ -69,8 +70,8 @@ module axi_ad9467_if #(
output [44:0] up_drdata,
input delay_clk,
input delay_rst,
output delay_locked);
output delay_locked
);
// internal registers
@ -132,8 +133,8 @@ module axi_ad9467_if #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
i_adc_data (
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
) i_adc_data (
.rx_clk (adc_clk),
.rx_data_in_p (adc_data_in_p[l_inst]),
.rx_data_in_n (adc_data_in_n[l_inst]),
@ -155,8 +156,8 @@ module axi_ad9467_if #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_CTRL (1),
.IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
i_adc_or (
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
) i_adc_or (
.rx_clk (adc_clk),
.rx_data_in_p (adc_or_in_p),
.rx_data_in_n (adc_or_in_n),
@ -172,8 +173,7 @@ module axi_ad9467_if #(
// clock
ad_data_clk
i_adc_clk (
ad_data_clk i_adc_clk (
.rst (1'b0),
.locked (),
.clk_in_p (adc_clk_in_p),
@ -181,6 +181,3 @@ module axi_ad9467_if #(
.clk (adc_clk));
endmodule
// ***************************************************************************
// ***************************************************************************

11
library/axi_ad9467/axi_ad9467_pnmon.v
View File

@ -47,7 +47,8 @@ module axi_ad9467_pnmon (
output adc_pn_oos,
output adc_pn_err,
input [ 3:0] adc_pnseq_sel);
input [ 3:0] adc_pnseq_sel
);
// internal registers
@ -161,7 +162,9 @@ module axi_ad9467_pnmon (
// pn oos & pn err
ad_pnmon #(.DATA_WIDTH(32)) i_pnmon (
ad_pnmon #(
.DATA_WIDTH(32)
) i_pnmon (
.adc_clk (adc_clk),
.adc_valid_in (adc_valid_in),
.adc_data_in (adc_pn_data_in),
@ -171,7 +174,3 @@ module axi_ad9467_pnmon (
.adc_pn_err (adc_pn_err));
endmodule
// ***************************************************************************
// ***************************************************************************

18
library/axi_ad9625/axi_ad9625.v
View File

@ -42,7 +42,8 @@ module axi_ad9625 #(
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0,
parameter DELAY_REFCLK_FREQUENCY = 200) (
parameter DELAY_REFCLK_FREQUENCY = 200
) (
// jesd interface
// rx_clk is (line-rate/40)
@ -87,7 +88,8 @@ module axi_ad9625 #(
output [ 31:0] s_axi_rdata,
input s_axi_rready,
input [ 2:0] s_axi_awprot,
input [ 2:0] s_axi_arprot);
input [ 2:0] s_axi_arprot
);
// internal registers
@ -143,8 +145,8 @@ module axi_ad9625 #(
assign adc_valid = 1'b1;
axi_ad9625_if #(
.ID (ID))
i_if (
.ID (ID)
) i_if (
.rx_clk (rx_clk),
.rx_sof (rx_sof),
.rx_data (rx_data),
@ -194,8 +196,8 @@ module axi_ad9625 #(
.DRP_DISABLE(1),
.USERPORTS_DISABLE(1),
.GPIO_DISABLE(1),
.START_CODE_DISABLE(1))
i_up_adc_common (
.START_CODE_DISABLE(1)
) i_up_adc_common (
.mmcm_rst (),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
@ -270,7 +272,3 @@ module axi_ad9625 #(
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************

15
library/axi_ad9625/axi_ad9625_channel.v
View File

@ -63,7 +63,8 @@ module axi_ad9625_channel (
input up_rreq,
input [ 13:0] up_raddr,
output [ 31:0] up_rdata,
output up_rack);
output up_rack
);
// internal signals
@ -86,7 +87,9 @@ module axi_ad9625_channel (
genvar n;
generate
for (n = 0; n < 16; n = n + 1) begin: g_ad_datafmt_1
ad_datafmt #(.DATA_WIDTH(12)) i_ad_datafmt (
ad_datafmt #(
.DATA_WIDTH(12)
) i_ad_datafmt (
.clk (adc_clk),
.valid (1'b1),
.data (adc_data[n*12+11:n*12]),
@ -104,8 +107,8 @@ module axi_ad9625_channel (
.USERPORTS_DISABLE(1),
.DATAFORMAT_DISABLE(0),
.DCFILTER_DISABLE(1),
.IQCORRECTION_DISABLE(1))
i_up_adc_channel (
.IQCORRECTION_DISABLE(1)
) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),
@ -152,7 +155,3 @@ module axi_ad9625_channel (
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************

16
library/axi_ad9625/axi_ad9625_if.v
View File

@ -37,7 +37,9 @@
module axi_ad9625_if #(
parameter ID = 0) (
parameter ID = 0
) (
// jesd interface
// rx_clk is (line-rate/40)
@ -55,7 +57,8 @@ module axi_ad9625_if #(
output [ 15:0] adc_sref,
input adc_sref_sync,
input [ 3:0] adc_raddr_in,
output [ 3:0] adc_raddr_out);
output [ 3:0] adc_raddr_out
);
// internal registers
@ -207,7 +210,10 @@ module axi_ad9625_if #(
// alignment fifo
ad_mem #(.ADDRESS_WIDTH(4), .DATA_WIDTH(192)) i_mem (
ad_mem #(
.ADDRESS_WIDTH(4),
.DATA_WIDTH(192)
) i_mem (
.clka (rx_clk),
.wea (1'b1),
.addra (adc_waddr),
@ -232,7 +238,3 @@ module axi_ad9625_if #(
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************

11
library/axi_ad9625/axi_ad9625_pnmon.v
View File

@ -49,7 +49,8 @@ module axi_ad9625_pnmon (
// processor interface PN9 (0x0), PN23 (0x1)
input [ 3:0] adc_pnseq_sel);
input [ 3:0] adc_pnseq_sel
);
// internal registers
@ -494,7 +495,9 @@ module axi_ad9625_pnmon (
// pn oos & pn error
ad_pnmon #(.DATA_WIDTH(192)) i_pnmon (
ad_pnmon #(
.DATA_WIDTH(192)
) i_pnmon (
.adc_clk (adc_clk),
.adc_valid_in (1'b1),
.adc_data_in (adc_pn_data_in),
@ -503,7 +506,3 @@ module axi_ad9625_pnmon (
.adc_pn_err (adc_pn_err));
endmodule
// ***************************************************************************
// ***************************************************************************

18
library/axi_ad9671/axi_ad9671.v
View File

@ -42,7 +42,8 @@ module axi_ad9671 #(
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0,
parameter QUAD_OR_DUAL_N = 1) (
parameter QUAD_OR_DUAL_N = 1
) (
// jesd interface
// rx_clk is (line-rate/40)
@ -87,8 +88,8 @@ module axi_ad9671 #(
output s_axi_rvalid,
output [ 1:0] s_axi_rresp,
output [ 31:0] s_axi_rdata,
input s_axi_rready);
input s_axi_rready
);
// internal registers
@ -159,8 +160,8 @@ module axi_ad9671 #(
axi_ad9671_if #(
.QUAD_OR_DUAL_N (QUAD_OR_DUAL_N),
.ID (ID))
i_if (
.ID (ID)
) i_if (
.rx_clk (rx_clk),
.rx_data (rx_data),
.rx_sof (rx_sof),
@ -197,7 +198,9 @@ module axi_ad9671 #(
genvar n;
generate
for (n = 0; n < 8; n = n + 1) begin: g_channel
axi_ad9671_channel #(.CHANNEL_ID(n)) i_channel (
axi_ad9671_channel #(
.CHANNEL_ID(n)
) i_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_valid (adc_valid_s),
@ -302,6 +305,3 @@ module axi_ad9671 #(
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************

19
library/axi_ad9671/axi_ad9671_channel.v
View File

@ -38,7 +38,8 @@
module axi_ad9671_channel #(
parameter CHANNEL_ID = 0) (
parameter CHANNEL_ID = 0
) (
// adc interface
@ -68,8 +69,8 @@ module axi_ad9671_channel #(
input up_rreq,
input [13:0] up_raddr,
output [31:0] up_rdata,
output up_rack);
output up_rack
);
// internal signals
@ -90,7 +91,9 @@ module axi_ad9671_channel #(
.adc_pn_err (adc_pn_err_s),
.adc_pnseq_sel (adc_pnseq_sel_s));
ad_datafmt #(.DATA_WIDTH(16)) i_ad_datafmt (
ad_datafmt #(
.DATA_WIDTH(16)
) i_ad_datafmt (
.clk (adc_clk),
.valid (adc_valid),
.data (adc_data),
@ -100,7 +103,9 @@ module axi_ad9671_channel #(
.dfmt_type (adc_dfmt_type_s),
.dfmt_se (adc_dfmt_se_s));
up_adc_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel (
up_adc_channel #(
.CHANNEL_ID(CHANNEL_ID)
) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),
@ -147,7 +152,3 @@ module axi_ad9671_channel #(
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************

16
library/axi_ad9671/axi_ad9671_if.v
View File

@ -38,7 +38,8 @@
module axi_ad9671_if #(
parameter QUAD_OR_DUAL_N = 1,
parameter ID = 0) (
parameter ID = 0
) (
// jesd interface
// rx_clk is (line-rate/40)
@ -75,8 +76,8 @@ module axi_ad9671_if #(
output reg adc_sync_status,
output reg adc_status,
input [ 3:0] adc_raddr_in,
output reg [ 3:0] adc_raddr_out);
output reg [ 3:0] adc_raddr_out
);
// internal wires
@ -184,7 +185,10 @@ module axi_ad9671_if #(
end
end
ad_mem #(.ADDRESS_WIDTH(4), .DATA_WIDTH(128)) i_mem (
ad_mem #(
.ADDRESS_WIDTH(4),
.DATA_WIDTH(128)
) i_mem (
.clka(rx_clk),
.wea(int_valid),
.addra(adc_waddr),
@ -210,7 +214,3 @@ module axi_ad9671_if #(
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************

11
library/axi_ad9671/axi_ad9671_pnmon.v
View File

@ -48,7 +48,8 @@ module axi_ad9671_pnmon (
output adc_pn_oos,
output adc_pn_err,
input [ 3:0] adc_pnseq_sel);
input [ 3:0] adc_pnseq_sel
);
// internal registers
@ -166,7 +167,9 @@ module axi_ad9671_pnmon (
// pn oos & pn err
ad_pnmon #(.DATA_WIDTH(32)) i_pnmon (
ad_pnmon #(
.DATA_WIDTH(32)
) i_pnmon (
.adc_clk (adc_clk),
.adc_valid_in (adc_pn_valid_s),
.adc_data_in (adc_pn_data_in),
@ -175,7 +178,3 @@ module axi_ad9671_pnmon (
.adc_pn_err (adc_pn_err));
endmodule
// ***************************************************************************
// ***************************************************************************

27
library/axi_ad9684/axi_ad9684.v
View File

@ -43,7 +43,8 @@ module axi_ad9684 #(
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group",
parameter OR_STATUS = 1) (
parameter OR_STATUS = 1
) (
// device interface ports
@ -92,8 +93,8 @@ module axi_ad9684 #(
output s_axi_rvalid,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
input s_axi_rready);
input s_axi_rready
);
// internal registers
@ -168,8 +169,8 @@ module axi_ad9684 #(
axi_ad9684_if #(
.FPGA_TECHNOLOGY(FPGA_TECHNOLOGY),
.IO_DELAY_GROUP(IO_DELAY_GROUP),
.OR_STATUS (OR_STATUS))
i_ad9684_if (
.OR_STATUS (OR_STATUS)
) i_ad9684_if (
.adc_clk_in_p (adc_clk_in_p),
.adc_clk_in_n (adc_clk_in_n),
.adc_data_in_p (adc_data_in_p),
@ -217,8 +218,8 @@ module axi_ad9684 #(
.DRP_DISABLE (6'h00),
.USERPORTS_DISABLE (0),
.GPIO_DISABLE (0),
.START_CODE_DISABLE(0))
i_up_adc_common (
.START_CODE_DISABLE(0)
) i_up_adc_common (
.mmcm_rst (rst_s),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
@ -265,8 +266,8 @@ module axi_ad9684 #(
axi_ad9684_channel #(
.CHANNEL_ID (0),
.Q_OR_I_N (0))
i_channel_0 (
.Q_OR_I_N (0)
) i_channel_0 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data (adc_rawdata_0_s),
@ -293,8 +294,8 @@ module axi_ad9684 #(
axi_ad9684_channel #(
.CHANNEL_ID (1),
.Q_OR_I_N (1))
i_channel_1 (
.Q_OR_I_N (1)
) i_channel_1 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data (adc_rawdata_1_s),
@ -320,8 +321,8 @@ module axi_ad9684 #(
// adc delay control instance
up_delay_cntrl #(
.DATA_WIDTH(15))
i_delay_cntrl (
.DATA_WIDTH(15)
) i_delay_cntrl (
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked_s),

16
library/axi_ad9684/axi_ad9684_channel.v
View File

@ -39,7 +39,8 @@ module axi_ad9684_channel #(
parameter Q_OR_I_N = 0,
parameter CHANNEL_ID = 0,
parameter DATAPATH_DISABLE = 0) (
parameter DATAPATH_DISABLE = 0
) (
// adc data interface
@ -69,8 +70,8 @@ module axi_ad9684_channel #(
input up_rreq,
input [13:0] up_raddr,
output [31:0] up_rdata,
output up_rack);
output up_rack
);
// internal signals
@ -94,7 +95,9 @@ module axi_ad9684_channel #(
genvar n;
generate
for (n = 0; n < 2; n = n + 1) begin: g_ad_datafmt_1
ad_datafmt #(.DATA_WIDTH(14)) i_ad_datafmt (
ad_datafmt #(
.DATA_WIDTH(14)
) i_ad_datafmt (
.clk (adc_clk),
.valid (1'b1),
.data (adc_data[n*14+13:n*14]),
@ -114,8 +117,8 @@ module axi_ad9684_channel #(
.USERPORTS_DISABLE (0),
.DATAFORMAT_DISABLE (0),
.DCFILTER_DISABLE (0),
.IQCORRECTION_DISABLE (0))
i_up_adc_channel (
.IQCORRECTION_DISABLE (0)
) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),
@ -162,4 +165,3 @@ module axi_ad9684_channel #(
.up_rack (up_rack));
endmodule

19
library/axi_ad9684/axi_ad9684_if.v
View File

@ -39,7 +39,8 @@ module axi_ad9684_if #(
parameter FPGA_TECHNOLOGY = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group",
parameter OR_STATUS = 0) (
parameter OR_STATUS = 0
) (
// device interface
input adc_clk_in_p,
@ -78,8 +79,8 @@ module axi_ad9684_if #(
input [31:0] up_drp_wdata,
output [31:0] up_drp_rdata,
output up_drp_ready,
output up_drp_locked);
output up_drp_locked
);
localparam DDR_OR_SDR_N = 1;
@ -110,8 +111,8 @@ module axi_ad9684_if #(
.IODELAY_CTRL(1),
.IODELAY_GROUP(IO_DELAY_GROUP),
.DDR_OR_SDR_N(DDR_OR_SDR_N),
.DATA_WIDTH(14))
i_adc_data (
.DATA_WIDTH(14)
) i_adc_data (
.rst(adc_rst),
.clk(adc_clk_in),
.div_clk(adc_div_clk),
@ -143,8 +144,8 @@ module axi_ad9684_if #(
.IODELAY_CTRL(0),
.IODELAY_GROUP(IO_DELAY_GROUP),
.DDR_OR_SDR_N(DDR_OR_SDR_N),
.DATA_WIDTH(1))
i_adc_or (
.DATA_WIDTH(1)
) i_adc_or (
.rst(adc_rst),
.clk(adc_clk_in),
.div_clk(adc_div_clk),
@ -188,8 +189,8 @@ module axi_ad9684_if #(
.MMCM_VCO_DIV (6),
.MMCM_VCO_MUL (12),
.MMCM_CLK0_DIV (2),
.MMCM_CLK1_DIV (4))
i_serdes_clk (
.MMCM_CLK1_DIV (4)
) i_serdes_clk (
.rst (rst),
.clk_in_p (adc_clk_in_p),
.clk_in_n (adc_clk_in_n),

11
library/axi_ad9684/axi_ad9684_pnmon.v
View File

@ -50,7 +50,8 @@ module axi_ad9684_pnmon (
// processor interface PN9 (0x0), PN23 (0x1)
input [ 3:0] adc_pnseq_sel);
input [ 3:0] adc_pnseq_sel
);
// internal registers
@ -159,7 +160,9 @@ module axi_ad9684_pnmon (
// pn oos & pn err
ad_pnmon #(.DATA_WIDTH(28)) i_pnmon (
ad_pnmon #(
.DATA_WIDTH(28)
) i_pnmon (
.adc_clk (adc_clk),
.adc_valid_in (1'b1),
.adc_data_in (adc_pn_data_in),
@ -168,7 +171,3 @@ module axi_ad9684_pnmon (
.adc_pn_err (adc_pn_err));
endmodule
// ***************************************************************************
// ***************************************************************************

18
library/axi_ad9739a/axi_ad9739a.v
View File

@ -48,7 +48,8 @@ module axi_ad9739a #(
parameter DAC_DDS_CORDIC_DW = 16,
parameter DAC_DDS_CORDIC_PHASE_DW = 16,
parameter DAC_DATAPATH_DISABLE = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group") (
parameter IO_DELAY_GROUP = "dev_if_delay_group"
) (
// dac interface
@ -91,8 +92,8 @@ module axi_ad9739a #(
output [ 1:0] s_axi_rresp,
input s_axi_rready,
input [ 2:0] s_axi_awprot,
input [ 2:0] s_axi_arprot);
input [ 2:0] s_axi_arprot
);
// internal clocks and resets
@ -135,7 +136,9 @@ module axi_ad9739a #(
// device interface
axi_ad9739a_if #(.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY)) i_if (
axi_ad9739a_if #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY)
) i_if (
.dac_clk_in_p (dac_clk_in_p),
.dac_clk_in_n (dac_clk_in_n),
.dac_clk_out_p (dac_clk_out_p),
@ -176,8 +179,8 @@ module axi_ad9739a #(
.DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.DATAPATH_DISABLE(DAC_DATAPATH_DISABLE))
i_core (
.DATAPATH_DISABLE(DAC_DATAPATH_DISABLE)
) i_core (
.dac_div_clk (dac_div_clk),
.dac_rst (dac_rst),
.dac_data_00 (dac_data_00_s),
@ -244,6 +247,3 @@ module axi_ad9739a #(
.up_rack (up_rack_s));
endmodule
// ***************************************************************************
// ***************************************************************************

18
library/axi_ad9739a/axi_ad9739a_channel.v
View File

@ -41,7 +41,8 @@ module axi_ad9739a_channel #(
parameter DAC_DDS_TYPE = 1,
parameter DAC_DDS_CORDIC_DW = 16,
parameter DAC_DDS_CORDIC_PHASE_DW = 16,
parameter DATAPATH_DISABLE = 0) (
parameter DATAPATH_DISABLE = 0
) (
// dac interface
@ -82,8 +83,8 @@ module axi_ad9739a_channel #(
input up_rreq,
input [ 13:0] up_raddr,
output [ 31:0] up_rdata,
output up_rack);
output up_rack
);
// internal signals
@ -169,8 +170,8 @@ module axi_ad9739a_channel #(
.DDS_TYPE (DAC_DDS_TYPE),
.CORDIC_DW (DAC_DDS_CORDIC_DW),
.CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.CLK_RATIO (16))
i_dds (
.CLK_RATIO (16)
) i_dds (
.clk (dac_div_clk),
.dac_dds_format (dac_dds_format),
.dac_data_sync (dac_data_sync),
@ -185,7 +186,9 @@ module axi_ad9739a_channel #(
// single channel processor
up_dac_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel (
up_dac_channel #(
.CHANNEL_ID(CHANNEL_ID)
) i_up_dac_channel (
.dac_clk (dac_div_clk),
.dac_rst (dac_rst),
.dac_dds_scale_1 (dac_dds_scale_1_s),
@ -227,6 +230,3 @@ module axi_ad9739a_channel #(
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************

14
library/axi_ad9739a/axi_ad9739a_core.v
View File

@ -45,7 +45,8 @@ module axi_ad9739a_core #(
parameter DAC_DDS_TYPE = 1,
parameter DAC_DDS_CORDIC_DW = 16,
parameter DAC_DDS_CORDIC_PHASE_DW = 16,
parameter DATAPATH_DISABLE = 0) (
parameter DATAPATH_DISABLE = 0
) (
// dac interface
@ -87,8 +88,8 @@ module axi_ad9739a_core #(
input up_rreq,
input [ 13:0] up_raddr,
output reg [ 31:0] up_rdata,
output reg up_rack);
output reg up_rack
);
// internal registers
@ -128,8 +129,8 @@ module axi_ad9739a_core #(
.DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.DATAPATH_DISABLE(DATAPATH_DISABLE))
i_channel_0 (
.DATAPATH_DISABLE(DATAPATH_DISABLE)
) i_channel_0 (
.dac_div_clk (dac_div_clk),
.dac_rst (dac_rst),
.dac_enable (dac_enable),
@ -213,6 +214,3 @@ module axi_ad9739a_core #(
.up_rack (up_rack_s));
endmodule
// ***************************************************************************
// ***************************************************************************

26
library/axi_ad9739a/axi_ad9739a_if.v
View File

@ -39,7 +39,8 @@
module axi_ad9739a_if #(
parameter FPGA_TECHNOLOGY = 0) (
parameter FPGA_TECHNOLOGY = 0
) (
// dac interface
@ -76,8 +77,8 @@ module axi_ad9739a_if #(
input [15:0] dac_data_12,
input [15:0] dac_data_13,
input [15:0] dac_data_14,
input [15:0] dac_data_15);
input [15:0] dac_data_15
);
// internal registers
@ -102,8 +103,8 @@ module axi_ad9739a_if #(
.DDR_OR_SDR_N(1),
.DATA_WIDTH(14),
.SERDES_FACTOR(8),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY))
i_serdes_out_data_a (
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY)
) i_serdes_out_data_a (
.rst (dac_rst),
.clk (dac_clk),
.div_clk (dac_div_clk),
@ -127,8 +128,8 @@ module axi_ad9739a_if #(
.DDR_OR_SDR_N(1),
.DATA_WIDTH(14),
.SERDES_FACTOR(8),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY))
i_serdes_out_data_b (
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY)
) i_serdes_out_data_b (
.rst (dac_rst),
.clk (dac_clk),
.div_clk (dac_div_clk),
@ -152,8 +153,8 @@ module axi_ad9739a_if #(
.DDR_OR_SDR_N(1),
.DATA_WIDTH(1),
.SERDES_FACTOR(8),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY))
i_serdes_out_clk (
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY)
) i_serdes_out_clk (
.rst (dac_rst),
.clk (dac_clk),
.div_clk (dac_div_clk),
@ -182,7 +183,9 @@ module axi_ad9739a_if #(
.I (dac_clk_in_s),
.O (dac_clk));
BUFR #(.BUFR_DIVIDE("4")) i_dac_div_clk_rbuf (
BUFR #(
.BUFR_DIVIDE("4")
) i_dac_div_clk_rbuf (
.CLR (1'b0),
.CE (1'b1),
.I (dac_clk_in_s),
@ -193,6 +196,3 @@ module axi_ad9739a_if #(
.O (dac_div_clk));
endmodule
// ***************************************************************************
// ***************************************************************************

18
library/axi_ad9783/axi_ad9783.v
View File

@ -45,7 +45,8 @@ module axi_ad9783 #(
parameter DAC_DDS_TYPE = 2,
parameter DAC_DDS_CORDIC_DW = 16,
parameter DAC_DDS_CORDIC_PHASE_DW = 16,
parameter DAC_DATAPATH_DISABLE = 0) (
parameter DAC_DATAPATH_DISABLE = 0
) (
// dac interface
// from dco1_p
@ -92,8 +93,8 @@ module axi_ad9783 #(
output [ 1:0] s_axi_rresp,
input s_axi_rready,
input [ 2:0] s_axi_awprot,
input [ 2:0] s_axi_arprot);
input [ 2:0] s_axi_arprot
);
// internal clocks and resets
@ -130,8 +131,8 @@ module axi_ad9783 #(
// device interface
axi_ad9783_if #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY))
i_if (
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY)
) i_if (
.dac_clk_in_p (dac_clk_in_p),
.dac_clk_in_n (dac_clk_in_n),
.dac_clk_out_p (dac_clk_out_p),
@ -161,8 +162,8 @@ module axi_ad9783 #(
.DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.DATAPATH_DISABLE(DAC_DATAPATH_DISABLE))
i_core (
.DATAPATH_DISABLE(DAC_DATAPATH_DISABLE)
) i_core (
.dac_div_clk (dac_div_clk),
.dac_rst (dac_rst_s),
.dac_data_a0 (dac_data_a0_s),
@ -223,6 +224,3 @@ module axi_ad9783 #(
.up_rack (up_rack_s));
endmodule
// ***************************************************************************
// ***************************************************************************

19
library/axi_ad9783/axi_ad9783_channel.v
View File

@ -41,7 +41,8 @@ module axi_ad9783_channel #(
parameter DAC_DDS_TYPE = 1,
parameter DAC_DDS_CORDIC_DW = 16,
parameter DAC_DDS_CORDIC_PHASE_DW = 16,
parameter DATAPATH_DISABLE = 0) (
parameter DATAPATH_DISABLE = 0
) (
// dac interface
@ -70,8 +71,8 @@ module axi_ad9783_channel #(
input up_rreq,
input [13:0] up_raddr,
output [31:0] up_rdata,
output up_rack);
output up_rack
);
// internal signals
@ -89,7 +90,6 @@ module axi_ad9783_channel #(
reg [23:0] dac_prbs_data = 'd0;
reg [15:0] dac_prbs_counter = 'd0;
// pn23 function
function [23:0] pn23;
input [23:0] din;
@ -155,8 +155,8 @@ module axi_ad9783_channel #(
.DDS_TYPE (DAC_DDS_TYPE),
.CORDIC_DW (DAC_DDS_CORDIC_DW),
.CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.CLK_RATIO (4))
i_dds (
.CLK_RATIO (4)
) i_dds (
.clk (dac_div_clk),
.dac_dds_format (dac_dds_format),
.dac_data_sync (dac_data_sync),
@ -172,8 +172,8 @@ module axi_ad9783_channel #(
// single channel processor
up_dac_channel #(
.CHANNEL_ID(CHANNEL_ID))
i_up_dac_channel (
.CHANNEL_ID(CHANNEL_ID)
) i_up_dac_channel (
.dac_clk (dac_div_clk),
.dac_rst (dac_rst),
.dac_dds_scale_1 (dac_dds_scale_1_s),
@ -215,6 +215,3 @@ module axi_ad9783_channel #(
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************

22
library/axi_ad9783/axi_ad9783_core.v
View File

@ -45,7 +45,8 @@ module axi_ad9783_core #(
parameter DAC_DDS_TYPE = 1,
parameter DAC_DDS_CORDIC_DW = 16,
parameter DAC_DDS_CORDIC_PHASE_DW = 16,
parameter DATAPATH_DISABLE = 0) (
parameter DATAPATH_DISABLE = 0
) (
// dac interface
@ -81,8 +82,8 @@ module axi_ad9783_core #(
input up_rreq,
input [ 13:0] up_raddr,
output reg [ 31:0] up_rdata,
output reg up_rack);
output reg up_rack
);
// internal registers
@ -129,8 +130,8 @@ module axi_ad9783_core #(
.DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.DATAPATH_DISABLE(DATAPATH_DISABLE))
i_channel_0 (
.DATAPATH_DISABLE(DATAPATH_DISABLE)
) i_channel_0 (
.dac_div_clk (dac_div_clk),
.dac_rst (dac_rst),
.dac_enable (dac_enable_0_reg),
@ -157,8 +158,8 @@ module axi_ad9783_core #(
.DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.DATAPATH_DISABLE(DATAPATH_DISABLE))
i_channel_1 (
.DATAPATH_DISABLE(DATAPATH_DISABLE)
) i_channel_1 (
.dac_div_clk (dac_div_clk),
.dac_rst (dac_rst),
.dac_enable (dac_enable_1_reg),
@ -187,8 +188,8 @@ module axi_ad9783_core #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE))
i_up_dac_common (
.DEV_PACKAGE (DEV_PACKAGE)
) i_up_dac_common (
.mmcm_rst (),
.dac_clk (dac_div_clk),
.dac_rst (dac_rst),
@ -230,6 +231,3 @@ module axi_ad9783_core #(
.up_rack (up_rack_s));
endmodule
// ***************************************************************************
// ***************************************************************************

22
library/axi_ad9783/axi_ad9783_if.v
View File

@ -39,7 +39,8 @@
module axi_ad9783_if #(
parameter FPGA_TECHNOLOGY = 0) (
parameter FPGA_TECHNOLOGY = 0
) (
// dac interface
@ -65,8 +66,8 @@ module axi_ad9783_if #(
input [15:0] dac_data_b0,
input [15:0] dac_data_b1,
input [15:0] dac_data_b2,
input [15:0] dac_data_b3);
input [15:0] dac_data_b3
);
// internal registers
@ -92,8 +93,8 @@ module axi_ad9783_if #(
.DDR_OR_SDR_N(1),
.DATA_WIDTH(16),
.SERDES_FACTOR(8),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY))
i_serdes_out_data (
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY)
) i_serdes_out_data (
.rst (dac_rst),
.clk (dac_clk_s),
.div_clk (dac_div_clk),
@ -117,8 +118,8 @@ module axi_ad9783_if #(
.DDR_OR_SDR_N(1),
.DATA_WIDTH(1),
.SERDES_FACTOR(8),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY))
i_serdes_out_clk (
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY)
) i_serdes_out_clk (
.rst (dac_rst),
.clk (dac_clk_s),
.div_clk (dac_div_clk),
@ -147,8 +148,8 @@ module axi_ad9783_if #(
.BUFGCE_DIVIDE (4),
.IS_CE_INVERTED (1'b0),
.IS_CLR_INVERTED (1'b0),
.IS_I_INVERTED (1'b0))
i_dac_div_clk_rbuf (
.IS_I_INVERTED (1'b0)
) i_dac_div_clk_rbuf (
.O (dac_div_clk_s),
.CE (1'b1),
.CLR (1'b0),
@ -159,6 +160,3 @@ module axi_ad9783_if #(
.O (dac_div_clk));
endmodule
// ***************************************************************************
// ***************************************************************************

17
library/axi_ad9963/axi_ad9963.v
View File

@ -56,7 +56,8 @@ module axi_ad9963 #(
parameter ADC_DCFILTER_DISABLE = 0,
parameter ADC_IQCORRECTION_DISABLE = 0,
parameter ADC_SCALECORRECTION_ONLY = 1,
parameter DELAY_REFCLK_FREQUENCY = 200) (
parameter DELAY_REFCLK_FREQUENCY = 200
) (
// physical interface (receive)
@ -130,7 +131,8 @@ module axi_ad9963 #(
output s_axi_rvalid,
output [31:0] s_axi_rdata,
output [ 1:0] s_axi_rresp,
input s_axi_rready);
input s_axi_rready
);
// internal registers
@ -189,8 +191,8 @@ module axi_ad9963 #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.ADC_IODELAY_ENABLE (ADC_IODELAY_ENABLE),
.IO_DELAY_GROUP (IO_DELAY_GROUP),
.DELAY_REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
i_dev_if (
.DELAY_REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
) i_dev_if (
.trx_clk (trx_clk),
.trx_iq (trx_iq),
.trx_data (trx_data),
@ -274,8 +276,8 @@ module axi_ad9963 #(
.DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.DATAPATH_DISABLE (DAC_DATAPATH_DISABLE))
i_tx (
.DATAPATH_DISABLE (DAC_DATAPATH_DISABLE)
) i_tx (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_data (dac_data_s),
@ -337,6 +339,3 @@ module axi_ad9963 #(
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************

41
library/axi_ad9963/axi_ad9963_if.v
View File

@ -42,7 +42,8 @@ module axi_ad9963_if #(
parameter FPGA_TECHNOLOGY = 0,
parameter ADC_IODELAY_ENABLE = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group",
parameter DELAY_REFCLK_FREQUENCY = 200) (
parameter DELAY_REFCLK_FREQUENCY = 200
) (
// physical interface (receive)
@ -86,7 +87,8 @@ module axi_ad9963_if #(
output [64:0] up_adc_drdata,
input delay_clk,
input delay_rst,
output delay_locked);
output delay_locked
);
// internal registers
@ -152,8 +154,7 @@ module axi_ad9963_if #(
.INIT_OUT(0),
.PRESELECT_I0("FALSE"),
.PRESELECT_I1("FALSE")
)
bufgctrl_adc (
) bufgctrl_adc (
.O(adc_clk),
.CE0(1'b1),
.CE1(1'b0),
@ -162,8 +163,7 @@ module axi_ad9963_if #(
.IGNORE0(1'b0),
.IGNORE1(1'b0),
.S0(up_adc_ce),
.S1(1'b0)
);
.S1(1'b0));
// receive data interface, ibuf -> idelay -> iddr
@ -175,8 +175,8 @@ module axi_ad9963_if #(
.IODELAY_ENABLE (ADC_IODELAY_ENABLE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
i_rx_data (
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
) i_rx_data (
.rx_clk (adc_clk),
.rx_data_in_p (trx_data[l_inst]),
.rx_data_in_n (1'b0),
@ -199,8 +199,8 @@ module axi_ad9963_if #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_ENABLE (ADC_IODELAY_ENABLE),
.IODELAY_CTRL (1),
.IODELAY_GROUP (IO_DELAY_GROUP))
i_rx_iq (
.IODELAY_GROUP (IO_DELAY_GROUP)
) i_rx_iq (
.rx_clk (adc_clk),
.rx_data_in_p (trx_iq),
.rx_data_in_n (1'b0),
@ -216,7 +216,9 @@ module axi_ad9963_if #(
// transmit data interface
BUFR #(.BUFR_DIVIDE(2)) i_div_clk_buf (
BUFR #(
.BUFR_DIVIDE(2)
) i_div_clk_buf (
.CLR (1'b0),
.CE (1'b1),
.I (tx_clk),
@ -226,8 +228,7 @@ module axi_ad9963_if #(
.INIT_OUT(0),
.PRESELECT_I0("FALSE"),
.PRESELECT_I1("FALSE")
)
bufgctrl_dac (
) bufgctrl_dac (
.O(dac_clk),
.CE0(1'b1),
.CE1(1'b0),
@ -236,16 +237,15 @@ module axi_ad9963_if #(
.IGNORE0(1'b0),
.IGNORE1(1'b0),
.S0(up_dac_ce),
.S1(1'b0)
);
.S1(1'b0));
generate
for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin: g_tx_data
ODDR #(
.DDR_CLK_EDGE ("SAME_EDGE"),
.INIT (1'b0),
.SRTYPE ("SYNC"))
i_tx_data_oddr (
.SRTYPE ("SYNC")
) i_tx_data_oddr (
.CE (1'b1),
.R (dac_rst),
.S (1'b0),
@ -259,8 +259,8 @@ module axi_ad9963_if #(
ODDR #(
.DDR_CLK_EDGE ("SAME_EDGE"),
.INIT (1'b0),
.SRTYPE ("SYNC"))
i_tx_data_oddr (
.SRTYPE ("SYNC")
) i_tx_data_oddr (
.CE (1'b1),
.R (dac_rst),
.S (1'b0),
@ -270,6 +270,3 @@ module axi_ad9963_if #(
.Q (tx_iq));
endmodule
// ***************************************************************************
// ***************************************************************************

23
library/axi_ad9963/axi_ad9963_rx.v
View File

@ -49,7 +49,8 @@ module axi_ad9963_rx #(
parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0) (
parameter DEV_PACKAGE = 0
) (
// adc interface
@ -91,7 +92,8 @@ module axi_ad9963_rx #(
input up_rreq,
input [13:0] up_raddr,
output reg [31:0] up_rdata,
output reg up_rack);
output reg up_rack
);
// configuration settings
@ -148,8 +150,8 @@ module axi_ad9963_rx #(
.DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
.DCFILTER_DISABLE (DCFILTER_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
.SCALECORRECTION_ONLY (SCALECORRECTION_ONLY))
i_rx_channel_0 (
.SCALECORRECTION_ONLY (SCALECORRECTION_ONLY)
) i_rx_channel_0 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_valid (adc_valid),
@ -183,8 +185,8 @@ module axi_ad9963_rx #(
.DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
.DCFILTER_DISABLE (DCFILTER_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
.SCALECORRECTION_ONLY (SCALECORRECTION_ONLY))
i_rx_channel_1 (
.SCALECORRECTION_ONLY (SCALECORRECTION_ONLY)
) i_rx_channel_1 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_valid (adc_valid),
@ -273,7 +275,10 @@ module axi_ad9963_rx #(
generate if (IODELAY_ENABLE == 1) begin
up_delay_cntrl #(.DATA_WIDTH(13), .BASE_ADDRESS(6'h02)) i_delay_cntrl (
up_delay_cntrl #(
.DATA_WIDTH(13),
.BASE_ADDRESS(6'h02)
) i_delay_cntrl (
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked),
@ -302,7 +307,3 @@ module axi_ad9963_rx #(
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************

21
library/axi_ad9963/axi_ad9963_rx_channel.v
View File

@ -45,7 +45,8 @@ module axi_ad9963_rx_channel #(
parameter DATAFORMAT_DISABLE = 0,
parameter DCFILTER_DISABLE = 0,
parameter IQCORRECTION_DISABLE = 0,
parameter SCALECORRECTION_ONLY = 1) (
parameter SCALECORRECTION_ONLY = 1
) (
// adc interface
@ -77,7 +78,8 @@ module axi_ad9963_rx_channel #(
input up_rreq,
input [13:0] up_raddr,
output [31:0] up_rdata,
output up_rack);
output up_rack
);
// internal signals
@ -116,7 +118,9 @@ module axi_ad9963_rx_channel #(
assign adc_dfmt_valid_s = adc_valid;
assign adc_dfmt_data_s = {{4{adc_data[11]}}, adc_data};
end else begin
ad_datafmt #(.DATA_WIDTH (12)) i_ad_datafmt (
ad_datafmt #(
.DATA_WIDTH (12)
) i_ad_datafmt (
.clk (adc_clk),
.valid (adc_valid),
.data (adc_data),
@ -145,10 +149,11 @@ module axi_ad9963_rx_channel #(
end
endgenerate
ad_iqcor #(.Q_OR_I_N (Q_OR_I_N),
ad_iqcor #(
.Q_OR_I_N (Q_OR_I_N),
.DISABLE(IQCORRECTION_DISABLE == 1),
.SCALE_ONLY(SCALECORRECTION_ONLY))
i_ad_iqcor (
.SCALE_ONLY(SCALECORRECTION_ONLY)
) i_ad_iqcor (
.clk (adc_clk),
.valid (adc_dcfilter_valid_s),
.data_in (adc_dcfilter_data_s),
@ -213,7 +218,3 @@ module axi_ad9963_rx_channel #(
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************

10
library/axi_ad9963/axi_ad9963_rx_pnmon.v
View File

@ -48,7 +48,8 @@ module axi_ad9963_rx_pnmon (
input [ 3:0] adc_pnseq_sel,
output adc_pn_oos,
output adc_pn_err);
output adc_pn_err
);
// internal registers
@ -105,7 +106,9 @@ module axi_ad9963_rx_pnmon (
// pn oos & pn err
ad_pnmon #(.DATA_WIDTH(24)) i_pnmon (
ad_pnmon #(
.DATA_WIDTH(24)
) i_pnmon (
.adc_clk (adc_clk),
.adc_valid_in (adc_valid),
.adc_data_in (adc_pn_data_in),
@ -115,6 +118,3 @@ module axi_ad9963_rx_pnmon (
.adc_pn_err (adc_pn_err));
endmodule
// ***************************************************************************
// ***************************************************************************

17
library/axi_ad9963/axi_ad9963_tx.v
View File

@ -47,7 +47,8 @@ module axi_ad9963_tx #(
parameter DAC_DDS_TYPE = 1,
parameter DAC_DDS_CORDIC_DW = 14,
parameter DAC_DDS_CORDIC_PHASE_DW = 13,
parameter DATAPATH_DISABLE = 0) (
parameter DATAPATH_DISABLE = 0
) (
// dac interface
@ -88,7 +89,8 @@ module axi_ad9963_tx #(
input up_rreq,
input [13:0] up_raddr,
output reg [31:0] up_rdata,
output reg up_rack);
output reg up_rack
);
// internal signals
@ -131,8 +133,8 @@ module axi_ad9963_tx #(
.DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.DATAPATH_DISABLE (DATAPATH_DISABLE))
i_tx_channel_0 (
.DATAPATH_DISABLE (DATAPATH_DISABLE)
) i_tx_channel_0 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_valid (dac_valid_i),
@ -165,8 +167,8 @@ module axi_ad9963_tx #(
.DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.DATAPATH_DISABLE (DATAPATH_DISABLE))
i_tx_channel_1 (
.DATAPATH_DISABLE (DATAPATH_DISABLE)
) i_tx_channel_1 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_valid (dac_valid_q),
@ -250,6 +252,3 @@ module axi_ad9963_tx #(
.up_rack (up_rack_s[2]));
endmodule
// ***************************************************************************
// ***************************************************************************

17
library/axi_ad9963/axi_ad9963_tx_channel.v
View File

@ -44,7 +44,8 @@ module axi_ad9963_tx_channel #(
parameter DAC_DDS_TYPE = 1,
parameter DAC_DDS_CORDIC_DW = 14,
parameter DAC_DDS_CORDIC_PHASE_DW = 13,
parameter DATAPATH_DISABLE = 0) (
parameter DATAPATH_DISABLE = 0
) (
// dac interface
@ -76,7 +77,8 @@ module axi_ad9963_tx_channel #(
input up_rreq,
input [13:0] up_raddr,
output [31:0] up_rdata,
output up_rack);
output up_rack
);
localparam PRBS_SEL = CHANNEL_ID;
localparam PRBS_P09 = 0;
@ -128,7 +130,9 @@ module axi_ad9963_tx_channel #(
assign dac_iqcor_valid_s = data_source_valid;
assign dac_iqcor_data_s = {dac_data_out, 4'd0};
end else begin
ad_iqcor #(.Q_OR_I_N (Q_OR_I_N)) i_ad_iqcor (
ad_iqcor #(
.Q_OR_I_N (Q_OR_I_N)
) i_ad_iqcor (
.clk (dac_clk),
.valid (data_source_valid),
.data_in ({dac_data_out, 4'd0}),
@ -205,8 +209,8 @@ module axi_ad9963_tx_channel #(
.DDS_TYPE (DAC_DDS_TYPE),
.CORDIC_DW (DAC_DDS_CORDIC_DW),
.CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.CLK_RATIO (1))
i_dds (
.CLK_RATIO (1)
) i_dds (
.clk (dac_clk),
.dac_dds_format (dac_dds_format),
.dac_data_sync (dac_data_sync),
@ -269,6 +273,3 @@ module axi_ad9963_tx_channel #(
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************

6
library/axi_adaq8092/axi_adaq8092.v
View File

@ -45,7 +45,8 @@ module axi_adaq8092 #(
parameter ADC_DATAPATH_DISABLE = 0,
parameter IO_DELAY_GROUP = "adc_if_delay_group",
parameter OUTPUT_MODE = 0,
parameter [27:0] POLARITY_MASK ='hfffffff) (
parameter [27:0] POLARITY_MASK ='hfffffff
) (
// adc interface (clk, data, over-range)
@ -99,7 +100,8 @@ module axi_adaq8092 #(
output [31:0] s_axi_rdata,
input s_axi_rready,
input [ 2:0] s_axi_awprot,
input [ 2:0] s_axi_arprot);
input [ 2:0] s_axi_arprot
);
// configuration settings

3
library/axi_adaq8092/axi_adaq8092_apb_decode.v
View File

@ -41,7 +41,8 @@ module axi_adaq8092_apb_decode (
input [27:0] adc_data,
input adc_clk,
input adc_abp_enb,
output [27:0] adc_data_decoded);
output [27:0] adc_data_decoded
);
// internal registers

6
library/axi_adaq8092/axi_adaq8092_channel.v
View File

@ -39,7 +39,8 @@
module axi_adaq8092_channel #(
parameter CHANNEL_ID = 0,
parameter DATAPATH_DISABLE = 0) (
parameter DATAPATH_DISABLE = 0
) (
// adc interface
@ -66,7 +67,8 @@ module axi_adaq8092_channel #(
input up_rreq,
input [13:0] up_raddr,
output [31:0] up_rdata,
output up_rack);
output up_rack
);
// internal signals

6
library/axi_adaq8092/axi_adaq8092_if.v
View File

@ -43,7 +43,8 @@ module axi_adaq8092_if #(
parameter IO_DELAY_GROUP = "adc_if_delay_group",
parameter DELAY_REFCLK_FREQUENCY = 200,
parameter [27:0] POLARITY_MASK ='hfffffff,
parameter OUTPUT_MODE = 0) (
parameter OUTPUT_MODE = 0
) (
// adc interface (clk, data, over-range)
// nominal clock 80 MHz, up to 105 MHz
@ -79,7 +80,8 @@ module axi_adaq8092_if #(
output [149:0] up_drdata,
input delay_clk,
input delay_rst,
output delay_locked);
output delay_locked
);
// internal registers

3
library/axi_adaq8092/axi_adaq8092_rand_decode.v
View File

@ -43,7 +43,8 @@ module axi_adaq8092_rand_decode (
input [27:0] adc_data,
input adc_clk,
input adc_rand_enb,
output [27:0] adc_data_decoded);
output [27:0] adc_data_decoded
);
// internal register

11
library/axi_adc_decimate/axi_adc_decimate.v
View File

@ -37,8 +37,8 @@
module axi_adc_decimate #(
parameter CORRECTION_DISABLE = 1) (
parameter CORRECTION_DISABLE = 1
) (
input adc_clk,
input adc_rst,
@ -76,7 +76,8 @@ module axi_adc_decimate #(
output s_axi_rvalid,
output [31:0] s_axi_rdata,
output [ 1:0] s_axi_rresp,
input s_axi_rready);
input s_axi_rready
);
// internal signals
@ -130,7 +131,6 @@ module axi_adc_decimate #(
.adc_dec_valid_b(adc_dec_valid_b));
axi_adc_decimate_reg axi_adc_decimate_reg (
.clk (adc_clk),
.adc_decimation_ratio (decimation_ratio),
@ -184,6 +184,3 @@ module axi_adc_decimate #(
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************

11
library/axi_adc_decimate/axi_adc_decimate_filter.v
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@ -35,11 +35,10 @@
`timescale 1ns/100ps
module axi_adc_decimate_filter #(
parameter CORRECTION_DISABLE = 1) (
parameter CORRECTION_DISABLE = 1
) (
input adc_clk,
input adc_rst,
@ -122,7 +121,8 @@ module axi_adc_decimate_filter #(
.filter_out(adc_fir_data_b),
.ce_out(adc_fir_valid_b));
ad_iqcor #(.Q_OR_I_N (0),
ad_iqcor #(
.Q_OR_I_N (0),
.DISABLE(CORRECTION_DISABLE),
.SCALE_ONLY(1)
) i_scale_correction_a (
@ -136,7 +136,8 @@ module axi_adc_decimate_filter #(
.iqcor_coeff_1 (adc_correction_coefficient_a),
.iqcor_coeff_2 (16'h0));
ad_iqcor #(.Q_OR_I_N (0),
ad_iqcor #(
.Q_OR_I_N (0),
.DISABLE(CORRECTION_DISABLE),
.SCALE_ONLY(1)
) i_scale_correction_b (

11
library/axi_adc_decimate/axi_adc_decimate_reg.v
View File

@ -58,7 +58,8 @@ module axi_adc_decimate_reg(
input up_rreq,
input [ 4:0] up_raddr,
output reg [31:0] up_rdata,
output reg up_rack);
output reg up_rack
);
// internal registers
@ -129,7 +130,9 @@ module axi_adc_decimate_reg(
end
end
up_xfer_cntrl #(.DATA_WIDTH(69)) i_xfer_cntrl (
up_xfer_cntrl #(
.DATA_WIDTH (69)
) i_xfer_cntrl (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_cntrl ({ up_config[1], // 1
@ -150,7 +153,3 @@ module axi_adc_decimate_reg(
adc_filter_mask})); // 3
endmodule
// ***************************************************************************
// ***************************************************************************

9
library/axi_adc_decimate/cic_decim.v
View File

@ -110,8 +110,7 @@ module cic_decim (
.clk(clk),
.ce(enable),
.data_in(data_stage[i]),
.data_out(data_stage[i+1])
);
.data_out(data_stage[i+1]));
end
endgenerate
@ -125,8 +124,7 @@ module cic_decim (
.ce(ce_comb),
.enable(filter_enable),
.data_in(data_stage[6]),
.data_out(data_stage[11])
);
.data_out(data_stage[11]));
cic_comb #(
.DATA_WIDTH(DATA_WIDTH),
@ -138,8 +136,7 @@ module cic_decim (
.ce(ce_comb),
.enable(filter_enable),
.data_in(data_stage[11]),
.data_out(data_stage[12])
);
.data_out(data_stage[12]));
assign data_final_stage = data_stage[2*NUM_STAGES];

14
library/axi_adc_trigger/axi_adc_trigger.v
View File

@ -40,7 +40,8 @@ module axi_adc_trigger #(
// parameters
parameter SIGN_BITS = 2,
parameter OUT_PIN_HOLD_N = 100000) (
parameter OUT_PIN_HOLD_N = 100000
) (
// interface
@ -89,8 +90,8 @@ module axi_adc_trigger #(
output s_axi_rvalid,
output [31:0] s_axi_rdata,
output [ 1:0] s_axi_rresp,
input s_axi_rready);
input s_axi_rready
);
localparam DW = 15 - SIGN_BITS;
@ -211,7 +212,6 @@ module axi_adc_trigger #(
reg trigger_out_hold;
reg trigger_out_ack;
// signal name changes
assign up_clk = s_axi_aclk;
@ -278,7 +278,6 @@ module axi_adc_trigger #(
trigger_o[1] <= (trig_o_hold_cnt_1 == 'd0) ? trigger_o_m[1] : trig_o_hold_1;
end
// 1. keep data in sync with the trigger. The trigger bypasses the variable
// fifo. The data goes through and it is delayed with 4 clock cycles)
// 2. For non max sample rate of the ADC, the trigger signal that originates
@ -344,7 +343,6 @@ module axi_adc_trigger #(
end
end
always @(posedge clk) begin
if (trigger_delay == 0) begin
if (streaming == 1'b1 && data_valid_a == 1'b1 && trigger_out_holdoff == 1'b1) begin
@ -569,7 +567,6 @@ module axi_adc_trigger #(
assign comp_low_b_s = !comp_high_b;
axi_adc_trigger_reg adc_trigger_registers (
.clk(clk),
.io_selection(io_selection),
@ -646,6 +643,3 @@ module axi_adc_trigger #(
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************

12
library/axi_adc_trigger/axi_adc_trigger_reg.v
View File

@ -78,7 +78,8 @@ module axi_adc_trigger_reg (
input up_rreq,
input [ 4:0] up_raddr,
output reg [31:0] up_rdata,
output reg up_rack);
output reg up_rack
);
localparam DEFAULT_OUT_HOLD = 100000; // 1ms
@ -239,7 +240,9 @@ module axi_adc_trigger_reg (
end
end
up_xfer_cntrl #(.DATA_WIDTH(262)) i_xfer_cntrl (
up_xfer_cntrl #(
.DATA_WIDTH(262)
) i_xfer_cntrl (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_cntrl ({ up_streaming, // 1
@ -259,7 +262,6 @@ module axi_adc_trigger_reg (
up_trigger_holdoff, // 32
up_trigger_out_hold_pins, // 20
up_trigger_delay}), // 32
.up_xfer_done (),
.d_rst (1'b0),
.d_clk (clk),
@ -282,7 +284,3 @@ module axi_adc_trigger_reg (
trigger_delay})); // 32
endmodule
// ***************************************************************************
// ***************************************************************************

28
library/axi_adrv9001/adrv9001_rx.v
View File

@ -44,6 +44,7 @@ module adrv9001_rx #(
parameter USE_BUFG = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group"
) (
// device interface
input rx_dclk_in_n_NC,
input rx_dclk_in_p_dclk_in,
@ -114,8 +115,8 @@ module adrv9001_rx #(
.DDR_OR_SDR_N (DDR_OR_SDR_N),
.DATA_WIDTH (NUM_LANES),
.DRP_WIDTH (DRP_WIDTH),
.SERDES_FACTOR (8))
i_serdes (
.SERDES_FACTOR (8)
) i_serdes (
.rst (adc_rst|ssi_rst),
.clk (adc_clk_in_fast),
.div_clk (adc_clk_div),
@ -196,7 +197,9 @@ module adrv9001_rx #(
.I (clk_in_s),
.O (adc_clk_in_fast));
BUFR #(.BUFR_DIVIDE("4")) i_div_clk_buf (
BUFR #(
.BUFR_DIVIDE("4")
) i_div_clk_buf (
.CLR (mssi_sync),
.CE (1'b1),
.I (clk_in_s),
@ -205,24 +208,19 @@ module adrv9001_rx #(
if (USE_BUFG == 1) begin
BUFG I_bufg (
.I (adc_clk_div_s),
.O (adc_clk_div)
);
.O (adc_clk_div));
end else begin
assign adc_clk_div = adc_clk_div_s;
end
xpm_cdc_async_rst
# (
xpm_cdc_async_rst #(
.DEST_SYNC_FF (10), // DECIMAL; range: 2-10
.INIT_SYNC_FF ( 0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
.RST_ACTIVE_HIGH ( 1) // DECIMAL; 0=active low reset, 1=active high reset
)
rst_syncro
(
) rst_syncro (
.src_arst (mssi_sync),
.dest_clk (adc_clk_div),
.dest_arst(ssi_rst )
);
.dest_arst(ssi_rst));
end else begin
wire adc_clk_in;
@ -254,8 +252,7 @@ module adrv9001_rx #(
) i_clk_buf_fast (
.O (adc_clk_in_fast),
.CE (1'b1),
.I (adc_clk_in)
);
.I (adc_clk_in));
BUFGCE_DIV #(
.BUFGCE_DIVIDE (4),
@ -266,8 +263,7 @@ module adrv9001_rx #(
.O (adc_clk_div),
.CE (1'b1),
.CLR (ssi_rst),
.I (adc_clk_in)
);
.I (adc_clk_in));
assign ssi_rst = ssi_rst_pos;

57
library/axi_adrv9001/adrv9001_rx_link.v
View File

@ -38,7 +38,6 @@
module adrv9001_rx_link #(
parameter CMOS_LVDS_N = 0
) (
input adc_rst,
input adc_clk_div,
input [7:0] adc_data_0,
@ -107,8 +106,7 @@ module adrv9001_rx_link #(
.idata (sdr_data_0),
.ivalid (adc_valid),
.strobe (sdr_data_strobe),
.odata (sdr_data_0_aligned)
);
.odata (sdr_data_0_aligned));
adrv9001_aligner4 i_rx_aligner4_1 (
.clk (adc_clk_div),
@ -116,8 +114,7 @@ module adrv9001_rx_link #(
.idata (sdr_data_1),
.ivalid (adc_valid),
.strobe (sdr_data_strobe),
.odata (sdr_data_1_aligned)
);
.odata (sdr_data_1_aligned));
adrv9001_aligner4 i_rx_aligner4_2 (
.clk (adc_clk_div),
@ -125,8 +122,7 @@ module adrv9001_rx_link #(
.idata (sdr_data_2),
.ivalid (adc_valid),
.strobe (sdr_data_strobe),
.odata (sdr_data_2_aligned)
);
.odata (sdr_data_2_aligned));
adrv9001_aligner4 i_rx_aligner4_3 (
.clk (adc_clk_div),
@ -134,8 +130,7 @@ module adrv9001_rx_link #(
.idata (sdr_data_3),
.ivalid (adc_valid),
.strobe (sdr_data_strobe),
.odata (sdr_data_3_aligned)
);
.odata (sdr_data_3_aligned));
adrv9001_aligner4 i_rx_aligner4_strobe (
.clk (adc_clk_div),
@ -144,8 +139,7 @@ module adrv9001_rx_link #(
.ivalid (adc_valid),
.strobe (sdr_data_strobe),
.ovalid (aligner4_ovalid),
.odata (sdr_data_strobe_aligned)
);
.odata (sdr_data_strobe_aligned));
adrv9001_pack #(
.WIDTH(4)
@ -156,8 +150,7 @@ module adrv9001_rx_link #(
.ivalid (aligner4_ovalid),
.sof (sdr_data_strobe_aligned[3]),
.odata (sdr_data_0_packed),
.ovalid (sdr_data_valid)
);
.ovalid (sdr_data_valid));
adrv9001_pack #(
.WIDTH(4)
@ -168,8 +161,7 @@ module adrv9001_rx_link #(
.ivalid (aligner4_ovalid),
.sof (sdr_data_strobe_aligned[3]),
.odata (sdr_data_1_packed),
.ovalid ()
);
.ovalid ());
adrv9001_pack #(
.WIDTH(4)
@ -179,8 +171,7 @@ module adrv9001_rx_link #(
.ivalid (aligner4_ovalid),
.sof (sdr_data_strobe_aligned[3]),
.odata (sdr_data_2_packed),
.ovalid ()
);
.ovalid ());
adrv9001_pack #(
.WIDTH(4)
@ -191,8 +182,7 @@ module adrv9001_rx_link #(
.ivalid (aligner4_ovalid),
.sof (sdr_data_strobe_aligned[3]),
.odata (sdr_data_3_packed),
.ovalid ()
);
.ovalid ());
adrv9001_pack #(
.WIDTH(4)
@ -203,8 +193,8 @@ module adrv9001_rx_link #(
.ivalid (aligner4_ovalid),
.sof (sdr_data_strobe_aligned[3]),
.odata (sdr_data_strobe_packed),
.ovalid ()
);
.ovalid ());
assign data_0 = rx_sdr_ddr_n ? sdr_data_0_packed : adc_data_0;
assign data_1 = rx_sdr_ddr_n ? sdr_data_1_packed : adc_data_1;
assign data_2 = rx_sdr_ddr_n ? sdr_data_2_packed : adc_data_2;
@ -248,8 +238,7 @@ module adrv9001_rx_link #(
.ivalid (data_valid),
.strobe (data_strobe),
.odata (rx_data8_0_aligned),
.ovalid (rx_data8_0_aligned_valid)
);
.ovalid (rx_data8_0_aligned_valid));
adrv9001_aligner8 i_rx_aligner8_1 (
.clk (adc_clk_div),
@ -258,8 +247,7 @@ module adrv9001_rx_link #(
.idata (data_1),
.strobe (data_strobe),
.odata (rx_data8_1_aligned),
.ovalid (rx_data8_1_aligned_valid)
);
.ovalid (rx_data8_1_aligned_valid));
generate if (CMOS_LVDS_N) begin : cmos_aligner8
adrv9001_aligner8 i_rx_aligner8_2 (
@ -268,16 +256,15 @@ module adrv9001_rx_link #(
.idata (data_2),
.ivalid (data_valid),
.strobe (data_strobe),
.odata (rx_data8_2_aligned)
);
.odata (rx_data8_2_aligned));
adrv9001_aligner8 i_rx_aligner8_3(
.clk (adc_clk_div),
.rst (adc_rst),
.idata (data_3),
.ivalid (data_valid),
.strobe (data_strobe),
.odata (rx_data8_3_aligned)
);
.odata (rx_data8_3_aligned));
end
endgenerate
@ -287,8 +274,7 @@ module adrv9001_rx_link #(
.idata (data_strobe),
.ivalid (data_valid),
.strobe (data_strobe),
.odata (rx_data8_strobe_aligned)
);
.odata (rx_data8_strobe_aligned));
adrv9001_pack #(
.WIDTH (8)
@ -300,8 +286,7 @@ module adrv9001_rx_link #(
.sof (rx_data8_strobe_aligned[7]),
.odata (rx_data16_0_packed),
.ovalid (rx_data16_0_packed_valid),
.osof (rx_data16_0_packed_osof)
);
.osof (rx_data16_0_packed_osof));
adrv9001_pack #(
.WIDTH (8)
@ -313,8 +298,7 @@ module adrv9001_rx_link #(
.sof (rx_data8_strobe_aligned[7]),
.odata (rx_data16_1_packed),
.ovalid (rx_data16_1_paked_valid),
.osof (rx_data16_1_packed_osof)
);
.osof (rx_data16_1_packed_osof));
adrv9001_pack #(
.WIDTH (16)
@ -326,8 +310,7 @@ module adrv9001_rx_link #(
.sof (rx_data16_0_packed_osof),
.odata (rx_data32_0_packed),
.ovalid (rx_data32_0_packed_valid),
.osof (rx_data32_0_packed_osof)
);
.osof (rx_data32_0_packed_osof));
generate if (CMOS_LVDS_N) begin
assign rx_data_i = ~rx_single_lane ? {rx_data8_1_aligned,rx_data8_0_aligned} :

27
library/axi_adrv9001/adrv9001_tx.v
View File

@ -103,8 +103,8 @@ module adrv9001_tx #(
.DDR_OR_SDR_N(1),
.DATA_WIDTH(NUM_LANES),
.SERDES_FACTOR(8),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY))
i_serdes (
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY)
) i_serdes (
.rst (dac_rst|ssi_rst),
.clk (dac_fast_clk),
.div_clk (dac_clk_div),
@ -184,7 +184,9 @@ module adrv9001_tx #(
.O (dac_fast_clk));
// SERDES slow clock
BUFR #(.BUFR_DIVIDE("4")) i_dac_div_clk_rbuf (
BUFR #(
.BUFR_DIVIDE("4")
) i_dac_div_clk_rbuf (
.CLR (mssi_sync),
.CE (1'b1),
.I (tx_dclk_in_s),
@ -193,24 +195,19 @@ module adrv9001_tx #(
if (USE_BUFG == 1) begin
BUFG I_bufg (
.I (dac_clk_div_s),
.O (dac_clk_div)
);
.O (dac_clk_div));
end else begin
assign dac_clk_div = dac_clk_div_s;
end
xpm_cdc_async_rst
# (
xpm_cdc_async_rst #(
.DEST_SYNC_FF (10), // DECIMAL; range: 2-10
.INIT_SYNC_FF ( 0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
.RST_ACTIVE_HIGH ( 1) // DECIMAL; 0=active low reset, 1=active high reset
)
rst_syncro
(
) rst_syncro (
.src_arst (mssi_sync),
.dest_clk (dac_clk_div),
.dest_arst(ssi_rst )
);
.dest_arst(ssi_rst));
end else begin
@ -228,8 +225,7 @@ module adrv9001_tx #(
) i_dac_clk_in_gbuf (
.O (dac_fast_clk),
.CE (1'b1),
.I (tx_dclk_in_s)
);
.I (tx_dclk_in_s));
BUFGCE_DIV #(
.BUFGCE_DIVIDE (4),
@ -240,8 +236,7 @@ module adrv9001_tx #(
.O (dac_clk_div),
.CE (1'b1),
.CLR (mssi_sync_2d),
.I (tx_dclk_in_s)
);
.I (tx_dclk_in_s));
assign ssi_rst = mssi_sync_2d;

9
library/axi_adrv9001/axi_adrv9001.v
View File

@ -404,8 +404,7 @@ module axi_adrv9001 #(
.tx2_single_lane (tx2_single_lane),
.tx2_sdr_ddr_n (tx2_sdr_ddr_n),
.tx2_symb_op (tx2_symb_op),
.tx2_symb_8_16b (tx2_symb_8_16b)
);
.tx2_symb_8_16b (tx2_symb_8_16b));
// common processor control
axi_adrv9001_core #(
@ -551,8 +550,7 @@ module axi_adrv9001 #(
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_rack (up_rack_s)
);
.up_rack (up_rack_s));
assign adc_1_valid_i0 = adc_1_valid;
assign adc_1_valid_q0 = adc_1_valid;
@ -603,8 +601,7 @@ module axi_adrv9001 #(
.up_wack (up_wack_s),
.up_raddr (up_raddr_s[12:0]),
.up_rreq (up_rreq_s),
.up_rack (up_rack_s)
);
.up_rack (up_rack_s));
// Alias Rx/Tx peripherals @ 0x8000
assign up_raddr_s[13] = 1'b0;

42
library/axi_adrv9001/axi_adrv9001_core.v
View File

@ -57,6 +57,7 @@ module axi_adrv9001_core #(
parameter DAC_DDS_CORDIC_DW = 20,
parameter DAC_DDS_CORDIC_PHASE_DW = 18
) (
// ADC interface
input rx1_clk,
output rx1_rst,
@ -245,8 +246,8 @@ module axi_adrv9001_core #(
sync_bits #(
.NUM_OF_BITS (6),
.ASYNC_CLK (1))
i_rx1_ctrl_sync (
.ASYNC_CLK (1)
) i_rx1_ctrl_sync (
.in_bits ({up_rx1_r1_mode,rx1_symb_op,rx1_symb_8_16b,rx1_sdr_ddr_n,rx1_single_lane,rx1_rst}),
.out_clk (rx2_clk),
.out_resetn (1'b1),
@ -254,8 +255,8 @@ module axi_adrv9001_core #(
sync_bits #(
.NUM_OF_BITS (6),
.ASYNC_CLK (1))
i_tx1_ctrl_sync (
.ASYNC_CLK (1)
) i_tx1_ctrl_sync (
.in_bits ({up_tx1_r1_mode,tx1_symb_op,tx1_symb_8_16b,tx1_sdr_ddr_n,tx1_single_lane,tx1_rst}),
.out_clk (tx2_clk),
.out_resetn (1'b1),
@ -324,8 +325,8 @@ module axi_adrv9001_core #(
sync_event #(
.NUM_OF_EVENTS (1),
.ASYNC_CLK (1))
i_rx_external_sync (
.ASYNC_CLK (1)
) i_rx_external_sync (
.in_clk (ref_clk),
.in_event (adc_sync_in),
.out_clk (rx1_clk),
@ -352,8 +353,8 @@ module axi_adrv9001_core #(
sync_event #(
.NUM_OF_EVENTS (1),
.ASYNC_CLK (1))
i_tx_external_sync (
.ASYNC_CLK (1)
) i_tx_external_sync (
.in_clk (ref_clk),
.in_event (dac_sync_in),
.out_clk (tx1_clk),
@ -388,8 +389,8 @@ module axi_adrv9001_core #(
.DEV_PACKAGE (DEV_PACKAGE),
.DATAFORMAT_DISABLE (0),
.DCFILTER_DISABLE (1),
.IQCORRECTION_DISABLE (1))
i_rx1 (
.IQCORRECTION_DISABLE (1)
) i_rx1 (
.adc_rst (rx1_rst),
.adc_clk (rx1_clk),
.adc_valid_A (rx1_data_valid & tdd_rx1_valid & sync_adc_valid),
@ -453,8 +454,8 @@ module axi_adrv9001_core #(
.DEV_PACKAGE (DEV_PACKAGE),
.DATAFORMAT_DISABLE (0),
.DCFILTER_DISABLE (1),
.IQCORRECTION_DISABLE (1))
i_rx2 (
.IQCORRECTION_DISABLE (1)
) i_rx2 (
.adc_rst (rx2_rst_loc),
.adc_clk (rx2_clk),
.adc_valid_A (rx2_data_valid & tdd_rx2_valid & sync_adc_valid),
@ -515,8 +516,8 @@ module axi_adrv9001_core #(
.IQCORRECTION_DISABLE (1),
.DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
i_tx1 (
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW)
) i_tx1 (
.dac_rst (tx1_rst),
.dac_clk (tx1_clk),
.dac_data_valid_A (tx1_data_valid_A),
@ -573,8 +574,8 @@ module axi_adrv9001_core #(
.IQCORRECTION_DISABLE (1),
.DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
i_tx2 (
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW)
) i_tx2 (
.dac_rst (tx2_rst_loc),
.dac_clk (tx2_clk),
.dac_data_valid_A (tx2_data_valid_A),
@ -616,8 +617,8 @@ module axi_adrv9001_core #(
up_delay_cntrl #(
.DATA_WIDTH(NUM_LANES),
.DRP_WIDTH(DRP_WIDTH),
.BASE_ADDRESS(6'h02))
i_delay_cntrl_rx1 (
.BASE_ADDRESS(6'h02)
) i_delay_cntrl_rx1 (
.delay_clk (delay_clk),
.delay_rst (delay_rx1_rst),
.delay_locked (delay_rx1_locked),
@ -639,8 +640,8 @@ module axi_adrv9001_core #(
.DATA_WIDTH(NUM_LANES),
.DRP_WIDTH(DRP_WIDTH),
.DISABLE(DISABLE_RX2_SSI),
.BASE_ADDRESS(6'h06))
i_delay_cntrl_rx2 (
.BASE_ADDRESS(6'h06)
) i_delay_cntrl_rx2 (
.delay_clk (delay_clk),
.delay_rst (delay_rx2_rst),
.delay_locked (delay_rx2_locked),
@ -723,4 +724,3 @@ module axi_adrv9001_core #(
assign tdd_sync_cntr = tdd_sync_cntr1 | tdd_sync_cntr2;
endmodule

21
library/axi_adrv9001/axi_adrv9001_if.v
View File

@ -267,8 +267,7 @@ module axi_adrv9001_if #(
.rx_single_lane (rx1_single_lane),
.rx_sdr_ddr_n (rx1_sdr_ddr_n),
.rx_symb_op (rx1_symb_op),
.rx_symb_8_16b (rx1_symb_8_16b)
);
.rx_symb_8_16b (rx1_symb_8_16b));
generate if (DISABLE_RX2_SSI == 0) begin
adrv9001_rx
@ -332,8 +331,7 @@ module axi_adrv9001_if #(
.rx_single_lane (rx2_single_lane),
.rx_sdr_ddr_n (rx2_sdr_ddr_n),
.rx_symb_op (rx2_symb_op),
.rx_symb_8_16b (rx2_symb_8_16b)
);
.rx_symb_8_16b (rx2_symb_8_16b));
end else begin
assign delay_rx2_locked = 1'b1;
assign up_rx2_drdata = 'h0;
@ -351,7 +349,6 @@ module axi_adrv9001_if #(
.USE_BUFG (TX_USE_BUFG),
.USE_RX_CLK_FOR_TX (USE_RX_CLK_FOR_TX)
) i_tx_1_phy (
.ref_clk (ref_clk),
.up_clk (up_clk),
@ -385,8 +382,7 @@ module axi_adrv9001_if #(
.dac_clk_ratio (dac_clk_ratio),
.mssi_sync (mssi_sync)
);
.mssi_sync (mssi_sync));
adrv9001_tx_link #(
.CMOS_LVDS_N (CMOS_LVDS_N),
@ -409,8 +405,7 @@ module axi_adrv9001_if #(
.tx_sdr_ddr_n (tx1_sdr_ddr_n),
.tx_single_lane (tx1_single_lane),
.tx_symb_op (tx1_symb_op),
.tx_symb_8_16b (tx1_symb_8_16b)
);
.tx_symb_8_16b (tx1_symb_8_16b));
generate if (DISABLE_TX2_SSI == 0) begin
adrv9001_tx #(
@ -420,7 +415,6 @@ module axi_adrv9001_if #(
.USE_BUFG (TX_USE_BUFG),
.USE_RX_CLK_FOR_TX (USE_RX_CLK_FOR_TX)
) i_tx_2_phy (
.ref_clk (ref_clk),
.up_clk (up_clk),
@ -452,8 +446,7 @@ module axi_adrv9001_if #(
.dac_data_clk (dac_2_data_clk),
.dac_data_valid (dac_2_data_valid),
.mssi_sync (mssi_sync)
);
.mssi_sync (mssi_sync));
adrv9001_tx_link #(
.CMOS_LVDS_N (CMOS_LVDS_N),
@ -476,8 +469,7 @@ module axi_adrv9001_if #(
.tx_sdr_ddr_n (tx2_sdr_ddr_n),
.tx_single_lane (tx2_single_lane),
.tx_symb_op (tx2_symb_op),
.tx_symb_8_16b (tx2_symb_8_16b)
);
.tx_symb_8_16b (tx2_symb_8_16b));
end else begin
assign tx2_clk = 1'b0;
assign tx2_dclk_out_n_NC = 1'b0;
@ -492,4 +484,3 @@ module axi_adrv9001_if #(
endgenerate
endmodule

24
library/axi_adrv9001/axi_adrv9001_rx.v
View File

@ -50,6 +50,7 @@ module axi_adrv9001_rx #(
parameter DCFILTER_DISABLE = 0,
parameter IQCORRECTION_DISABLE = 1
) (
// adc interface
output adc_rst,
input adc_clk,
@ -199,8 +200,8 @@ end else begin : core_enabled
.DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
.DCFILTER_DISABLE (DCFILTER_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
.DATA_WIDTH (16))
i_rx_channel_0 (
.DATA_WIDTH (16)
) i_rx_channel_0 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_valid_in (adc_valid_A),
@ -236,8 +237,8 @@ end else begin : core_enabled
.DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
.DCFILTER_DISABLE (DCFILTER_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
.DATA_WIDTH (16))
i_rx_channel_1 (
.DATA_WIDTH (16)
) i_rx_channel_1 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_valid_in (adc_valid_A),
@ -273,8 +274,8 @@ end else begin : core_enabled
.DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
.DCFILTER_DISABLE (DCFILTER_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
.DATA_WIDTH (16))
i_rx_channel_2 (
.DATA_WIDTH (16)
) i_rx_channel_2 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_valid_in (adc_valid_B),
@ -310,8 +311,8 @@ end else begin : core_enabled
.DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
.DCFILTER_DISABLE (DCFILTER_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
.DATA_WIDTH (16))
i_rx_channel_3 (
.DATA_WIDTH (16)
) i_rx_channel_3 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_valid_in (adc_valid_B),
@ -350,8 +351,8 @@ end else begin : core_enabled
.DRP_DISABLE(1),
.USERPORTS_DISABLE(1),
.GPIO_DISABLE(1),
.START_CODE_DISABLE(1))
i_up_adc_common (
.START_CODE_DISABLE(1)
) i_up_adc_common (
.mmcm_rst (),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
@ -405,6 +406,3 @@ end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************

26
library/axi_adrv9001/axi_adrv9001_rx_channel.v
View File

@ -45,6 +45,7 @@ module axi_adrv9001_rx_channel #(
parameter IQCORRECTION_DISABLE = 0,
parameter DATA_WIDTH = 16
) (
// adc interface
input adc_clk,
input adc_rst,
@ -145,7 +146,9 @@ module axi_adrv9001_rx_channel #(
assign adc_dfmt_valid_s[n] = adc_valid_in_s;
assign adc_dfmt_data_s[((16*n)+15):(16*n)] = adc_data_in_s[((16*n)+15):(16*n)];
end else begin
ad_datafmt #(.DATA_WIDTH (16)) i_ad_datafmt (
ad_datafmt #(
.DATA_WIDTH (16)
) i_ad_datafmt (
.clk (adc_clk),
.valid (adc_valid_in_s),
.data (adc_data_in_s[((16*n)+15):(16*n)]),
@ -182,7 +185,9 @@ module axi_adrv9001_rx_channel #(
assign adc_valid_out_s[n] = adc_dcfilter_valid_s[n];
assign adc_data_out[((16*n)+15):(16*n)] = adc_dcfilter_data_s[((16*n)+15):(16*n)];
end else begin
ad_iqcor #(.Q_OR_I_N (Q_OR_I_N)) i_ad_iqcor (
ad_iqcor #(
.Q_OR_I_N (Q_OR_I_N)
) i_ad_iqcor (
.clk (adc_clk),
.valid (adc_dcfilter_valid_s[n]),
.data_in (adc_dcfilter_data_s[((16*n)+15):(16*n)]),
@ -217,8 +222,7 @@ module axi_adrv9001_rx_channel #(
.clk_en (adc_valid_in_s),
.pn_init (adc_pn_oos_s),
.pn_data_in (adc_data_in_s),
.pn_data_out (pn7_data)
);
.pn_data_out (pn7_data));
// PN15 x^15 + x^14 + 1
ad_pngen #(
@ -231,8 +235,7 @@ module axi_adrv9001_rx_channel #(
.clk_en (adc_valid_in_s),
.pn_init (adc_pn_oos_s),
.pn_data_in (adc_data_in_s),
.pn_data_out (pn15_data)
);
.pn_data_out (pn15_data));
// reference nibble ramp and full ramp generator
// next value is always the currently received value incremented
@ -260,8 +263,7 @@ module axi_adrv9001_rx_channel #(
.adc_data_pn (adc_data_pn),
.adc_pattern_has_zero (adc_pnseq_sel[3]),
.adc_pn_oos (adc_pn_oos_s),
.adc_pn_err (adc_pn_err_s)
);
.adc_pn_err (adc_pn_err_s));
up_adc_channel #(
.COMMON_ID (COMMON_ID),
@ -269,8 +271,8 @@ module axi_adrv9001_rx_channel #(
.USERPORTS_DISABLE(1),
.DATAFORMAT_DISABLE(DATAFORMAT_DISABLE),
.DCFILTER_DISABLE(DCFILTER_DISABLE),
.IQCORRECTION_DISABLE(IQCORRECTION_DISABLE))
i_up_adc_channel (
.IQCORRECTION_DISABLE(IQCORRECTION_DISABLE)
) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),
@ -319,7 +321,3 @@ module axi_adrv9001_rx_channel #(
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************

7
library/axi_adrv9001/axi_adrv9001_tdd.v
View File

@ -79,7 +79,8 @@ module axi_adrv9001_tdd #(
input up_rreq,
input [13:0] up_raddr,
output [31:0] up_rdata,
output up_rack);
output up_rack
);
generate
if (ENABLED == 1) begin
@ -215,8 +216,8 @@ module axi_adrv9001_tdd #(
ad_tdd_control #(
.TX_DATA_PATH_DELAY(),
.CONTROL_PATH_DELAY())
i_tdd_control(
.CONTROL_PATH_DELAY()
) i_tdd_control(
.clk(clk),
.rst(rst),
.tdd_enable(tdd_enable_s),

25
library/axi_adrv9001/axi_adrv9001_tx.v
View File

@ -55,6 +55,7 @@ module axi_adrv9001_tx #(
parameter DAC_DDS_CORDIC_DW = 20,
parameter DAC_DDS_CORDIC_PHASE_DW = 18
) (
// dac interface
output dac_rst,
input dac_clk,
@ -108,6 +109,7 @@ module axi_adrv9001_tx #(
output reg [ 31:0] up_rdata,
output reg up_rack
);
generate
if (ENABLED == 0) begin : core_disabled
@ -227,8 +229,8 @@ end else begin : core_enabled
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
.DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
i_tx_channel_0 (
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW)
) i_tx_channel_0 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_data_in_req (dac_valid),
@ -262,8 +264,8 @@ end else begin : core_enabled
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
.DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
i_tx_channel_1 (
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW)
) i_tx_channel_1 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_data_in_req (),
@ -297,8 +299,8 @@ end else begin : core_enabled
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
.DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
i_tx_channel_2 (
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW)
) i_tx_channel_2 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_data_in_req (),
@ -332,8 +334,8 @@ end else begin : core_enabled
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
.DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
i_tx_channel_3 (
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW)
) i_tx_channel_3 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_data_in_req (),
@ -369,8 +371,8 @@ end else begin : core_enabled
.COMMON_ID(COMMON_BASE_ADDR),
.DRP_DISABLE(1),
.USERPORTS_DISABLE(1),
.GPIO_DISABLE(1))
i_up_dac_common (
.GPIO_DISABLE(1)
) i_up_dac_common (
.mmcm_rst (),
.dac_clk (dac_clk),
.dac_rst (dac_rst),
@ -423,6 +425,3 @@ end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************

19
library/axi_adrv9001/axi_adrv9001_tx_channel.v
View File

@ -46,6 +46,7 @@ module axi_adrv9001_tx_channel #(
parameter DAC_DDS_CORDIC_DW = 20,
parameter DAC_DDS_CORDIC_PHASE_DW = 18
) (
// dac interface
input dac_clk,
input dac_rst,
@ -105,7 +106,9 @@ module axi_adrv9001_tx_channel #(
assign dac_data_in_req = dac_data_out_req;
end else begin
ad_iqcor #(.Q_OR_I_N (Q_OR_I_N)) i_ad_iqcor_0 (
ad_iqcor #(
.Q_OR_I_N (Q_OR_I_N)
) i_ad_iqcor_0 (
.clk (dac_clk),
.valid (dac_data_out_req),
.data_in (dac_data_iq_out[15:0]),
@ -133,8 +136,7 @@ module axi_adrv9001_tx_channel #(
.reset (dac_rst),
.clk_en (dac_data_in_req),
.pn_init (1'b0),
.pn_data_out (pn7_data)
);
.pn_data_out (pn7_data));
// PN15 x^15 + x^14 + 1
ad_pngen #(
@ -146,8 +148,7 @@ module axi_adrv9001_tx_channel #(
.reset (dac_rst),
.clk_en (dac_data_in_req),
.pn_init (1'b0),
.pn_data_out (pn15_data)
);
.pn_data_out (pn15_data));
// full ramp generator
always @(posedge dac_clk) begin
@ -183,8 +184,8 @@ module axi_adrv9001_tx_channel #(
.DDS_TYPE (DAC_DDS_TYPE),
.CORDIC_DW (DAC_DDS_CORDIC_DW),
.CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.CLK_RATIO (1))
i_dds (
.CLK_RATIO (1)
) i_dds (
.clk (dac_clk),
.dac_dds_format (dac_dds_format),
.dac_data_sync (dac_data_sync),
@ -204,8 +205,8 @@ module axi_adrv9001_tx_channel #(
.CHANNEL_ID (CHANNEL_ID),
.DDS_DISABLE(DDS_DISABLE),
.USERPORTS_DISABLE(1),
.IQCORRECTION_DISABLE(IQCORRECTION_DISABLE))
i_up_dac_channel (
.IQCORRECTION_DISABLE(IQCORRECTION_DISABLE)
) i_up_dac_channel (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_dds_scale_1 (dac_dds_scale_1_s),

1
library/axi_adrv9001/intel/adrv9001_rx.v
View File

@ -44,6 +44,7 @@ module adrv9001_rx #(
parameter USE_BUFG = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group"
) (
// device interface
input rx_dclk_in_n_NC,
input rx_dclk_in_p_dclk_in,

14
library/axi_clkgen/axi_clkgen.v
View File

@ -52,7 +52,8 @@ module axi_clkgen #(
parameter real CLK0_DIV = 6.000,
parameter real CLK0_PHASE = 0.000,
parameter integer CLK1_DIV = 6,
parameter real CLK1_PHASE = 0.000) (
parameter real CLK1_PHASE = 0.000
) (
// clocks
@ -83,8 +84,8 @@ module axi_clkgen #(
output [ 1:0] s_axi_rresp,
input s_axi_rready,
input [ 2:0] s_axi_awprot,
input [ 2:0] s_axi_arprot);
input [ 2:0] s_axi_arprot
);
// reset and clocks
@ -199,8 +200,8 @@ module axi_clkgen #(
.MMCM_CLK0_DIV (CLK0_DIV),
.MMCM_CLK0_PHASE (CLK0_PHASE),
.MMCM_CLK1_DIV (CLK1_DIV),
.MMCM_CLK1_PHASE (CLK1_PHASE))
i_mmcm_drp (
.MMCM_CLK1_PHASE (CLK1_PHASE)
) i_mmcm_drp (
.clk (clk),
.clk2 (clk2),
.clk_sel(clk_sel_s),
@ -219,6 +220,3 @@ module axi_clkgen #(
.up_drp_locked (up_drp_locked_s));
endmodule
// ***************************************************************************
// ***************************************************************************

12
library/axi_clock_monitor/axi_clock_monitor.v
View File

@ -38,7 +38,8 @@
module axi_clock_monitor #(
parameter ID = 0,
parameter NUM_OF_CLOCKS = 1) (
parameter NUM_OF_CLOCKS = 1
) (
// clocks
@ -83,7 +84,8 @@ module axi_clock_monitor #(
output s_axi_rvalid,
output [31:0] s_axi_rdata,
output [ 1:0] s_axi_rresp,
input s_axi_rready);
input s_axi_rready
);
// local parameters
@ -226,8 +228,7 @@ module axi_clock_monitor #(
.up_clk(up_clk),
.up_d_count(clk_mon_count[n]),
.d_rst(1'b0),
.d_clk(clock[n])
);
.d_clk(clock[n]));
end
for (n = NUM_OF_CLOCKS; n < 16; n = n + 1) begin: clk_mon_z
assign clk_mon_count[n] = 21'd0;
@ -266,6 +267,3 @@ module axi_clock_monitor #(
.up_rack (up_rack_o_s));
endmodule
// ***************************************************************************
// ***************************************************************************

25
library/axi_dac_interpolate/axi_dac_interpolate.v
View File

@ -37,8 +37,8 @@
module axi_dac_interpolate #(
parameter CORRECTION_DISABLE = 1) (
parameter CORRECTION_DISABLE = 1
) (
input dac_clk,
input dac_rst,
@ -87,8 +87,8 @@ module axi_dac_interpolate #(
output s_axi_rvalid,
output [31:0] s_axi_rdata,
output [ 1:0] s_axi_rresp,
input s_axi_rready);
input s_axi_rready
);
reg [ 1:0] trigger_i_m1;
reg [ 1:0] trigger_i_m2;
@ -212,8 +212,8 @@ module axi_dac_interpolate #(
assign underflow = underflow_a | underflow_b;
axi_dac_interpolate_filter #(
.CORRECTION_DISABLE(CORRECTION_DISABLE))
i_filter_a (
.CORRECTION_DISABLE (CORRECTION_DISABLE)
) i_filter_a (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
@ -238,12 +238,11 @@ module axi_dac_interpolate #(
.dma_valid (dma_valid_a),
.dma_valid_adjacent (dma_valid_b),
.dac_correction_enable(dac_correction_enable_a),
.dac_correction_coefficient(dac_correction_coefficient_a)
);
.dac_correction_coefficient(dac_correction_coefficient_a));
axi_dac_interpolate_filter #(
.CORRECTION_DISABLE(CORRECTION_DISABLE))
i_filter_b (
.CORRECTION_DISABLE(CORRECTION_DISABLE)
) i_filter_b (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
@ -268,8 +267,7 @@ module axi_dac_interpolate #(
.dma_valid (dma_valid_b),
.dma_valid_adjacent (dma_valid_a),
.dac_correction_enable(dac_correction_enable_b),
.dac_correction_coefficient(dac_correction_coefficient_b)
);
.dac_correction_coefficient(dac_correction_coefficient_b));
axi_dac_interpolate_reg axi_dac_interpolate_reg_inst (
@ -332,6 +330,3 @@ module axi_dac_interpolate #(
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************

12
library/axi_dac_interpolate/axi_dac_interpolate_filter.v
View File

@ -35,11 +35,10 @@
`timescale 1ns/100ps
module axi_dac_interpolate_filter #(
parameter CORRECTION_DISABLE = 1) (
parameter CORRECTION_DISABLE = 1
) (
input dac_clk,
input dac_rst,
@ -96,10 +95,11 @@ module axi_dac_interpolate_filter #(
wire dma_valid_ch_sync;
wire dma_valid_ch;
ad_iqcor #(.Q_OR_I_N (0),
ad_iqcor #(
.Q_OR_I_N (0),
.DISABLE(CORRECTION_DISABLE),
.SCALE_ONLY(1))
i_ad_iqcor (
.SCALE_ONLY(1)
) i_ad_iqcor (
.clk (dac_clk),
.valid (dac_valid),
.data_in (dac_data),

11
library/axi_dac_interpolate/axi_dac_interpolate_reg.v
View File

@ -62,7 +62,8 @@ module axi_dac_interpolate_reg(
input up_rreq,
input [ 4:0] up_raddr,
output reg [31:0] up_rdata,
output reg up_rack);
output reg up_rack
);
// internal registers
@ -167,7 +168,9 @@ module axi_dac_interpolate_reg(
end
end
up_xfer_cntrl #(.DATA_WIDTH(128)) i_xfer_cntrl (
up_xfer_cntrl #(
.DATA_WIDTH(128)
) i_xfer_cntrl (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_cntrl ({ up_config[1], // 1
@ -198,7 +201,3 @@ module axi_dac_interpolate_reg(
dac_filter_mask_a})); // 3
endmodule
// ***************************************************************************
// ***************************************************************************

30
library/axi_dac_interpolate/cic_interp.v
View File

@ -37,27 +37,17 @@
`timescale 1 ns / 1 ns
module cic_interp
(
clk,
clk_enable,
reset,
filter_in,
rate,
load_rate,
filter_out,
ce_out
module cic_interp (
input clk,
input clk_enable,
input reset,
input signed [30:0] filter_in, //sfix31_En30
input [15:0] rate, //ufix16
input load_rate,
output signed [109:0] filter_out, //sfix110_En30
output ce_out
);
input clk;
input clk_enable;
input reset;
input signed [30:0] filter_in; //sfix31_En30
input [15:0] rate; //ufix16
input load_rate;
output signed [109:0] filter_out; //sfix110_En30
output ce_out;
////////////////////////////////////////////////////////////////
//Module Architecture: cic_interp
////////////////////////////////////////////////////////////////
@ -611,4 +601,4 @@ module cic_interp
// Assignment Statements
assign ce_out = phase_0;
assign filter_out = output_register;
endmodule // cic_interp
endmodule

25
library/axi_dac_interpolate/fir_interp.v
View File

@ -40,23 +40,15 @@
`timescale 1 ns / 1 ns
module fir_interp
(
clk,
clk_enable,
reset,
filter_in,
filter_out,
ce_out
module fir_interp (
input clk,
input clk_enable,
input reset,
input signed [15:0] filter_in, //sfix16_En15
output signed [35:0] filter_out, //sfix36_En30
output ce_out
);
input clk;
input clk_enable;
input reset;
input signed [15:0] filter_in; //sfix16_En15
output signed [35:0] filter_out; //sfix36_En30
output ce_out;
////////////////////////////////////////////////////////////////
//Module Architecture: fir_interp
////////////////////////////////////////////////////////////////
@ -214,7 +206,6 @@ module fir_interp
end
end // Delay_Pipeline_process
assign product_mux = (cur_count == 2'b00) ? coeffphase1_12 :
coeffphase2_12;
assign product = delay_pipeline[11] * product_mux;
@ -387,4 +378,4 @@ module fir_interp
// Assignment Statements
assign ce_out = phase_1;
assign filter_out = output_register;
endmodule // fir_interp
endmodule

4
library/axi_dmac/address_generator.v
View File

@ -43,8 +43,8 @@ module address_generator #(
parameter BEATS_PER_BURST_WIDTH = 4,
parameter BYTES_PER_BEAT_WIDTH = $clog2(DMA_DATA_WIDTH/8),
parameter LENGTH_WIDTH = 8,
parameter CACHE_COHERENT = 0)(
parameter CACHE_COHERENT = 0
) (
input clk,
input resetn,

10
library/axi_dmac/axi_dmac.v
View File

@ -65,6 +65,7 @@ module axi_dmac #(
parameter ALLOW_ASYM_MEM = 0,
parameter CACHE_COHERENT_DEST = 0
) (
// Slave AXI interface
input s_axi_aclk,
input s_axi_aresetn,
@ -186,8 +187,6 @@ module axi_dmac #(
output [AXI_ID_WIDTH_SRC-1:0] m_src_axi_wid,
input [AXI_ID_WIDTH_SRC-1:0] m_src_axi_bid,
// Slave streaming AXI interface
input s_axis_aclk,
output s_axis_ready,
@ -234,7 +233,6 @@ module axi_dmac #(
output [7:0] dest_diag_level_bursts
);
localparam DMA_TYPE_AXI_MM = 0;
localparam DMA_TYPE_AXI_STREAM = 1;
localparam DMA_TYPE_FIFO = 2;
@ -465,8 +463,7 @@ axi_dmac_regmap #(
.dbg_src_addr(m_src_axi_araddr),
.dbg_status(dbg_status),
.dbg_ids0(dbg_ids0),
.dbg_ids1(dbg_ids1)
);
.dbg_ids1(dbg_ids1));
axi_dmac_transfer #(
.DMA_DATA_WIDTH_SRC(DMA_DATA_WIDTH_SRC),
@ -596,8 +593,7 @@ axi_dmac_transfer #(
.dbg_src_response_id(src_response_id),
.dbg_status(dbg_status),
.dest_diag_level_bursts(dest_diag_level_bursts)
);
.dest_diag_level_bursts(dest_diag_level_bursts));
assign m_dest_axi_arvalid = 1'b0;
assign m_dest_axi_rready = 1'b0;

17
library/axi_dmac/axi_dmac_burst_memory.v
View File

@ -85,7 +85,7 @@ localparam DATA_WIDTH_MEM = DATA_WIDTH_SRC > DATA_WIDTH_DEST ?
localparam MEM_RATIO = DATA_WIDTH_SRC > DATA_WIDTH_DEST ?
DATA_WIDTH_SRC / DATA_WIDTH_DEST : DATA_WIDTH_DEST / DATA_WIDTH_SRC;
/* A burst can have up to 256 beats */
// A burst can have up to 256 beats
localparam BURST_LEN = MAX_BYTES_PER_BURST / (DATA_WIDTH_MEM / 8);
localparam BURST_LEN_WIDTH = BURST_LEN > 128 ? 8 :
BURST_LEN > 64 ? 7 :
@ -369,8 +369,7 @@ axi_dmac_resize_src #(
.mem_data (src_mem_data),
.mem_data_last (src_mem_data_last),
.mem_data_valid_bytes (src_mem_data_valid_bytes),
.mem_data_partial_burst (src_mem_data_partial_burst)
);
.mem_data_partial_burst (src_mem_data_partial_burst));
assign src_burst_len_data = {src_mem_data_partial_burst,
src_beat_counter,
@ -390,8 +389,7 @@ ad_mem_asym #(
.clkb (dest_clk),
.reb (dest_beat),
.addrb (dest_raddr),
.doutb (dest_mem_data)
);
.doutb (dest_mem_data));
axi_dmac_resize_dest #(
.DATA_WIDTH_DEST (DATA_WIDTH_DEST),
@ -410,8 +408,7 @@ axi_dmac_resize_dest #(
.dest_data_ready (dest_data_ready),
.dest_data (dest_data),
.dest_data_last (dest_data_last),
.dest_data_strb (dest_data_strb)
);
.dest_data_strb (dest_data_strb));
sync_bits #(
.NUM_OF_BITS (ID_WIDTH),
@ -420,8 +417,7 @@ sync_bits #(
.in_bits (src_id),
.out_clk (dest_clk),
.out_resetn (1'b1),
.out_bits (dest_src_id)
);
.out_bits (dest_src_id));
sync_bits #(
.NUM_OF_BITS (ID_WIDTH),
@ -430,8 +426,7 @@ sync_bits #(
.in_bits (dest_id),
.out_clk (src_clk),
.out_resetn (1'b1),
.out_bits (src_dest_id)
);
.out_bits (src_dest_id));
assign dest_request_id = dest_src_id;
assign dest_data_response_id = dest_id;

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