docs: Add cn0561 doc (#1245)
* docs: Add cn0561 doc. Update by guidelines Signed-off-by: laurent-19 <laurentiu.popa@analog.com> --------- Signed-off-by: laurent-19 <laurentiu.popa@analog.com>main
laurent-19
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@ -29,6 +29,7 @@ HDL Reference Designs
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AD9434-FMC <projects/ad9434_fmc/index>
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AD9783-EBZ <projects/ad9783_ebz/index>
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ADAQ7980-SDZ <projects/adaq7980_sdz/index>
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CN0561 <projects/cn0561/index>
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.. role:: red
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.. role:: green
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@ -0,0 +1,286 @@
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.. _cn0561:
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CN0561 HDL project
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===============================================================================
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Overview
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-------------------------------------------------------------------------------
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The :adi:`AD4134` is a quad channel, low noise, simultaneous sampling,
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precision analog-to-digital converter (ADC), based on the continuous time
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sigma-delta (CTSD) modulation scheme. This architecture inherently rejects
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signals around the ADC aliasing frequency band, giving the device its inherent
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antialiasing capability, and removesthe need for a complex external
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antialiasing filter.
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This device has four independent converter channels in parallel, each with a
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CTSD modulator and a digital decimation and filtering path. It enables
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simultaneous sampling of four signal sources, with a maximum input bandwidth
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of 391.5 kHz. It supports a wide range of ODR frequencies, from 0.01 kSPS to
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1496 kSPS wih less than 0.01 SPS adjustment resolution, allowing the user to
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granularly vary sampling speed to achieve coherent sampling.
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The :adi:`AD4134` supports two device configuration schemes: serial peripheral
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interface (SPI) and hardware pin configuration (pin control mode).
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The SPI control mode offers access to all the features and configuration
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options available on the chip. Pin control mode offers the benefit of
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simplifying the device configuration, enabling the device to operate
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autonomously after power-up operating in a standalone mode.
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The HDL reference design for the EVAL-CN0561 provides all the interfaces that
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are necessary to interact with the device using a Xilinx FPGA development
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board; to acquire data from the ADC device, supporting continuous data
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capture at maximum 1.5 MSPS data rate. However, due to a hardware limitation,
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the Cora-Z7s variant will only support a maximum data clock of 24MHz,
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in contrast with 48MHz supported on the Zedboard.
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Supported boards
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-------------------------------------------------------------------------------
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- :adi:`EVAL-CN0561 <EVAL-CN0561>`
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Supported devices
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-------------------------------------------------------------------------------
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- :adi:`AD4134`
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Supported carriers
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-------------------------------------------------------------------------------
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- :xilinx:`ZedBoard <products/boards-and-kits/1-8dyf-11.html>` on FMC slot
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- :xilinx:`Cora Z7-07S <https://digilent.com/shop/cora-z7-zynq-7000-single-core-for-arm-fpga-soc-development/>` on Arduino type headers
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- `DE10-Nano <https://www.intel.com/content/www/us/en/developer/topic-technology/edge-5g/hardware/fpga-de10-nano.html>`__ on Arduino type headers
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Block design
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-------------------------------------------------------------------------------
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The reference design uses the SPI Engine Framework to interface with
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the AD4134 ADC and only supports the slave mode with both DCLK and ODR
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generated by the FPGA. The device sends data on the 4 DIN bits.
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Block diagram
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The data path and clock domains are depicted in the below diagrams:
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.. image:: cn0561_hdl.svg
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:width: 800
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:align: center
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:alt: CN0561/ZED/Cora Z7-07S block diagram *
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.. admonition:: Legend
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:class: note
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``*`` The block design for Cora Z7-07S remains the same, the only
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difference is the data clock frequency of 24MHz.
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Jumper setup
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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.. list-table::
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:widths: 15 5 45
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:header-rows: 1
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* - Jumper/Solder link
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- Position
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- Description
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* - P10
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- Mounted
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- MODE (Slave) and DEC0/DCLKIO (DCLK Input)
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* - P13
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- 1-2
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- Current sources and fault protection powered from board ±15V sources
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* - P15
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- 1-2
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- Current sources and fault protection powered from board ±15V sources
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CPU/Memory interconnects addresses
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The addresses are dependent on the architecture of the FPGA, having an offset
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added to the base address from HDL(see more at :ref:`architecture`).
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======================== ===========
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Instance Address
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======================== ===========
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spi_cn0561_axi_regmap 0x44A0_0000
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axi_cn0561_dma 0x44A3_0000
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odr_generator 0x44B0_0000
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axi_cn0561_clkgen 0x44B1_0000
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======================== ===========
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SPI connections
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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.. list-table::
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:widths: 25 25 25 25
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:header-rows: 1
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* - SPI type
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- SPI manager instance
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- SPI subordinate
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- CS
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* - PS
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- SPI 0
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- AD4134
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- 0
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GPIOs
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The Software GPIO number is calculated as follows:
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- Zynq-7000: if PS7 is used, then offset is 54
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.. list-table::
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:widths: 25 25 25 25
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:header-rows: 2
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* - GPIO signal
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- Direction
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- HDL GPIO EMIO
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- Software GPIO
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* -
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- (from FPGA view)
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-
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- Zynq-7000
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* - cn0561_gpio[7:4]
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- INOUT
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- 42:39
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- 96:93
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* - cn0561_gpio[2:0]
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- INOUT
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- 38:36
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- 92:90
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* - cn0561_pinbspi
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- INOUT
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- 35
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- 89
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* - cn0561_mode
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- INOUT
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- 34
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- 88
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* - cn0561_pdn
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- INOUT
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- 33
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- 87
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* - cn0561_resetn
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- INOUT
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- 32
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- 86
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Interrupts
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Below are the Programmable Logic interrupts used in this project.
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=============== === ========== ===========
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Instance name HDL Linux Zynq Actual Zynq
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=============== === ========== ===========
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axi_cn0561_dma 13 57 89
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spi_cn0561 12 56 88
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=============== === ========== ===========
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Building the HDL project
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-------------------------------------------------------------------------------
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The design is built upon ADI's generic HDL reference design framework.
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ADI does not distribute the bit/elf files of these projects so they
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must be built from the sources available :git-hdl:`here </>`. To get
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the source you must
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`clone <https://git-scm.com/book/en/v2/Git-Basics-Getting-a-Git-Repository>`__
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the HDL repository, and then build the project as follows:.
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**Linux/Cygwin/WSL**
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.. code-block::
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:linenos:
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user@analog:~$ cd hdl/projects/cn0561/zed
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user@analog:~/hdl/projects/cn0561/zed$ make
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A more comprehensive build guide can be found in the :ref:`build_hdl`
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user guide.
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Resources
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-------------------------------------------------------------------------------
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Hardware related
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- Product datasheet: :adi:`AD4134`
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HDL related
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- :git-hdl:`CN0561 HDL project source code <projects/cn0561>`
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.. list-table::
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:widths: 30 35 35
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:header-rows: 1
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* - IP name
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- Source code link
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- Documentation link
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* - AXI_CLKGEN
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- :git-hdl:`library/axi_clkgen`
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- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_clkgen>`
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* - AXI_DMAC
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- :git-hdl:`library/axi_dmac`
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- :ref:`here <axi_dmac>`
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* - AXI_HDMI_TX **
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- :git-hdl:`library/axi_hdmi_tx`
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- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_hdmi_tx>`
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* - AXI_I2S_ADI *
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- :git-hdl:`library/axi_i2s_adi`
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- ---
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* - AXI_PWM_GEN
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- :git-hdl:`library/axi_pwm_gen`
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- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_pwm_gen>`
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* - AXI_SDDIF_TX *
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- :git-hdl:`library/axi_spdif_tx`
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- ---
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* - AXI_SYSID
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- :git-hdl:`library/axi_sysid`
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- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_sysid>`
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* - AXI_SPI_ENGINE
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- :git-hdl:`library/spi_engine/axi_spi_engine`
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- :ref:`here <spi_engine axi>`
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* - SPI_ENGINE_EXECUTION
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- :git-hdl:`library/spi_engine/spi_engine_execution`
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- :ref:`here <spi_engine execution>`
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* - SPI_ENGINE_INTERCONNECT
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- :git-hdl:`library/spi_engine/spi_engine_interconnect`
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- :ref:`here <spi_engine interconnect>`
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* - SPI_ENGINE_OFFLOAD
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- :git-hdl:`library/spi_engine/spi_engine_offload`
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- :ref:`here <spi_engine offload>`
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* - AXI_SYSID_ROM
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- :git-hdl:`library/sysid_rom`
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- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_sysid>`
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* - UTIL_I2C_MIXER *
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- :git-hdl:`library/util_i2c_mixer`
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- ---
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.. admonition:: Legend
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:class: note
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- ``*`` instantiated only for Zed carrier
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- ``**`` instantiated only for Zed and De10Nano carriers
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- :ref:`SPI Engine Framework documentation <spi_engine>`
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Software related
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- :git-no-os:`CN0561 No-OS project source code <projects/cn0561>`
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- :git-no-os:`AD4134/AD7134 No-OS Driver source code <drivers/adc/ad713x>`
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- :dokuwiki:`AD4134/AD7134 No-OS Driver documentation <resources/tools-software/uc-drivers/ad713x>`
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- :dokuwiki:`How to build No-OS <resources/no-os/build>`
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.. include:: ../common/more_information.rst
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.. include:: ../common/support.rst
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