library: Fix broken parameters
Fix the broken parameters for the following IP cores: axi_i2s_adi, axi_spdif_tx, util_cpack. Make additional name changes on the local parameters.main
Istvan Csomortani
parent
da315eb6c0
commit
0c3f110bff
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@ -19,30 +19,30 @@ entity axi_i2s_adi is
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generic
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(
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-- ADD USER GENERICS BELOW THIS LINE ---------------
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C_SLOT_WIDTH : integer := 24;
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C_LRCLK_POL : integer := 0; -- LRCLK Polarity (0 - Falling edge, 1 - Rising edge)
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C_BCLK_POL : integer := 0; -- BCLK Polarity (0 - Falling edge, 1 - Rising edge)
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SLOT_WIDTH : integer := 24;
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LRCLK_POL : integer := 0; -- LRCLK Polarity (0 - Falling edge, 1 - Rising edge)
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BCLK_POL : integer := 0; -- BCLK Polarity (0 - Falling edge, 1 - Rising edge)
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-- ADD USER GENERICS ABOVE THIS LINE ---------------
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-- DO NOT EDIT BELOW THIS LINE ---------------------
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-- Bus protocol parameters, do not add to or delete
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C_S_AXI_DATA_WIDTH : integer := 32;
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C_S_AXI_ADDR_WIDTH : integer := 32;
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C_FAMILY : string := "virtex6";
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S_AXI_DATA_WIDTH : integer := 32;
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S_AXI_ADDRESS_WIDTH : integer := 32;
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DEVICE_FAMILY : string := "virtex6";
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-- DO NOT EDIT ABOVE THIS LINE ---------------------
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C_DMA_TYPE : integer := 0;
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C_NUM_CH : integer := 1;
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C_HAS_TX : integer := 1;
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C_HAS_RX : integer := 1
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DMA_TYPE : integer := 0;
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NUM_OF_CHANNEL : integer := 1;
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HAS_TX : integer := 1;
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HAS_RX : integer := 1
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);
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port
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(
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-- Serial Data interface
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DATA_CLK_I : in std_logic;
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BCLK_O : out std_logic_vector(C_NUM_CH - 1 downto 0);
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LRCLK_O : out std_logic_vector(C_NUM_CH - 1 downto 0);
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SDATA_O : out std_logic_vector(C_NUM_CH - 1 downto 0);
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SDATA_I : in std_logic_vector(C_NUM_CH - 1 downto 0);
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BCLK_O : out std_logic_vector(NUM_OF_CHANNEL - 1 downto 0);
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LRCLK_O : out std_logic_vector(NUM_OF_CHANNEL - 1 downto 0);
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SDATA_O : out std_logic_vector(NUM_OF_CHANNEL - 1 downto 0);
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SDATA_I : in std_logic_vector(NUM_OF_CHANNEL - 1 downto 0);
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-- AXI Streaming DMA TX interface
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S_AXIS_ACLK : in std_logic;
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@ -85,17 +85,17 @@ entity axi_i2s_adi is
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-- AXI bus interface
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S_AXI_ACLK : in std_logic;
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S_AXI_ARESETN : in std_logic;
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S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
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S_AXI_AWADDR : in std_logic_vector(S_AXI_ADDRESS_WIDTH-1 downto 0);
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S_AXI_AWVALID : in std_logic;
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S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
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S_AXI_WDATA : in std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0);
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S_AXI_WSTRB : in std_logic_vector((S_AXI_DATA_WIDTH/8)-1 downto 0);
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S_AXI_WVALID : in std_logic;
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S_AXI_BREADY : in std_logic;
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S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
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S_AXI_ARADDR : in std_logic_vector(S_AXI_ADDRESS_WIDTH-1 downto 0);
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S_AXI_ARVALID : in std_logic;
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S_AXI_RREADY : in std_logic;
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S_AXI_ARREADY : out std_logic;
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S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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S_AXI_RDATA : out std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0);
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S_AXI_RRESP : out std_logic_vector(1 downto 0);
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S_AXI_RVALID : out std_logic;
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S_AXI_WREADY : out std_logic;
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@ -113,13 +113,13 @@ architecture Behavioral of axi_i2s_adi is
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signal i2s_reset : std_logic;
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signal tx_fifo_reset : std_logic;
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signal tx_enable : Boolean;
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signal tx_data : std_logic_vector(C_SLOT_WIDTH - 1 downto 0);
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signal tx_data : std_logic_vector(SLOT_WIDTH - 1 downto 0);
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signal tx_ack : std_logic;
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signal tx_stb : std_logic;
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signal rx_enable : Boolean;
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signal rx_fifo_reset : std_logic;
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signal rx_data : std_logic_vector(C_SLOT_WIDTH - 1 downto 0);
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signal rx_data : std_logic_vector(SLOT_WIDTH - 1 downto 0);
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signal rx_ack : std_logic;
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signal rx_stb : std_logic;
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@ -135,7 +135,7 @@ signal I2S_CONTROL_REG : std_logic_vector(31 downto 0);
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signal I2S_CLK_CONTROL_REG : std_logic_vector(31 downto 0);
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signal PERIOD_LEN_REG : std_logic_vector(31 downto 0);
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constant FIFO_AWIDTH : integer := integer(ceil(log2(real(C_NUM_CH * 8))));
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constant FIFO_AWIDTH : integer := integer(ceil(log2(real(NUM_OF_CHANNEL * 8))));
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-- Audio samples FIFO
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constant RAM_ADDR_WIDTH : integer := 7;
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@ -175,7 +175,7 @@ begin
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end if;
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end process;
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streaming_dma_tx_gen: if C_DMA_TYPE = 0 and C_HAS_TX = 1 generate
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streaming_dma_tx_gen: if DMA_TYPE = 0 and HAS_TX = 1 generate
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tx_fifo : entity axi_streaming_dma_tx_fifo
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generic map(
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RAM_ADDR_WIDTH => FIFO_AWIDTH,
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@ -199,11 +199,11 @@ begin
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);
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end generate;
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no_streaming_dma_tx_gen: if C_DMA_TYPE /= 0 or C_HAS_TX /= 1 generate
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no_streaming_dma_tx_gen: if DMA_TYPE /= 0 or HAS_TX /= 1 generate
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S_AXIS_TREADY <= '0';
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end generate;
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streaming_dma_rx_gen: if C_DMA_TYPE = 0 and C_HAS_RX = 1 generate
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streaming_dma_rx_gen: if DMA_TYPE = 0 and HAS_RX = 1 generate
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rx_fifo : entity axi_streaming_dma_rx_fifo
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generic map(
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RAM_ADDR_WIDTH => FIFO_AWIDTH,
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@ -232,7 +232,7 @@ begin
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M_AXIS_TDATA(7 downto 0) <= (others => '0');
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end generate;
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no_streaming_dma_rx_gen: if C_DMA_TYPE /= 0 or C_HAS_RX /= 1 generate
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no_streaming_dma_rx_gen: if DMA_TYPE /= 0 or HAS_RX /= 1 generate
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M_AXIS_TDATA <= (others => '0');
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M_AXIS_TLAST <= '0';
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M_AXIS_TVALID <= '0';
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@ -241,7 +241,7 @@ begin
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pl330_dma_tx_gen: if C_DMA_TYPE = 1 and C_HAS_TX = 1 generate
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pl330_dma_tx_gen: if DMA_TYPE = 1 and HAS_TX = 1 generate
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tx_fifo_stb <= '1' when wr_addr = 11 and wr_stb = '1' else '0';
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tx_fifo: entity pl330_dma_fifo
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@ -275,14 +275,14 @@ begin
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);
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end generate;
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no_pl330_dma_tx_gen: if C_DMA_TYPE /= 1 or C_HAS_TX /= 1 generate
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no_pl330_dma_tx_gen: if DMA_TYPE /= 1 or HAS_TX /= 1 generate
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DMA_REQ_TX_DAREADY <= '0';
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DMA_REQ_TX_DRVALID <= '0';
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DMA_REQ_TX_DRTYPE <= (others => '0');
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DMA_REQ_TX_DRLAST <= '0';
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end generate;
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pl330_dma_rx_gen: if C_DMA_TYPE = 1 and C_HAS_RX = 1 generate
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pl330_dma_rx_gen: if DMA_TYPE = 1 and HAS_RX = 1 generate
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rx_fifo_ack <= '1' when rd_addr = 10 and rd_ack = '1' else '0';
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rx_fifo: entity pl330_dma_fifo
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@ -317,7 +317,7 @@ begin
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end generate;
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no_pl330_dma_rx_gen: if C_DMA_TYPE /= 1 or C_HAS_RX /= 1 generate
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no_pl330_dma_rx_gen: if DMA_TYPE /= 1 or HAS_RX /= 1 generate
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DMA_REQ_RX_DAREADY <= '0';
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DMA_REQ_RX_DRVALID <= '0';
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DMA_REQ_RX_DRTYPE <= (others => '0');
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@ -326,12 +326,12 @@ begin
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ctrl : entity i2s_controller
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generic map (
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C_SLOT_WIDTH => C_SLOT_WIDTH,
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C_BCLK_POL => C_BCLK_POL,
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C_LRCLK_POL => C_LRCLK_POL,
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C_NUM_CH => C_NUM_CH,
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C_HAS_TX => C_HAS_TX,
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C_HAS_RX => C_HAS_RX
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C_SLOT_WIDTH => SLOT_WIDTH,
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C_BCLK_POL => BCLK_POL,
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C_LRCLK_POL => LRCLK_POL,
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C_NUM_CH => NUM_OF_CHANNEL,
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C_HAS_TX => HAS_TX,
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C_HAS_RX => HAS_RX
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)
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port map (
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clk => S_AXI_ACLK,
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@ -368,8 +368,8 @@ begin
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ctrlif: entity axi_ctrlif
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generic map (
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C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
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C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
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C_S_AXI_ADDR_WIDTH => S_AXI_ADDRESS_WIDTH,
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C_S_AXI_DATA_WIDTH => S_AXI_DATA_WIDTH,
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C_NUM_REG => 12
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)
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port map(
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@ -74,26 +74,26 @@ adi_add_bus "I2S" "master" \
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adi_add_bus_clock "DATA_CLK_I" "i2s"
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adi_set_bus_dependency "S_AXIS" "S_AXIS" \
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"(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 0)"
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"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 0)"
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adi_set_bus_dependency "M_AXIS" "M_AXIS" \
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"(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 0)"
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"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 0)"
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adi_set_bus_dependency "DMA_ACK_TX" "DMA_REQ_TX_DA" \
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"(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)"
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"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)"
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adi_set_bus_dependency "DMA_REQ_TX" "DMA_REQ_TX_DR" \
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"(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)"
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"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)"
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adi_set_ports_dependency "DMA_REQ_TX_ACLK" \
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"(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)"
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"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)"
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adi_set_ports_dependency "DMA_REQ_TX_RSTN" \
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"(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)"
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"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)"
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adi_set_bus_dependency "DMA_ACK_RX" "DMA_REQ_RX_DA" \
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"(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)"
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"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)"
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adi_set_bus_dependency "DMA_REQ_RX" "DMA_REQ_RX_DR" \
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"(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)"
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"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)"
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adi_set_ports_dependency "DMA_REQ_RX_ACLK" \
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"(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)"
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"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)"
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adi_set_ports_dependency "DMA_REQ_RX_RSTN" \
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"(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)"
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"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)"
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ipx::save_core [ipx::current_core]
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@ -49,10 +49,10 @@ use work.pl330_dma_fifo;
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entity axi_spdif_tx is
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generic (
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C_S_AXI_DATA_WIDTH : integer := 32;
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C_S_AXI_ADDR_WIDTH : integer := 32;
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C_FAMILY : string := "virtex6";
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C_DMA_TYPE : integer := 0
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S_AXI_DATA_WIDTH : integer := 32;
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S_AXI_ADDRESS_WIDTH : integer := 32;
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DEVICE_FAMILY : string := "virtex6";
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DMA_TYPE : integer := 0
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);
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port (
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--SPDIF ports
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@ -62,17 +62,17 @@ entity axi_spdif_tx is
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--AXI Lite interface
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S_AXI_ACLK : in std_logic;
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S_AXI_ARESETN : in std_logic;
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S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
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S_AXI_AWADDR : in std_logic_vector(S_AXI_ADDRESS_WIDTH-1 downto 0);
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S_AXI_AWVALID : in std_logic;
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S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
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S_AXI_WDATA : in std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0);
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S_AXI_WSTRB : in std_logic_vector((S_AXI_DATA_WIDTH/8)-1 downto 0);
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S_AXI_WVALID : in std_logic;
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S_AXI_BREADY : in std_logic;
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S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
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S_AXI_ARADDR : in std_logic_vector(S_AXI_ADDRESS_WIDTH-1 downto 0);
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S_AXI_ARVALID : in std_logic;
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S_AXI_RREADY : in std_logic;
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S_AXI_ARREADY : out std_logic;
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S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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S_AXI_RDATA : out std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0);
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S_AXI_RRESP : out std_logic_vector(1 downto 0);
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S_AXI_RVALID : out std_logic;
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S_AXI_WREADY : out std_logic;
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@ -109,8 +109,8 @@ architecture IMP of axi_spdif_tx is
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------------------------------------------
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-- SPDIF signals
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------------------------------------------
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signal config_reg : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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signal chstatus_reg : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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signal config_reg : std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0);
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signal chstatus_reg : std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0);
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signal chstat_freq : std_logic_vector(1 downto 0);
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signal chstat_gstat, chstat_preem, chstat_copy, chstat_audio : std_logic;
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@ -140,7 +140,7 @@ begin
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enable <= conf_txdata = '1';
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fifo_data_ack <= channel and sample_data_ack;
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streaming_dma_gen: if C_DMA_TYPE = 0 generate
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streaming_dma_gen: if DMA_TYPE = 0 generate
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fifo: entity axi_streaming_dma_tx_fifo
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generic map (
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RAM_ADDR_WIDTH => 3,
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@ -162,11 +162,11 @@ begin
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);
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end generate;
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no_streaming_dma_gen: if C_DMA_TYPE /= 0 generate
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no_streaming_dma_gen: if DMA_TYPE /= 0 generate
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S_AXIS_TREADY <= '0';
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end generate;
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pl330_dma_gen: if C_DMA_TYPE = 1 generate
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pl330_dma_gen: if DMA_TYPE = 1 generate
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tx_fifo_stb <= '1' when wr_addr = 3 and wr_stb = '1' else '0';
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fifo: entity pl330_dma_fifo
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@ -199,7 +199,7 @@ begin
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);
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end generate;
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no_pl330_dma_gen: if C_DMA_TYPE /= 1 generate
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no_pl330_dma_gen: if DMA_TYPE /= 1 generate
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DMA_REQ_DAREADY <= '0';
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DMA_REQ_DRVALID <= '0';
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DMA_REQ_DRTYPE <= (others => '0');
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@ -255,8 +255,8 @@ begin
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ctrlif: entity axi_ctrlif
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generic map (
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C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
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C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
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C_S_AXI_ADDR_WIDTH => S_AXI_ADDRESS_WIDTH,
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C_S_AXI_DATA_WIDTH => S_AXI_DATA_WIDTH,
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C_NUM_REG => 4
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)
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port map(
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@ -35,16 +35,16 @@ adi_add_bus "DMA_REQ" "master" \
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adi_add_bus_clock "DMA_REQ_ACLK" "DMA_REQ:DMA_ACK" "DMA_REQ_RSTN"
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adi_set_bus_dependency "S_AXIS" "S_AXIS" \
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"(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 0)"
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"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 0)"
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adi_set_bus_dependency "DMA_ACK" "DMA_REQ_DA" \
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"(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)"
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"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)"
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adi_set_bus_dependency "DMA_REQ" "DMA_REQ_DR" \
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"(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)"
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"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)"
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adi_set_ports_dependency "DMA_REQ_ACLK" \
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"(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)"
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"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)"
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adi_set_ports_dependency "DMA_REQ_RSTN" \
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"(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)"
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"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)"
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ipx::save_core [ipx::current_core]
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@ -79,11 +79,10 @@ module util_cpack (
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parameter CHANNEL_DATA_WIDTH = 32;
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parameter NUM_OF_CHANNELS = 8;
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localparam CH_SCNT = CHANNEL_DATA_WIDTH/16;
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localparam SAMPLES_PCHANNEL = CHANNEL_DATA_WIDTH/16;
|
||||
localparam NUM_OF_CHANNELS_M = 8;
|
||||
localparam P_DW = NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH;
|
||||
localparam BUS_DATA_WIDTH = NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH;
|
||||
localparam NUM_OF_CHANNELS_P = NUM_OF_CHANNELS;
|
||||
localparam P_SCNT = P_DW/16;
|
||||
|
||||
// adc interface
|
||||
|
||||
|
|
@ -126,7 +125,7 @@ module util_cpack (
|
|||
reg [((NUM_OF_CHANNELS_M*CHANNEL_DATA_WIDTH)-1):0] adc_data_d = 'd0;
|
||||
reg adc_mux_valid = 'd0;
|
||||
reg [(NUM_OF_CHANNELS_M-1):0] adc_mux_enable = 'd0;
|
||||
reg [((CH_SCNT*16*79)-1):0] adc_mux_data = 'd0;
|
||||
reg [((SAMPLES_PCHANNEL*16*79)-1):0] adc_mux_data = 'd0;
|
||||
reg adc_valid = 'd0;
|
||||
reg adc_sync = 'd0;
|
||||
reg [((NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH)-1):0] adc_data = 'd0;
|
||||
|
|
@ -137,26 +136,26 @@ module util_cpack (
|
|||
wire [(NUM_OF_CHANNELS_M-1):0] adc_valid_s;
|
||||
wire [((NUM_OF_CHANNELS_M*CHANNEL_DATA_WIDTH)-1):0] adc_data_s;
|
||||
wire [((NUM_OF_CHANNELS_M*CHANNEL_DATA_WIDTH)-1):0] adc_data_intlv_s;
|
||||
wire [(CH_SCNT-1):0] adc_mux_valid_s;
|
||||
wire [(CH_SCNT-1):0] adc_mux_enable_0_s;
|
||||
wire [(CH_SCNT-1):0] adc_mux_enable_1_s;
|
||||
wire [(CH_SCNT-1):0] adc_mux_enable_2_s;
|
||||
wire [(CH_SCNT-1):0] adc_mux_enable_3_s;
|
||||
wire [(CH_SCNT-1):0] adc_mux_enable_4_s;
|
||||
wire [(CH_SCNT-1):0] adc_mux_enable_5_s;
|
||||
wire [(CH_SCNT-1):0] adc_mux_enable_6_s;
|
||||
wire [(CH_SCNT-1):0] adc_mux_enable_7_s;
|
||||
wire [((CH_SCNT*16*1)-1):0] adc_mux_data_0_s;
|
||||
wire [((CH_SCNT*16*2)-1):0] adc_mux_data_1_s;
|
||||
wire [((CH_SCNT*16*3)-1):0] adc_mux_data_2_s;
|
||||
wire [((CH_SCNT*16*4)-1):0] adc_mux_data_3_s;
|
||||
wire [((CH_SCNT*16*5)-1):0] adc_mux_data_4_s;
|
||||
wire [((CH_SCNT*16*6)-1):0] adc_mux_data_5_s;
|
||||
wire [((CH_SCNT*16*7)-1):0] adc_mux_data_6_s;
|
||||
wire [((CH_SCNT*16*8)-1):0] adc_mux_data_7_s;
|
||||
wire [(SAMPLES_PCHANNEL-1):0] adc_mux_valid_s;
|
||||
wire [(SAMPLES_PCHANNEL-1):0] adc_mux_enable_0_s;
|
||||
wire [(SAMPLES_PCHANNEL-1):0] adc_mux_enable_1_s;
|
||||
wire [(SAMPLES_PCHANNEL-1):0] adc_mux_enable_2_s;
|
||||
wire [(SAMPLES_PCHANNEL-1):0] adc_mux_enable_3_s;
|
||||
wire [(SAMPLES_PCHANNEL-1):0] adc_mux_enable_4_s;
|
||||
wire [(SAMPLES_PCHANNEL-1):0] adc_mux_enable_5_s;
|
||||
wire [(SAMPLES_PCHANNEL-1):0] adc_mux_enable_6_s;
|
||||
wire [(SAMPLES_PCHANNEL-1):0] adc_mux_enable_7_s;
|
||||
wire [((SAMPLES_PCHANNEL*16*1)-1):0] adc_mux_data_0_s;
|
||||
wire [((SAMPLES_PCHANNEL*16*2)-1):0] adc_mux_data_1_s;
|
||||
wire [((SAMPLES_PCHANNEL*16*3)-1):0] adc_mux_data_2_s;
|
||||
wire [((SAMPLES_PCHANNEL*16*4)-1):0] adc_mux_data_3_s;
|
||||
wire [((SAMPLES_PCHANNEL*16*5)-1):0] adc_mux_data_4_s;
|
||||
wire [((SAMPLES_PCHANNEL*16*6)-1):0] adc_mux_data_5_s;
|
||||
wire [((SAMPLES_PCHANNEL*16*7)-1):0] adc_mux_data_6_s;
|
||||
wire [((SAMPLES_PCHANNEL*16*8)-1):0] adc_mux_data_7_s;
|
||||
wire [(NUM_OF_CHANNELS_M-1):0] adc_dsf_valid_s;
|
||||
wire [(NUM_OF_CHANNELS_M-1):0] adc_dsf_sync_s;
|
||||
wire [(P_DW-1):0] adc_dsf_data_s[(NUM_OF_CHANNELS_M-1):0];
|
||||
wire [(BUS_DATA_WIDTH-1):0] adc_dsf_data_s[(NUM_OF_CHANNELS_M-1):0];
|
||||
|
||||
// loop variables
|
||||
|
||||
|
|
@ -199,7 +198,7 @@ module util_cpack (
|
|||
// interleave data
|
||||
|
||||
generate
|
||||
for (n = 0; n < CH_SCNT; n = n + 1) begin: g_intlv
|
||||
for (n = 0; n < SAMPLES_PCHANNEL; n = n + 1) begin: g_intlv
|
||||
assign adc_data_intlv_s[((16*NUM_OF_CHANNELS_M*(n+1))-1):(16*NUM_OF_CHANNELS_M*n)] =
|
||||
{ adc_data_d[(((CHANNEL_DATA_WIDTH*7)+(16*(n+1)))-1):((CHANNEL_DATA_WIDTH*7)+(16*n))],
|
||||
adc_data_d[(((CHANNEL_DATA_WIDTH*6)+(16*(n+1)))-1):((CHANNEL_DATA_WIDTH*6)+(16*n))],
|
||||
|
|
@ -215,7 +214,7 @@ module util_cpack (
|
|||
// mux
|
||||
|
||||
generate
|
||||
for (n = 0; n < CH_SCNT; n = n + 1) begin: g_mux
|
||||
for (n = 0; n < SAMPLES_PCHANNEL; n = n + 1) begin: g_mux
|
||||
util_cpack_mux i_mux (
|
||||
.adc_clk (adc_clk),
|
||||
.adc_valid (adc_valid_d),
|
||||
|
|
@ -253,22 +252,22 @@ module util_cpack (
|
|||
adc_mux_enable[5] <= & adc_mux_enable_5_s;
|
||||
adc_mux_enable[6] <= & adc_mux_enable_6_s;
|
||||
adc_mux_enable[7] <= & adc_mux_enable_7_s;
|
||||
adc_mux_data[((CH_SCNT*16* 9)-1):(CH_SCNT*16* 1)] <= 'd0;
|
||||
adc_mux_data[((CH_SCNT*16*19)-1):(CH_SCNT*16*12)] <= 'd0;
|
||||
adc_mux_data[((CH_SCNT*16*29)-1):(CH_SCNT*16*23)] <= 'd0;
|
||||
adc_mux_data[((CH_SCNT*16*39)-1):(CH_SCNT*16*34)] <= 'd0;
|
||||
adc_mux_data[((CH_SCNT*16*49)-1):(CH_SCNT*16*45)] <= 'd0;
|
||||
adc_mux_data[((CH_SCNT*16*59)-1):(CH_SCNT*16*56)] <= 'd0;
|
||||
adc_mux_data[((CH_SCNT*16*69)-1):(CH_SCNT*16*67)] <= 'd0;
|
||||
adc_mux_data[((CH_SCNT*16*79)-1):(CH_SCNT*16*78)] <= 'd0;
|
||||
adc_mux_data[((CH_SCNT*16* 1)-1):(CH_SCNT*16* 0)] <= adc_mux_data_0_s;
|
||||
adc_mux_data[((CH_SCNT*16*12)-1):(CH_SCNT*16*10)] <= adc_mux_data_1_s;
|
||||
adc_mux_data[((CH_SCNT*16*23)-1):(CH_SCNT*16*20)] <= adc_mux_data_2_s;
|
||||
adc_mux_data[((CH_SCNT*16*34)-1):(CH_SCNT*16*30)] <= adc_mux_data_3_s;
|
||||
adc_mux_data[((CH_SCNT*16*45)-1):(CH_SCNT*16*40)] <= adc_mux_data_4_s;
|
||||
adc_mux_data[((CH_SCNT*16*56)-1):(CH_SCNT*16*50)] <= adc_mux_data_5_s;
|
||||
adc_mux_data[((CH_SCNT*16*67)-1):(CH_SCNT*16*60)] <= adc_mux_data_6_s;
|
||||
adc_mux_data[((CH_SCNT*16*78)-1):(CH_SCNT*16*70)] <= adc_mux_data_7_s;
|
||||
adc_mux_data[((SAMPLES_PCHANNEL*16* 9)-1):(SAMPLES_PCHANNEL*16* 1)] <= 'd0;
|
||||
adc_mux_data[((SAMPLES_PCHANNEL*16*19)-1):(SAMPLES_PCHANNEL*16*12)] <= 'd0;
|
||||
adc_mux_data[((SAMPLES_PCHANNEL*16*29)-1):(SAMPLES_PCHANNEL*16*23)] <= 'd0;
|
||||
adc_mux_data[((SAMPLES_PCHANNEL*16*39)-1):(SAMPLES_PCHANNEL*16*34)] <= 'd0;
|
||||
adc_mux_data[((SAMPLES_PCHANNEL*16*49)-1):(SAMPLES_PCHANNEL*16*45)] <= 'd0;
|
||||
adc_mux_data[((SAMPLES_PCHANNEL*16*59)-1):(SAMPLES_PCHANNEL*16*56)] <= 'd0;
|
||||
adc_mux_data[((SAMPLES_PCHANNEL*16*69)-1):(SAMPLES_PCHANNEL*16*67)] <= 'd0;
|
||||
adc_mux_data[((SAMPLES_PCHANNEL*16*79)-1):(SAMPLES_PCHANNEL*16*78)] <= 'd0;
|
||||
adc_mux_data[((SAMPLES_PCHANNEL*16* 1)-1):(SAMPLES_PCHANNEL*16* 0)] <= adc_mux_data_0_s;
|
||||
adc_mux_data[((SAMPLES_PCHANNEL*16*12)-1):(SAMPLES_PCHANNEL*16*10)] <= adc_mux_data_1_s;
|
||||
adc_mux_data[((SAMPLES_PCHANNEL*16*23)-1):(SAMPLES_PCHANNEL*16*20)] <= adc_mux_data_2_s;
|
||||
adc_mux_data[((SAMPLES_PCHANNEL*16*34)-1):(SAMPLES_PCHANNEL*16*30)] <= adc_mux_data_3_s;
|
||||
adc_mux_data[((SAMPLES_PCHANNEL*16*45)-1):(SAMPLES_PCHANNEL*16*40)] <= adc_mux_data_4_s;
|
||||
adc_mux_data[((SAMPLES_PCHANNEL*16*56)-1):(SAMPLES_PCHANNEL*16*50)] <= adc_mux_data_5_s;
|
||||
adc_mux_data[((SAMPLES_PCHANNEL*16*67)-1):(SAMPLES_PCHANNEL*16*60)] <= adc_mux_data_6_s;
|
||||
adc_mux_data[((SAMPLES_PCHANNEL*16*78)-1):(SAMPLES_PCHANNEL*16*70)] <= adc_mux_data_7_s;
|
||||
end
|
||||
|
||||
// store & fwd
|
||||
|
|
@ -284,7 +283,7 @@ module util_cpack (
|
|||
.adc_clk (adc_clk),
|
||||
.adc_valid (adc_mux_valid),
|
||||
.adc_enable (adc_mux_enable[n]),
|
||||
.adc_data (adc_mux_data[((CH_SCNT*16*((11*n)+1))-1):(CH_SCNT*16*10*n)]),
|
||||
.adc_data (adc_mux_data[((SAMPLES_PCHANNEL*16*((11*n)+1))-1):(SAMPLES_PCHANNEL*16*10*n)]),
|
||||
.adc_dsf_valid (adc_dsf_valid_s[n]),
|
||||
.adc_dsf_sync (adc_dsf_sync_s[n]),
|
||||
.adc_dsf_data (adc_dsf_data_s[n]));
|
||||
|
|
|
|||
Loading…
Reference in New Issue