diff --git a/projects/fmcadc2/common/fmcadc2_bd.tcl b/projects/fmcadc2/common/fmcadc2_bd.tcl index cb9cdc59f..ab24416bb 100644 --- a/projects/fmcadc2/common/fmcadc2_bd.tcl +++ b/projects/fmcadc2/common/fmcadc2_bd.tcl @@ -39,7 +39,7 @@ set_property -dict [list CONFIG.RX_CDR_CFG {0x03000023ff20400020}] $util_fmcadc2 # reference clocks & resets create_bd_port -dir I rx_ref_clk_0 -create_bd_port -dir O rx_clk +create_bd_port -dir O rx_core_clk ad_xcvrpll rx_ref_clk_0 util_fmcadc2_xcvr/qpll_ref_clk_* ad_xcvrpll rx_ref_clk_0 util_fmcadc2_xcvr/cpll_ref_clk_* @@ -47,19 +47,19 @@ ad_xcvrpll axi_ad9625_xcvr/up_pll_rst util_fmcadc2_xcvr/up_qpll_rst_* ad_xcvrpll axi_ad9625_xcvr/up_pll_rst util_fmcadc2_xcvr/up_cpll_rst_* ad_connect sys_cpu_resetn util_fmcadc2_xcvr/up_rstn ad_connect sys_cpu_clk util_fmcadc2_xcvr/up_clk -ad_connect util_fmcadc2_xcvr/rx_out_clk_0 rx_clk # connections (adc) ad_xcvrcon util_fmcadc2_xcvr axi_ad9625_xcvr axi_ad9625_jesd ad_connect util_fmcadc2_xcvr/rx_out_clk_0 axi_ad9625_core/rx_clk +ad_connect util_fmcadc2_xcvr/rx_out_clk_0 rx_core_clk ad_connect axi_ad9625_jesd/rx_tdata axi_ad9625_core/rx_data ad_connect axi_ad9625_jesd/rx_start_of_frame axi_ad9625_core/rx_sof ad_connect sys_cpu_clk axi_ad9625_fifo/dma_clk ad_connect sys_cpu_clk axi_ad9625_dma/s_axis_aclk ad_connect sys_cpu_resetn axi_ad9625_dma/m_dest_axi_aresetn ad_connect axi_ad9625_core/adc_clk axi_ad9625_fifo/adc_clk -ad_connect axi_ad9625_fifo/adc_rst axi_ad9625_core/adc_rst +ad_connect axi_ad9625_jesd_rstgen/peripheral_reset axi_ad9625_fifo/adc_rst ad_connect axi_ad9625_core/adc_enable axi_ad9625_fifo/adc_wr ad_connect axi_ad9625_core/adc_data axi_ad9625_fifo/adc_wdata ad_connect axi_ad9625_core/adc_dovf axi_ad9625_fifo/adc_wovf diff --git a/projects/fmcadc2/vc707/Makefile b/projects/fmcadc2/vc707/Makefile index 826055268..ab081ce8b 100644 --- a/projects/fmcadc2/vc707/Makefile +++ b/projects/fmcadc2/vc707/Makefile @@ -19,6 +19,7 @@ M_DEPS += ../../common/vc707/vc707_system_mig.prj M_DEPS += ../../common/vc707/vc707_system_constr.xdc M_DEPS += ../../common/vc707/vc707_system_bd.tcl M_DEPS += ../../../library/xilinx/common/ad_iobuf.v +M_DEPS += ../../../library/common/ad_sysref_gen.v M_DEPS += ../../../library/axi_ad9625/axi_ad9625.xpr M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr diff --git a/projects/fmcadc2/vc707/system_constr.xdc b/projects/fmcadc2/vc707/system_constr.xdc index 0a29e3cd0..b0a63362c 100644 --- a/projects/fmcadc2/vc707/system_constr.xdc +++ b/projects/fmcadc2/vc707/system_constr.xdc @@ -42,5 +42,6 @@ create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_ set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9625_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]] -set_property shreg_extract no [get_cells -hier -filter {name =~ *rx_sysref_m*}] -set_false_path -to [get_cells -hier -filter {name =~ *rx_sysref_m* && IS_SEQUENTIAL}] +set_property shreg_extract no [get_cells -hier -filter {name =~ *sysref_en_m*}] +set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m* && IS_SEQUENTIAL}] + diff --git a/projects/fmcadc2/vc707/system_project.tcl b/projects/fmcadc2/vc707/system_project.tcl index a9ca97db1..2d69eb87d 100644 --- a/projects/fmcadc2/vc707/system_project.tcl +++ b/projects/fmcadc2/vc707/system_project.tcl @@ -11,6 +11,7 @@ adi_project_files fmcadc2_vc707 [list \ "system_top.v" \ "system_constr.xdc" \ "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/common/ad_sysref_gen.v" \ "$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ] set_property is_enabled false [get_files *system_axi*_spi*.xdc] diff --git a/projects/fmcadc2/vc707/system_top.v b/projects/fmcadc2/vc707/system_top.v index f69d887c6..be9a8bf87 100644 --- a/projects/fmcadc2/vc707/system_top.v +++ b/projects/fmcadc2/vc707/system_top.v @@ -181,13 +181,6 @@ module system_top ( output spi_adf4355_le_or_clk; inout spi_adf4355_ce_or_sdio; - // internal registers - - reg rx_sysref = 'd0; - reg rx_sysref_m1 = 'd0; - reg rx_sysref_m2 = 'd0; - reg rx_sysref_m3 = 'd0; - // internal signals wire [63:0] gpio_i; @@ -198,19 +191,14 @@ module system_top ( wire spi_miso; wire rx_ref_clk; wire rx_sync; + wire rx_sysref; + wire rx_clk; // default logic assign fan_pwm = 1'b1; assign iic_rstn = 1'b1; - // sysref internal - - always @(posedge rx_clk) begin - rx_sysref_m1 <= gpio_o[34]; - rx_sysref_m2 <= rx_sysref_m1; - rx_sysref <= rx_sysref_m2; - end // instantiations @@ -231,10 +219,6 @@ module system_top ( .O (rx_sync_p), .OB (rx_sync_n)); - // spi - - assign gpio_i[37:36] = gpio_o[37:36]; - fmcadc2_spi i_fmcadc2_spi ( .spi_adf4355 (gpio_o[36]), .spi_adf4355_ce (gpio_o[37]), @@ -262,6 +246,11 @@ module system_top ( .dio_o (gpio_i[20:0]), .dio_p (gpio_bd)); + ad_sysref_gen i_sysref ( + .core_clk (rx_clk), + .sysref_en (gpio_o[34]), + .sysref_out (rx_sysref)); + system_wrapper i_system_wrapper ( .ddr3_addr (ddr3_addr), .ddr3_ba (ddr3_ba), @@ -323,6 +312,7 @@ module system_top ( .rx_ref_clk_0 (rx_ref_clk), .rx_sync_0 (rx_sync), .rx_sysref_0 (rx_sysref), + .rx_core_clk (rx_clk), .sgmii_rxn (sgmii_rxn), .sgmii_rxp (sgmii_rxp), .sgmii_txn (sgmii_txn), @@ -338,8 +328,7 @@ module system_top ( .sys_clk_p (sys_clk_p), .sys_rst (sys_rst), .uart_sin (uart_sin), - .uart_sout (uart_sout), - .rx_clk (rx_clk)); + .uart_sout (uart_sout)); endmodule diff --git a/projects/fmcadc2/zc706/Makefile b/projects/fmcadc2/zc706/Makefile index 3aff736fa..f90b83008 100644 --- a/projects/fmcadc2/zc706/Makefile +++ b/projects/fmcadc2/zc706/Makefile @@ -21,6 +21,7 @@ M_DEPS += ../../common/zc706/zc706_system_constr.xdc M_DEPS += ../../common/zc706/zc706_system_bd.tcl M_DEPS += ../../../library/xilinx/common/ad_lvds_out.v M_DEPS += ../../../library/xilinx/common/ad_iobuf.v +M_DEPS += ../../../library/common/ad_sysref_gen.v M_DEPS += ../../../library/axi_ad9625/axi_ad9625.xpr M_DEPS += ../../../library/xilinx/axi_adcfifo/axi_adcfifo.xpr M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr diff --git a/projects/fmcadc2/zc706/system_constr.xdc b/projects/fmcadc2/zc706/system_constr.xdc index 89fc7716d..f811cf7de 100644 --- a/projects/fmcadc2/zc706/system_constr.xdc +++ b/projects/fmcadc2/zc706/system_constr.xdc @@ -41,3 +41,7 @@ create_clock -name rx_ref_clk -period 1.60 [get_ports rx_ref_clk_p] create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/util_fmcadc2_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK] set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9625_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]] + +set_property shreg_extract no [get_cells -hier -filter {name =~ *sysref_en_m*}] +set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m* && IS_SEQUENTIAL}] + diff --git a/projects/fmcadc2/zc706/system_project.tcl b/projects/fmcadc2/zc706/system_project.tcl index 4f65ab5fb..777034487 100644 --- a/projects/fmcadc2/zc706/system_project.tcl +++ b/projects/fmcadc2/zc706/system_project.tcl @@ -10,6 +10,7 @@ adi_project_files fmcadc2_zc706 [list \ "system_constr.xdc" \ "$ad_hdl_dir/library/xilinx/common/ad_lvds_out.v" \ "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/common/ad_sysref_gen.v" \ "$ad_hdl_dir/projects/common/zc706/zc706_system_mig_constr.xdc" \ "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ] diff --git a/projects/fmcadc2/zc706/system_top.v b/projects/fmcadc2/zc706/system_top.v index 7d5ed8355..714fdd451 100644 --- a/projects/fmcadc2/zc706/system_top.v +++ b/projects/fmcadc2/zc706/system_top.v @@ -195,11 +195,6 @@ module system_top ( output spi_adf4355_le_or_clk; inout spi_adf4355_ce_or_sdio; - // internal registers - - reg rx_sysref = 'd0; - reg rx_sysref_d = 'd0; - // internal signals wire [63:0] gpio_i; @@ -216,13 +211,7 @@ module system_top ( wire rx_ref_clk; wire rx_sync; wire rx_clk; - - // sysref internal - - always @(posedge rx_clk) begin - rx_sysref_d <= gpio_o[34]; - rx_sysref <= rx_sysref_d; - end + wire rx_sysref; // instantiations @@ -245,8 +234,6 @@ module system_top ( // spi - assign gpio_i[37:36] = gpio_o[37:36]; - fmcadc2_spi i_fmcadc2_spi ( .spi_adf4355 (gpio_o[36]), .spi_adf4355_ce (gpio_o[37]), @@ -274,6 +261,11 @@ module system_top ( .dio_o (gpio_i[14:0]), .dio_p (gpio_bd)); + ad_sysref_gen i_sysref ( + .core_clk (rx_clk), + .sysref_en (gpio_o[34]), + .sysref_out (rx_sysref)); + system_wrapper i_system_wrapper ( .ddr3_addr (ddr3_addr), .ddr3_ba (ddr3_ba), @@ -353,6 +345,7 @@ module system_top ( .rx_ref_clk_0 (rx_ref_clk), .rx_sync_0 (rx_sync), .rx_sysref_0 (rx_sysref), + .rx_core_clk (rx_clk), .spdif (spdif), .spi0_clk_i (spi0_clk), .spi0_clk_o (spi0_clk), @@ -374,8 +367,7 @@ module system_top ( .spi1_sdo_o (spi1_mosi), .sys_clk_clk_n (sys_clk_n), .sys_clk_clk_p (sys_clk_p), - .sys_rst (sys_rst), - .rx_clk (rx_clk)); + .sys_rst (sys_rst)); endmodule