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docs: Add HDMI IP cores, update regmap (#1336) 

Add axi_hdmi_tx and axi_hdmi_rx IP core
Update adi_regmap_hdmi.txt

Signed-off-by: Jorge Marques <jorge.marques@analog.com>
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.. _axi_hdmi_rx:
AXI HDMI RX
===============================================================================
.. hdl-component-diagram::
The :git-hdl:`AXI HDMI RX <library/axi_hdmi_rx>` IP core can be used to interface
the :adi:`ADV7611` device using an FPGA.
Features
-------------------------------------------------------------------------------
* AXI based configuration
* Supports multiple resolution (max 1080p)
* Supports embedded sync video reception (16bit data)
* YCbCr or RGB color space output
* Supported on FMC-IMAGEON Xilinx Reference Design
Files
--------------------------------------------------------------------------------
.. list-table::
:header-rows: 1
* - Name
- Description
* - :git-hdl:`library/axi_hdmi_rx/axi_hdmi_rx.v`
- Verilog source for the peripheral.
.. _axi_hdmi_rx block-diagram:
Block Diagram
--------------------------------------------------------------------------------
.. image:: block_diagram.svg
:alt: AXI HDMI RX block diagram
:align: center
Configuration Parameters
-------------------------------------------------------------------------------
.. hdl-parameters::
* - ID
- Core ID should be unique for each axi_hdmi_rx IP in the system.
* - IO_INTERFACE
- Type of the IO interface. 0 - Allow sampling of data on falling edge of
the HDMI clock. others - always sample the input data on rising edge.
Interfaces
-------------------------------------------------------------------------------
.. hdl-interfaces::
* - hdmi_rx_clk
- Pixel clock.
* - hdmi_rx_data
- HDMI data.
* - s_axi
- DMA AXIS interface (vdma).
* - hdmi_clk
- Output clock.
* - hdmi_dma_sof
- Start of frame.
* - hdmi_dma_de
- Data enable.
* - hdmi_dma_data
- HDMI DMA data.
* - hdmi_dma_ovf
- Data overflow signal.
* - hdmi_dma_unf
- Data underflow signal.
Detailed description
-------------------------------------------------------------------------------
The top module (**axi_hdmi_rx**), instantiates:
* axi_hdmi_rx_core module
* the HDMI RX register map
* the AXI handling interface
In **axi_hdmi_rx_core** module the video information is manipulated by passing
through several processing blocks (see :ref:`axi_hdmi_rx block-diagram`):
* Embedded Sync module acquires the video information and splits it into video
data and synchronization signals.
* Chroma supersampling block, super samples the video information to obtain a
24 bit video information, has no impact on the video quality.
* CSC (Color Space Conversion) –converts the video information from YCbCr color
space to RGB color space. If YCbCr is the desired output color space the CSC
block can be bypassed by setting to 1 the value of CSC_BYPASS in ``CNTRL`` register.
* Sync monitoring - monitors the recovered hsync and vsync against the programmed
expected resolution. Asserts out of sync and resolutions mismatch indicators
in the ``TPM_STATUS2`` register.
Register Map
-------------------------------------------------------------------------------
.. hdl-regmap::
:name: HDMI_RX
Design considerations
-------------------------------------------------------------------------------
Additional IPs needed:
* :ref:`axi_dmac`
* :git-hdl:`library/axi_spdif_tx`
The :ref:`axi_dmac` is used to get the video information from the core into memory.
The audio path is separated from the video path, for audio
:git-hdl:`axi_spdif_tx <library/axi_spdif_tx>` core is needed to receive the audio
information from the ADV7611 device and transmit it to the memory.
The whole system needs to be controlled by a processor (ARM or a softcore) that can
program the registers.
Software support
-------------------------------------------------------------------------------
The core can be controlled by no-Os or Linux
* :dokuwiki:`FMC-IMAGEON Xilinx Reference Design <resources/fpga/xilinx/fmc/fmc-imageon>`
* :git-linux:`ADV7604, ADV7611, ADV7612 Linux Driver <drivers/media/i2c/adv7604.c>`
References
-------------------------------------------------------------------------------
* :git-hdl:`library/axi_hdmi_rx`
* :git-hdl:`projects/imageon`
* :dokuwiki:`FMC-IMAGEON Xilinx Reference Design <resources/fpga/xilinx/fmc/fmc-imageon>`
* :dokuwiki:`Zynq & Altera SoC Quick Start Guide <resources/tools-software/linux-software/kuiper-linux>`

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.. _axi_hdmi_tx:
AXI HDMI TX
===============================================================================
.. hdl-component-diagram::
The :git-hdl:`AXI HDMI TX <library/axi_hdmi_tx>` IP core can be used to interface
the :adi:`ADV7511` and :adi:`ADV7123` devices using an FPGA.
Features
-------------------------------------------------------------------------------
* AXI based configuration
* Supports multiple resolution (max 1080p)
* Video transmission on 36/24/16 bits or 8 bits RGB
* Supports embedded sync (16bit data)
* YCbCr or RGB color space output
* Data clipping (min. and max. for each chroma/color value)
* Supports Xilinx 7 Series and Ultrascale devices.
* Supports Altera 5 Series SoC
Files
--------------------------------------------------------------------------------
.. list-table::
:header-rows: 1
* - Name
- Description
* - :git-hdl:`library/axi_hdmi_tx/axi_hdmi_tx.v`
- Verilog source for the peripheral.
.. _axi_hdmi_tx block-diagram:
Block Diagram
--------------------------------------------------------------------------------
.. image:: block_diagram.svg
:alt: AXI HDMI TX block diagram
:align: center
Configuration Parameters
-------------------------------------------------------------------------------
.. hdl-parameters::
* - ID
- Core ID should be unique for each axi_hdmi_tx IP in the system.
* - FPGA_TECHNOLOGY
- Used to select the FPGA Technolgy; beyond the "Choices/Range" listed, also
supports Altera 5 series (101) devices.
* - CR_CB_N
- | Used in the chroma subsampling process, selecting which of the red or blue
| data components will be transmitted first in-between green samples. 1 = red, 0 = blue
* - INTERFACE
- | Interface type towards the 7511. Available options: 16_BIT, 24_BIT, 36_BIT,
| 16_BIT_EMBEDDED_SYNC, VGA_INTERFACE
* - OUT_CLK_POLARITY
- 0 = Launch on rising edge, 1 = Launch on falling edge.
Interfaces
-------------------------------------------------------------------------------
.. hdl-interfaces::
* - reference_clk
- Pixel clock, generated by an axi_clkgen IP core (axi_hdmi_clkgen in
reference design.
* - hdmi_out_clk
- Output clock.
* - s_axis
- DMA AXIS interface (vdma).
* - hdmi_16_hsync
- Horizontal sync signal.
* - hdmi_16_vsync
- Vertical sync signal.
* - hdmi_16_data_e
- Data enable signal.
* - hdmi_16_data
- HDMI data.
* - hdmi_16_es_data
- HDMI embedded sync data.
* - hdmi_24_hsync
- Horizontal sync signal.
* - hdmi_24_vsync
- Vertical sync signal.
* - hdmi_24_data_e
- Data enable signal.
* - hdmi_24_data
- HDMI data.
* - hdmi_36_hsync
- Horizontal sync signal.
* - hdmi_36_vsync
- Vertical sync signal.
* - hdmi_36_data_e
- Data enable signal.
* - hdmi_36_data
- HDMI data.
* - vga_out_clk
- Output clock.
* - vga_hsync
- Horizontal sync signal.
* - vga_vsync
- Vertical sync signal.
* - vga_red
- VGA red data.
* - vga_green
- VGA green data.
* - vga_blue
- VGA red data.
Detailed description
-------------------------------------------------------------------------------
The top module (**axi_hdmi_tx**), instantiates:
* axi_hdmi_tx_core module
* axi_hdmi_tx_vdma module
* the HDMI TX register map
* the AXI handling interface
In **axi_hdmi_tx_core** module the video information is manipulated by passing
through several processing blocks (see :ref:`axi_hdmi_tx block-diagram`):
* **CSC (Color Space Converter)** –converts the video information from RGB color
space to YCbCr color space. If RGB is the desired output color space the CSC
block can be bypassed by setting to 1 the value of CSC_BYPASS register.
* **Data Clipping** bloc gives the possibility of limiting the minimum and
maximum color range values. This block is controlled by FULL_RANGE, CLIPP_MAX
and CLIPP_MIN registers.
* **Chroma subsampling** block as its name suggests, samples the video
information to obtain a video information that requires less bandwidth and
has a minimum impact on the video quality experienced by human eyes.
* **Embedded Sync** module interleaves the video synchronization signals with
the video information, obtaining a more compact transmission path.
* **Sync Signals** block is responsible for generating the video synchronization
signals for video resolutions written in HDMI interface Control register.
The **axi_hdmi_tx_vdma** module ensures the clock domain crossing circuit
between the video source, typically a :ref:`axi_dmac` core and the
**axi_hdmi_core**, which works at different clock speeds depending on the
required resolution.
Register Map
-------------------------------------------------------------------------------
.. hdl-regmap::
:name: HDMI_TX
Design considerations
-------------------------------------------------------------------------------
Additional IPs needed:
* :ref:`axi_dmac`
* :ref:`axi_clkgen`
* :git-hdl:`library/axi_spdif_tx`
:ref:`axi_dmac` provides a high-bandwidth direct memory access for the video stream.
The core is configured as follows:
.. code:: tcl
ad_ip_instance axi_dmac axi_hdmi_dma
ad_ip_parameter axi_hdmi_dma CONFIG.DMA_TYPE_SRC 0
ad_ip_parameter axi_hdmi_dma CONFIG.DMA_TYPE_DEST 1
ad_ip_parameter axi_hdmi_dma CONFIG.CYCLIC true
ad_ip_parameter axi_hdmi_dma CONFIG.DMA_2D_TRANSFER true
ad_ip_parameter axi_hdmi_dma CONFIG.DMA_DATA_WIDTH_DEST 64
The audio path is separated from the video path, for audio **axi_spdif_tx** core
(:git-hdl:`axi_spdif_tx <library/axi_spdif_tx>`) is needed to transmit the audio
information to the ADV7511 device.
The whole system needs to be controlled by a processor (ARM or a soft core) that
can programs the registers.
``axi_clkgen`` generates the clock frequency required for the desired resolution
(pixel clock), the frequency is software configurable
(:git-no-OS:`Example adv7511_zc706 no-Os software <projects/adv7511>`).
Examples for different data width configurations
-------------------------------------------------------------------------------
The :adi:`ADV7511 <media/en/technical-documentation/user-guides/ADV7511_Hardware_Users_Guide.pdf>`
can accept video data from as few as eight pins (either YCbCr 4:2:2 double data
rate [DDR] or YCbCr 4:2:2 with 2x pixel clock) to as many as 36 pins (RGB 4:4:4
or YCbCr 4:4:4). In addition it can accept HSYNC, VSYNC and DE (Data Enable)
The **axi_hdmi_tx** core support the following video input connections:
* 36 bits with HSYNC, VSYNC and DE (:git-hdl:`hdl_2017_r1:projects/adv7511/vc707` development board)
* 24 bits with HSYNC, VSYNC and DE (:git-hdl:`projects/adv7511/zc706` development board)
* 16 bits with HSYNC, VSYNC and DE (:git-hdl:`projects/adv7511/zed`)
* 16 bits with embedded SYNC (TX interface of the :git-hdl:`IMAGEON <projects/imageon>` board)
Software support
-------------------------------------------------------------------------------
The core can be controlled by no-Os or Linux
* :dokuwiki:`Linux Driver <resources/tools-software/linux-drivers/drm/adv7511>`
* :dokuwiki:`Reference design with no-OS example <resources/fpga/xilinx/kc705/adv7511>`
* :git-no-OS:`projects/adv7511`
References
-------------------------------------------------------------------------------
* :git-hdl:`library/axi_hdmi_tx`
* :dokuwiki:`Zynq & Altera SoC Quick Start Guide <resources/tools-software/linux-software/kuiper-linux>`
* :dokuwiki:`FMC-IMAGEON Xilinx Reference Design <resources/fpga/xilinx/fmc/fmc-imageon>`
* :dokuwiki:`ADV7511 Xilinx Evaluation Boards Reference Design <resources/fpga/xilinx/kc705/adv7511>`

188
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@ -8,12 +8,12 @@ ENDTITLE
REG
0x0010
REG_RSTN
RSTN
HDMI Interface Control & Status
ENDREG
FIELD
[0] 0x0
[0] 0x00000000
RSTN
RW
Reset, a common reset is used for all the interface modules,
@ -25,12 +25,12 @@ ENDFIELD
REG
0x0011
REG_CNTRL1
CNTRL1
HDMI Interface Control & Status
ENDREG
FIELD
[2] 0x0
[2] 0x00000000
SS_BYPASS
RW
If set (0x1) bypasses the chroma sub-sampler. This is primarily intended to be used to send
@ -38,18 +38,18 @@ the test-pattern directly to the HDMI transmitter without modifying it.
ENDFIELD
FIELD
[1] 0x0
[1] 0x00000000
RESERVED
RO
Reserved
ENDFIELD
FIELD
[0] 0x0
[0] 0x00000000
CSC_BYPASS
RW
If set (0x1) bypasses color space conversion (if equipped). And depending on its value, the
default value of color space boundaries is set in the REG_CLIPP_MAX and REG_CLIPP_MIN registers.
default value of color space boundaries is set in the CLIPP_MAX and CLIPP_MIN registers.
ENDFIELD
############################################################################################
@ -57,12 +57,12 @@ ENDFIELD
REG
0x0012
REG_CNTRL2
CNTRL2
HDMI Interface Control & Status
ENDREG
FIELD
[1:0] 0x0
[1:0] 0x00000000
SOURCE_SEL
RW
Select the HDMI data source- register constant (0x3), incr-pattern (0x2),
@ -74,13 +74,13 @@ ENDFIELD
REG
0x0013
REG_CNTRL3
CNTRL3
HDMI Interface Control & Status
ENDREG
FIELD
[23:0] 0x000000
CONST_RGB[23:0]
[23:0] 0x00000000
CONST_RGB
RW
This is the RGB value transmitted, if the source is constant (see above).
ENDFIELD
@ -90,13 +90,13 @@ ENDFIELD
REG
0x0015
REG_CLK_FREQ
CLK_FREQ
HDMI Interface Control & Status
ENDREG
FIELD
[31:0] 0x00000000
CLK_FREQ[31:0]
CLK_FREQ
RO
Interface clock frequency. This is relative to the processor clock and in many cases is
100MHz. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor
@ -111,13 +111,13 @@ ENDFIELD
REG
0x0016
REG_CLK_RATIO
CLK_RATIO
HDMI Interface Control & Status
ENDREG
FIELD
[31:0] 0x00000000
CLK_RATIO[31:0]
CLK_RATIO
RO
Interface clock ratio - as a factor actual received clock. This is implementation specific
and depends on any serial to parallel conversion and interface type (ddr/sdr/qdr).
@ -128,12 +128,12 @@ ENDFIELD
REG
0x0017
REG_STATUS
STATUS
ADC Interface Control & Status
ENDREG
FIELD
[0] 0x0
[0] 0x00000000
STATUS
RO
Interface status, if set indicates no errors. If not set, there
@ -145,19 +145,19 @@ ENDFIELD
REG
0x0018
REG_VDMA_STATUS
VDMA_STATUS
HDMI Interface Control & Status
ENDREG
FIELD
[1] 0x0
[1] 0x00000000
VDMA_OVF
RW1C
If set, indicates vdma overflow.
ENDFIELD
FIELD
[0] 0x0
[0] 0x00000000
VDMA_UNF
RW1C
If set, indicates vdma underflow.
@ -168,19 +168,19 @@ ENDFIELD
REG
0x0019
REG_TPM_STATUS
TPM_STATUS
HDMI Interface Control & Status
ENDREG
FIELD
[1] 0x0
[1] 0x00000000
HDMI_TPM_OOS
RW1C
If set, indicates TPM OOS at the HDMI interface.
ENDFIELD
FIELD
[0] 0x0
[0] 0x00000000
VDMA_TPM_OOS
RW1C
If set, indicates TPM OOS at the VDMA interface.
@ -191,20 +191,20 @@ ENDFIELD
REG
0x001a
REG_CLIPP_MAX
CLIPP_MAX
HDMI Interface Control & Status
ENDREG
FIELD
[23:16] 0xF0
R_MAX/Cr_MAX
[23:16] 0x000000F0
R_MAX/CR_MAX
RW
Defines the maximum value for clipping the red or red-difference chroma component.
Default value are 0xf0 for red-difference chroma and 0xfe for red.
ENDFIELD
FIELD
[16:8] 0xEB
[16:8] 0x000000EB
G_MAX/Y_MAX
RW
Defines the maximum value for clipping the green or luma component.
@ -212,8 +212,8 @@ Default values are 0xeb for luma and and 0xfe for green.
ENDFIELD
FIELD
[7:0] 0xF0
B_MAX/Cb_MAX
[7:0] 0x000000F0
B_MAX/CB_MAX
RW
Defines the maximum value for clipping the blue or blue-difference chroma component.
Default value are 0xf0 for blue-difference chroma and 0xfe for blue.
@ -224,20 +224,20 @@ ENDFIELD
REG
0x001b
REG_CLIPP_MIN
CLIPP_MIN
HDMI Interface Control & Status
ENDREG
FIELD
[23:16] 0x10
R_MIN/Cr_MIN
[23:16] 0x00000010
R_MIN/CR_MIN
RW
Defines the minimum value for clipping the red or red-difference chroma component.
Default value are 0x10 for red-difference chroma and 0x01 for red.
ENDFIELD
FIELD
[16:8] 0x10
[16:8] 0x00000010
G_MIN/Y_MIN
RW
Defines the minimum value for clipping the green or luma component.
@ -245,8 +245,8 @@ Default values are 0x10 for luma and and 0x01 for green.
ENDFIELD
FIELD
[7:0] 0x10
B_MIN/Cb_MIN
[7:0] 0x00000010
B_MIN/CB_MIN
RW
Defines the minimum value for clipping the blue or blue-difference chroma component.
Default value are 0x10 for blue-difference chroma and 0x01 for blue.
@ -257,20 +257,20 @@ ENDFIELD
REG
0x0100
REG_HSYNC_1
HSYNC_1
HDMI Interface Control & Status
ENDREG
FIELD
[31:16] 0x0000
H_LINE_ACTIVE[15:0]
[31:16] 0x00000000
H_LINE_ACTIVE
RW
This is the horizontal line active pixel width (active resolution length). e.g. 1920 (1080p)
ENDFIELD
FIELD
[15:0] 0x0000
H_LINE_WIDTH[15:0]
[15:0] 0x00000000
H_LINE_WIDTH
RW
This is the horizontal line width (no. of pixel clocks per line). e.g. 2200 (1080p)
ENDFIELD
@ -280,13 +280,13 @@ ENDFIELD
REG
0x0101
REG_HSYNC_2
HSYNC_2
HDMI Interface Control & Status
ENDREG
FIELD
[15:0] 0x0000
H_SYNC_WIDTH[15:0]
[15:0] 0x00000000
H_SYNC_WIDTH
RW
This is the horizontal sync width (no. of pixel clocks). e.g. 44 (1080p)
ENDFIELD
@ -296,21 +296,21 @@ ENDFIELD
REG
0x0102
REG_HSYNC_3
HSYNC_3
HDMI Interface Control & Status
ENDREG
FIELD
[31:16] 0x0000
H_ENABLE_MAX[15:0]
[31:16] 0x00000000
H_ENABLE_MAX
RW
This is the horizontal data enable maximum. It is the sum of H_ENABLE_MIN and the active
pixel width. e.g. 2112 (192 + 1920) (1080p)
ENDFIELD
FIELD
[15:0] 0x0000
H_ENABLE_MIN[15:0]
[15:0] 0x00000000
H_ENABLE_MIN
RW
This is the horizontal data enable minimum. It is the sum of horizontal back porch (number
of clock cycles between the falling edge of HSYNC to the rising edge of DE) and the sync
@ -322,20 +322,20 @@ ENDFIELD
REG
0x0110
REG_VSYNC_1
VSYNC_1
HDMI Interface Control & Status
ENDREG
FIELD
[31:16] 0x0000
V_FRAME_ACTIVE[15:0]
[31:16] 0x00000000
V_FRAME_ACTIVE
RW
This is the vertical frame active line width (active resolution height). e.g. 1080 (1080p)
ENDFIELD
FIELD
[15:0] 0x0000
V_FRAME_WIDTH[15:0]
[15:0] 0x00000000
V_FRAME_WIDTH
RW
This is the vertical frame width (no. of lines per frame). e.g. 1125 (1080p)
ENDFIELD
@ -345,13 +345,13 @@ ENDFIELD
REG
0x0111
REG_VSYNC_2
VSYNC_2
HDMI Interface Control & Status
ENDREG
FIELD
[15:0] 0x0000
V_SYNC_WIDTH[15:0]
[15:0] 0x00000000
V_SYNC_WIDTH
RW
This is the vertical sync width (no. of lines). e.g. 5 (1080p)
ENDFIELD
@ -361,21 +361,21 @@ ENDFIELD
REG
0x0112
REG_VSYNC_3
VSYNC_3
HDMI Interface Control & Status
ENDREG
FIELD
[31:16] 0x0000
V_ENABLE_MAX[15:0]
[31:16] 0x00000000
V_ENABLE_MAX
RW
This is the vertical data enable maximum. It is the sum of V_ENABLE_MIN and the active
pixel height. e.g. 1121 (41 + 1080) (1080p)
ENDFIELD
FIELD
[15:0] 0x0000
V_ENABLE_MIN[15:0]
[15:0] 0x00000000
V_ENABLE_MIN
RW
This is the vertical data enable minimum. It is the sum of vertical back porch (number of lines
between the falling edge of VSYNC to the rising edge of DE) and the sync width.
@ -387,7 +387,7 @@ ENDFIELD
TITLE
HDMI Receive (axi_hdmi_rx)
hdmi_rx
HDMI_RX
ENDTITLE
############################################################################################
@ -395,12 +395,12 @@ ENDTITLE
REG
0x0010
REG_RSTN
RSTN
HDMI Interface Control & Status
ENDREG
FIELD
[0] 0x0
[0] 0x00000000
RSTN
RW
Reset, a common reset is used for all the interface modules,
@ -412,12 +412,12 @@ ENDFIELD
REG
0x0011
REG_CNTRL
CNTRL
HDMI Interface Control & Status
ENDREG
FIELD
[3] 0x0
[3] 0x00000000
EDGE_SEL
RW
If set (0x1), incoming data is registered on the falling edge of the clock first. The
@ -425,21 +425,21 @@ default uses rising edge.
ENDFIELD
FIELD
[2] 0x0
[2] 0x00000000
BGR
RW
If set (0x1), output BGR. The default is RGB.
ENDFIELD
FIELD
[1] 0x0
[1] 0x00000000
PACKED
RW
If set (0x1) pack 24bit RGB data on 32bit dwords. The default pads the MSB to zeros.
ENDFIELD
FIELD
[0] 0x0
[0] 0x00000000
CSC_BYPASS
RW
If set (0x1) bypasses color space conversion (if equipped).
@ -450,13 +450,13 @@ ENDFIELD
REG
0x0015
REG_CLK_FREQ
CLK_FREQ
HDMI Interface Control & Status
ENDREG
FIELD
[31:0] 0x00000000
CLK_FREQ[31:0]
CLK_FREQ
RO
Interface clock frequency. This is relative to the processor clock and in many cases is
100MHz. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor
@ -471,13 +471,13 @@ ENDFIELD
REG
0x0016
REG_CLK_RATIO
CLK_RATIO
HDMI Interface Control & Status
ENDREG
FIELD
[31:0] 0x00000000
CLK_RATIO[31:0]
CLK_RATIO
RO
Interface clock ratio - as a factor actual received clock. This is implementation specific
and depends on any serial to parallel conversion and interface type (ddr/sdr/qdr).
@ -488,19 +488,19 @@ ENDFIELD
REG
0x0018
REG_VDMA_STATUS
VDMA_STATUS
HDMI Interface Control & Status
ENDREG
FIELD
[1] 0x0
[1] 0x00000000
VDMA_OVF
RW1C
If set, indicates vdma overflow.
ENDFIELD
FIELD
[0] 0x0
[0] 0x00000000
VDMA_UNF
RW1C
If set, indicates vdma underflow.
@ -511,12 +511,12 @@ ENDFIELD
REG
0x0019
REG_TPM_STATUS1
TPM_STATUS1
HDMI Interface Control & Status
ENDREG
FIELD
[1] 0x0
[1] 0x00000000
HDMI_TPM_OOS
RW1C
If set, indicates TPM OOS at the HDMI interface.
@ -527,33 +527,33 @@ ENDFIELD
REG
0x0020
REG_TPM_STATUS2
TPM_STATUS2
HDMI Interface Control & Status
ENDREG
FIELD
[3] 0x0
[3] 0x00000000
VS_OOS
RW1C
If set, indicates VSYNC OOS - the core is unabled to detect/track VSYNC. Consecutive frames have different number of lines.
ENDFIELD
FIELD
[2] 0x0
[2] 0x00000000
HS_OOS
RW1C
If set, indicates HSYNC OOS - the core is unabled to detect/track HSYNC. Consecutive lines have different lengths.
ENDFIELD
FIELD
[1] 0x0
[1] 0x00000000
VS_MISMATCH
RW1C
If set, indicates received (detected) & programmed VSYNC (number of lines) mismatch. Incoming frames are stable but not the expected resolution.
ENDFIELD
FIELD
[0] 0x0
[0] 0x00000000
HS_MISMATCH
RW1C
If set, indicates received (detected) & programmed HSYNC (number of pixels) mismatch. Incoming frames are stable but not the expected resolution.
@ -564,20 +564,20 @@ ENDFIELD
REG
0x0100
REG_HVCOUNTS1
HVCOUNTS1
HDMI Interface Control & Status
ENDREG
FIELD
[31:16] 0x0000
VS_COUNT[15:0]
[31:16] 0x00000000
VS_COUNT
RW
This is the expected active horizontal pixel lines (active resolution length). e.g. 1080 (1080p)
ENDFIELD
FIELD
[15:0] 0x0000
HS_COUNT[15:0]
[15:0] 0x00000000
HS_COUNT
RW
This is the expected horizontal pixel count (no. of pixel clocks per line). e.g. 1920 (1080p)
ENDFIELD
@ -587,21 +587,21 @@ ENDFIELD
REG
0x0101
REG_HVCOUNTS2
HVCOUNTS2
HDMI Interface Control & Status
ENDREG
FIELD
[31:16] 0x0000
VS_COUNT[15:0]
[31:16] 0x00000000
VS_COUNT
RO
This is the detected horizontal active pixel lines (active resolution length).
This field is valid only if VS_OOS is zero.
ENDFIELD
FIELD
[15:0] 0x0000
HS_COUNT[15:0]
[15:0] 0x00000000
HS_COUNT
RO
This is the detected horizontal pixel count (no. of pixel clocks per line).
This field is valid only if HS_OOS is zero.