jesd204_rx/tx: make SYSREF IOB placement optional
In case when the SYSREF is connected to an FPGA IO which has a limitation on the IOB register IN_FF clock line and the required ref clock is high we can't use the IOB registers. e.g. the max clock rate on zcu102 HP IO FF is 312MHz but ref clock is 375MHz; If IOB is used in this case a pulse width violation is reported. This change makes the IOB placement selectable in such case or for targets which don't require class 1 operation.main
Laszlo Nagy
Laszlo Nagy
parent
4d8008e64c
commit
0caea39bad
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@ -14,7 +14,7 @@ GENERIC_DEPS += jesd204_rx_cgs.v
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GENERIC_DEPS += jesd204_rx_ctrl.v
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GENERIC_DEPS += jesd204_rx_lane.v
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XILINX_DEPS += jesd204_rx_constr.xdc
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XILINX_DEPS += jesd204_rx_constr.ttcl
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XILINX_DEPS += jesd204_rx_ip.tcl
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XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_cfg.xml
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@ -41,6 +41,12 @@
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# “The design and implementation of the JESD204 HDL Core used in this project
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# is copyright © 2016-2017, Analog Devices, Inc.”
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#
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<: set ComponentName [getComponentNameString] :>
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<: setOutputDirectory "./" :>
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<: setFileName [ttcl_add $ComponentName "_constr"] :>
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<: setFileExtension ".xdc" :>
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<: setFileProcessingOrder late :>
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<: set sysref_iob [get_property PARAM_VALUE.SYSREF_IOB] :>
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set_property ASYNC_REG TRUE \
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[get_cells {i_lmfc/sysref_d1_reg}] \
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@ -48,5 +54,5 @@ set_property ASYNC_REG TRUE \
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# Make sure that the device clock to sysref skew is at least somewhat
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# predictable
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set_property IOB TRUE \
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set_property IOB <=: $sysref_iob :> \
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[get_cells {i_lmfc/sysref_r_reg}]
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@ -54,15 +54,12 @@ adi_ip_files jesd204_rx [list \
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"jesd204_ilas_monitor.v" \
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"align_mux.v" \
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"jesd204_lane_latency_monitor.v" \
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"jesd204_rx_constr.xdc" \
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"jesd204_rx_constr.ttcl" \
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"jesd204_rx.v" \
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]
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adi_ip_properties_lite jesd204_rx
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set_property PROCESSING_ORDER LATE [ipx::get_files jesd204_rx_constr.xdc \
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-of_objects [ipx::get_file_groups -of_objects [ipx::current_core] \
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-filter {NAME =~ *synthesis*}]]
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adi_ip_ttcl jesd204_rx "jesd204_rx_constr.ttcl"
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adi_ip_add_core_dependencies { \
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analog.com:user:jesd204_common:1.0 \
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@ -139,4 +136,18 @@ adi_add_bus "rx_event" "master" \
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adi_add_bus_clock "clk" "rx_cfg:rx_ilas_config:rx_event:rx_status:rx_data" "reset"
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set cc [ipx::current_core]
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set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
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set param [ipx::add_user_parameter SYSREF_IOB $cc]
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set_property -dict {value_resolve_type user value_format bool value true} $param
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set param [ipgui::add_param -name {SYSREF_IOB} -component $cc -parent $page0]
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set_property -dict [list \
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display_name {Place SYSREF in IOB} \
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widget {checkBox} \
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show_label true \
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] $param
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ipx::create_xgui_files [ipx::current_core]
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ipx::save_core [ipx::current_core]
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@ -9,7 +9,7 @@ GENERIC_DEPS += jesd204_tx.v
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GENERIC_DEPS += jesd204_tx_ctrl.v
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GENERIC_DEPS += jesd204_tx_lane.v
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XILINX_DEPS += jesd204_tx_constr.xdc
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XILINX_DEPS += jesd204_tx_constr.ttcl
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XILINX_DEPS += jesd204_tx_ip.tcl
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XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_cfg.xml
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@ -41,6 +41,12 @@
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# “The design and implementation of the JESD204 HDL Core used in this project
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# is copyright © 2016-2017, Analog Devices, Inc.”
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#
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<: set ComponentName [getComponentNameString] :>
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<: setOutputDirectory "./" :>
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<: setFileName [ttcl_add $ComponentName "_constr"] :>
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<: setFileExtension ".xdc" :>
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<: setFileProcessingOrder late :>
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<: set sysref_iob [get_property PARAM_VALUE.SYSREF_IOB] :>
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set_property ASYNC_REG TRUE \
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[get_cells {i_lmfc/sysref_d1_reg}] \
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@ -48,5 +54,5 @@ set_property ASYNC_REG TRUE \
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# Make sure that the device clock to sysref skew is at least somewhat
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# predictable
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set_property IOB TRUE \
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set_property IOB <=: $sysref_iob :> \
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[get_cells {i_lmfc/sysref_r_reg}]
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@ -49,15 +49,12 @@ adi_ip_create jesd204_tx
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adi_ip_files jesd204_tx [list \
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"jesd204_tx_lane.v" \
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"jesd204_tx_ctrl.v" \
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"jesd204_tx_constr.xdc" \
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"jesd204_tx_constr.ttcl" \
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"jesd204_tx.v"
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]
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adi_ip_properties_lite jesd204_tx
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set_property PROCESSING_ORDER LATE [ipx::get_files jesd204_tx_constr.xdc \
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-of_objects [ipx::get_file_groups -of_objects [ipx::current_core] \
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-filter {NAME =~ *synthesis*}]]
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adi_ip_ttcl jesd204_tx "jesd204_tx_constr.ttcl"
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adi_ip_add_core_dependencies { \
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analog.com:user:jesd204_common:1.0 \
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@ -139,4 +136,18 @@ adi_add_bus "tx_ctrl" "slave" \
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adi_add_bus_clock "clk" "tx_data:tx_cfg:tx_ilas_config:tx_event:tx_status:tx_ctrl" \
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"reset"
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set cc [ipx::current_core]
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set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
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set param [ipx::add_user_parameter SYSREF_IOB $cc]
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set_property -dict {value_resolve_type user value_format bool value true} $param
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set param [ipgui::add_param -name {SYSREF_IOB} -component $cc -parent $page0]
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set_property -dict [list \
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display_name {Place SYSREF in IOB} \
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widget {checkBox} \
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show_label true \
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] $param
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ipx::create_xgui_files [ipx::current_core]
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ipx::save_core [ipx::current_core]
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