fmcadc5-sync- add ldo psync
Rejeesh Kutty
parent
0442e7d404
commit
0cb2316cb9
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@ -55,6 +55,10 @@ module axi_fmcadc5_sync #(parameter integer ID = 0) (
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output rx_sync_1_p,
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output rx_sync_1_n,
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// switching regulator clocks
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output psync,
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// delay interface
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input delay_rst,
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@ -62,12 +66,14 @@ module axi_fmcadc5_sync #(parameter integer ID = 0) (
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// spi override
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output up_spi_req,
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input up_spi_gnt,
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output [ 7:0] up_spi_csn,
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output up_spi_clk,
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output up_spi_mosi,
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input up_spi_miso,
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input [ 7:0] spi_csn_o,
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input spi_clk_o,
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input spi_sdo_o,
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output [ 7:0] spi_csn,
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output spi_clk,
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output spi_mosi,
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input spi_miso,
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// axi interface
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@ -99,6 +105,8 @@ module axi_fmcadc5_sync #(parameter integer ID = 0) (
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// internal registers
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reg [ 7:0] up_psync_count = 'd0;
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reg up_psync = 'd0;
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reg up_sysref_ack_t_m1 = 'd0;
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reg up_sysref_ack_t_m2 = 'd0;
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reg up_sysref_ack_t_m3 = 'd0;
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@ -118,8 +126,12 @@ module axi_fmcadc5_sync #(parameter integer ID = 0) (
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reg up_sync_status_0 = 'd0;
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reg up_delay_ld = 'd0;
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reg [ 4:0] up_delay_wdata = 'd0;
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reg up_spi_req_int = 'd0;
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reg [ 7:0] up_spi_csn_int = 'd0;
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reg up_spi_clk_int = 'd0;
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reg up_spi_mosi_int = 'd0;
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reg up_spi_gnt = 'd0;
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reg up_spi_req = 'd0;
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reg [ 7:0] up_spi_csn = 'd0;
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reg [ 5:0] up_spi_cnt = 'd0;
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reg [ 31:0] up_spi_clk_32 = 'd0;
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reg [ 31:0] up_spi_out_32 = 'd0;
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@ -163,6 +175,7 @@ module axi_fmcadc5_sync #(parameter integer ID = 0) (
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wire up_sysref_ack_t_s;
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wire up_sync_status_t_s;
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wire up_spi_gnt_s;
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wire [ 31:0] up_spi_out_32_s;
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wire [ 7:0] up_spi_in_s;
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wire rx_sysref_control_t_s;
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@ -184,6 +197,26 @@ module axi_fmcadc5_sync #(parameter integer ID = 0) (
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assign up_rstn = s_axi_aresetn;
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assign up_clk = s_axi_aclk;
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// switching regulator clocks (~602K)
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assign psync = up_psync;
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 1'b0) begin
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up_psync_count <= 7'd0;
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up_psync <= 1'b0;
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end else begin
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if (up_psync_count >= 7'h52) begin
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up_psync_count <= 7'd0;
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end else begin
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up_psync_count <= up_psync_count + 1'b1;
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end
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if (up_psync_count >= 7'h4f) begin
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up_psync <= ~up_psync;
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end
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end
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end
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// sysref register(s)
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assign up_sysref_ack_t_s = up_sysref_ack_t_m3 ^ up_sysref_ack_t_m2;
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@ -285,12 +318,37 @@ module axi_fmcadc5_sync #(parameter integer ID = 0) (
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end
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end
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// spi access
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// switching must be glitchless
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assign up_spi_req = up_spi_req_int;
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assign up_spi_csn = up_spi_csn_int;
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assign up_spi_clk = up_spi_clk_32[31];
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assign up_spi_mosi = up_spi_out_32[31];
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assign spi_csn = up_spi_csn_int;
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assign spi_clk = up_spi_clk_int;
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assign spi_mosi = up_spi_mosi_int;
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always @(negedge up_clk) begin
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if (up_spi_gnt == 1'b1) begin
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up_spi_csn_int <= up_spi_csn;
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up_spi_clk_int <= up_spi_clk_32[31];
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up_spi_mosi_int <= up_spi_out_32[31];
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end else begin
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up_spi_csn_int <= spi_csn_o;
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up_spi_clk_int <= spi_clk_o;
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up_spi_mosi_int <= spi_sdo_o;
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end
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end
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assign up_spi_gnt_s = (&spi_csn_o) & ~spi_clk_o;
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always @(posedge up_clk or negedge up_rstn) begin
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if (up_rstn == 1'b0) begin
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up_spi_gnt <= 1'd0;
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end else begin
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if (up_spi_gnt_s == 1'b1) begin
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up_spi_gnt <= up_spi_req;
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end
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end
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end
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// spi data stretching
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assign up_spi_out_32_s[31:28] = {4{up_wdata_s[7]}};
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assign up_spi_out_32_s[27:24] = {4{up_wdata_s[6]}};
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@ -314,8 +372,8 @@ module axi_fmcadc5_sync #(parameter integer ID = 0) (
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_spi_req_int <= 1'd0;
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up_spi_csn_int <= {8{1'b1}};
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up_spi_req <= 1'd0;
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up_spi_csn <= {8{1'b1}};
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up_spi_cnt <= 6'd0;
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up_spi_clk_32 <= 32'd0;
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up_spi_out_32 <= 32'd0;
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@ -323,22 +381,22 @@ module axi_fmcadc5_sync #(parameter integer ID = 0) (
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up_spi_out <= 8'd0;
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end else begin
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if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h0010)) begin
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up_spi_req_int <= up_wdata_s[0];
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up_spi_req <= up_wdata_s[0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h0012)) begin
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up_spi_csn_int <= up_wdata_s[7:0];
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up_spi_csn <= up_wdata_s[7:0];
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end
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if (up_spi_cnt[5] == 1'b1) begin
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up_spi_cnt <= up_spi_cnt + 1'b1;
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up_spi_clk_32 <= {up_spi_clk_32[30:0], 1'd0};
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up_spi_out_32 <= {up_spi_out_32[30:0], 1'd0};
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up_spi_in_32 <= {up_spi_in_32[30:0], up_spi_miso};
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up_spi_in_32 <= {up_spi_in_32[30:0], spi_miso};
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up_spi_out <= up_spi_out;
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end else if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h0013)) begin
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up_spi_cnt <= 6'h20;
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up_spi_clk_32 <= {8{4'h6}};
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up_spi_out_32 <= up_spi_out_32_s;
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up_spi_in_32 <= {31'd0, up_spi_miso};
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up_spi_in_32 <= {31'd0, spi_miso};
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up_spi_out <= up_wdata_s[7:0];
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end
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end
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@ -371,9 +429,9 @@ module axi_fmcadc5_sync #(parameter integer ID = 0) (
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14'h0000: up_rdata <= PCORE_VERSION;
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14'h0001: up_rdata <= ID;
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14'h0002: up_rdata <= up_scratch;
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14'h0010: up_rdata <= {31'd0, up_spi_req_int};
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14'h0010: up_rdata <= {31'd0, up_spi_req};
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14'h0011: up_rdata <= {31'd0, up_spi_gnt};
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14'h0012: up_rdata <= {24'd0, up_spi_csn_int};
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14'h0012: up_rdata <= {24'd0, up_spi_csn};
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14'h0013: up_rdata <= {24'd0, up_spi_out};
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14'h0014: up_rdata <= {24'd0, up_spi_in_s};
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14'h0015: up_rdata <= {31'd0, up_spi_cnt[5]};
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