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adv9009zu11eg: Update FPGA to -2. Update DDR4 clock frequency

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Adrian Costina 2019-11-22 12:52:46 +00:00
parent c44b4957b5
commit 0cb5c0bdaf
2 changed files with 4 additions and 4 deletions
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2
projects/adrv9009zu11eg/adrv2crr_fmc/system_project.tcl
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@ -3,7 +3,7 @@ source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
set p_device "xczu11eg-ffvf1517-1-e"
set p_device "xczu11eg-ffvf1517-2-i"
set sys_zynq 2
adi_project adrv9009zu11eg

6
projects/adrv9009zu11eg/common/adrv9009zu11eg_bd.tcl
View File

@ -189,10 +189,10 @@ ad_ip_instance ip:ddr4 ddr4_1
ad_ip_parameter ddr4_1 CONFIG.C0.DDR4_DataWidth {32}
ad_ip_parameter ddr4_1 CONFIG.C0.DDR4_AxiDataWidth {256}
ad_ip_parameter ddr4_1 CONFIG.C0.DDR4_AxiAddressWidth {31}
ad_ip_parameter ddr4_1 CONFIG.C0.DDR4_InputClockPeriod {3332}
ad_ip_parameter ddr4_1 CONFIG.C0.DDR4_MemoryPart {MT40A512M16HA-083E}
ad_ip_parameter ddr4_1 CONFIG.C0.DDR4_InputClockPeriod {3334}
ad_ip_parameter ddr4_1 CONFIG.C0.DDR4_MemoryPart {MT40A512M16HA-075E}
ad_ip_parameter ddr4_1 CONFIG.C0.BANK_GROUP_WIDTH {1}
ad_ip_parameter ddr4_1 CONFIG.C0.DDR4_CasLatency {16}
ad_ip_parameter ddr4_1 CONFIG.C0.DDR4_CasLatency {18}
ad_connect ddr4_rtl_1 ddr4_1/C0_DDR4