util_clkdiv: set OOC default clock constraints

library/util_clkdiv/Makefile

@@ -8,6 +8,7 @@ LIBRARY_NAME := util_clkdiv
 
 XILINX_DEPS += util_clkdiv.v
 XILINX_DEPS += util_clkdiv_constr.xdc
+XILINX_DEPS += util_clkdiv_ooc.ttcl
 XILINX_DEPS += util_clkdiv_ip.tcl
 
 ALTERA_DEPS += util_clkdiv_alt.v

library/util_clkdiv/util_clkdiv_ip.tcl

@@ -4,10 +4,13 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
 adi_ip_create util_clkdiv
 adi_ip_files util_clkdiv [list \
   "util_clkdiv_constr.xdc" \
+  "util_clkdiv_ooc.ttcl" \
   "util_clkdiv.v" ]
 
 adi_ip_properties_lite util_clkdiv
 
+adi_ip_ttcl util_clkdiv "util_clkdiv_ooc.ttcl"
+
 set_property processing_order LATE [ipx::get_files "util_clkdiv_constr.xdc" \
                   -of_objects [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}]]
 

library/util_clkdiv/util_clkdiv_ooc.ttcl

@@ -0,0 +1,17 @@
+
+<: setFileUsedIn { out_of_context synthesis implementation } :>
+<: ;#Component and file information :>
+<: set ComponentName [getComponentNameString] :>
+<: setOutputDirectory "./" :>
+<: setFileName $ComponentName :>
+<: setFileExtension "_ooc.xdc" :>
+
+# This XDC is used only for OOC mode of synthesis, implementation.
+# These are default values for timing driven synthesis during OOC flow.
+# These values will be overwritten during implementation with information
+# from top level.
+
+create_clock -name clk -period 10 [get_ports clk]
+
+################################################################################
+