From 0cc07a20c8ca0f489c4ea0bfd6efe66c5d99bcde Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Fri, 12 Apr 2019 15:29:52 +0100 Subject: [PATCH] util_clkdiv: set OOC default clock constraints --- library/util_clkdiv/Makefile | 1 + library/util_clkdiv/util_clkdiv_ip.tcl | 3 +++ library/util_clkdiv/util_clkdiv_ooc.ttcl | 17 +++++++++++++++++ 3 files changed, 21 insertions(+) create mode 100644 library/util_clkdiv/util_clkdiv_ooc.ttcl diff --git a/library/util_clkdiv/Makefile b/library/util_clkdiv/Makefile index 3a98e00ea..5db47081c 100644 --- a/library/util_clkdiv/Makefile +++ b/library/util_clkdiv/Makefile @@ -8,6 +8,7 @@ LIBRARY_NAME := util_clkdiv XILINX_DEPS += util_clkdiv.v XILINX_DEPS += util_clkdiv_constr.xdc +XILINX_DEPS += util_clkdiv_ooc.ttcl XILINX_DEPS += util_clkdiv_ip.tcl ALTERA_DEPS += util_clkdiv_alt.v diff --git a/library/util_clkdiv/util_clkdiv_ip.tcl b/library/util_clkdiv/util_clkdiv_ip.tcl index a8083a8e9..d5bd56dce 100644 --- a/library/util_clkdiv/util_clkdiv_ip.tcl +++ b/library/util_clkdiv/util_clkdiv_ip.tcl @@ -4,10 +4,13 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl adi_ip_create util_clkdiv adi_ip_files util_clkdiv [list \ "util_clkdiv_constr.xdc" \ + "util_clkdiv_ooc.ttcl" \ "util_clkdiv.v" ] adi_ip_properties_lite util_clkdiv +adi_ip_ttcl util_clkdiv "util_clkdiv_ooc.ttcl" + set_property processing_order LATE [ipx::get_files "util_clkdiv_constr.xdc" \ -of_objects [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}]] diff --git a/library/util_clkdiv/util_clkdiv_ooc.ttcl b/library/util_clkdiv/util_clkdiv_ooc.ttcl new file mode 100644 index 000000000..dba16a49c --- /dev/null +++ b/library/util_clkdiv/util_clkdiv_ooc.ttcl @@ -0,0 +1,17 @@ + +<: setFileUsedIn { out_of_context synthesis implementation } :> +<: ;#Component and file information :> +<: set ComponentName [getComponentNameString] :> +<: setOutputDirectory "./" :> +<: setFileName $ComponentName :> +<: setFileExtension "_ooc.xdc" :> + +# This XDC is used only for OOC mode of synthesis, implementation. +# These are default values for timing driven synthesis during OOC flow. +# These values will be overwritten during implementation with information +# from top level. + +create_clock -name clk -period 10 [get_ports clk] + +################################################################################ +