axi_mc_current_monitor: updated core to latest axi interface implementation
parent
21591dc485
commit
0d2888a5a6
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@ -45,16 +45,16 @@ module axi_mc_current_monitor
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// physical interface
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input adc_ia_dat_i,
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output adc_ia_clk_o,
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input adc_ib_dat_i,
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output adc_ib_clk_o,
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input adc_it_dat_i,
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output adc_it_clk_o,
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input adc_vbus_dat_i,
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output adc_vbus_clk_o,
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input adc_ia_dat_i,
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output adc_ia_clk_o,
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input adc_ib_dat_i,
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output adc_ib_clk_o,
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input adc_it_dat_i,
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output adc_it_clk_o,
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input adc_vbus_dat_i,
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output adc_vbus_clk_o,
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input ref_clk,
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input ref_clk,
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output [17:0] ia_o,
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output [17:0] ib_o,
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@ -106,7 +106,8 @@ reg adc_valid = 'd0;
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reg [63:0] adc_data = 'd0;
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reg [47:0] adc_data_3 = 'd0;
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reg [31:0] up_rdata = 'd0;
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reg up_ack = 'd0;
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reg up_wack = 'd0;
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reg up_rack = 'd0;
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reg [1:0] adc_data_cnt = 'd0;
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reg [9:0] adc_clk_cnt = 'd0; // used to generate 10 MHz clock for ADCs
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reg adc_clk_reg = 'd0; // used to generate 10 MHz clock for ADCs
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@ -136,9 +137,10 @@ wire up_clk;
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// internal signals
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wire up_sel_s;
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wire up_wr_s;
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wire [13:0] up_addr_s;
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wire up_rreq_s;
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wire up_wreq_s;
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wire [13:0] up_waddr_s;
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wire [13:0] up_raddr_s;
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wire [31:0] up_wdata_s;
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wire [31:0] up_adc_common_rdata_s;
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wire up_adc_common_ack_s;
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@ -483,12 +485,14 @@ begin
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if(up_rstn == 0)
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begin
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up_rdata <= 'd0;
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up_ack <= 'd0;
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up_rack <= 'd0;
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up_wack <= 'd0;
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end
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else
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begin
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up_rdata <= up_adc_common_rdata_s | up_rdata_0_s | up_rdata_1_s | up_rdata_2_s | up_rdata_3_s ;
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up_ack <= up_adc_common_ack_s | up_ack_0_s | up_ack_1_s | up_ack_2_s | up_ack_3_s ;
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up_rack <= up_adc_common_rack_s | up_rack_0_s | up_rack_1_s | up_rack_2_s | up_rack_3_s ;
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up_wack <= up_adc_common_wack_s | up_wack_0_s | up_wack_1_s | up_wack_2_s | up_wack_3_s ;
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end
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end
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@ -547,6 +551,8 @@ up_adc_channel #(.PCORE_ADC_CHID(0)) i_up_adc_channel_ia(
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.adc_dcfilt_coeff(),
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.adc_iqcor_coeff_1(),
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.adc_iqcor_coeff_2(),
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.adc_pnseq_sel(),
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.adc_data_sel(),
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.adc_pn_err(1'b0),
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.adc_pn_oos(1'b0),
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.adc_or(1'b0),
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@ -569,12 +575,14 @@ up_adc_channel #(.PCORE_ADC_CHID(0)) i_up_adc_channel_ia(
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.adc_usr_decimation_n(16'd1),
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.up_rstn(up_rstn),
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.up_clk(up_clk),
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.up_sel(up_sel_s),
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.up_wr(up_wr_s),
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.up_addr(up_addr_s),
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.up_wdata(up_wdata_s),
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.up_rdata(up_rdata_0_s),
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.up_ack(up_ack_0_s));
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_0_s),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_0_s),
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.up_rack (up_rack_0_s));
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up_adc_channel #(.PCORE_ADC_CHID(1)) i_up_adc_channel_ib(
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.adc_clk(adc_clk_s),
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@ -611,12 +619,14 @@ up_adc_channel #(.PCORE_ADC_CHID(1)) i_up_adc_channel_ib(
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.adc_usr_decimation_n(16'd1),
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.up_rstn(up_rstn),
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.up_clk(up_clk),
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.up_sel(up_sel_s),
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.up_wr(up_wr_s),
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.up_addr(up_addr_s),
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.up_wdata(up_wdata_s),
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.up_rdata(up_rdata_1_s),
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.up_ack(up_ack_1_s));
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_1_s),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_1_s),
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.up_rack (up_rack_1_s));
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up_adc_channel #(.PCORE_ADC_CHID(2)) i_up_adc_channel_it(
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.adc_clk(adc_clk_s),
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@ -653,12 +663,14 @@ up_adc_channel #(.PCORE_ADC_CHID(2)) i_up_adc_channel_it(
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.adc_usr_decimation_n(16'd1),
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.up_rstn(up_rstn),
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.up_clk(up_clk),
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.up_sel(up_sel_s),
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.up_wr(up_wr_s),
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.up_addr(up_addr_s),
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.up_wdata(up_wdata_s),
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.up_rdata(up_rdata_2_s),
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.up_ack(up_ack_2_s));
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_2_s),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_2_s),
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.up_rack (up_rack_2_s));
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up_adc_channel #(.PCORE_ADC_CHID(3)) i_up_adc_channel_vbus(
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.adc_clk(adc_clk_s),
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@ -695,13 +707,14 @@ up_adc_channel #(.PCORE_ADC_CHID(3)) i_up_adc_channel_vbus(
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.adc_usr_decimation_n(16'd1),
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.up_rstn(up_rstn),
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.up_clk(up_clk),
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.up_sel(up_sel_s),
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.up_wr(up_wr_s),
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.up_addr(up_addr_s),
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.up_wdata(up_wdata_s),
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.up_rdata(up_rdata_3_s),
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.up_ack(up_ack_3_s));
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_3_s),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_3_s),
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.up_rack (up_rack_3_s));
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// common processor control
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@ -713,9 +726,16 @@ up_adc_common i_up_adc_common(
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.adc_ddr_edgesel(),
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.adc_pin_mode(),
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.adc_status(1'b1),
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.adc_sync_status(1'b0),
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.adc_status_ovf(adc_dovf_i),
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.adc_status_unf(adc_dunf_i),
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.adc_clk_ratio(32'd1),
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.adc_start_code(),
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.adc_sync(),
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.up_status_pn_err(1'b0),
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.up_status_pn_oos(1'b0),
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.up_status_or(1'b0),
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.delay_clk(1'b0),
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.delay_rst(),
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@ -739,16 +759,19 @@ up_adc_common i_up_adc_common(
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.up_usr_chanmax(),
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.adc_usr_chanmax(8'd0),
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.up_adc_gpio_in(32'h0),
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.up_adc_gpio_out(),
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.up_rstn(up_rstn),
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.up_clk(up_clk),
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.up_sel(up_sel_s),
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.up_wr(up_wr_s),
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.up_addr(up_addr_s),
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.up_wdata(up_wdata_s),
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.up_rdata(up_adc_common_rdata_s),
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.up_ack(up_adc_common_ack_s)
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);
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_adc_common_wack_s),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_adc_common_rdata_s),
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.up_rack (up_adc_common_rack_s));
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// up bus interface
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@ -772,12 +795,14 @@ up_axi i_up_axi(
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.up_axi_rresp(s_axi_rresp),
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.up_axi_rdata(s_axi_rdata),
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.up_axi_rready(s_axi_rready),
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.up_sel(up_sel_s),
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.up_wr(up_wr_s),
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.up_addr(up_addr_s),
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.up_wdata(up_wdata_s),
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.up_rdata(up_rdata),
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.up_ack(up_ack));
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata),
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.up_rack (up_rack));
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endmodule
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