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axi|util_adxcvr: Expose TX configurable driver ports 

Expose the TX configurable driver ports, more specifically the
TX_DIFFCTRL, TX_POSTCURSORE and TX_PRECURSORE for software. This
provides a soft tunning capability of the transmit side of the
transceivers, in cases where the insertion loss of the channel is too
high or low, comparing to the default value supported by the default
configuration of the GTs.

You can find information about these configuration ports under the
section called 'TX Configurable Driver' in the GT transceivers user
guide. (UG476, UG576)
main
Istvan Csomortani 2018-10-01 16:36:39 +01:00 committed by István Csomortáni
parent 2602f239fa
commit 0d3e05b311
7 changed files with 254 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
library/interfaces/interfaces_ip.tcl
View File

@ -20,6 +20,9 @@ adi_if_ports output 1 lpm_dfe_n
adi_if_ports output 3 rate
adi_if_ports output 2 sys_clk_sel
adi_if_ports output 3 out_clk_sel
adi_if_ports output 4 tx_diffctrl
adi_if_ports output 5 tx_postcursor
adi_if_ports output 5 tx_precursor
adi_if_ports output 1 enb
adi_if_ports output 12 addr
adi_if_ports output 1 wr

108
library/xilinx/axi_adxcvr/axi_adxcvr.v
View File

@ -47,6 +47,9 @@ module axi_adxcvr #(
parameter integer QPLL_ENABLE = 1,
parameter LPM_OR_DFE_N = 1,
parameter [ 2:0] RATE = 3'd0,
parameter [ 3:0] TX_DIFFCTRL = 4'd8,
parameter [ 4:0] TX_POSTCURSOR = 3'd0,
parameter [ 4:0] TX_PRECURSOR = 3'd0,
parameter [ 1:0] SYS_CLK_SEL = 2'd3,
parameter [ 2:0] OUT_CLK_SEL = 3'd4) (
@ -72,6 +75,9 @@ module axi_adxcvr #(
output [ 2:0] up_ch_rate_0,
output [ 1:0] up_ch_sys_clk_sel_0,
output [ 2:0] up_ch_out_clk_sel_0,
output [ 3:0] up_ch_tx_diffctrl_0,
output [ 4:0] up_ch_tx_postcursor_0,
output [ 4:0] up_ch_tx_precursor_0,
output up_ch_enb_0,
output [11:0] up_ch_addr_0,
output up_ch_wr_0,
@ -94,6 +100,9 @@ module axi_adxcvr #(
output [ 2:0] up_ch_rate_1,
output [ 1:0] up_ch_sys_clk_sel_1,
output [ 2:0] up_ch_out_clk_sel_1,
output [ 3:0] up_ch_tx_diffctrl_1,
output [ 4:0] up_ch_tx_postcursor_1,
output [ 4:0] up_ch_tx_precursor_1,
output up_ch_enb_1,
output [11:0] up_ch_addr_1,
output up_ch_wr_1,
@ -116,6 +125,9 @@ module axi_adxcvr #(
output [ 2:0] up_ch_rate_2,
output [ 1:0] up_ch_sys_clk_sel_2,
output [ 2:0] up_ch_out_clk_sel_2,
output [ 3:0] up_ch_tx_diffctrl_2,
output [ 4:0] up_ch_tx_postcursor_2,
output [ 4:0] up_ch_tx_precursor_2,
output up_ch_enb_2,
output [11:0] up_ch_addr_2,
output up_ch_wr_2,
@ -138,6 +150,9 @@ module axi_adxcvr #(
output [ 2:0] up_ch_rate_3,
output [ 1:0] up_ch_sys_clk_sel_3,
output [ 2:0] up_ch_out_clk_sel_3,
output [ 3:0] up_ch_tx_diffctrl_3,
output [ 4:0] up_ch_tx_postcursor_3,
output [ 4:0] up_ch_tx_precursor_3,
output up_ch_enb_3,
output [11:0] up_ch_addr_3,
output up_ch_wr_3,
@ -167,6 +182,9 @@ module axi_adxcvr #(
output [ 2:0] up_ch_rate_4,
output [ 1:0] up_ch_sys_clk_sel_4,
output [ 2:0] up_ch_out_clk_sel_4,
output [ 3:0] up_ch_tx_diffctrl_4,
output [ 4:0] up_ch_tx_postcursor_4,
output [ 4:0] up_ch_tx_precursor_4,
output up_ch_enb_4,
output [11:0] up_ch_addr_4,
output up_ch_wr_4,
@ -189,6 +207,9 @@ module axi_adxcvr #(
output [ 2:0] up_ch_rate_5,
output [ 1:0] up_ch_sys_clk_sel_5,
output [ 2:0] up_ch_out_clk_sel_5,
output [ 3:0] up_ch_tx_diffctrl_5,
output [ 4:0] up_ch_tx_postcursor_5,
output [ 4:0] up_ch_tx_precursor_5,
output up_ch_enb_5,
output [11:0] up_ch_addr_5,
output up_ch_wr_5,
@ -211,6 +232,9 @@ module axi_adxcvr #(
output [ 2:0] up_ch_rate_6,
output [ 1:0] up_ch_sys_clk_sel_6,
output [ 2:0] up_ch_out_clk_sel_6,
output [ 3:0] up_ch_tx_diffctrl_6,
output [ 4:0] up_ch_tx_postcursor_6,
output [ 4:0] up_ch_tx_precursor_6,
output up_ch_enb_6,
output [11:0] up_ch_addr_6,
output up_ch_wr_6,
@ -233,6 +257,9 @@ module axi_adxcvr #(
output [ 2:0] up_ch_rate_7,
output [ 1:0] up_ch_sys_clk_sel_7,
output [ 2:0] up_ch_out_clk_sel_7,
output [ 3:0] up_ch_tx_diffctrl_7,
output [ 4:0] up_ch_tx_postcursor_7,
output [ 4:0] up_ch_tx_precursor_7,
output up_ch_enb_7,
output [11:0] up_ch_addr_7,
output up_ch_wr_7,
@ -262,6 +289,9 @@ module axi_adxcvr #(
output [ 2:0] up_ch_rate_8,
output [ 1:0] up_ch_sys_clk_sel_8,
output [ 2:0] up_ch_out_clk_sel_8,
output [ 3:0] up_ch_tx_diffctrl_8,
output [ 4:0] up_ch_tx_postcursor_8,
output [ 4:0] up_ch_tx_precursor_8,
output up_ch_enb_8,
output [11:0] up_ch_addr_8,
output up_ch_wr_8,
@ -284,6 +314,9 @@ module axi_adxcvr #(
output [ 2:0] up_ch_rate_9,
output [ 1:0] up_ch_sys_clk_sel_9,
output [ 2:0] up_ch_out_clk_sel_9,
output [ 3:0] up_ch_tx_diffctrl_9,
output [ 4:0] up_ch_tx_postcursor_9,
output [ 4:0] up_ch_tx_precursor_9,
output up_ch_enb_9,
output [11:0] up_ch_addr_9,
output up_ch_wr_9,
@ -306,6 +339,9 @@ module axi_adxcvr #(
output [ 2:0] up_ch_rate_10,
output [ 1:0] up_ch_sys_clk_sel_10,
output [ 2:0] up_ch_out_clk_sel_10,
output [ 3:0] up_ch_tx_diffctrl_10,
output [ 4:0] up_ch_tx_postcursor_10,
output [ 4:0] up_ch_tx_precursor_10,
output up_ch_enb_10,
output [11:0] up_ch_addr_10,
output up_ch_wr_10,
@ -328,6 +364,9 @@ module axi_adxcvr #(
output [ 2:0] up_ch_rate_11,
output [ 1:0] up_ch_sys_clk_sel_11,
output [ 2:0] up_ch_out_clk_sel_11,
output [ 3:0] up_ch_tx_diffctrl_11,
output [ 4:0] up_ch_tx_postcursor_11,
output [ 4:0] up_ch_tx_precursor_11,
output up_ch_enb_11,
output [11:0] up_ch_addr_11,
output up_ch_wr_11,
@ -357,6 +396,9 @@ module axi_adxcvr #(
output [ 2:0] up_ch_rate_12,
output [ 1:0] up_ch_sys_clk_sel_12,
output [ 2:0] up_ch_out_clk_sel_12,
output [ 3:0] up_ch_tx_diffctrl_12,
output [ 4:0] up_ch_tx_postcursor_12,
output [ 4:0] up_ch_tx_precursor_12,
output up_ch_enb_12,
output [11:0] up_ch_addr_12,
output up_ch_wr_12,
@ -379,6 +421,9 @@ module axi_adxcvr #(
output [ 2:0] up_ch_rate_13,
output [ 1:0] up_ch_sys_clk_sel_13,
output [ 2:0] up_ch_out_clk_sel_13,
output [ 3:0] up_ch_tx_diffctrl_13,
output [ 4:0] up_ch_tx_postcursor_13,
output [ 4:0] up_ch_tx_precursor_13,
output up_ch_enb_13,
output [11:0] up_ch_addr_13,
output up_ch_wr_13,
@ -401,6 +446,9 @@ module axi_adxcvr #(
output [ 2:0] up_ch_rate_14,
output [ 1:0] up_ch_sys_clk_sel_14,
output [ 2:0] up_ch_out_clk_sel_14,
output [ 3:0] up_ch_tx_diffctrl_14,
output [ 4:0] up_ch_tx_postcursor_14,
output [ 4:0] up_ch_tx_precursor_14,
output up_ch_enb_14,
output [11:0] up_ch_addr_14,
output up_ch_wr_14,
@ -423,6 +471,9 @@ module axi_adxcvr #(
output [ 2:0] up_ch_rate_15,
output [ 1:0] up_ch_sys_clk_sel_15,
output [ 2:0] up_ch_out_clk_sel_15,
output [ 3:0] up_ch_tx_diffctrl_15,
output [ 4:0] up_ch_tx_postcursor_15,
output [ 4:0] up_ch_tx_precursor_15,
output up_ch_enb_15,
output [11:0] up_ch_addr_15,
output up_ch_wr_15,
@ -533,6 +584,9 @@ module axi_adxcvr #(
wire [ 2:0] up_ch_rate;
wire [ 1:0] up_ch_sys_clk_sel;
wire [ 2:0] up_ch_out_clk_sel;
wire [ 3:0] up_ch_tx_diffctrl;
wire [ 4:0] up_ch_tx_postcursor;
wire [ 4:0] up_ch_tx_precursor;
wire up_ch_pll_locked_0_s;
wire up_ch_rst_done_0_s;
wire up_ch_pll_locked_1_s;
@ -676,6 +730,9 @@ module axi_adxcvr #(
assign up_ch_rate_0 = up_ch_rate;
assign up_ch_sys_clk_sel_0 = up_ch_sys_clk_sel;
assign up_ch_out_clk_sel_0 = up_ch_out_clk_sel;
assign up_ch_tx_diffctrl_0 = up_ch_tx_diffctrl;
assign up_ch_tx_postcursor_0 = up_ch_tx_postcursor;
assign up_ch_tx_precursor_0 = up_ch_tx_precursor;
axi_adxcvr_mstatus #(
.XCVR_ID (0),
@ -736,6 +793,9 @@ module axi_adxcvr #(
assign up_ch_rate_1 = up_ch_rate;
assign up_ch_sys_clk_sel_1 = up_ch_sys_clk_sel;
assign up_ch_out_clk_sel_1 = up_ch_out_clk_sel;
assign up_ch_tx_diffctrl_1 = up_ch_tx_diffctrl;
assign up_ch_tx_postcursor_1 = up_ch_tx_postcursor;
assign up_ch_tx_precursor_1 = up_ch_tx_precursor;
axi_adxcvr_mstatus #(
.XCVR_ID (1),
@ -796,6 +856,9 @@ module axi_adxcvr #(
assign up_ch_rate_2 = up_ch_rate;
assign up_ch_sys_clk_sel_2 = up_ch_sys_clk_sel;
assign up_ch_out_clk_sel_2 = up_ch_out_clk_sel;
assign up_ch_tx_diffctrl_2 = up_ch_tx_diffctrl;
assign up_ch_tx_postcursor_2 = up_ch_tx_postcursor;
assign up_ch_tx_precursor_2 = up_ch_tx_precursor;
axi_adxcvr_mstatus #(
.XCVR_ID (2),
@ -856,6 +919,9 @@ module axi_adxcvr #(
assign up_ch_rate_3 = up_ch_rate;
assign up_ch_sys_clk_sel_3 = up_ch_sys_clk_sel;
assign up_ch_out_clk_sel_3 = up_ch_out_clk_sel;
assign up_ch_tx_diffctrl_3 = up_ch_tx_diffctrl;
assign up_ch_tx_postcursor_3 = up_ch_tx_postcursor;
assign up_ch_tx_precursor_3 = up_ch_tx_precursor;
axi_adxcvr_mstatus #(
.XCVR_ID (3),
@ -936,6 +1002,9 @@ module axi_adxcvr #(
assign up_ch_rate_4 = up_ch_rate;
assign up_ch_sys_clk_sel_4 = up_ch_sys_clk_sel;
assign up_ch_out_clk_sel_4 = up_ch_out_clk_sel;
assign up_ch_tx_diffctrl_4 = up_ch_tx_diffctrl;
assign up_ch_tx_postcursor_4 = up_ch_tx_postcursor;
assign up_ch_tx_precursor_4 = up_ch_tx_precursor;
axi_adxcvr_mstatus #(
.XCVR_ID (4),
@ -996,6 +1065,9 @@ module axi_adxcvr #(
assign up_ch_rate_5 = up_ch_rate;
assign up_ch_sys_clk_sel_5 = up_ch_sys_clk_sel;
assign up_ch_out_clk_sel_5 = up_ch_out_clk_sel;
assign up_ch_tx_diffctrl_5 = up_ch_tx_diffctrl;
assign up_ch_tx_postcursor_5 = up_ch_tx_postcursor;
assign up_ch_tx_precursor_5 = up_ch_tx_precursor;
axi_adxcvr_mstatus #(
.XCVR_ID (5),
@ -1056,6 +1128,9 @@ module axi_adxcvr #(
assign up_ch_rate_6 = up_ch_rate;
assign up_ch_sys_clk_sel_6 = up_ch_sys_clk_sel;
assign up_ch_out_clk_sel_6 = up_ch_out_clk_sel;
assign up_ch_tx_diffctrl_6 = up_ch_tx_diffctrl;
assign up_ch_tx_postcursor_6 = up_ch_tx_postcursor;
assign up_ch_tx_precursor_6 = up_ch_tx_precursor;
axi_adxcvr_mstatus #(
.XCVR_ID (6),
@ -1116,6 +1191,9 @@ module axi_adxcvr #(
assign up_ch_rate_7 = up_ch_rate;
assign up_ch_sys_clk_sel_7 = up_ch_sys_clk_sel;
assign up_ch_out_clk_sel_7 = up_ch_out_clk_sel;
assign up_ch_tx_diffctrl_7 = up_ch_tx_diffctrl;
assign up_ch_tx_postcursor_7 = up_ch_tx_postcursor;
assign up_ch_tx_precursor_7 = up_ch_tx_precursor;
axi_adxcvr_mstatus #(
.XCVR_ID (7),
@ -1196,6 +1274,9 @@ module axi_adxcvr #(
assign up_ch_rate_8 = up_ch_rate;
assign up_ch_sys_clk_sel_8 = up_ch_sys_clk_sel;
assign up_ch_out_clk_sel_8 = up_ch_out_clk_sel;
assign up_ch_tx_diffctrl_8 = up_ch_tx_diffctrl;
assign up_ch_tx_postcursor_8 = up_ch_tx_postcursor;
assign up_ch_tx_precursor_8 = up_ch_tx_precursor;
axi_adxcvr_mstatus #(
.XCVR_ID (8),
@ -1256,6 +1337,9 @@ module axi_adxcvr #(
assign up_ch_rate_9 = up_ch_rate;
assign up_ch_sys_clk_sel_9 = up_ch_sys_clk_sel;
assign up_ch_out_clk_sel_9 = up_ch_out_clk_sel;
assign up_ch_tx_diffctrl_9 = up_ch_tx_diffctrl;
assign up_ch_tx_postcursor_9 = up_ch_tx_postcursor;
assign up_ch_tx_precursor_9 = up_ch_tx_precursor;
axi_adxcvr_mstatus #(
.XCVR_ID (9),
@ -1316,6 +1400,9 @@ module axi_adxcvr #(
assign up_ch_rate_10 = up_ch_rate;
assign up_ch_sys_clk_sel_10 = up_ch_sys_clk_sel;
assign up_ch_out_clk_sel_10 = up_ch_out_clk_sel;
assign up_ch_tx_diffctrl_10 = up_ch_tx_diffctrl;
assign up_ch_tx_postcursor_10 = up_ch_tx_postcursor;
assign up_ch_tx_precursor_10 = up_ch_tx_precursor;
axi_adxcvr_mstatus #(
.XCVR_ID (10),
@ -1376,6 +1463,9 @@ module axi_adxcvr #(
assign up_ch_rate_11 = up_ch_rate;
assign up_ch_sys_clk_sel_11 = up_ch_sys_clk_sel;
assign up_ch_out_clk_sel_11 = up_ch_out_clk_sel;
assign up_ch_tx_diffctrl_11 = up_ch_tx_diffctrl;
assign up_ch_tx_postcursor_11 = up_ch_tx_postcursor;
assign up_ch_tx_precursor_11 = up_ch_tx_precursor;
axi_adxcvr_mstatus #(
.XCVR_ID (11),
@ -1456,6 +1546,9 @@ module axi_adxcvr #(
assign up_ch_rate_12 = up_ch_rate;
assign up_ch_sys_clk_sel_12 = up_ch_sys_clk_sel;
assign up_ch_out_clk_sel_12 = up_ch_out_clk_sel;
assign up_ch_tx_diffctrl_12 = up_ch_tx_diffctrl;
assign up_ch_tx_postcursor_12 = up_ch_tx_postcursor;
assign up_ch_tx_precursor_12 = up_ch_tx_precursor;
axi_adxcvr_mstatus #(
.XCVR_ID (12),
@ -1516,6 +1609,9 @@ module axi_adxcvr #(
assign up_ch_rate_13 = up_ch_rate;
assign up_ch_sys_clk_sel_13 = up_ch_sys_clk_sel;
assign up_ch_out_clk_sel_13 = up_ch_out_clk_sel;
assign up_ch_tx_diffctrl_13 = up_ch_tx_diffctrl;
assign up_ch_tx_postcursor_13 = up_ch_tx_postcursor;
assign up_ch_tx_precursor_13 = up_ch_tx_precursor;
axi_adxcvr_mstatus #(
.XCVR_ID (13),
@ -1576,6 +1672,9 @@ module axi_adxcvr #(
assign up_ch_rate_14 = up_ch_rate;
assign up_ch_sys_clk_sel_14 = up_ch_sys_clk_sel;
assign up_ch_out_clk_sel_14 = up_ch_out_clk_sel;
assign up_ch_tx_diffctrl_14 = up_ch_tx_diffctrl;
assign up_ch_tx_postcursor_14 = up_ch_tx_postcursor;
assign up_ch_tx_precursor_14 = up_ch_tx_precursor;
axi_adxcvr_mstatus #(
.XCVR_ID (14),
@ -1636,6 +1735,9 @@ module axi_adxcvr #(
assign up_ch_rate_15 = up_ch_rate;
assign up_ch_sys_clk_sel_15 = up_ch_sys_clk_sel;
assign up_ch_out_clk_sel_15 = up_ch_out_clk_sel;
assign up_ch_tx_diffctrl_15 = up_ch_tx_diffctrl;
assign up_ch_tx_postcursor_15 = up_ch_tx_postcursor;
assign up_ch_tx_precursor_15 = up_ch_tx_precursor;
axi_adxcvr_mstatus #(
.XCVR_ID (15),
@ -1723,6 +1825,9 @@ module axi_adxcvr #(
.QPLL_ENABLE (QPLL_ENABLE),
.LPM_OR_DFE_N (LPM_OR_DFE_N),
.RATE (RATE),
.TX_DIFFCTRL (TX_DIFFCTRL),
.TX_POSTCURSOR (TX_POSTCURSOR),
.TX_PRECURSOR (TX_PRECURSOR),
.SYS_CLK_SEL (SYS_CLK_SEL),
.OUT_CLK_SEL (OUT_CLK_SEL))
i_up (
@ -1741,6 +1846,9 @@ module axi_adxcvr #(
.up_ch_rate (up_ch_rate),
.up_ch_sys_clk_sel (up_ch_sys_clk_sel),
.up_ch_out_clk_sel (up_ch_out_clk_sel),
.up_ch_tx_diffctrl (up_ch_tx_diffctrl),
.up_ch_tx_postcursor (up_ch_tx_postcursor),
.up_ch_tx_precursor (up_ch_tx_precursor),
.up_ch_sel (up_ch_sel),
.up_ch_enb (up_ch_enb),
.up_ch_addr (up_ch_addr),

3
library/xilinx/axi_adxcvr/axi_adxcvr_ip.tcl
View File

@ -50,6 +50,9 @@ for {set n 0} {$n < 16} {incr n} {
"rate up_ch_rate_${n} "\
"sys_clk_sel up_ch_sys_clk_sel_${n} "\
"out_clk_sel up_ch_out_clk_sel_${n} "\
"tx_diffctrl up_ch_tx_diffctrl_${n} "\
"tx_postcursor up_ch_tx_postcursor_${n} "\
"tx_precursor up_ch_tx_precursor_${n} "\
"enb up_ch_enb_${n} "\
"addr up_ch_addr_${n} "\
"wr up_ch_wr_${n} "\

29
library/xilinx/axi_adxcvr/axi_adxcvr_up.v
View File

@ -46,6 +46,9 @@ module axi_adxcvr_up #(
parameter integer QPLL_ENABLE = 1,
parameter LPM_OR_DFE_N = 1,
parameter [ 2:0] RATE = 3'd0,
parameter [ 3:0] TX_DIFFCTRL = 4'd8,
parameter [ 4:0] TX_POSTCURSOR = 5'd0,
parameter [ 4:0] TX_PRECURSOR = 5'd0,
parameter [ 1:0] SYS_CLK_SEL = 2'd3,
parameter [ 2:0] OUT_CLK_SEL = 3'd4) (
@ -69,6 +72,9 @@ module axi_adxcvr_up #(
output [ 2:0] up_ch_rate,
output [ 1:0] up_ch_sys_clk_sel,
output [ 2:0] up_ch_out_clk_sel,
output [ 3:0] up_ch_tx_diffctrl,
output [ 4:0] up_ch_tx_postcursor,
output [ 4:0] up_ch_tx_precursor,
output [ 7:0] up_ch_sel,
output up_ch_enb,
output [11:0] up_ch_addr,
@ -128,6 +134,9 @@ module axi_adxcvr_up #(
reg [ 2:0] up_rate = RATE;
reg [ 1:0] up_sys_clk_sel = SYS_CLK_SEL;
reg [ 2:0] up_out_clk_sel = OUT_CLK_SEL;
reg [ 3:0] up_tx_diffctrl = TX_DIFFCTRL;
reg [ 4:0] up_tx_postcursor = TX_POSTCURSOR;
reg [ 4:0] up_tx_precursor = TX_PRECURSOR;
reg [ 7:0] up_icm_sel = 'd0;
reg up_icm_enb = 'd0;
reg up_icm_wr = 'd0;
@ -229,6 +238,9 @@ module axi_adxcvr_up #(
assign up_ch_rate = up_rate;
assign up_ch_sys_clk_sel = up_sys_clk_sel;
assign up_ch_out_clk_sel = up_out_clk_sel;
assign up_ch_tx_diffctrl = up_tx_diffctrl;
assign up_ch_tx_postcursor = up_tx_postcursor;
assign up_ch_tx_precursor = up_tx_precursor;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
@ -236,6 +248,9 @@ module axi_adxcvr_up #(
up_rate <= RATE;
up_sys_clk_sel <= SYS_CLK_SEL;
up_out_clk_sel <= OUT_CLK_SEL;
up_tx_diffctrl <= TX_DIFFCTRL;
up_tx_postcursor <= TX_POSTCURSOR;
up_tx_precursor <= TX_PRECURSOR;
end else begin
if ((up_wreq == 1'b1) && (up_waddr == 10'h008)) begin
up_lpm_dfe_n <= up_wdata[12];
@ -243,6 +258,15 @@ module axi_adxcvr_up #(
up_sys_clk_sel <= up_wdata[5:4];
up_out_clk_sel <= up_wdata[2:0];
end
if ((up_wreq == 1'b1) && (up_waddr == 10'h030)) begin
up_tx_diffctrl <= up_wdata[3:0];
end
if ((up_wreq == 1'b1) && (up_waddr == 10'h031)) begin
up_tx_postcursor <= up_wdata[4:0];
end
if ((up_wreq == 1'b1) && (up_waddr == 10'h032)) begin
up_tx_precursor <= up_wdata[4:0];
end
end
end
@ -447,7 +471,7 @@ module axi_adxcvr_up #(
assign up_rparam_s[31:24] = 8'd0;
// xilinx specific
assign up_rparam_s[23:21] = 3'd0;
assign up_rparam_s[20:20] = (QPLL_ENABLE == 0) ? 1'b0 : 1'b1;
assign up_rparam_s[19:16] = XCVR_TYPE[3:0];
@ -488,6 +512,9 @@ module axi_adxcvr_up #(
10'h02c: up_rdata_d <= {20'd0, up_ies_hoffset_step};
10'h02d: up_rdata_d <= up_ies_start_addr;
10'h02e: up_rdata_d <= {31'd0, up_es_status};
10'h030: up_rdata_d <= up_tx_diffctrl;
10'h031: up_rdata_d <= up_tx_postcursor;
10'h032: up_rdata_d <= up_tx_precursor;
default: up_rdata_d <= 32'd0;
endcase
end else begin

96
library/xilinx/util_adxcvr/util_adxcvr.v
View File

@ -130,6 +130,9 @@ module util_adxcvr #(
input [ 2:0] up_tx_rate_0,
input [ 1:0] up_tx_sys_clk_sel_0,
input [ 2:0] up_tx_out_clk_sel_0,
input [ 3:0] up_tx_diffctrl_0,
input [ 4:0] up_tx_postcursor_0,
input [ 4:0] up_tx_precursor_0,
input up_tx_enb_0,
input [11:0] up_tx_addr_0,
input up_tx_wr_0,
@ -185,6 +188,9 @@ module util_adxcvr #(
input [ 2:0] up_tx_rate_1,
input [ 1:0] up_tx_sys_clk_sel_1,
input [ 2:0] up_tx_out_clk_sel_1,
input [ 3:0] up_tx_diffctrl_1,
input [ 4:0] up_tx_postcursor_1,
input [ 4:0] up_tx_precursor_1,
input up_tx_enb_1,
input [11:0] up_tx_addr_1,
input up_tx_wr_1,
@ -240,6 +246,9 @@ module util_adxcvr #(
input [ 2:0] up_tx_rate_2,
input [ 1:0] up_tx_sys_clk_sel_2,
input [ 2:0] up_tx_out_clk_sel_2,
input [ 3:0] up_tx_diffctrl_2,
input [ 4:0] up_tx_postcursor_2,
input [ 4:0] up_tx_precursor_2,
input up_tx_enb_2,
input [11:0] up_tx_addr_2,
input up_tx_wr_2,
@ -295,6 +304,9 @@ module util_adxcvr #(
input [ 2:0] up_tx_rate_3,
input [ 1:0] up_tx_sys_clk_sel_3,
input [ 2:0] up_tx_out_clk_sel_3,
input [ 3:0] up_tx_diffctrl_3,
input [ 4:0] up_tx_postcursor_3,
input [ 4:0] up_tx_precursor_3,
input up_tx_enb_3,
input [11:0] up_tx_addr_3,
input up_tx_wr_3,
@ -358,6 +370,9 @@ module util_adxcvr #(
input [ 2:0] up_tx_rate_4,
input [ 1:0] up_tx_sys_clk_sel_4,
input [ 2:0] up_tx_out_clk_sel_4,
input [ 3:0] up_tx_diffctrl_4,
input [ 4:0] up_tx_postcursor_4,
input [ 4:0] up_tx_precursor_4,
input up_tx_enb_4,
input [11:0] up_tx_addr_4,
input up_tx_wr_4,
@ -413,6 +428,9 @@ module util_adxcvr #(
input [ 2:0] up_tx_rate_5,
input [ 1:0] up_tx_sys_clk_sel_5,
input [ 2:0] up_tx_out_clk_sel_5,
input [ 3:0] up_tx_diffctrl_5,
input [ 4:0] up_tx_postcursor_5,
input [ 4:0] up_tx_precursor_5,
input up_tx_enb_5,
input [11:0] up_tx_addr_5,
input up_tx_wr_5,
@ -468,6 +486,9 @@ module util_adxcvr #(
input [ 2:0] up_tx_rate_6,
input [ 1:0] up_tx_sys_clk_sel_6,
input [ 2:0] up_tx_out_clk_sel_6,
input [ 3:0] up_tx_diffctrl_6,
input [ 4:0] up_tx_postcursor_6,
input [ 4:0] up_tx_precursor_6,
input up_tx_enb_6,
input [11:0] up_tx_addr_6,
input up_tx_wr_6,
@ -523,6 +544,9 @@ module util_adxcvr #(
input [ 2:0] up_tx_rate_7,
input [ 1:0] up_tx_sys_clk_sel_7,
input [ 2:0] up_tx_out_clk_sel_7,
input [ 3:0] up_tx_diffctrl_7,
input [ 4:0] up_tx_postcursor_7,
input [ 4:0] up_tx_precursor_7,
input up_tx_enb_7,
input [11:0] up_tx_addr_7,
input up_tx_wr_7,
@ -586,6 +610,9 @@ module util_adxcvr #(
input [ 2:0] up_tx_rate_8,
input [ 1:0] up_tx_sys_clk_sel_8,
input [ 2:0] up_tx_out_clk_sel_8,
input [ 3:0] up_tx_diffctrl_8,
input [ 4:0] up_tx_postcursor_8,
input [ 4:0] up_tx_precursor_8,
input up_tx_enb_8,
input [11:0] up_tx_addr_8,
input up_tx_wr_8,
@ -641,6 +668,9 @@ module util_adxcvr #(
input [ 2:0] up_tx_rate_9,
input [ 1:0] up_tx_sys_clk_sel_9,
input [ 2:0] up_tx_out_clk_sel_9,
input [ 3:0] up_tx_diffctrl_9,
input [ 4:0] up_tx_postcursor_9,
input [ 4:0] up_tx_precursor_9,
input up_tx_enb_9,
input [11:0] up_tx_addr_9,
input up_tx_wr_9,
@ -696,6 +726,9 @@ module util_adxcvr #(
input [ 2:0] up_tx_rate_10,
input [ 1:0] up_tx_sys_clk_sel_10,
input [ 2:0] up_tx_out_clk_sel_10,
input [ 3:0] up_tx_diffctrl_10,
input [ 4:0] up_tx_postcursor_10,
input [ 4:0] up_tx_precursor_10,
input up_tx_enb_10,
input [11:0] up_tx_addr_10,
input up_tx_wr_10,
@ -751,6 +784,9 @@ module util_adxcvr #(
input [ 2:0] up_tx_rate_11,
input [ 1:0] up_tx_sys_clk_sel_11,
input [ 2:0] up_tx_out_clk_sel_11,
input [ 3:0] up_tx_diffctrl_11,
input [ 4:0] up_tx_postcursor_11,
input [ 4:0] up_tx_precursor_11,
input up_tx_enb_11,
input [11:0] up_tx_addr_11,
input up_tx_wr_11,
@ -814,6 +850,9 @@ module util_adxcvr #(
input [ 2:0] up_tx_rate_12,
input [ 1:0] up_tx_sys_clk_sel_12,
input [ 2:0] up_tx_out_clk_sel_12,
input [ 3:0] up_tx_diffctrl_12,
input [ 4:0] up_tx_postcursor_12,
input [ 4:0] up_tx_precursor_12,
input up_tx_enb_12,
input [11:0] up_tx_addr_12,
input up_tx_wr_12,
@ -869,6 +908,9 @@ module util_adxcvr #(
input [ 2:0] up_tx_rate_13,
input [ 1:0] up_tx_sys_clk_sel_13,
input [ 2:0] up_tx_out_clk_sel_13,
input [ 3:0] up_tx_diffctrl_13,
input [ 4:0] up_tx_postcursor_13,
input [ 4:0] up_tx_precursor_13,
input up_tx_enb_13,
input [11:0] up_tx_addr_13,
input up_tx_wr_13,
@ -924,6 +966,9 @@ module util_adxcvr #(
input [ 2:0] up_tx_rate_14,
input [ 1:0] up_tx_sys_clk_sel_14,
input [ 2:0] up_tx_out_clk_sel_14,
input [ 3:0] up_tx_diffctrl_14,
input [ 4:0] up_tx_postcursor_14,
input [ 4:0] up_tx_precursor_14,
input up_tx_enb_14,
input [11:0] up_tx_addr_14,
input up_tx_wr_14,
@ -979,6 +1024,9 @@ module util_adxcvr #(
input [ 2:0] up_tx_rate_15,
input [ 1:0] up_tx_sys_clk_sel_15,
input [ 2:0] up_tx_out_clk_sel_15,
input [ 3:0] up_tx_diffctrl_15,
input [ 4:0] up_tx_postcursor_15,
input [ 4:0] up_tx_precursor_15,
input up_tx_enb_15,
input [11:0] up_tx_addr_15,
input up_tx_wr_15,
@ -1105,6 +1153,9 @@ module util_adxcvr #(
.up_tx_rate (up_tx_rate_0),
.up_tx_sys_clk_sel (up_tx_sys_clk_sel_0),
.up_tx_out_clk_sel (up_tx_out_clk_sel_0),
.up_tx_diffctrl (up_tx_diffctrl_0),
.up_tx_postcursor (up_tx_postcursor_0),
.up_tx_precursor (up_tx_precursor_0),
.up_tx_enb (up_tx_enb_0),
.up_tx_addr (up_tx_addr_0),
.up_tx_wr (up_tx_wr_0),
@ -1200,6 +1251,9 @@ module util_adxcvr #(
.up_tx_rate (up_tx_rate_1),
.up_tx_sys_clk_sel (up_tx_sys_clk_sel_1),
.up_tx_out_clk_sel (up_tx_out_clk_sel_1),
.up_tx_diffctrl (up_tx_diffctrl_1),
.up_tx_postcursor (up_tx_postcursor_1),
.up_tx_precursor (up_tx_precursor_1),
.up_tx_enb (up_tx_enb_1),
.up_tx_addr (up_tx_addr_1),
.up_tx_wr (up_tx_wr_1),
@ -1295,6 +1349,9 @@ module util_adxcvr #(
.up_tx_rate (up_tx_rate_2),
.up_tx_sys_clk_sel (up_tx_sys_clk_sel_2),
.up_tx_out_clk_sel (up_tx_out_clk_sel_2),
.up_tx_diffctrl (up_tx_diffctrl_2),
.up_tx_postcursor (up_tx_postcursor_2),
.up_tx_precursor (up_tx_precursor_2),
.up_tx_enb (up_tx_enb_2),
.up_tx_addr (up_tx_addr_2),
.up_tx_wr (up_tx_wr_2),
@ -1390,6 +1447,9 @@ module util_adxcvr #(
.up_tx_rate (up_tx_rate_3),
.up_tx_sys_clk_sel (up_tx_sys_clk_sel_3),
.up_tx_out_clk_sel (up_tx_out_clk_sel_3),
.up_tx_diffctrl (up_tx_diffctrl_3),
.up_tx_postcursor (up_tx_postcursor_3),
.up_tx_precursor (up_tx_precursor_3),
.up_tx_enb (up_tx_enb_3),
.up_tx_addr (up_tx_addr_3),
.up_tx_wr (up_tx_wr_3),
@ -1515,6 +1575,9 @@ module util_adxcvr #(
.up_tx_rate (up_tx_rate_4),
.up_tx_sys_clk_sel (up_tx_sys_clk_sel_4),
.up_tx_out_clk_sel (up_tx_out_clk_sel_4),
.up_tx_diffctrl (up_tx_diffctrl_4),
.up_tx_postcursor (up_tx_postcursor_4),
.up_tx_precursor (up_tx_precursor_4),
.up_tx_enb (up_tx_enb_4),
.up_tx_addr (up_tx_addr_4),
.up_tx_wr (up_tx_wr_4),
@ -1610,6 +1673,9 @@ module util_adxcvr #(
.up_tx_rate (up_tx_rate_5),
.up_tx_sys_clk_sel (up_tx_sys_clk_sel_5),
.up_tx_out_clk_sel (up_tx_out_clk_sel_5),
.up_tx_diffctrl (up_tx_diffctrl_5),
.up_tx_postcursor (up_tx_postcursor_5),
.up_tx_precursor (up_tx_precursor_5),
.up_tx_enb (up_tx_enb_5),
.up_tx_addr (up_tx_addr_5),
.up_tx_wr (up_tx_wr_5),
@ -1705,6 +1771,9 @@ module util_adxcvr #(
.up_tx_rate (up_tx_rate_6),
.up_tx_sys_clk_sel (up_tx_sys_clk_sel_6),
.up_tx_out_clk_sel (up_tx_out_clk_sel_6),
.up_tx_diffctrl (up_tx_diffctrl_6),
.up_tx_postcursor (up_tx_postcursor_6),
.up_tx_precursor (up_tx_precursor_6),
.up_tx_enb (up_tx_enb_6),
.up_tx_addr (up_tx_addr_6),
.up_tx_wr (up_tx_wr_6),
@ -1800,6 +1869,9 @@ module util_adxcvr #(
.up_tx_rate (up_tx_rate_7),
.up_tx_sys_clk_sel (up_tx_sys_clk_sel_7),
.up_tx_out_clk_sel (up_tx_out_clk_sel_7),
.up_tx_diffctrl (up_tx_diffctrl_7),
.up_tx_postcursor (up_tx_postcursor_7),
.up_tx_precursor (up_tx_precursor_7),
.up_tx_enb (up_tx_enb_7),
.up_tx_addr (up_tx_addr_7),
.up_tx_wr (up_tx_wr_7),
@ -1925,6 +1997,9 @@ module util_adxcvr #(
.up_tx_rate (up_tx_rate_8),
.up_tx_sys_clk_sel (up_tx_sys_clk_sel_8),
.up_tx_out_clk_sel (up_tx_out_clk_sel_8),
.up_tx_diffctrl (up_tx_diffctrl_8),
.up_tx_postcursor (up_tx_postcursor_8),
.up_tx_precursor (up_tx_precursor_8),
.up_tx_enb (up_tx_enb_8),
.up_tx_addr (up_tx_addr_8),
.up_tx_wr (up_tx_wr_8),
@ -2020,6 +2095,9 @@ module util_adxcvr #(
.up_tx_rate (up_tx_rate_9),
.up_tx_sys_clk_sel (up_tx_sys_clk_sel_9),
.up_tx_out_clk_sel (up_tx_out_clk_sel_9),
.up_tx_diffctrl (up_tx_diffctrl_9),
.up_tx_postcursor (up_tx_postcursor_9),
.up_tx_precursor (up_tx_precursor_9),
.up_tx_enb (up_tx_enb_9),
.up_tx_addr (up_tx_addr_9),
.up_tx_wr (up_tx_wr_9),
@ -2115,6 +2193,9 @@ module util_adxcvr #(
.up_tx_rate (up_tx_rate_10),
.up_tx_sys_clk_sel (up_tx_sys_clk_sel_10),
.up_tx_out_clk_sel (up_tx_out_clk_sel_10),
.up_tx_diffctrl (up_tx_diffctrl_10),
.up_tx_postcursor (up_tx_postcursor_10),
.up_tx_precursor (up_tx_precursor_10),
.up_tx_enb (up_tx_enb_10),
.up_tx_addr (up_tx_addr_10),
.up_tx_wr (up_tx_wr_10),
@ -2210,6 +2291,9 @@ module util_adxcvr #(
.up_tx_rate (up_tx_rate_11),
.up_tx_sys_clk_sel (up_tx_sys_clk_sel_11),
.up_tx_out_clk_sel (up_tx_out_clk_sel_11),
.up_tx_diffctrl (up_tx_diffctrl_11),
.up_tx_postcursor (up_tx_postcursor_11),
.up_tx_precursor (up_tx_precursor_11),
.up_tx_enb (up_tx_enb_11),
.up_tx_addr (up_tx_addr_11),
.up_tx_wr (up_tx_wr_11),
@ -2335,6 +2419,9 @@ module util_adxcvr #(
.up_tx_rate (up_tx_rate_12),
.up_tx_sys_clk_sel (up_tx_sys_clk_sel_12),
.up_tx_out_clk_sel (up_tx_out_clk_sel_12),
.up_tx_diffctrl (up_tx_diffctrl_12),
.up_tx_postcursor (up_tx_postcursor_12),
.up_tx_precursor (up_tx_precursor_12),
.up_tx_enb (up_tx_enb_12),
.up_tx_addr (up_tx_addr_12),
.up_tx_wr (up_tx_wr_12),
@ -2430,6 +2517,9 @@ module util_adxcvr #(
.up_tx_rate (up_tx_rate_13),
.up_tx_sys_clk_sel (up_tx_sys_clk_sel_13),
.up_tx_out_clk_sel (up_tx_out_clk_sel_13),
.up_tx_diffctrl (up_tx_diffctrl_13),
.up_tx_postcursor (up_tx_postcursor_13),
.up_tx_precursor (up_tx_precursor_13),
.up_tx_enb (up_tx_enb_13),
.up_tx_addr (up_tx_addr_13),
.up_tx_wr (up_tx_wr_13),
@ -2525,6 +2615,9 @@ module util_adxcvr #(
.up_tx_rate (up_tx_rate_14),
.up_tx_sys_clk_sel (up_tx_sys_clk_sel_14),
.up_tx_out_clk_sel (up_tx_out_clk_sel_14),
.up_tx_diffctrl (up_tx_diffctrl_14),
.up_tx_postcursor (up_tx_postcursor_14),
.up_tx_precursor (up_tx_precursor_14),
.up_tx_enb (up_tx_enb_14),
.up_tx_addr (up_tx_addr_14),
.up_tx_wr (up_tx_wr_14),
@ -2620,6 +2713,9 @@ module util_adxcvr #(
.up_tx_rate (up_tx_rate_15),
.up_tx_sys_clk_sel (up_tx_sys_clk_sel_15),
.up_tx_out_clk_sel (up_tx_out_clk_sel_15),
.up_tx_diffctrl (up_tx_diffctrl_15),
.up_tx_postcursor (up_tx_postcursor_15),
.up_tx_precursor (up_tx_precursor_15),
.up_tx_enb (up_tx_enb_15),
.up_tx_addr (up_tx_addr_15),
.up_tx_wr (up_tx_wr_15),

3
library/xilinx/util_adxcvr/util_adxcvr_ip.tcl
View File

@ -188,6 +188,9 @@ for {set n 0} {$n < 16} {incr n} {
"rate up_tx_rate_${n} "\
"sys_clk_sel up_tx_sys_clk_sel_${n} "\
"out_clk_sel up_tx_out_clk_sel_${n} "\
"tx_diffctrl up_tx_diffctrl_${n} "\
"tx_postcursor up_tx_postcursor_${n} "\
"tx_precursor up_tx_precursor_${n} "\
"enb up_tx_enb_${n} "\
"addr up_tx_addr_${n} "\
"wr up_tx_wr_${n} "\

23
library/xilinx/util_adxcvr/util_adxcvr_xch.v
View File

@ -118,6 +118,9 @@ module util_adxcvr_xch #(
input [ 2:0] up_tx_rate,
input [ 1:0] up_tx_sys_clk_sel,
input [ 2:0] up_tx_out_clk_sel,
input [ 3:0] up_tx_diffctrl,
input [ 4:0] up_tx_postcursor,
input [ 4:0] up_tx_precursor,
input up_tx_enb,
input [11:0] up_tx_addr,
input up_tx_wr,
@ -688,7 +691,7 @@ module util_adxcvr_xch #(
.TXDATA ({32'd0, tx_data}),
.TXDEEMPH (1'h0),
.TXDETECTRX (1'h0),
.TXDIFFCTRL (4'h8),
.TXDIFFCTRL (up_tx_diffctrl),
.TXDIFFPD (1'h0),
.TXDLYBYPASS (1'h1),
.TXDLYEN (1'h0),
@ -718,11 +721,11 @@ module util_adxcvr_xch #(
.TXPISOPD (1'h0),
.TXPMARESET (1'h0),
.TXPOLARITY (TX_POLARITY),
.TXPOSTCURSOR (5'h0),
.TXPOSTCURSOR (up_tx_postcursor),
.TXPOSTCURSORINV (1'h0),
.TXPRBSFORCEERR (1'h0),
.TXPRBSSEL (3'd0),
.TXPRECURSOR (5'h0),
.TXPRECURSOR (up_tx_precursor),
.TXPRECURSORINV (1'h0),
.TXQPIBIASEN (1'h0),
.TXQPISTRONGPDOWN (1'h0),
@ -1422,7 +1425,7 @@ module util_adxcvr_xch #(
.TXDATAEXTENDRSVD (8'h0),
.TXDEEMPH (1'h0),
.TXDETECTRX (1'h0),
.TXDIFFCTRL (4'h8),
.TXDIFFCTRL (up_tx_diffctrl),
.TXDIFFPD (1'h0),
.TXDLYBYPASS (1'h1),
.TXDLYEN (1'h0),
@ -1463,11 +1466,11 @@ module util_adxcvr_xch #(
.TXPMARESET (1'h0),
.TXPMARESETDONE (),
.TXPOLARITY (TX_POLARITY),
.TXPOSTCURSOR (5'h0),
.TXPOSTCURSOR (up_tx_postcursor),
.TXPOSTCURSORINV (1'h0),
.TXPRBSFORCEERR (1'h0),
.TXPRBSSEL (4'h0),
.TXPRECURSOR (5'h0),
.TXPRECURSOR (up_tx_precursor),
.TXPRECURSORINV (1'h0),
.TXPRGDIVRESETDONE (),
.TXPROGDIVRESET (up_tx_rst),
@ -1544,7 +1547,7 @@ module util_adxcvr_xch #(
.A_RXOSCALRESET (1'b0),
.A_RXPROGDIVRESET (1'b0),
.A_RXTERMINATION (1'b1),
.A_TXDIFFCTRL (5'b01100),
.A_TXDIFFCTRL (5'b10110),
.A_TXPROGDIVRESET (1'b0),
.CAPBYPASS_FORCE (1'b0),
.CBCC_DATA_SOURCE_SEL ("DECODED"),
@ -2300,7 +2303,7 @@ module util_adxcvr_xch #(
.TXDCCRESET (1'd0),
.TXDEEMPH (2'd0),
.TXDETECTRX (1'd0),
.TXDIFFCTRL (5'b00000),
.TXDIFFCTRL ({up_tx_diffctrl, 1'b0}),
.TXDLYBYPASS (1'd1),
.TXDLYEN (1'd0),
.TXDLYHOLD (1'd0),
@ -2346,10 +2349,10 @@ module util_adxcvr_xch #(
.TXPMARESET (1'd0),
.TXPMARESETDONE (),
.TXPOLARITY (TX_POLARITY),
.TXPOSTCURSOR (5'd0),
.TXPOSTCURSOR (up_tx_postcursor),
.TXPRBSFORCEERR (1'd0),
.TXPRBSSEL (4'd0),
.TXPRECURSOR (5'd0),
.TXPRECURSOR (up_tx_precursor),
.TXPRGDIVRESETDONE (),
.TXPROGDIVRESET (up_tx_rst),
.TXQPIBIASEN (1'd0),