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axi_hdmi_tx update for: ZedBoard, ZC706, ZC702, de10nano, ADRV9361-Z7035 (#897)

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PopPaul2021 2022-03-29 16:51:21 +03:00 committed by GitHub
parent de70157e3a
commit 0d44bfb4dd
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GPG Key ID: 4AEE18F83AFDEB23
10 changed files with 112 additions and 52 deletions
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34
library/axi_hdmi_tx/axi_hdmi_tx.v
View File

@ -45,8 +45,9 @@ module axi_hdmi_tx #(
// hdmi interface
input hdmi_clk,
input reference_clk,
output hdmi_out_clk,
output vga_out_clk,
// 16-bit interface
@ -62,6 +63,14 @@ module axi_hdmi_tx #(
output hdmi_24_vsync,
output hdmi_24_data_e,
output [23:0] hdmi_24_data,
// VGA interface
output vga_hsync,
output vga_vsync,
output [7:0] vga_red,
output [7:0] vga_green,
output [7:0] vga_blue,
// 36-bit interface
@ -114,7 +123,7 @@ module axi_hdmi_tx #(
wire up_rstn;
wire up_clk;
wire hdmi_rst;
wire reference_rst;
wire vdma_rst;
// internal signals
@ -160,6 +169,7 @@ module axi_hdmi_tx #(
assign up_rstn = s_axi_aresetn;
assign up_clk = s_axi_aclk;
assign vga_out_clk = hdmi_out_clk;
// axi interface
@ -195,8 +205,8 @@ module axi_hdmi_tx #(
// processor interface
up_hdmi_tx i_up (
.hdmi_clk (hdmi_clk),
.hdmi_rst (hdmi_rst),
.hdmi_clk (reference_clk),
.hdmi_rst (reference_rst),
.hdmi_csc_bypass (hdmi_csc_bypass_s),
.hdmi_ss_bypass (hdmi_ss_bypass_s),
.hdmi_srcsel (hdmi_srcsel_s),
@ -255,11 +265,12 @@ module axi_hdmi_tx #(
// hdmi interface
axi_hdmi_tx_core #(
.INTERFACE(INTERFACE),
.CR_CB_N(CR_CB_N),
.EMBEDDED_SYNC(EMBEDDED_SYNC))
i_tx_core (
.hdmi_clk (hdmi_clk),
.hdmi_rst (hdmi_rst),
.reference_clk (reference_clk),
.reference_rst (reference_rst),
.hdmi_16_hsync (hdmi_16_hsync),
.hdmi_16_vsync (hdmi_16_vsync),
.hdmi_16_data_e (hdmi_16_data_e),
@ -269,6 +280,11 @@ module axi_hdmi_tx #(
.hdmi_24_vsync (hdmi_24_vsync),
.hdmi_24_data_e (hdmi_24_data_e),
.hdmi_24_data (hdmi_24_data),
.vga_hsync(vga_hsync),
.vga_vsync(vga_vsync),
.vga_red(vga_red),
.vga_green(vga_green),
.vga_blue(vga_blue),
.hdmi_36_hsync (hdmi_36_hsync),
.hdmi_36_vsync (hdmi_36_vsync),
.hdmi_36_data_e (hdmi_36_data_e),
@ -308,7 +324,7 @@ module axi_hdmi_tx #(
.SR (1'b0),
.D1 (~OUT_CLK_POLARITY),
.D2 (OUT_CLK_POLARITY),
.C (hdmi_clk),
.C (reference_clk),
.Q (hdmi_out_clk));
end
if (FPGA_TECHNOLOGY == INTEL_5SERIES) begin
@ -321,7 +337,7 @@ module axi_hdmi_tx #(
.outclocken (1'b1),
.datain_h (~OUT_CLK_POLARITY),
.datain_l (OUT_CLK_POLARITY),
.outclock (hdmi_clk),
.outclock (reference_clk),
.oe_out (),
.dataout (hdmi_out_clk));
end
@ -332,7 +348,7 @@ module axi_hdmi_tx #(
.CE (1'b1),
.D1 (~OUT_CLK_POLARITY),
.D2 (OUT_CLK_POLARITY),
.C (hdmi_clk),
.C (reference_clk),
.Q (hdmi_out_clk));
end
endgenerate

69
library/axi_hdmi_tx/axi_hdmi_tx_core.v
View File

@ -39,12 +39,13 @@
module axi_hdmi_tx_core #(
parameter CR_CB_N = 0,
parameter EMBEDDED_SYNC = 0) (
parameter EMBEDDED_SYNC = 0,
parameter INTERFACE = "16_BIT") (
// hdmi interface
input hdmi_clk,
input hdmi_rst,
input reference_clk,
input reference_rst,
// 16-bit interface
@ -61,6 +62,14 @@ module axi_hdmi_tx_core #(
output reg hdmi_24_data_e,
output reg [23:0] hdmi_24_data,
// VGA interface
output reg vga_hsync,
output reg vga_vsync,
output reg [7:0] vga_red,
output reg [7:0] vga_green,
output reg [7:0] vga_blue,
// 36-bit interface
output reg hdmi_36_hsync,
@ -209,8 +218,8 @@ module axi_hdmi_tx_core #(
// status and enable
always @(posedge hdmi_clk) begin
if (hdmi_rst == 1'b1) begin
always @(posedge reference_clk) begin
if (reference_rst == 1'b1) begin
hdmi_status <= 1'b0;
hdmi_enable <= 1'b0;
end else begin
@ -228,7 +237,7 @@ module axi_hdmi_tx_core #(
// hdmi counters
always @(posedge hdmi_clk) begin
always @(posedge reference_clk) begin
if (hdmi_hs_count >= hdmi_hl_width_s) begin
hdmi_hs_count <= 0;
end else begin
@ -245,8 +254,8 @@ module axi_hdmi_tx_core #(
// hdmi start of frame
always @(posedge hdmi_clk) begin
if (hdmi_rst == 1'b1) begin
always @(posedge reference_clk) begin
if (reference_rst == 1'b1) begin
hdmi_fs_toggle <= 1'b0;
hdmi_fs <= 1'b0;
end else begin
@ -273,8 +282,8 @@ module axi_hdmi_tx_core #(
assign hdmi_fs_ret_s = hdmi_fs_ret_toggle_m2 ^ hdmi_fs_ret_toggle_m3;
always @(posedge hdmi_clk or posedge hdmi_rst) begin
if (hdmi_rst == 1'b1) begin
always @(posedge reference_clk or posedge reference_rst) begin
if (reference_rst == 1'b1) begin
hdmi_fs_ret_toggle_m1 <= 1'd0;
hdmi_fs_ret_toggle_m2 <= 1'd0;
hdmi_fs_ret_toggle_m3 <= 1'd0;
@ -285,14 +294,14 @@ module axi_hdmi_tx_core #(
end
end
always @(posedge hdmi_clk) begin
always @(posedge reference_clk) begin
hdmi_fs_ret <= hdmi_fs_ret_s;
hdmi_fs_waddr <= vdma_fs_waddr;
end
// hdmi sync signals
always @(posedge hdmi_clk) begin
always @(posedge reference_clk) begin
if (EMBEDDED_SYNC == 1) begin
hdmi_hs <= 1'b0;
if (hdmi_hs_count <= hdmi_he_width_s) begin
@ -333,8 +342,8 @@ module axi_hdmi_tx_core #(
assign hdmi_de_s = hdmi_hs_de & hdmi_vs_de;
always @(posedge hdmi_clk) begin
if (hdmi_rst == 1'b1) begin
always @(posedge reference_clk) begin
if (reference_rst == 1'b1) begin
hdmi_raddr <= 10'd0;
end else if (hdmi_fs == 1'b1) begin
hdmi_raddr <= {hdmi_fs_waddr, 1'b0};
@ -346,7 +355,7 @@ module axi_hdmi_tx_core #(
// control and data pipe line
always @(posedge hdmi_clk) begin
always @(posedge reference_clk) begin
hdmi_hs_d <= hdmi_hs;
hdmi_vs_d <= hdmi_vs;
hdmi_hs_de_d <= hdmi_hs_de;
@ -368,18 +377,19 @@ module axi_hdmi_tx_core #(
assign hdmi_tpm_mismatch_s = (hdmi_data_2d_s == hdmi_tpm_data) ? 1'b0 : hdmi_de_2d;
assign hdmi_tpg_data_s = hdmi_tpm_data;
always @(posedge hdmi_clk) begin
if ((hdmi_rst == 1'b1) || (hdmi_fs_ret == 1'b1)) begin
always @(posedge reference_clk) begin
if ((reference_rst == 1'b1) || (hdmi_fs_ret == 1'b1)) begin
hdmi_tpm_data <= 'd0;
end else if (hdmi_de_2d == 1'b1) begin
hdmi_tpm_data <= hdmi_tpm_data + 1'b1;
end
hdmi_tpm_oos <= hdmi_tpm_mismatch_s;
end
// hdmi data select
always @(posedge hdmi_clk) begin
always @(posedge reference_clk) begin
hdmi_hsync <= hdmi_hs_2d;
hdmi_vsync <= hdmi_vs_2d;
hdmi_hsync_data_e <= hdmi_hs_de_2d;
@ -395,7 +405,7 @@ module axi_hdmi_tx_core #(
// Color space conversion bypass (RGB/YCbCr)
always @(posedge hdmi_clk) begin
always @(posedge reference_clk) begin
if (hdmi_csc_bypass == 1'b1) begin
hdmi_24_csc_hsync <= hdmi_hsync;
hdmi_24_csc_vsync <= hdmi_vsync;
@ -415,7 +425,7 @@ module axi_hdmi_tx_core #(
// hdmi clipping
always @(posedge hdmi_clk) begin
always @(posedge reference_clk) begin
hdmi_clip_hs_d <= hdmi_24_csc_hsync;
hdmi_clip_vs_d <= hdmi_24_csc_vsync;
hdmi_clip_hs_de_d <= hdmi_24_csc_hsync_data_e;
@ -455,7 +465,7 @@ module axi_hdmi_tx_core #(
// hdmi csc 16, 24 and 36 outputs
always @(posedge hdmi_clk) begin
always @(posedge reference_clk) begin
hdmi_36_hsync <= hdmi_clip_hs_d;
hdmi_36_vsync <= hdmi_clip_vs_d;
@ -469,6 +479,13 @@ module axi_hdmi_tx_core #(
hdmi_24_data_e <= hdmi_clip_de_d;
hdmi_24_data <= hdmi_clip_data;
//VGA INTERFACE SIGNALS
vga_hsync <= hdmi_clip_hs_d;
vga_vsync <= hdmi_clip_vs_d;
vga_red <= hdmi_clip_data[23:16];
vga_green <= hdmi_clip_data[15:8];
vga_blue <= hdmi_clip_data[7:0];
hdmi_16_hsync <= hdmi_16_hsync_d;
hdmi_16_vsync <= hdmi_16_vsync_d;
hdmi_16_data_e <= hdmi_16_data_e_d;
@ -494,7 +511,7 @@ module axi_hdmi_tx_core #(
// hdmi embedded sync
always @(posedge hdmi_clk) begin
always @(posedge reference_clk) begin
hdmi_es_hs_de <= hdmi_16_hsync_data_e_d;
hdmi_es_vs_de <= hdmi_16_vsync_data_e_d;
if (hdmi_16_data_e_d == 1'b0) begin
@ -516,7 +533,7 @@ module axi_hdmi_tx_core #(
.wea (vdma_wr),
.addra (vdma_waddr),
.dina (vdma_wdata),
.clkb (hdmi_clk),
.clkb (reference_clk),
.reb (1'b1),
.addrb (hdmi_raddr[9:1]),
.doutb (hdmi_rdata_s));
@ -524,7 +541,7 @@ module axi_hdmi_tx_core #(
// color space coversion, RGB to CrYCb
ad_csc_RGB2CrYCb #(.DELAY_DATA_WIDTH(5)) i_csc_RGB2CrYCb (
.clk (hdmi_clk),
.clk (reference_clk),
.RGB_sync ({hdmi_hsync,
hdmi_vsync,
hdmi_hsync_data_e,
@ -541,7 +558,7 @@ module axi_hdmi_tx_core #(
// sub sampling, 444 to 422
ad_ss_444to422 #(.DELAY_DATA_WIDTH(5), .CR_CB_N(CR_CB_N)) i_ss_444to422 (
.clk (hdmi_clk),
.clk (reference_clk),
.s444_de (hdmi_clip_de_d),
.s444_sync ({hdmi_clip_hs_d,
hdmi_clip_vs_d,
@ -559,7 +576,7 @@ module axi_hdmi_tx_core #(
// embedded sync
axi_hdmi_tx_es #(.DATA_WIDTH(16)) i_es (
.hdmi_clk (hdmi_clk),
.reference_clk (reference_clk),
.hdmi_hs_de (hdmi_es_hs_de),
.hdmi_vs_de (hdmi_es_vs_de),
.hdmi_data_de (hdmi_es_data),

4
library/axi_hdmi_tx/axi_hdmi_tx_es.v
View File

@ -42,7 +42,7 @@ module axi_hdmi_tx_es #(
// hdmi interface
input hdmi_clk,
input reference_clk,
input hdmi_hs_de,
input hdmi_vs_de,
input [(DATA_WIDTH-1):0] hdmi_data_de,
@ -73,7 +73,7 @@ module axi_hdmi_tx_es #(
assign hdmi_sav_s = (hdmi_vs_de == 1) ? {BYTE_WIDTH{8'h80}} : {BYTE_WIDTH{8'hab}};
assign hdmi_eav_s = (hdmi_vs_de == 1) ? {BYTE_WIDTH{8'h9d}} : {BYTE_WIDTH{8'hb6}};
always @(posedge hdmi_clk) begin
always @(posedge reference_clk) begin
hdmi_hs_de_d <= hdmi_hs_de;
case ({hdmi_hs_de_4d, hdmi_hs_de_3d, hdmi_hs_de_2d,
hdmi_hs_de_d, hdmi_hs_de})

34
library/axi_hdmi_tx/axi_hdmi_tx_hw.tcl
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@ -58,7 +58,7 @@ add_parameter INTERFACE STRING "16_BIT"
set_parameter_property INTERFACE DEFAULT_VALUE "16_BIT"
set_parameter_property INTERFACE DISPLAY_NAME INTERFACE
set_parameter_property INTERFACE TYPE STRING
set_parameter_property INTERFACE ALLOWED_RANGES { "16_BIT" "24_BIT" "36_BIT" "16_BIT_EMBEDDED_SYNC" }
set_parameter_property INTERFACE ALLOWED_RANGES { "16_BIT" "24_BIT" "36_BIT" "16_BIT_EMBEDDED_SYNC" "VGA_INTERFACE" }
set_parameter_property INTERFACE HDL_PARAMETER false
add_parameter DEVICE STRING ""
@ -72,14 +72,10 @@ adi_add_device_spec_param "FPGA_TECHNOLOGY"
ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn
# hdmi interface
# reference clock interface
add_interface hdmi_clock clock end
add_interface_port hdmi_clock hdmi_clk clk Input 1
add_interface hdmi_if conduit end
set_interface_property hdmi_if associatedClock hdmi_clock
add_interface_port hdmi_if hdmi_out_clk h_clk Output 1
add_interface reference_clk clock end
add_interface_port reference_clk reference_clk clk Input 1
# streaming dma
@ -99,26 +95,48 @@ proc add_out_interface {} {
set interface [get_parameter_value INTERFACE]
switch $interface {
"16_BIT" {
add_interface hdmi_if conduit end
set_interface_property hdmi_if associatedClock reference_clk
add_interface_port hdmi_if hdmi_out_clk h_clk Output 1
add_interface_port hdmi_if hdmi_16_hsync h16_hsync Output 1
add_interface_port hdmi_if hdmi_16_vsync h16_vsync Output 1
add_interface_port hdmi_if hdmi_16_data_e h16_data_e Output 1
add_interface_port hdmi_if hdmi_16_data h16_data Output 16
}
"24_BIT" {
add_interface hdmi_if conduit end
set_interface_property hdmi_if associatedClock reference_clk
add_interface_port hdmi_if hdmi_out_clk h_clk Output 1
add_interface_port hdmi_if hdmi_24_hsync h24_hsync Output 1
add_interface_port hdmi_if hdmi_24_vsync h24_vsync Output 1
add_interface_port hdmi_if hdmi_24_data_e h24_data_e Output 1
add_interface_port hdmi_if hdmi_24_data h24_data Output 24
}
"36_BIT" {
add_interface hdmi_if conduit end
set_interface_property hdmi_if associatedClock reference_clk
add_interface_port hdmi_if hdmi_out_clk h_clk Output 1
add_interface_port hdmi_if hdmi_36_hsync h36_hsync Output 1
add_interface_port hdmi_if hdmi_36_vsync h36_vsync Output 1
add_interface_port hdmi_if hdmi_36_data_e h36_data_e Output 1
add_interface_port hdmi_if hdmi_36_data h36_data Output 36
}
"16_BIT_EMBEDDED_SYNC" {
add_interface hdmi_if conduit end
set_interface_property hdmi_if associatedClock reference_clk
add_interface_port hdmi_if hdmi_out_clk h_clk Output 1
add_interface_port hdmi_if hdmi_16_es_data h16_es_data Output 16
}
"VGA_INTERFACE" {
add_interface vga_if conduit end
set_interface_property vga_if associatedClock reference_clk
add_interface_port vga_if vga_out_clk vga_clk Output 1
add_interface_port vga_if vga_hsync vga_hsync Output 1
add_interface_port vga_if vga_vsync vga_vsync Output 1
add_interface_port vga_if vga_red vga_red Output 8
add_interface_port vga_if vga_green vga_green Output 8
add_interface_port vga_if vga_blue vga_blue Output 8
}
}
}

13
library/axi_hdmi_tx/axi_hdmi_tx_ip.tcl
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@ -37,6 +37,9 @@ set_property driver_value 0 [ipx::get_ports *hsync* -of_objects [ipx::current_co
set_property driver_value 0 [ipx::get_ports *vsync* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *data* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *es_data* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *red* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *green* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *blue* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *vdma_end_of_frame* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *vdma_valid* -of_objects [ipx::current_core]]
@ -45,9 +48,12 @@ set_property driver_value 0 [ipx::get_ports *vdma_ready* -of_objects [ipx::curre
set_property value_format string [ipx::get_user_parameters INTERFACE -of_objects [ipx::current_core]]
set_property value_format string [ipx::get_hdl_parameters INTERFACE -of_objects [ipx::current_core]]
set_property value_validation_list {16_BIT 24_BIT 36_BIT 16_BIT_EMBEDDED_SYNC} \
set_property value_validation_list {16_BIT 24_BIT 36_BIT 16_BIT_EMBEDDED_SYNC VGA_INTERFACE} \
[ipx::get_user_parameters INTERFACE -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.INTERFACE')) == "16_BIT" || spirit:decode(id('MODELPARAM_VALUE.INTERFACE')) == "24_BIT" || spirit:decode(id('MODELPARAM_VALUE.INTERFACE')) == "36_BIT" || spirit:decode(id('MODELPARAM_VALUE.INTERFACE')) == "16_BIT_EMBEDDED_SYNC" } \
[ipx::get_ports *hdmi_out_clk* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.INTERFACE')) == "16_BIT"} \
[ipx::get_ports *hdmi_16* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.INTERFACE')) == "24_BIT"} \
@ -56,6 +62,8 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.INTERFACE
[ipx::get_ports *hdmi_36* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.INTERFACE')) == "16_BIT_EMBEDDED_SYNC"} \
[ipx::get_ports *hdmi_16_es_data* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.INTERFACE')) == "VGA_INTERFACE"} \
[ipx::get_ports *vga* -of_objects [ipx::current_core]]
adi_add_bus "s_axis" "slave" \
"xilinx.com:interface:axis_rtl:1.0" \
@ -65,8 +73,9 @@ adi_add_bus "s_axis" "slave" \
{"vdma_data" "TDATA"} \
{"vdma_end_of_frame" "TLAST"} ]
ipx::infer_bus_interface hdmi_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface reference_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface hdmi_out_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface vga_out_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface vdma_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::associate_bus_interfaces -busif s_axis -clock vdma_clk [ipx::current_core]

2
projects/adrv9361z7035/common/ccfmc_bd.tcl
View File

@ -91,7 +91,7 @@ ad_connect sys_rgmii_rstgen/peripheral_reset sys_rgmii/rx_reset
# hdmi
ad_connect sys_cpu_clk axi_hdmi_core/vdma_clk
ad_connect axi_hdmi_core/hdmi_clk axi_hdmi_clkgen/clk_0
ad_connect axi_hdmi_core/reference_clk axi_hdmi_clkgen/clk_0
ad_connect axi_hdmi_core/hdmi_out_clk hdmi_out_clk
ad_connect axi_hdmi_core/hdmi_16_hsync hdmi_hsync
ad_connect axi_hdmi_core/hdmi_16_vsync hdmi_vsync

2
projects/common/de10nano/de10nano_system_qsys.tcl
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@ -303,7 +303,7 @@ add_connection pixel_clk_pll.outclk1 video_dmac.m_src_axi_clock
add_connection pixel_clk_pll.outclk1 video_dmac.if_m_axis_aclk
add_connection pixel_clk_pll.outclk1 sys_hps.f2h_sdram0_clock
add_connection pixel_clk_pll.outclk1 axi_hdmi_tx_0.vdma_clock
add_connection pixel_clk_pll.outclk0 axi_hdmi_tx_0.hdmi_clock
add_connection pixel_clk_pll.outclk0 axi_hdmi_tx_0.reference_clk
add_connection sys_clk.clk_reset pixel_clk_pll.reset
add_connection sys_clk.clk_reset pixel_clk_pll_reconfig.mgmt_reset

2
projects/common/zc702/zc702_system_bd.tcl
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@ -164,7 +164,7 @@ ad_connect spi1_sdi_i sys_ps7/SPI1_MISO_I
# hdmi
ad_connect sys_cpu_clk axi_hdmi_core/vdma_clk
ad_connect axi_hdmi_core/hdmi_clk axi_hdmi_clkgen/clk_0
ad_connect axi_hdmi_core/reference_clk axi_hdmi_clkgen/clk_0
ad_connect axi_hdmi_core/hdmi_out_clk hdmi_out_clk
ad_connect axi_hdmi_core/hdmi_16_hsync hdmi_hsync
ad_connect axi_hdmi_core/hdmi_16_vsync hdmi_vsync

2
projects/common/zc706/zc706_system_bd.tcl
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@ -165,7 +165,7 @@ ad_connect spi1_sdi_i sys_ps7/SPI1_MISO_I
# hdmi
ad_connect sys_cpu_clk axi_hdmi_core/vdma_clk
ad_connect axi_hdmi_core/hdmi_clk axi_hdmi_clkgen/clk_0
ad_connect axi_hdmi_core/reference_clk axi_hdmi_clkgen/clk_0
ad_connect axi_hdmi_core/hdmi_out_clk hdmi_out_clk
ad_connect axi_hdmi_core/hdmi_24_hsync hdmi_hsync
ad_connect axi_hdmi_core/hdmi_24_vsync hdmi_vsync

2
projects/common/zed/zed_system_bd.tcl
View File

@ -209,7 +209,7 @@ ad_connect spi1_sdi_i sys_ps7/SPI1_MISO_I
# hdmi
ad_connect sys_cpu_clk axi_hdmi_core/vdma_clk
ad_connect axi_hdmi_core/hdmi_clk axi_hdmi_clkgen/clk_0
ad_connect axi_hdmi_core/reference_clk axi_hdmi_clkgen/clk_0
ad_connect axi_hdmi_core/hdmi_out_clk hdmi_out_clk
ad_connect axi_hdmi_core/hdmi_16_hsync hdmi_hsync
ad_connect axi_hdmi_core/hdmi_16_vsync hdmi_vsync