ad9081_fmca_ebz: Update path to common block design
Use absolute paths so ad9082 wrapper project can include the system_bd.tcl instead of duplicating code.main
parent
680d28476c
commit
0d9e38bdbe
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@ -7,7 +7,7 @@ set dac_fifo_samples_per_converter [expr $ad_project_params(TX_KS_PER_CHANNEL)*1
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source $ad_hdl_dir/projects/common/vcu118/vcu118_system_bd.tcl
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source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl
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source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
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source ../common/ad9081_fmca_ebz_bd.tcl
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source $ad_hdl_dir/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
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source $ad_hdl_dir/projects/scripts/adi_pd.tcl
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ad_ip_parameter axi_mxfe_rx_jesd/rx CONFIG.NUM_INPUT_PIPELINE 2
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@ -7,7 +7,7 @@ set dac_fifo_samples_per_converter [expr 32*1024]
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source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
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source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl
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source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
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source ../common/ad9081_fmca_ebz_bd.tcl
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source $ad_hdl_dir/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
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source $ad_hdl_dir/projects/scripts/adi_pd.tcl
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@ -11,7 +11,7 @@ source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
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ad_mem_hp0_interconnect $sys_cpu_clk sys_ps8/S_AXI_HP0
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source ../common/ad9081_fmca_ebz_bd.tcl
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source $ad_hdl_dir/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
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source $ad_hdl_dir/projects/scripts/adi_pd.tcl
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#system ID
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