ad_dds: Add sine generator using CORDIC algorithm
https://en.wikipedia.org/wiki/CORDIC Configurable in/out data width (14,16,18,20); The HDL implementation requires pipelines, resulting in a data_width + 2 clock cycles delay between the phase input data and the sine data. For this reason, a ddata (delay data) was propagated through the pipeline stages to help in future use scenariosmain
AndreiGrozav
AndreiGrozav
parent
9b01b9f37c
commit
0e114a39e3
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module ad_dds_cordic_pipe#(
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// parameters
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parameter DW = 16,
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parameter DELAY_DW = 1,
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parameter SHIFT = 0) (
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// interface
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input clk,
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(* keep = "TRUE" *) input dir,
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(* keep = "TRUE" *) input signed [ DW-1:0] dataa_x,
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(* keep = "TRUE" *) input signed [ DW-1:0] dataa_y,
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(* keep = "TRUE" *) input signed [ DW-1:0] dataa_z,
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(* keep = "TRUE" *) input signed [ DW-1:0] datab_x,
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(* keep = "TRUE" *) input signed [ DW-1:0] datab_y,
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(* keep = "TRUE" *) input signed [ DW-1:0] datab_z,
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(* keep = "TRUE" *) output reg signed [ DW-1:0] result_x,
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(* keep = "TRUE" *) output reg signed [ DW-1:0] result_y,
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(* keep = "TRUE" *) output reg signed [ DW-1:0] result_z,
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output signed [ DW-1:0] sgn_shift_x,
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output signed [ DW-1:0] sgn_shift_y,
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input [DELAY_DW:1] data_delay_in,
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output [DELAY_DW:1] data_delay_out
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);
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// internal registers
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reg [DELAY_DW:1] data_delay = 'd0;
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// stage rotation
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always @(posedge clk)
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begin
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case(dir)
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1'b0: begin
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result_x <= dataa_x - datab_y;
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result_y <= dataa_y + datab_x;
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result_z <= dataa_z - datab_z;
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end
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1'b1: begin
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result_x <= dataa_x + datab_y;
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result_y <= dataa_y - datab_x;
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result_z <= dataa_z + datab_z;
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end
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endcase
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end
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// stage shift
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assign sgn_shift_x = result_x >>> SHIFT + 1;
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assign sgn_shift_y = result_y >>> SHIFT + 1;
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generate
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if (DELAY_DW > 1) begin
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always @(posedge clk)
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begin
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data_delay <= data_delay_in;
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end
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end
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endgenerate
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assign data_delay_out = data_delay;
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endmodule
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@ -0,0 +1,236 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
|
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module ad_dds_sine_cordic #(
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// parameters
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parameter CORDIC_DW = 16,
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parameter DELAY_DW = 1) (
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// interface
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input clk,
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input [CORDIC_DW-1:0] angle,
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output reg [CORDIC_DW-1:0] sine,
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input [ DELAY_DW-1:0] ddata_in,
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output reg [ DELAY_DW-1:0] ddata_out);
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// 1.647 = gain of the system
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localparam [19:0] X_VALUE_20 = 318327; // ((20^2)/2)/1.647
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localparam [17:0] X_VALUE_18 = 79582; // ((18^2)/2)/1.647
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localparam [15:0] X_VALUE_16 = 19883; // ((16^2)/2)/1.647
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localparam [13:0] X_VALUE_14 = 4970; // ((14^2)/2)/1.647
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localparam Y_VALUE = 0;
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// internal registers
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reg signed [CORDIC_DW-1:0] x0 = 'd0;
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reg signed [CORDIC_DW-1:0] y0 = 'd0;
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reg signed [CORDIC_DW-1:0] z0 = 'd0;
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// internal signals
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wire [CORDIC_DW-1:0] x_value;
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wire signed [CORDIC_DW-1:0] x_s [0:CORDIC_DW-1];
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wire signed [CORDIC_DW-1:0] y_s [0:CORDIC_DW-1];
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wire signed [CORDIC_DW-1:0] z_s [0:CORDIC_DW-1];
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wire signed [CORDIC_DW-1:0] x_shr_s [0:CORDIC_DW-1];
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wire signed [CORDIC_DW-1:0] y_shr_s [0:CORDIC_DW-1];
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wire [ DELAY_DW-1:0] data_in_d [0:CORDIC_DW-1];
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wire [CORDIC_DW-1:0] atan_table[0:CORDIC_DW-2];
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wire [ 1:0] quadrant;
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// arc tangent LUT
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generate
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if (CORDIC_DW == 20) begin
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assign x_value = X_VALUE_20;
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assign atan_table[ 0] = 20'b00100000000000000000; // 45
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assign atan_table[ 1] = 20'b00010010111001000000; // 26.56505118
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assign atan_table[ 2] = 20'b00001001111110110100; // 14.03624347
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assign atan_table[ 3] = 20'b00000101000100010001; // 7.125016349
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assign atan_table[ 4] = 20'b00000010100010110001; // 3.576334375
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assign atan_table[ 5] = 20'b00000001010001011101; // 1.789910608
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assign atan_table[ 6] = 20'b00000000101000101111; // 0.895173710
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assign atan_table[ 7] = 20'b00000000010100011000; // 0.447614171
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assign atan_table[ 8] = 20'b00000000001010001100; // 0.223810500
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assign atan_table[ 9] = 20'b00000000000101000110; // 0.111905677
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assign atan_table[10] = 20'b00000000000010100011; // 0.055952892
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assign atan_table[11] = 20'b00000000000001010001; // 0.027976453
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assign atan_table[12] = 20'b00000000000000101001; // 0.013988227
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assign atan_table[13] = 20'b00000000000000010100; // 0.006994114
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assign atan_table[14] = 20'b00000000000000001010; // 0.003497057
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assign atan_table[15] = 20'b00000000000000000101; // 0.001748528
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assign atan_table[16] = 20'b00000000000000000011; // 0.000874264
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assign atan_table[17] = 20'b00000000000000000001; // 0.000437132
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assign atan_table[18] = 20'b00000000000000000001; // 0.000218566
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end else if (CORDIC_DW == 18) begin
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assign x_value = X_VALUE_18;
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assign atan_table[ 0] = 18'b001000000000000000; // 45
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assign atan_table[ 1] = 18'b000100101110010000; // 26.56505118
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assign atan_table[ 2] = 18'b000010011111101101; // 14.03624347
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assign atan_table[ 3] = 18'b000001010001000100; // 7.125016349
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assign atan_table[ 4] = 18'b000000101000101100; // 3.576334375
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assign atan_table[ 5] = 18'b000000010100010111; // 1.789910608
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assign atan_table[ 6] = 18'b000000001010001100; // 0.895173710
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assign atan_table[ 7] = 18'b000000000101000110; // 0.447614171
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assign atan_table[ 8] = 18'b000000000010100011; // 0.223810500
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assign atan_table[ 9] = 18'b000000000001010001; // 0.111905677
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assign atan_table[10] = 18'b000000000000101001; // 0.055952892
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assign atan_table[11] = 18'b000000000000010100; // 0.027976453
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assign atan_table[12] = 18'b000000000000001010; // 0.013988227
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assign atan_table[13] = 18'b000000000000000101; // 0.006994114
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assign atan_table[14] = 18'b000000000000000011; // 0.003497057
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assign atan_table[15] = 18'b000000000000000001; // 0.001748528
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assign atan_table[16] = 18'b000000000000000001; // 0.000874264
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end else if (CORDIC_DW == 16) begin
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assign x_value = X_VALUE_16;
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assign atan_table[ 0] = 15'b0010000000000000; // 45
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assign atan_table[ 1] = 15'b0001001011100100; // 26.56505118
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assign atan_table[ 2] = 15'b0000100111111011; // 14.03624347
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assign atan_table[ 3] = 15'b0000010100010001; // 7.125016349
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assign atan_table[ 4] = 15'b0000001010001011; // 3.576334375
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assign atan_table[ 5] = 15'b0000000101000110; // 1.789910608
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assign atan_table[ 6] = 15'b0000000010100011; // 0.895173710
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assign atan_table[ 7] = 15'b0000000001010001; // 0.447614171
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assign atan_table[ 8] = 15'b0000000000101001; // 0.223810500
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assign atan_table[ 9] = 15'b0000000000010100; // 0.111905677
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assign atan_table[10] = 15'b0000000000001010; // 0.055952892
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assign atan_table[11] = 15'b0000000000000101; // 0.027976453
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assign atan_table[12] = 15'b0000000000000011; // 0.013988227
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assign atan_table[13] = 15'b0000000000000001; // 0.006994114
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assign atan_table[14] = 15'b0000000000000001; // 0.003497057
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end else if (CORDIC_DW == 14) begin
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assign x_value = X_VALUE_14;
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assign atan_table[ 0] = 13'b00100000000000; // 45
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assign atan_table[ 1] = 13'b00010010111001; // 26.56505118
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assign atan_table[ 2] = 13'b00001001111111; // 14.03624347
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assign atan_table[ 3] = 13'b00000101000100; // 7.125016349
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assign atan_table[ 4] = 13'b00000010100011; // 3.576334375
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assign atan_table[ 5] = 13'b00000001010001; // 1.789910608
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assign atan_table[ 6] = 13'b00000000101001; // 0.895173710
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assign atan_table[ 7] = 13'b00000000010100; // 0.447614171
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assign atan_table[ 8] = 13'b00000000001010; // 0.223810500
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assign atan_table[ 9] = 13'b00000000000101; // 0.111905677
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assign atan_table[10] = 13'b00000000000011; // 0.055952892
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assign atan_table[11] = 13'b00000000000001; // 0.027976453
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assign atan_table[12] = 13'b00000000000001; // 0.013988227
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end
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endgenerate
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// pre-rotating
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// first two bits represent the quadrant in the unit circle
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assign quadrant = angle[CORDIC_DW-1:CORDIC_DW-2];
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always @(posedge clk)
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begin
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case (quadrant)
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2'b00,
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2'b11:
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begin
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x0 <= x_value;
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y0 <= Y_VALUE;
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z0 <= angle;
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end
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2'b01:
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begin
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x0 <= Y_VALUE;
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y0 <= x_value;
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z0 <= {2'b00, angle[CORDIC_DW-3:0]};
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end
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2'b10:
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begin
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x0 <= Y_VALUE;
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y0 <= -x_value;
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z0 <= {2'b11 ,angle[CORDIC_DW-3:0]};
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end
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endcase
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end
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assign x_s[0] = x0;
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assign y_s[0] = y0;
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assign z_s[0] = z0;
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assign x_shr_s[0] = x0;
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assign y_shr_s[0] = y0;
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assign data_in_d[0] = ddata_in;
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// cordic pipeline
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genvar i;
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generate
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for (i=0; i < CORDIC_DW-1; i=i+1) begin: rotation
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ad_dds_cordic_pipe #(
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.DW (CORDIC_DW),
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.DELAY_DW (DELAY_DW),
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.SHIFT(i))
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pipe (
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.clk (clk),
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.dataa_x (x_s[i]),
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.dataa_y (y_s[i]),
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.dataa_z (z_s[i]),
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.datab_x (x_shr_s[i]),
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.datab_y (y_shr_s[i]),
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.datab_z (atan_table[i]),
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.dir (z_s[i][CORDIC_DW-1]),
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.result_x (x_s[i+1]),
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.result_y (y_s[i+1]),
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.result_z (z_s[i+1]),
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.sgn_shift_x (x_shr_s[i+1]),
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.sgn_shift_y (y_shr_s[i+1]),
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.data_delay_in (data_in_d[i]),
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.data_delay_out (data_in_d[i+1])
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);
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end
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endgenerate
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// x and y are cos(angle) and sin(angle)
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always @(posedge clk) begin
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ddata_out <= data_in_d[CORDIC_DW-1];
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sine <= y_s[CORDIC_DW-1];
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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