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axi_dmac: Brought up the transfer request signal for the dest_fifo and dest_axi_stream interface.

main
Istvan Csomortani 2015-03-26 12:17:29 +02:00
parent 2d05193093
commit 0e1a60e8b7
4 changed files with 16 additions and 3 deletions
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8
library/axi_dmac/axi_dmac.v
View File

@ -153,6 +153,7 @@ module axi_dmac (
input m_axis_ready,
output m_axis_valid,
output [C_DMA_DATA_WIDTH_DEST-1:0] m_axis_data,
output m_axis_xfer_req,
// Input FIFO interface
input fifo_wr_clk,
@ -167,7 +168,8 @@ module axi_dmac (
input fifo_rd_en,
output fifo_rd_valid,
output [C_DMA_DATA_WIDTH_DEST-1:0] fifo_rd_dout,
output fifo_rd_underflow
output fifo_rd_underflow,
output fifo_rd_xfer_req
);
parameter PCORE_ID = 0;
@ -595,8 +597,9 @@ dmac_request_arb #(
.m_axis_ready(m_axis_ready),
.m_axis_valid(m_axis_valid),
.m_axis_data(m_axis_data),
.m_axis_xfer_req(m_axis_xfer_req),
.fifo_wr_clk(fifo_wr_clk),
.fifo_wr_en(fifo_wr_en),
.fifo_wr_din(fifo_wr_din),
@ -610,6 +613,7 @@ dmac_request_arb #(
.fifo_rd_valid(fifo_rd_valid),
.fifo_rd_dout(fifo_rd_dout),
.fifo_rd_underflow(fifo_rd_underflow),
.fifo_rd_xfer_req(fifo_rd_xfer_req),
// DBG
.dbg_dest_request_id(dest_request_id),

2
library/axi_dmac/dest_axi_stream.v
View File

@ -44,6 +44,7 @@ module dmac_dest_axi_stream (
output enabled,
input sync_id,
output sync_id_ret,
output xfer_req,
input [C_ID_WIDTH-1:0] request_id,
output [C_ID_WIDTH-1:0] response_id,
@ -94,6 +95,7 @@ dmac_data_mover # (
.enable(enable),
.enabled(data_enabled),
.sync_id(sync_id),
.xfer_req(xfer_req),
.request_id(request_id),
.response_id(data_id),

3
library/axi_dmac/dest_fifo_inf.v
View File

@ -56,6 +56,8 @@ module dmac_dest_fifo_inf (
output valid,
output underflow,
output xfer_req,
output fifo_ready,
input fifo_valid,
input [C_DATA_WIDTH-1:0] fifo_data,
@ -109,6 +111,7 @@ dmac_data_mover # (
.enable(enable),
.enabled(data_enabled),
.sync_id(sync_id),
.xfer_req(xfer_req),
.request_id(request_id),
.response_id(data_id),

6
library/axi_dmac/request_arb.v
View File

@ -109,6 +109,7 @@ module dmac_request_arb (
input m_axis_ready,
output m_axis_valid,
output [C_DMA_DATA_WIDTH_DEST-1:0] m_axis_data,
output m_axis_xfer_req,
// Input FIFO interface
input fifo_wr_clk,
@ -124,6 +125,7 @@ module dmac_request_arb (
output fifo_rd_valid,
output [C_DMA_DATA_WIDTH_DEST-1:0] fifo_rd_dout,
output fifo_rd_underflow,
output fifo_rd_xfer_req,
output [C_ID_WIDTH-1:0] dbg_dest_request_id,
output [C_ID_WIDTH-1:0] dbg_dest_address_id,
@ -493,6 +495,7 @@ dmac_dest_axi_stream #(
.data_id(data_id),
.sync_id(dest_sync_id),
.sync_id_ret(dest_sync_id_ret),
.xfer_req(m_axis_xfer_req),
.data_eot(data_eot),
.response_eot(response_eot),
@ -561,7 +564,8 @@ dmac_dest_fifo_inf #(
.en(fifo_rd_en),
.valid(fifo_rd_valid),
.dout(fifo_rd_dout),
.underflow(fifo_rd_underflow)
.underflow(fifo_rd_underflow),
.xfer_req(fifo_rd_xfer_req)
);
end else begin