diff --git a/library/axi_ad9122/axi_ad9122_core.v b/library/axi_ad9122/axi_ad9122_core.v index be6ccbf8c..a94b81232 100644 --- a/library/axi_ad9122/axi_ad9122_core.v +++ b/library/axi_ad9122/axi_ad9122_core.v @@ -218,6 +218,7 @@ module axi_ad9122_core #( .dac_status_ovf (dac_dovf), .dac_status_unf (dac_dunf), .dac_clk_ratio (32'd4), + .up_dac_ce (), .up_drp_sel (up_drp_sel), .up_drp_wr (up_drp_wr), .up_drp_addr (up_drp_addr), diff --git a/library/axi_ad9144/axi_ad9144_core.v b/library/axi_ad9144/axi_ad9144_core.v index 73c014d5a..d41c13ddb 100644 --- a/library/axi_ad9144/axi_ad9144_core.v +++ b/library/axi_ad9144/axi_ad9144_core.v @@ -241,6 +241,7 @@ module axi_ad9144_core #( .dac_status_ovf (dac_dovf), .dac_status_unf (dac_dunf), .dac_clk_ratio (32'd4), + .up_dac_ce (), .up_drp_sel (), .up_drp_wr (), .up_drp_addr (), diff --git a/library/axi_ad9152/axi_ad9152_core.v b/library/axi_ad9152/axi_ad9152_core.v index c6bf8df32..54f36b413 100644 --- a/library/axi_ad9152/axi_ad9152_core.v +++ b/library/axi_ad9152/axi_ad9152_core.v @@ -179,6 +179,7 @@ module axi_ad9152_core #( .dac_status_ovf (dac_dovf), .dac_status_unf (dac_dunf), .dac_clk_ratio (32'd4), + .up_dac_ce (), .up_drp_sel (), .up_drp_wr (), .up_drp_addr (), diff --git a/library/axi_ad9162/axi_ad9162_core.v b/library/axi_ad9162/axi_ad9162_core.v index 756e84061..6fb05f654 100644 --- a/library/axi_ad9162/axi_ad9162_core.v +++ b/library/axi_ad9162/axi_ad9162_core.v @@ -152,6 +152,7 @@ module axi_ad9162_core #( .dac_status_ovf (dac_dovf), .dac_status_unf (dac_dunf), .dac_clk_ratio (32'd16), + .up_dac_ce (), .up_drp_sel (), .up_drp_wr (), .up_drp_addr (), diff --git a/library/axi_ad9361/axi_ad9361_tx.v b/library/axi_ad9361/axi_ad9361_tx.v index f6794af5c..8b38f984e 100644 --- a/library/axi_ad9361/axi_ad9361_tx.v +++ b/library/axi_ad9361/axi_ad9361_tx.v @@ -118,7 +118,7 @@ module axi_ad9361_tx #( // internal registers reg dac_data_sync = 'd0; - reg [ 7:0] dac_rate_cnt = 'd0; + reg [15:0] dac_rate_cnt = 'd0; reg dac_valid_int = 'd0; reg dac_valid_i0_int = 'd0; reg dac_valid_q0_int = 'd0; @@ -136,7 +136,7 @@ module axi_ad9361_tx #( wire dac_data_sync_s; wire dac_dds_format_s; - wire [ 7:0] dac_datarate_s; + wire [15:0] dac_datarate_s; wire [47:0] dac_data_int_s; wire [ 5:0] up_wack_s; wire [ 5:0] up_rack_s; @@ -153,10 +153,10 @@ module axi_ad9361_tx #( // rate counters and data sync signals always @(posedge dac_clk) begin - if ((dac_data_sync == 1'b1) || (dac_rate_cnt == 8'd0)) begin + if ((dac_data_sync == 1'b1) || (dac_rate_cnt == 16'd0)) begin dac_rate_cnt <= dac_datarate_s; end else begin - dac_rate_cnt <= dac_rate_cnt - 1'b1; + dac_rate_cnt <= dac_rate_cnt - 1; end end @@ -169,7 +169,7 @@ module axi_ad9361_tx #( assign dac_valid_q1 = dac_valid_q1_int; always @(posedge dac_clk) begin - dac_valid_int <= (dac_rate_cnt == 8'd0) ? 1'b1 : 1'b0; + dac_valid_int <= (dac_rate_cnt == 16'd0) ? 1'b1 : 1'b0; dac_valid_i0_int <= dac_valid_int; dac_valid_q0_int <= dac_valid_int; dac_valid_i1_int <= dac_valid_int & ~dac_r1_mode; diff --git a/library/axi_ad9371/axi_ad9371_tx.v b/library/axi_ad9371/axi_ad9371_tx.v index 9b034dcd5..036b21d9d 100644 --- a/library/axi_ad9371/axi_ad9371_tx.v +++ b/library/axi_ad9371/axi_ad9371_tx.v @@ -259,6 +259,7 @@ module axi_ad9371_tx #( .dac_status_ovf (dac_dovf), .dac_status_unf (dac_dunf), .dac_clk_ratio (32'd2), + .up_dac_ce (), .up_drp_sel (), .up_drp_wr (), .up_drp_addr (), @@ -280,7 +281,7 @@ module axi_ad9371_tx #( .up_raddr (up_raddr), .up_rdata (up_rdata_s[4]), .up_rack (up_rack_s[4])); - + endmodule // *************************************************************************** diff --git a/library/axi_ad9739a/axi_ad9739a_core.v b/library/axi_ad9739a/axi_ad9739a_core.v index d56680ebc..d882e322e 100644 --- a/library/axi_ad9739a/axi_ad9739a_core.v +++ b/library/axi_ad9739a/axi_ad9739a_core.v @@ -176,6 +176,7 @@ module axi_ad9739a_core #( .dac_status_ovf (dac_dovf), .dac_status_unf (dac_dunf), .dac_clk_ratio (32'd16), + .up_dac_ce (), .up_drp_sel (), .up_drp_wr (), .up_drp_addr (),