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axi dac cores: Add missing ports to up_dac_common instance

main
AndreiGrozav 2017-05-12 13:37:34 +03:00
parent d93a6d062e
commit 0e1e507541
7 changed files with 12 additions and 6 deletions
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1
library/axi_ad9122/axi_ad9122_core.v
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@ -218,6 +218,7 @@ module axi_ad9122_core #(
.dac_status_ovf (dac_dovf), .dac_status_ovf (dac_dovf),
.dac_status_unf (dac_dunf), .dac_status_unf (dac_dunf),
.dac_clk_ratio (32'd4), .dac_clk_ratio (32'd4),
.up_dac_ce (),
.up_drp_sel (up_drp_sel), .up_drp_sel (up_drp_sel),
.up_drp_wr (up_drp_wr), .up_drp_wr (up_drp_wr),
.up_drp_addr (up_drp_addr), .up_drp_addr (up_drp_addr),

1
library/axi_ad9144/axi_ad9144_core.v
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@ -241,6 +241,7 @@ module axi_ad9144_core #(
.dac_status_ovf (dac_dovf), .dac_status_ovf (dac_dovf),
.dac_status_unf (dac_dunf), .dac_status_unf (dac_dunf),
.dac_clk_ratio (32'd4), .dac_clk_ratio (32'd4),
.up_dac_ce (),
.up_drp_sel (), .up_drp_sel (),
.up_drp_wr (), .up_drp_wr (),
.up_drp_addr (), .up_drp_addr (),

1
library/axi_ad9152/axi_ad9152_core.v
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@ -179,6 +179,7 @@ module axi_ad9152_core #(
.dac_status_ovf (dac_dovf), .dac_status_ovf (dac_dovf),
.dac_status_unf (dac_dunf), .dac_status_unf (dac_dunf),
.dac_clk_ratio (32'd4), .dac_clk_ratio (32'd4),
.up_dac_ce (),
.up_drp_sel (), .up_drp_sel (),
.up_drp_wr (), .up_drp_wr (),
.up_drp_addr (), .up_drp_addr (),

1
library/axi_ad9162/axi_ad9162_core.v
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@ -152,6 +152,7 @@ module axi_ad9162_core #(
.dac_status_ovf (dac_dovf), .dac_status_ovf (dac_dovf),
.dac_status_unf (dac_dunf), .dac_status_unf (dac_dunf),
.dac_clk_ratio (32'd16), .dac_clk_ratio (32'd16),
.up_dac_ce (),
.up_drp_sel (), .up_drp_sel (),
.up_drp_wr (), .up_drp_wr (),
.up_drp_addr (), .up_drp_addr (),

10
library/axi_ad9361/axi_ad9361_tx.v
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@ -118,7 +118,7 @@ module axi_ad9361_tx #(
// internal registers // internal registers
reg dac_data_sync = 'd0; reg dac_data_sync = 'd0;
reg [ 7:0] dac_rate_cnt = 'd0; reg [15:0] dac_rate_cnt = 'd0;
reg dac_valid_int = 'd0; reg dac_valid_int = 'd0;
reg dac_valid_i0_int = 'd0; reg dac_valid_i0_int = 'd0;
reg dac_valid_q0_int = 'd0; reg dac_valid_q0_int = 'd0;
@ -136,7 +136,7 @@ module axi_ad9361_tx #(
wire dac_data_sync_s; wire dac_data_sync_s;
wire dac_dds_format_s; wire dac_dds_format_s;
wire [ 7:0] dac_datarate_s; wire [15:0] dac_datarate_s;
wire [47:0] dac_data_int_s; wire [47:0] dac_data_int_s;
wire [ 5:0] up_wack_s; wire [ 5:0] up_wack_s;
wire [ 5:0] up_rack_s; wire [ 5:0] up_rack_s;
@ -153,10 +153,10 @@ module axi_ad9361_tx #(
// rate counters and data sync signals // rate counters and data sync signals
always @(posedge dac_clk) begin always @(posedge dac_clk) begin
if ((dac_data_sync == 1'b1) || (dac_rate_cnt == 8'd0)) begin if ((dac_data_sync == 1'b1) || (dac_rate_cnt == 16'd0)) begin
dac_rate_cnt <= dac_datarate_s; dac_rate_cnt <= dac_datarate_s;
end else begin end else begin
dac_rate_cnt <= dac_rate_cnt - 1'b1; dac_rate_cnt <= dac_rate_cnt - 1;
end end
end end
@ -169,7 +169,7 @@ module axi_ad9361_tx #(
assign dac_valid_q1 = dac_valid_q1_int; assign dac_valid_q1 = dac_valid_q1_int;
always @(posedge dac_clk) begin always @(posedge dac_clk) begin
dac_valid_int <= (dac_rate_cnt == 8'd0) ? 1'b1 : 1'b0; dac_valid_int <= (dac_rate_cnt == 16'd0) ? 1'b1 : 1'b0;
dac_valid_i0_int <= dac_valid_int; dac_valid_i0_int <= dac_valid_int;
dac_valid_q0_int <= dac_valid_int; dac_valid_q0_int <= dac_valid_int;
dac_valid_i1_int <= dac_valid_int & ~dac_r1_mode; dac_valid_i1_int <= dac_valid_int & ~dac_r1_mode;

3
library/axi_ad9371/axi_ad9371_tx.v
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@ -259,6 +259,7 @@ module axi_ad9371_tx #(
.dac_status_ovf (dac_dovf), .dac_status_ovf (dac_dovf),
.dac_status_unf (dac_dunf), .dac_status_unf (dac_dunf),
.dac_clk_ratio (32'd2), .dac_clk_ratio (32'd2),
.up_dac_ce (),
.up_drp_sel (), .up_drp_sel (),
.up_drp_wr (), .up_drp_wr (),
.up_drp_addr (), .up_drp_addr (),
@ -280,7 +281,7 @@ module axi_ad9371_tx #(
.up_raddr (up_raddr), .up_raddr (up_raddr),
.up_rdata (up_rdata_s[4]), .up_rdata (up_rdata_s[4]),
.up_rack (up_rack_s[4])); .up_rack (up_rack_s[4]));
endmodule endmodule
// *************************************************************************** // ***************************************************************************

1
library/axi_ad9739a/axi_ad9739a_core.v
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@ -176,6 +176,7 @@ module axi_ad9739a_core #(
.dac_status_ovf (dac_dovf), .dac_status_ovf (dac_dovf),
.dac_status_unf (dac_dunf), .dac_status_unf (dac_dunf),
.dac_clk_ratio (32'd16), .dac_clk_ratio (32'd16),
.up_dac_ce (),
.up_drp_sel (), .up_drp_sel (),
.up_drp_wr (), .up_drp_wr (),
.up_drp_addr (), .up_drp_addr (),