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pzsdr1/pzsdr2: audio_clkgen: Disable clock source buffer insertion 

Depending on the configuration of the clock source type of the input clock
the clocking wizard will instantiate all kinds of buffers on the input
clock signal.

For these particular projects there is no need to add any kind of buffer
since the source is already coming from a global clock buffer.  So set the
configuration accordingly.

Avoids the following warning:
	[Opt 31-32] Removing redundant IBUF since it is not being driven by a
	top-level port. i_system_wrapper/system_i/sys_audio_clkgen/inst/clkin1_ibufg
	Resolution: The tool has removed redundant IBUF. To resolve this
	warning, check for redundant IBUF in the input design.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2017-04-21 12:56:57 +02:00
parent 95a46bf1e1
commit 0e6cc95d0d
3 changed files with 3 additions and 0 deletions
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1
projects/pzsdr1/common/ccbox_bd.tcl
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@ -21,6 +21,7 @@ set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_
set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen
set_property -dict [list CONFIG.USE_RESET {true} CONFIG.RESET_TYPE {ACTIVE_LOW}] $sys_audio_clkgen set_property -dict [list CONFIG.USE_RESET {true} CONFIG.RESET_TYPE {ACTIVE_LOW}] $sys_audio_clkgen
set_property -dict [list CONFIG.USE_PHASE_ALIGNMENT false] $sys_audio_clkgen set_property -dict [list CONFIG.USE_PHASE_ALIGNMENT false] $sys_audio_clkgen
set_property -dict [list CONFIG.PRIM_SOURCE No_buffer] $sys_audio_clkgen
set axi_i2s_adi [create_bd_cell -type ip -vlnv analog.com:user:axi_i2s_adi:1.0 axi_i2s_adi] set axi_i2s_adi [create_bd_cell -type ip -vlnv analog.com:user:axi_i2s_adi:1.0 axi_i2s_adi]
set_property -dict [list CONFIG.DMA_TYPE {1}] $axi_i2s_adi set_property -dict [list CONFIG.DMA_TYPE {1}] $axi_i2s_adi

1
projects/pzsdr2/common/ccbox_bd.tcl
View File

@ -21,6 +21,7 @@ set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_
set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen
set_property -dict [list CONFIG.USE_RESET {true} CONFIG.RESET_TYPE {ACTIVE_LOW}] $sys_audio_clkgen set_property -dict [list CONFIG.USE_RESET {true} CONFIG.RESET_TYPE {ACTIVE_LOW}] $sys_audio_clkgen
set_property -dict [list CONFIG.USE_PHASE_ALIGNMENT false] $sys_audio_clkgen set_property -dict [list CONFIG.USE_PHASE_ALIGNMENT false] $sys_audio_clkgen
set_property -dict [list CONFIG.PRIM_SOURCE No_buffer] $sys_audio_clkgen
set axi_i2s_adi [create_bd_cell -type ip -vlnv analog.com:user:axi_i2s_adi:1.0 axi_i2s_adi] set axi_i2s_adi [create_bd_cell -type ip -vlnv analog.com:user:axi_i2s_adi:1.0 axi_i2s_adi]
set_property -dict [list CONFIG.DMA_TYPE {1}] $axi_i2s_adi set_property -dict [list CONFIG.DMA_TYPE {1}] $axi_i2s_adi

1
projects/pzsdr2/common/ccfmc_bd.tcl
View File

@ -56,6 +56,7 @@ set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_
set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen
set_property -dict [list CONFIG.USE_RESET {true} CONFIG.RESET_TYPE {ACTIVE_LOW}] $sys_audio_clkgen set_property -dict [list CONFIG.USE_RESET {true} CONFIG.RESET_TYPE {ACTIVE_LOW}] $sys_audio_clkgen
set_property -dict [list CONFIG.USE_PHASE_ALIGNMENT false] $sys_audio_clkgen set_property -dict [list CONFIG.USE_PHASE_ALIGNMENT false] $sys_audio_clkgen
set_property -dict [list CONFIG.PRIM_SOURCE No_buffer] $sys_audio_clkgen
set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core] set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core]
set_property -dict [list CONFIG.DMA_TYPE {1}] $axi_spdif_tx_core set_property -dict [list CONFIG.DMA_TYPE {1}] $axi_spdif_tx_core