From 0eacde9158c83af98c5315b5b772810d89d02fde Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Tue, 13 Jun 2017 09:52:16 -0400 Subject: [PATCH] fmcjesdadc1/a5soc- alt 16.1 updates --- projects/fmcjesdadc1/a5soc/system_constr.sdc | 16 ++-------------- projects/fmcjesdadc1/a5soc/system_project.tcl | 15 ++++++--------- 2 files changed, 8 insertions(+), 23 deletions(-) diff --git a/projects/fmcjesdadc1/a5soc/system_constr.sdc b/projects/fmcjesdadc1/a5soc/system_constr.sdc index e2cc1a715..a3fba4b81 100644 --- a/projects/fmcjesdadc1/a5soc/system_constr.sdc +++ b/projects/fmcjesdadc1/a5soc/system_constr.sdc @@ -1,22 +1,10 @@ create_clock -period "4.000 ns" -name ref_clk [get_ports {ref_clk}] -create_clock -period "20.000 ns" -name sys_cpu_clk [get_pins {i_system_bd|sys_hps|fpga_interfaces|clocks_resets|h2f_user0_clk}] -create_clock -period "10.000 ns" -name sys_dma_clk [get_pins {i_system_bd|sys_hps|fpga_interfaces|clocks_resets|h2f_user1_clk}] derive_pll_clocks derive_clock_uncertainty set_false_path -to [get_registers *sysref_en_m1*] - -set_false_path -from [get_clocks {sys_cpu_clk}] -through [get_nets *altera_jesd204_rx_ctl_inst*]\ - -to [get_clocks {i_system_bd|avl_ad9250_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}] - -set_false_path -from [get_clocks {i_system_bd|avl_ad9250_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}]\ - -through [get_nets *altera_jesd204_rx_ctl_inst*] -to [get_clocks {sys_cpu_clk}] - -set_false_path -from [get_clocks {sys_cpu_clk}] -through [get_nets *altera_jesd204_rx_csr_inst*]\ - -to [get_clocks {i_system_bd|avl_ad9250_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}] - -set_false_path -from [get_clocks {i_system_bd|avl_ad9250_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}]\ - -through [get_nets *altera_jesd204_rx_csr_inst*] -to [get_clocks {sys_cpu_clk}] +set_false_path -from [get_clocks *h2f_user0_clk*] -through [get_nets *altera_jesd204*] -to [get_clocks *divclk*] +set_false_path -from [get_clocks *divclk*] -through [get_nets *altera_jesd204*] -to [get_clocks *h2f_user0_clk*] diff --git a/projects/fmcjesdadc1/a5soc/system_project.tcl b/projects/fmcjesdadc1/a5soc/system_project.tcl index 30a3c78f9..5f444fa73 100755 --- a/projects/fmcjesdadc1/a5soc/system_project.tcl +++ b/projects/fmcjesdadc1/a5soc/system_project.tcl @@ -1,18 +1,15 @@ -load_package flow - source ../../scripts/adi_env.tcl -project_new fmcjesdadc1_a5soc -overwrite +source ../../scripts/adi_project_alt.tcl -source "../../common/a5soc/a5soc_system_assign.tcl" +adi_project_altera fmcjesdadc1_a5soc + +source $ad_hdl_dir/projects/common/a5soc/a5soc_system_assign.tcl + +# files set_global_assignment -name VERILOG_FILE ../common/fmcjesdadc1_spi.v set_global_assignment -name VERILOG_FILE ../../../library/common/ad_sysref_gen.v -set_global_assignment -name VERILOG_FILE system_top.v -set_global_assignment -name QSYS_FILE system_bd.qsys - -set_global_assignment -name SDC_FILE system_constr.sdc -set_global_assignment -name TOP_LEVEL_ENTITY system_top # reference clock