template_kv260: Add template design for kv260 evaluation board
alin724
Alin-Tudor Sferle
parent
830b5aecb6
commit
0f3462c83b
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####################################################################################
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## Copyright (c) 2023 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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####################################################################################
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PROJECT_NAME := template_kv260
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M_DEPS += ../../scripts/adi_pd.tcl
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M_DEPS += ../../common/kv260/kv260_system_constr.xdc
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M_DEPS += ../../common/kv260/kv260_system_bd.tcl
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M_DEPS += ../../../library/common/ad_iobuf.v
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LIB_DEPS += axi_sysid
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LIB_DEPS += sysid_rom
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include ../../scripts/project-xilinx.mk
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@ -0,0 +1,150 @@
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# create board design
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# set Kria SOM240_1 connector to KV260 evaluation carrier
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set_property board_connections {som240_1_connector xilinx.com:kv260_carrier:som240_1_connector:1.3} [current_project]
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# default ports
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# default ports
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create_bd_port -dir O -from 2 -to 0 spi0_csn
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create_bd_port -dir O spi0_sclk
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create_bd_port -dir O spi0_mosi
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create_bd_port -dir I spi0_miso
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create_bd_port -dir I -from 94 -to 0 gpio_i
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create_bd_port -dir O -from 94 -to 0 gpio_o
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create_bd_port -dir O -from 94 -to 0 gpio_t
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# instance: sys_ps8
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ad_ip_instance zynq_ultra_ps_e sys_ps8
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apply_bd_automation -rule xilinx.com:bd_rule:zynq_ultra_ps_e \
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-config {apply_board_preset 1} [get_bd_cells sys_ps8]
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set_property -dict "CONFIG.PSU__PSS_REF_CLK__FREQMHZ 33.333333333 CONFIG.PSU__DDRC__CWL 16" [get_bd_cells sys_ps8]
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ad_ip_parameter sys_ps8 CONFIG.PSU__USE__M_AXI_GP0 0
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ad_ip_parameter sys_ps8 CONFIG.PSU__USE__M_AXI_GP1 0
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ad_ip_parameter sys_ps8 CONFIG.PSU__USE__M_AXI_GP2 1
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ad_ip_parameter sys_ps8 CONFIG.PSU__MAXIGP2__DATA_WIDTH 32
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ad_ip_parameter sys_ps8 CONFIG.PSU__FPGA_PL0_ENABLE 1
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ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL}
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ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ 100
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ad_ip_parameter sys_ps8 CONFIG.PSU__FPGA_PL1_ENABLE 1
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ad_ip_parameter sys_ps8 CONFIG.PSU__FPGA_PL2_ENABLE 1
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ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {IOPLL}
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ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ 250
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ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {IOPLL}
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ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ 500
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ad_ip_parameter sys_ps8 CONFIG.PSU__USE__IRQ0 1
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ad_ip_parameter sys_ps8 CONFIG.PSU__USE__IRQ1 1
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ad_ip_parameter sys_ps8 CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE 1
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set_property -dict [list \
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CONFIG.PSU__SPI0__PERIPHERAL__ENABLE 1 \
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CONFIG.PSU__SPI0__PERIPHERAL__IO {EMIO} \
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CONFIG.PSU__SPI0__GRP_SS1__ENABLE 1 \
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CONFIG.PSU__SPI0__GRP_SS2__ENABLE 1 \
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CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ 100 \
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] [get_bd_cells sys_ps8]
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# processor system reset instances for all the three system clocks
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ad_ip_instance proc_sys_reset sys_rstgen
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ad_ip_parameter sys_rstgen CONFIG.C_EXT_RST_WIDTH 1
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ad_ip_instance proc_sys_reset sys_250m_rstgen
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ad_ip_parameter sys_250m_rstgen CONFIG.C_EXT_RST_WIDTH 1
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ad_ip_instance proc_sys_reset sys_500m_rstgen
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ad_ip_parameter sys_500m_rstgen CONFIG.C_EXT_RST_WIDTH 1
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# system reset/clock definitions
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ad_connect sys_cpu_clk sys_ps8/pl_clk0
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ad_connect sys_250m_clk sys_ps8/pl_clk1
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ad_connect sys_500m_clk sys_ps8/pl_clk2
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ad_connect sys_ps8/pl_resetn0 sys_rstgen/ext_reset_in
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ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk
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ad_connect sys_ps8/pl_resetn0 sys_250m_rstgen/ext_reset_in
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ad_connect sys_250m_clk sys_250m_rstgen/slowest_sync_clk
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ad_connect sys_ps8/pl_resetn0 sys_500m_rstgen/ext_reset_in
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ad_connect sys_500m_clk sys_500m_rstgen/slowest_sync_clk
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ad_connect sys_cpu_reset sys_rstgen/peripheral_reset
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ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn
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ad_connect sys_250m_reset sys_250m_rstgen/peripheral_reset
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ad_connect sys_250m_resetn sys_250m_rstgen/peripheral_aresetn
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ad_connect sys_500m_reset sys_500m_rstgen/peripheral_reset
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ad_connect sys_500m_resetn sys_500m_rstgen/peripheral_aresetn
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# generic system clocks&resets pointers
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set sys_cpu_clk [get_bd_nets sys_cpu_clk]
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set sys_dma_clk [get_bd_nets sys_250m_clk]
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set sys_iodelay_clk [get_bd_nets sys_500m_clk]
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set sys_cpu_reset [get_bd_nets sys_cpu_reset]
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set sys_cpu_resetn [get_bd_nets sys_cpu_resetn]
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set sys_dma_reset [get_bd_nets sys_250m_reset]
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set sys_dma_resetn [get_bd_nets sys_250m_resetn]
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set sys_iodelay_reset [get_bd_nets sys_500m_reset]
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set sys_iodelay_resetn [get_bd_nets sys_500m_resetn]
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# gpio
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ad_connect gpio_i sys_ps8/emio_gpio_i
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ad_connect gpio_o sys_ps8/emio_gpio_o
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ad_connect gpio_t sys_ps8/emio_gpio_t
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# spi
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ad_ip_instance xlconcat spi0_csn_concat
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ad_ip_parameter spi0_csn_concat CONFIG.NUM_PORTS 3
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ad_connect sys_ps8/emio_spi0_ss_o_n spi0_csn_concat/In0
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ad_connect sys_ps8/emio_spi0_ss1_o_n spi0_csn_concat/In1
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ad_connect sys_ps8/emio_spi0_ss2_o_n spi0_csn_concat/In2
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ad_connect spi0_csn_concat/dout spi0_csn
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ad_connect sys_ps8/emio_spi0_sclk_o spi0_sclk
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ad_connect sys_ps8/emio_spi0_m_o spi0_mosi
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ad_connect sys_ps8/emio_spi0_m_i spi0_miso
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ad_connect sys_ps8/emio_spi0_ss_i_n VCC
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ad_connect sys_ps8/emio_spi0_sclk_i GND
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ad_connect sys_ps8/emio_spi0_s_i GND
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ad_ip_instance xlconcat sys_concat_intc_0
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ad_ip_parameter sys_concat_intc_0 CONFIG.NUM_PORTS 8
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ad_ip_instance xlconcat sys_concat_intc_1
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ad_ip_parameter sys_concat_intc_1 CONFIG.NUM_PORTS 8
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ad_connect sys_concat_intc_0/dout sys_ps8/pl_ps_irq0
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ad_connect sys_concat_intc_1/dout sys_ps8/pl_ps_irq1
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ad_connect sys_concat_intc_1/In7 GND
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ad_connect sys_concat_intc_1/In6 GND
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ad_connect sys_concat_intc_1/In5 GND
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ad_connect sys_concat_intc_1/In4 GND
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ad_connect sys_concat_intc_1/In3 GND
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ad_connect sys_concat_intc_1/In2 GND
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ad_connect sys_concat_intc_1/In1 GND
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ad_connect sys_concat_intc_1/In0 GND
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ad_connect sys_concat_intc_0/In7 GND
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ad_connect sys_concat_intc_0/In6 GND
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ad_connect sys_concat_intc_0/In5 GND
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ad_connect sys_concat_intc_0/In4 GND
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ad_connect sys_concat_intc_0/In3 GND
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ad_connect sys_concat_intc_0/In2 GND
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ad_connect sys_concat_intc_0/In1 GND
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ad_connect sys_concat_intc_0/In0 GND
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# system id
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ad_ip_instance axi_sysid axi_sysid_0
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ad_ip_instance sysid_rom rom_sys_0
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ad_connect axi_sysid_0/rom_addr rom_sys_0/rom_addr
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ad_connect axi_sysid_0/sys_rom_data rom_sys_0/rom_data
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ad_connect sys_cpu_clk rom_sys_0/clk
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ad_cpu_interconnect 0x45000000 axi_sysid_0
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@ -0,0 +1,5 @@
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# constraints
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set_property -dict {PACKAGE_PIN A12 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4} [get_ports fan_en_b]; # Bank 45 VCCO - som240_1_b13 - IO_L11P_AD9P_45
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set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN ENABLE [current_design]
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source $ad_hdl_dir/projects/scripts/adi_pd.tcl
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source $ad_hdl_dir/projects/common/kv260/kv260_system_bd.tcl
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#system ID
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ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
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ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt"
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ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
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sysid_gen_sys_init_file
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source ../../../scripts/adi_env.tcl
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source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
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source $ad_hdl_dir/projects/scripts/adi_board.tcl
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adi_project template_kv260
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adi_project_files template_kv260 [list \
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"system_top.v" \
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"$ad_hdl_dir/library/common/ad_iobuf.v" \
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"$ad_hdl_dir/projects/common/kv260/kv260_system_constr.xdc" ]
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adi_project_run template_kv260
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@ -0,0 +1,61 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2023 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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output fan_en_b
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);
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wire [94:0] gpio_i;
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wire [94:0] gpio_o;
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assign gpio_i[94:1] = gpio_o[94:1];
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assign fan_en_b = gpio_o[0];
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// instantiations
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system_wrapper i_system_wrapper (
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.gpio_i (gpio_i),
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.gpio_o (gpio_o),
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.gpio_t (),
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.spi0_csn (),
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.spi0_miso (1'b0),
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.spi0_mosi (),
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.spi0_sclk ());
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endmodule
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@ -121,6 +121,10 @@ proc adi_project {project_name {mode 0} {parameter_list {}} } {
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set device "xc7vx690tffg1761-2"
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set board [lindex [lsearch -all -inline [get_board_parts] *vc709*] end]
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}
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if [regexp "_kv260" $project_name] {
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set device "xck26-sfvc784-2LV-c"
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set board [lindex [lsearch -all -inline [get_board_parts] *kv260*] end]
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}
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adi_project_create $project_name $mode $parameter_list $device $board
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}
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@ -163,6 +167,8 @@ proc adi_project_create {project_name mode parameter_list device {board "not-app
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if [regexp "^xc7z" $p_device] {
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set sys_zynq 1
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} elseif [regexp "^xck" $p_device] {
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set sys_zynq 2
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} elseif [regexp "^xczu" $p_device] {
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set sys_zynq 2
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} elseif [regexp "^xcv\[ecmph\]" $p_device] {
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