From 0f37dd6424aa106520d03dbc2f4ebcecbf211e6f Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Fri, 19 Feb 2016 14:09:57 +0200
Subject: [PATCH] fmcjesdadc1: Fixed project

- changed system_project.tcl so that all base designs to be included
- changed DMA properties to take into consideration the new parameter names
- changed reset bridges to asynchronous
- increased maximum burst size of the DMA bridge
- changed the data_width of the memory bus to 256, as with 512 timing violations may occur
- changed base addresses for the base system to be the same as in the previous release
---
 projects/common/a5gt/a5gt_system_bd.qsys      | 942 ++++++++++++------
 projects/fmcjesdadc1/a5gt/system_bd.qsys      |  90 +-
 projects/fmcjesdadc1/a5gt/system_constr.sdc   |   7 +-
 projects/fmcjesdadc1/a5gt/system_project.tcl  |   4 +-
 .../fmcjesdadc1/common/fmcjesdadc1_bd.qsys    | 216 ++--
 5 files changed, 780 insertions(+), 479 deletions(-)

diff --git a/projects/common/a5gt/a5gt_system_bd.qsys b/projects/common/a5gt/a5gt_system_bd.qsys
index c7491b125..37f968cb1 100644
--- a/projects/common/a5gt/a5gt_system_bd.qsys
+++ b/projects/common/a5gt/a5gt_system_bd.qsys
@@ -9,14 +9,6 @@
    categories="System" />
  <parameter name="bonusData"><![CDATA[bonusData 
 {
-   element $${FILENAME}
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria V";
-         type = "String";
-      }
-   }
    element a5gt_system_bd
    {
       datum _originalDeviceFamily
@@ -25,21 +17,47 @@
          type = "String";
       }
    }
+   element cpu_clk
+   {
+      datum _sortIndex
+      {
+         value = "21";
+         type = "int";
+      }
+   }
+   element cpu_reset
+   {
+      datum _sortIndex
+      {
+         value = "22";
+         type = "int";
+      }
+   }
    element mem_clk
    {
       datum _sortIndex
       {
-         value = "17";
+         value = "19";
          type = "int";
       }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
    }
    element mem_rst
    {
       datum _sortIndex
       {
-         value = "18";
+         value = "20";
          type = "int";
       }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
    }
    element sys_clk
    {
@@ -66,7 +84,7 @@
    {
       datum baseAddress
       {
-         value = "557844480";
+         value = "354473984";
          type = "String";
       }
    }
@@ -74,9 +92,14 @@
    {
       datum _sortIndex
       {
-         value = "15";
+         value = "17";
          type = "int";
       }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
    }
    element sys_cpu_interconnect.s0
    {
@@ -90,7 +113,7 @@
    {
       datum _sortIndex
       {
-         value = "5";
+         value = "6";
          type = "int";
       }
       datum sopceditor_expanded
@@ -108,7 +131,7 @@
       }
       datum baseAddress
       {
-         value = "268435456";
+         value = "0";
          type = "String";
       }
    }
@@ -116,12 +139,12 @@
    {
       datum _sortIndex
       {
-         value = "6";
+         value = "7";
          type = "int";
       }
       datum sopceditor_expanded
       {
-         value = "1";
+         value = "0";
          type = "boolean";
       }
    }
@@ -129,7 +152,7 @@
    {
       datum baseAddress
       {
-         value = "557846528";
+         value = "354476032";
          type = "String";
       }
    }
@@ -137,15 +160,20 @@
    {
       datum _sortIndex
       {
-         value = "7";
+         value = "8";
          type = "int";
       }
+      datum sopceditor_expanded
+      {
+         value = "0";
+         type = "boolean";
+      }
    }
    element sys_ethernet_dma_rx.csr
    {
       datum baseAddress
       {
-         value = "557847680";
+         value = "354477120";
          type = "String";
       }
    }
@@ -153,7 +181,7 @@
    {
       datum baseAddress
       {
-         value = "557847648";
+         value = "354477152";
          type = "String";
       }
    }
@@ -161,7 +189,7 @@
    {
       datum baseAddress
       {
-         value = "557847776";
+         value = "354477184";
          type = "String";
       }
    }
@@ -169,15 +197,20 @@
    {
       datum _sortIndex
       {
-         value = "8";
+         value = "9";
          type = "int";
       }
+      datum sopceditor_expanded
+      {
+         value = "0";
+         type = "boolean";
+      }
    }
    element sys_ethernet_dma_tx.csr
    {
       datum baseAddress
       {
-         value = "557847712";
+         value = "354477056";
          type = "String";
       }
    }
@@ -185,11 +218,53 @@
    {
       datum baseAddress
       {
-         value = "557847616";
+         value = "354477088";
          type = "String";
       }
    }
    element sys_gpio
+   {
+      datum _sortIndex
+      {
+         value = "14";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "0";
+         type = "boolean";
+      }
+   }
+   element sys_gpio.s1
+   {
+      datum baseAddress
+      {
+         value = "354477248";
+         type = "String";
+      }
+   }
+   element sys_gpio_bd
+   {
+      datum _sortIndex
+      {
+         value = "15";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "0";
+         type = "boolean";
+      }
+   }
+   element sys_gpio_bd.s1
+   {
+      datum baseAddress
+      {
+         value = "354477344";
+         type = "String";
+      }
+   }
+   element sys_id
    {
       datum _sortIndex
       {
@@ -198,44 +273,7 @@
       }
       datum sopceditor_expanded
       {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_gpio.s1
-   {
-      datum baseAddress
-      {
-         value = "557847760";
-         type = "String";
-      }
-   }
-   element sys_gpio_bd
-   {
-      datum _sortIndex
-      {
-         value = "12";
-         type = "int";
-      }
-   }
-   element sys_gpio_bd.s1
-   {
-      datum baseAddress
-      {
-         value = "557847744";
-         type = "String";
-      }
-   }
-   element sys_id
-   {
-      datum _sortIndex
-      {
-         value = "11";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
+         value = "0";
          type = "boolean";
       }
    }
@@ -243,7 +281,7 @@
    {
       datum baseAddress
       {
-         value = "557847784";
+         value = "354477272";
          type = "String";
       }
    }
@@ -269,7 +307,15 @@
       }
       datum baseAddress
       {
-         value = "555745280";
+         value = "352321536";
+         type = "String";
+      }
+   }
+   element sys_int_mem.s2
+   {
+      datum baseAddress
+      {
+         value = "352321536";
          type = "String";
       }
    }
@@ -277,17 +323,27 @@
    {
       datum _sortIndex
       {
-         value = "19";
+         value = "23";
          type = "int";
       }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
    }
    element sys_mem_interconnect
    {
       datum _sortIndex
       {
-         value = "16";
+         value = "18";
          type = "int";
       }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
    }
    element sys_pll
    {
@@ -314,7 +370,28 @@
    {
       datum _sortIndex
       {
-         value = "14";
+         value = "16";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "0";
+         type = "boolean";
+      }
+   }
+   element sys_spi.spi_control_port
+   {
+      datum baseAddress
+      {
+         value = "354477312";
+         type = "String";
+      }
+   }
+   element sys_tcm_mem
+   {
+      datum _sortIndex
+      {
+         value = "5";
          type = "int";
       }
       datum sopceditor_expanded
@@ -323,15 +400,65 @@
          type = "boolean";
       }
    }
-   element sys_spi.spi_control_port
+   element sys_tcm_mem.s1
    {
       datum baseAddress
       {
-         value = "557847552";
+         value = "354467840";
+         type = "String";
+      }
+   }
+   element sys_tcm_mem.s2
+   {
+      datum baseAddress
+      {
+         value = "354467840";
          type = "String";
       }
    }
    element sys_timer
+   {
+      datum _sortIndex
+      {
+         value = "11";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "0";
+         type = "boolean";
+      }
+   }
+   element sys_timer.s1
+   {
+      datum baseAddress
+      {
+         value = "354477216";
+         type = "String";
+      }
+   }
+   element sys_timer_2nd
+   {
+      datum _sortIndex
+      {
+         value = "12";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "0";
+         type = "boolean";
+      }
+   }
+   element sys_timer_2nd.s1
+   {
+      datum baseAddress
+      {
+         value = "354477376";
+         type = "String";
+      }
+   }
+   element sys_uart
    {
       datum _sortIndex
       {
@@ -340,28 +467,7 @@
       }
       datum sopceditor_expanded
       {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element sys_timer.s1
-   {
-      datum baseAddress
-      {
-         value = "557847584";
-         type = "String";
-      }
-   }
-   element sys_uart
-   {
-      datum _sortIndex
-      {
-         value = "9";
-         type = "int";
-      }
-      datum sopceditor_expanded
-      {
-         value = "1";
+         value = "0";
          type = "boolean";
       }
    }
@@ -369,7 +475,7 @@
    {
       datum baseAddress
       {
-         value = "557847792";
+         value = "354477280";
          type = "String";
       }
    }
@@ -466,6 +572,12 @@
  <parameter name="timeStamp" value="0" />
  <parameter name="useTestBenchNamingPattern" value="false" />
  <instanceScript></instanceScript>
+ <interface name="cpu_clk" internal="cpu_clk.out_clk" type="clock" dir="start" />
+ <interface
+   name="cpu_rst"
+   internal="cpu_reset.out_reset"
+   type="reset"
+   dir="start" />
  <interface name="mem_clk" internal="mem_clk.out_clk" type="clock" dir="start" />
  <interface name="mem_rst" internal="mem_rst.out_reset" type="reset" dir="start" />
  <interface
@@ -551,33 +663,49 @@
    dir="end" />
  <interface name="sys_rst" internal="sys_rst.in_reset" type="reset" dir="end" />
  <interface name="sys_spi" internal="sys_spi.external" type="conduit" dir="end" />
- <module name="mem_clk" kind="altera_clock_bridge" version="15.0" enabled="1">
+ <module name="cpu_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
   <parameter name="DERIVED_CLOCK_RATE" value="100000000" />
   <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
   <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
  </module>
- <module name="mem_rst" kind="altera_reset_bridge" version="15.0" enabled="1">
+ <module
+   name="cpu_reset"
+   kind="altera_reset_bridge"
+   version="15.1"
+   enabled="1">
   <parameter name="ACTIVE_LOW_RESET" value="0" />
-  <parameter name="AUTO_CLK_CLOCK_RATE" value="100000000" />
+  <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
   <parameter name="NUM_RESET_OUTPUTS" value="1" />
-  <parameter name="SYNCHRONOUS_EDGES" value="deassert" />
+  <parameter name="SYNCHRONOUS_EDGES" value="none" />
   <parameter name="USE_RESET_REQUEST" value="0" />
  </module>
- <module name="sys_clk" kind="altera_clock_bridge" version="15.0" enabled="1">
+ <module name="mem_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
+  <parameter name="DERIVED_CLOCK_RATE" value="100000000" />
+  <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
+  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
+ </module>
+ <module name="mem_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
+  <parameter name="ACTIVE_LOW_RESET" value="0" />
+  <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
+  <parameter name="NUM_RESET_OUTPUTS" value="1" />
+  <parameter name="SYNCHRONOUS_EDGES" value="none" />
+  <parameter name="USE_RESET_REQUEST" value="0" />
+ </module>
+ <module name="sys_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
   <parameter name="DERIVED_CLOCK_RATE" value="0" />
   <parameter name="EXPLICIT_CLOCK_RATE" value="1000000000" />
   <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
  </module>
- <module name="sys_cpu" kind="altera_nios2_gen2" version="15.0" enabled="1">
-  <parameter name="AUTO_CLK_CLOCK_DOMAIN" value="6" />
-  <parameter name="AUTO_CLK_RESET_DOMAIN" value="6" />
+ <module name="sys_cpu" kind="altera_nios2_gen2" version="15.1" enabled="1">
+  <parameter name="AUTO_CLK_CLOCK_DOMAIN" value="14" />
+  <parameter name="AUTO_CLK_RESET_DOMAIN" value="14" />
   <parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" />
   <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
   <parameter name="bht_ramBlockType" value="Automatic" />
   <parameter name="breakOffset" value="32" />
   <parameter name="breakSlave">sys_cpu.jtag_debug_module</parameter>
   <parameter name="cdx_enabled" value="false" />
-  <parameter name="clockFrequency" value="1000000000" />
+  <parameter name="clockFrequency" value="100000000" />
   <parameter name="cpuArchRev" value="1" />
   <parameter name="cpuID" value="0" />
   <parameter name="cpuReset" value="false" />
@@ -588,13 +716,13 @@
   <parameter name="dataAddrWidth" value="30" />
   <parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
   <parameter name="dataMasterHighPerformanceMapParam" value="" />
-  <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='sys_ddr3_cntrl.avl' start='0x10000000' end='0x20000000' /><slave name='sys_cpu_interconnect.s0' start='0x20000000' end='0x21000000' /><slave name='sys_int_mem.s1' start='0x21200000' end='0x21400000' /><slave name='sys_cpu.debug_mem_slave' start='0x21400800' end='0x21401000' /><slave name='sys_ethernet.control_port' start='0x21401000' end='0x21401400' /><slave name='sys_spi.spi_control_port' start='0x21401400' end='0x21401420' /><slave name='sys_timer.s1' start='0x21401420' end='0x21401440' /><slave name='sys_ethernet_dma_tx.descriptor_slave' start='0x21401440' end='0x21401460' /><slave name='sys_ethernet_dma_rx.descriptor_slave' start='0x21401460' end='0x21401480' /><slave name='sys_ethernet_dma_rx.csr' start='0x21401480' end='0x214014A0' /><slave name='sys_ethernet_dma_tx.csr' start='0x214014A0' end='0x214014C0' /><slave name='sys_gpio_bd.s1' start='0x214014C0' end='0x214014D0' /><slave name='sys_gpio.s1' start='0x214014D0' end='0x214014E0' /><slave name='sys_ethernet_dma_rx.response' start='0x214014E0' end='0x214014E8' /><slave name='sys_id.control_slave' start='0x214014E8' end='0x214014F0' /><slave name='sys_uart.avalon_jtag_slave' start='0x214014F0' end='0x214014F8' /></address-map>]]></parameter>
+  <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='sys_ddr3_cntrl.avl' start='0x0' end='0x10000000' type='altera_mem_if_ddr3_emif.avl' /><slave name='sys_int_mem.s1' start='0x15000000' end='0x150C0000' type='altera_avalon_onchip_memory2.s1' /><slave name='sys_cpu.debug_mem_slave' start='0x1520D800' end='0x1520E000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sys_ethernet.control_port' start='0x1520E000' end='0x1520E400' type='altera_eth_tse.control_port' /><slave name='sys_ethernet_dma_tx.csr' start='0x1520E400' end='0x1520E420' type='altera_msgdma.csr' /><slave name='sys_ethernet_dma_tx.descriptor_slave' start='0x1520E420' end='0x1520E440' type='altera_msgdma.descriptor_slave' /><slave name='sys_ethernet_dma_rx.csr' start='0x1520E440' end='0x1520E460' type='altera_msgdma.csr' /><slave name='sys_ethernet_dma_rx.descriptor_slave' start='0x1520E460' end='0x1520E480' type='altera_msgdma.descriptor_slave' /><slave name='sys_ethernet_dma_rx.response' start='0x1520E480' end='0x1520E488' type='altera_msgdma.response' /><slave name='sys_timer.s1' start='0x1520E4A0' end='0x1520E4C0' type='altera_avalon_timer.s1' /><slave name='sys_gpio.s1' start='0x1520E4C0' end='0x1520E4D0' type='altera_avalon_pio.s1' /><slave name='sys_id.control_slave' start='0x1520E4D8' end='0x1520E4E0' type='altera_avalon_sysid_qsys.control_slave' /><slave name='sys_uart.avalon_jtag_slave' start='0x1520E4E0' end='0x1520E4E8' type='altera_avalon_jtag_uart.avalon_jtag_slave' /><slave name='sys_spi.spi_control_port' start='0x1520E500' end='0x1520E520' type='altera_avalon_spi.spi_control_port' /><slave name='sys_gpio_bd.s1' start='0x1520E520' end='0x1520E530' type='altera_avalon_pio.s1' /><slave name='sys_timer_2nd.s1' start='0x1520E540' end='0x1520E560' type='altera_avalon_timer.s1' /><slave name='sys_cpu_interconnect.s0' start='0x20000000' end='0x21000000' type='altera_avalon_mm_bridge.s0' /></address-map>]]></parameter>
   <parameter name="data_master_high_performance_paddr_base" value="0" />
   <parameter name="data_master_high_performance_paddr_size" value="0" />
   <parameter name="data_master_paddr_base" value="0" />
   <parameter name="data_master_paddr_size" value="0" />
   <parameter name="dcache_bursts" value="false" />
-  <parameter name="dcache_numTCDM" value="0" />
+  <parameter name="dcache_numTCDM" value="1" />
   <parameter name="dcache_ramBlockType" value="Automatic" />
   <parameter name="dcache_size" value="32768" />
   <parameter name="dcache_tagramBlockType" value="Automatic" />
@@ -610,7 +738,7 @@
   <parameter name="debug_traceType" value="none" />
   <parameter name="debug_triggerArming" value="true" />
   <parameter name="deviceFamilyName" value="Arria V" />
-  <parameter name="deviceFeaturesSystemInfo">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
+  <parameter name="deviceFeaturesSystemInfo">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
   <parameter name="dividerType" value="no_div" />
   <parameter name="exceptionOffset" value="32" />
   <parameter name="exceptionSlave" value="sys_ddr3_cntrl.avl" />
@@ -621,27 +749,27 @@
   <parameter name="flash_instruction_master_paddr_base" value="0" />
   <parameter name="flash_instruction_master_paddr_size" value="0" />
   <parameter name="icache_burstType" value="None" />
-  <parameter name="icache_numTCIM" value="0" />
+  <parameter name="icache_numTCIM" value="1" />
   <parameter name="icache_ramBlockType" value="Automatic" />
   <parameter name="icache_size" value="32768" />
   <parameter name="icache_tagramBlockType" value="Automatic" />
   <parameter name="impl" value="Fast" />
-  <parameter name="instAddrWidth" value="30" />
-  <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='sys_ddr3_cntrl.avl' start='0x10000000' end='0x20000000' /><slave name='sys_int_mem.s1' start='0x21200000' end='0x21400000' /><slave name='sys_cpu.debug_mem_slave' start='0x21400800' end='0x21401000' /></address-map>]]></parameter>
+  <parameter name="instAddrWidth" value="29" />
+  <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='sys_ddr3_cntrl.avl' start='0x0' end='0x10000000' type='altera_mem_if_ddr3_emif.avl' /><slave name='sys_int_mem.s2' start='0x15000000' end='0x150C0000' type='altera_avalon_onchip_memory2.s2' /><slave name='sys_cpu.debug_mem_slave' start='0x1520D800' end='0x1520E000' type='altera_nios2_gen2.debug_mem_slave' /></address-map>]]></parameter>
   <parameter name="instructionMasterHighPerformanceAddrWidth" value="1" />
   <parameter name="instructionMasterHighPerformanceMapParam" value="" />
   <parameter name="instruction_master_high_performance_paddr_base" value="0" />
   <parameter name="instruction_master_high_performance_paddr_size" value="0" />
   <parameter name="instruction_master_paddr_base" value="0" />
   <parameter name="instruction_master_paddr_size" value="0" />
-  <parameter name="internalIrqMaskSystemInfo" value="32767" />
+  <parameter name="internalIrqMaskSystemInfo" value="65535" />
   <parameter name="io_regionbase" value="0" />
   <parameter name="io_regionsize" value="0" />
   <parameter name="master_addr_map" value="false" />
   <parameter name="mmu_TLBMissExcOffset" value="4096" />
-  <parameter name="mmu_TLBMissExcSlave" value="sys_ddr3_cntrl.avl" />
+  <parameter name="mmu_TLBMissExcSlave" value="sys_int_mem.s2" />
   <parameter name="mmu_autoAssignTlbPtrSz" value="false" />
-  <parameter name="mmu_enabled" value="false" />
+  <parameter name="mmu_enabled" value="true" />
   <parameter name="mmu_processIDNumBits" value="8" />
   <parameter name="mmu_ramBlockType" value="Automatic" />
   <parameter name="mmu_tlbNumWays" value="16" />
@@ -708,16 +836,16 @@
   <parameter name="setting_support31bitdcachebypass" value="true" />
   <parameter name="setting_usedesignware" value="false" />
   <parameter name="shift_rot_impl" value="0" />
-  <parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" />
-  <parameter name="tightlyCoupledDataMaster0MapParam" value="" />
+  <parameter name="tightlyCoupledDataMaster0AddrWidth" value="29" />
+  <parameter name="tightlyCoupledDataMaster0MapParam"><![CDATA[<address-map><slave name='sys_tcm_mem.s1' start='0x1520C000' end='0x1520D000' type='altera_avalon_onchip_memory2.s1' /></address-map>]]></parameter>
   <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
   <parameter name="tightlyCoupledDataMaster1MapParam" value="" />
   <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
   <parameter name="tightlyCoupledDataMaster2MapParam" value="" />
   <parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
   <parameter name="tightlyCoupledDataMaster3MapParam" value="" />
-  <parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="1" />
-  <parameter name="tightlyCoupledInstructionMaster0MapParam" value="" />
+  <parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="29" />
+  <parameter name="tightlyCoupledInstructionMaster0MapParam"><![CDATA[<address-map><slave name='sys_tcm_mem.s2' start='0x1520C000' end='0x1520D000' type='altera_avalon_onchip_memory2.s2' /></address-map>]]></parameter>
   <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
   <parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
   <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
@@ -747,11 +875,11 @@
  <module
    name="sys_cpu_interconnect"
    kind="altera_avalon_mm_bridge"
-   version="15.0"
+   version="15.1"
    enabled="1">
   <parameter name="ADDRESS_UNITS" value="SYMBOLS" />
   <parameter name="ADDRESS_WIDTH" value="24" />
-  <parameter name="AUTO_CLK_CLOCK_RATE" value="1000000000" />
+  <parameter name="AUTO_CLK_CLOCK_RATE" value="100000000" />
   <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
   <parameter name="DATA_WIDTH" value="32" />
   <parameter name="LINEWRAPBURSTS" value="0" />
@@ -767,7 +895,7 @@
  <module
    name="sys_ddr3_cntrl"
    kind="altera_mem_if_ddr3_emif"
-   version="15.0"
+   version="15.1"
    enabled="1">
   <parameter name="ABSTRACT_REAL_COMPARE_TEST" value="false" />
   <parameter name="ABS_RAM_MEM_INIT_FILENAME" value="meminit" />
@@ -1086,7 +1214,7 @@
   <parameter name="WEIGHT_PORT" value="0,0,0,0,0,0" />
   <parameter name="WRBUFFER_ADDR_WIDTH" value="6" />
  </module>
- <module name="sys_ethernet" kind="altera_eth_tse" version="15.0" enabled="1">
+ <module name="sys_ethernet" kind="altera_eth_tse" version="15.1" enabled="1">
   <parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" />
   <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
   <parameter name="core_variation" value="MAC_ONLY" />
@@ -1130,15 +1258,23 @@
  <module
    name="sys_ethernet_dma_rx"
    kind="altera_msgdma"
-   version="15.0"
+   version="15.1"
    enabled="1">
+  <parameter name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_MAP" value="" />
+  <parameter
+     name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_WIDTH"
+     value="AddressWidth = -1" />
+  <parameter name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_MAP" value="" />
+  <parameter
+     name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH"
+     value="AddressWidth = -1" />
   <parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" />
   <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
   <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
   <parameter name="AUTO_MM_READ_ADDRESS_MAP" value="" />
   <parameter name="AUTO_MM_READ_ADDRESS_WIDTH" value="AddressWidth = -1" />
-  <parameter name="AUTO_MM_WRITE_ADDRESS_MAP"><![CDATA[<address-map><slave name='sys_ddr3_cntrl.avl' start='0x10000000' end='0x20000000' /></address-map>]]></parameter>
-  <parameter name="AUTO_MM_WRITE_ADDRESS_WIDTH" value="AddressWidth = 29" />
+  <parameter name="AUTO_MM_WRITE_ADDRESS_MAP"><![CDATA[<address-map><slave name='sys_ddr3_cntrl.avl' start='0x0' end='0x10000000' /></address-map>]]></parameter>
+  <parameter name="AUTO_MM_WRITE_ADDRESS_WIDTH" value="AddressWidth = 28" />
   <parameter name="BURST_ENABLE" value="1" />
   <parameter name="BURST_WRAPPING_SUPPORT" value="0" />
   <parameter name="CHANNEL_ENABLE" value="0" />
@@ -1149,26 +1285,40 @@
   <parameter name="ENHANCED_FEATURES" value="1" />
   <parameter name="ERROR_ENABLE" value="1" />
   <parameter name="ERROR_WIDTH" value="6" />
+  <parameter name="FIX_ADDRESS_WIDTH" value="32" />
   <parameter name="MAX_BURST_COUNT" value="64" />
   <parameter name="MAX_BYTE" value="2048" />
   <parameter name="MAX_STRIDE" value="1" />
   <parameter name="MODE" value="2" />
   <parameter name="PACKET_ENABLE" value="1" />
+  <parameter name="PREFETCHER_DATA_WIDTH" value="32" />
+  <parameter name="PREFETCHER_ENABLE" value="0" />
+  <parameter name="PREFETCHER_MAX_READ_BURST_COUNT" value="2" />
+  <parameter name="PREFETCHER_READ_BURST_ENABLE" value="0" />
   <parameter name="PROGRAMMABLE_BURST_ENABLE" value="0" />
   <parameter name="RESPONSE_PORT" value="0" />
   <parameter name="STRIDE_ENABLE" value="0" />
   <parameter name="TRANSFER_TYPE" value="Unaligned Accesses" />
+  <parameter name="USE_FIX_ADDRESS_WIDTH" value="0" />
  </module>
  <module
    name="sys_ethernet_dma_tx"
    kind="altera_msgdma"
-   version="15.0"
+   version="15.1"
    enabled="1">
+  <parameter name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_MAP" value="" />
+  <parameter
+     name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_WIDTH"
+     value="AddressWidth = -1" />
+  <parameter name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_MAP" value="" />
+  <parameter
+     name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH"
+     value="AddressWidth = -1" />
   <parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" />
   <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
   <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
-  <parameter name="AUTO_MM_READ_ADDRESS_MAP"><![CDATA[<address-map><slave name='sys_ddr3_cntrl.avl' start='0x10000000' end='0x20000000' /></address-map>]]></parameter>
-  <parameter name="AUTO_MM_READ_ADDRESS_WIDTH" value="AddressWidth = 29" />
+  <parameter name="AUTO_MM_READ_ADDRESS_MAP"><![CDATA[<address-map><slave name='sys_ddr3_cntrl.avl' start='0x0' end='0x10000000' /></address-map>]]></parameter>
+  <parameter name="AUTO_MM_READ_ADDRESS_WIDTH" value="AddressWidth = 28" />
   <parameter name="AUTO_MM_WRITE_ADDRESS_MAP" value="" />
   <parameter name="AUTO_MM_WRITE_ADDRESS_WIDTH" value="AddressWidth = -1" />
   <parameter name="BURST_ENABLE" value="1" />
@@ -1181,21 +1331,27 @@
   <parameter name="ENHANCED_FEATURES" value="1" />
   <parameter name="ERROR_ENABLE" value="1" />
   <parameter name="ERROR_WIDTH" value="1" />
+  <parameter name="FIX_ADDRESS_WIDTH" value="32" />
   <parameter name="MAX_BURST_COUNT" value="64" />
   <parameter name="MAX_BYTE" value="2048" />
   <parameter name="MAX_STRIDE" value="1" />
   <parameter name="MODE" value="1" />
   <parameter name="PACKET_ENABLE" value="1" />
+  <parameter name="PREFETCHER_DATA_WIDTH" value="32" />
+  <parameter name="PREFETCHER_ENABLE" value="0" />
+  <parameter name="PREFETCHER_MAX_READ_BURST_COUNT" value="2" />
+  <parameter name="PREFETCHER_READ_BURST_ENABLE" value="0" />
   <parameter name="PROGRAMMABLE_BURST_ENABLE" value="0" />
   <parameter name="RESPONSE_PORT" value="2" />
   <parameter name="STRIDE_ENABLE" value="0" />
   <parameter name="TRANSFER_TYPE" value="Unaligned Accesses" />
+  <parameter name="USE_FIX_ADDRESS_WIDTH" value="0" />
  </module>
- <module name="sys_gpio" kind="altera_avalon_pio" version="15.0" enabled="1">
+ <module name="sys_gpio" kind="altera_avalon_pio" version="15.1" enabled="1">
   <parameter name="bitClearingEdgeCapReg" value="false" />
   <parameter name="bitModifyingOutReg" value="false" />
   <parameter name="captureEdge" value="false" />
-  <parameter name="clockRate" value="1000000000" />
+  <parameter name="clockRate" value="100000000" />
   <parameter name="direction" value="InOut" />
   <parameter name="edgeType" value="RISING" />
   <parameter name="generateIRQ" value="true" />
@@ -1208,12 +1364,12 @@
  <module
    name="sys_gpio_bd"
    kind="altera_avalon_pio"
-   version="15.0"
+   version="15.1"
    enabled="1">
   <parameter name="bitClearingEdgeCapReg" value="false" />
   <parameter name="bitModifyingOutReg" value="false" />
   <parameter name="captureEdge" value="false" />
-  <parameter name="clockRate" value="1000000000" />
+  <parameter name="clockRate" value="100000000" />
   <parameter name="direction" value="InOut" />
   <parameter name="edgeType" value="RISING" />
   <parameter name="generateIRQ" value="true" />
@@ -1226,7 +1382,7 @@
  <module
    name="sys_id"
    kind="altera_avalon_sysid_qsys"
-   version="15.0"
+   version="15.1"
    enabled="1">
   <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
   <parameter name="id" value="0" />
@@ -1234,7 +1390,7 @@
  <module
    name="sys_int_mem"
    kind="altera_avalon_onchip_memory2"
-   version="15.0"
+   version="15.1"
    enabled="1">
   <parameter name="allowInSystemMemoryContentEditor" value="false" />
   <parameter name="autoInitializationFileName">$${FILENAME}_sys_int_mem</parameter>
@@ -1242,13 +1398,13 @@
   <parameter name="copyInitFile" value="false" />
   <parameter name="dataWidth" value="32" />
   <parameter name="deviceFamily" value="Arria V" />
-  <parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
-  <parameter name="dualPort" value="false" />
+  <parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
+  <parameter name="dualPort" value="true" />
   <parameter name="ecc_enabled" value="false" />
   <parameter name="initMemContent" value="true" />
   <parameter name="initializationFileName" value="onchip_mem.hex" />
   <parameter name="instanceID" value="NONE" />
-  <parameter name="memorySize" value="2097152" />
+  <parameter name="memorySize" value="786432" />
   <parameter name="readDuringWriteMode" value="DONT_CARE" />
   <parameter name="resetrequest_enabled" value="true" />
   <parameter name="simAllowMRAMContentsFile" value="false" />
@@ -1260,8 +1416,8 @@
   <parameter name="useShallowMemBlocks" value="false" />
   <parameter name="writable" value="true" />
  </module>
- <module name="sys_intr" kind="altera_irq_bridge" version="15.0" enabled="1">
-  <parameter name="AUTO_CLK_CLOCK_RATE" value="1000000000" />
+ <module name="sys_intr" kind="altera_irq_bridge" version="15.1" enabled="1">
+  <parameter name="AUTO_CLK_CLOCK_RATE" value="100000000" />
   <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
   <parameter name="AUTO_RECEIVER_IRQ_INTERRUPTS_USED" value="0" />
   <parameter name="IRQ_N" value="0" />
@@ -1270,24 +1426,24 @@
  <module
    name="sys_mem_interconnect"
    kind="altera_avalon_mm_bridge"
-   version="15.0"
+   version="15.1"
    enabled="1">
   <parameter name="ADDRESS_UNITS" value="SYMBOLS" />
   <parameter name="ADDRESS_WIDTH" value="29" />
   <parameter name="AUTO_CLK_CLOCK_RATE" value="100000000" />
   <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
-  <parameter name="DATA_WIDTH" value="512" />
+  <parameter name="DATA_WIDTH" value="256" />
   <parameter name="LINEWRAPBURSTS" value="0" />
-  <parameter name="MAX_BURST_SIZE" value="1" />
+  <parameter name="MAX_BURST_SIZE" value="64" />
   <parameter name="MAX_PENDING_RESPONSES" value="4" />
   <parameter name="PIPELINE_COMMAND" value="1" />
   <parameter name="PIPELINE_RESPONSE" value="1" />
   <parameter name="SYMBOL_WIDTH" value="8" />
-  <parameter name="SYSINFO_ADDR_WIDTH" value="29" />
-  <parameter name="USE_AUTO_ADDRESS_WIDTH" value="0" />
+  <parameter name="SYSINFO_ADDR_WIDTH" value="28" />
+  <parameter name="USE_AUTO_ADDRESS_WIDTH" value="1" />
   <parameter name="USE_RESPONSE" value="0" />
  </module>
- <module name="sys_pll" kind="altera_pll" version="15.0" enabled="1">
+ <module name="sys_pll" kind="altera_pll" version="15.1" enabled="1">
   <parameter name="debug_print_output" value="false" />
   <parameter name="debug_use_rbc_taf_method" value="false" />
   <parameter name="device" value="5AGTFD7K3F40I3" />
@@ -1404,7 +1560,7 @@
   <parameter name="gui_fractional_cout" value="32" />
   <parameter name="gui_mif_generate" value="false" />
   <parameter name="gui_multiply_factor" value="1" />
-  <parameter name="gui_number_of_clocks" value="3" />
+  <parameter name="gui_number_of_clocks" value="4" />
   <parameter name="gui_operation_mode" value="direct" />
   <parameter name="gui_output_clock_frequency0" value="125.0" />
   <parameter name="gui_output_clock_frequency1" value="25.0" />
@@ -1490,20 +1646,20 @@
   <parameter name="gui_switchover_mode">Automatic Switchover</parameter>
   <parameter name="gui_use_locked" value="true" />
  </module>
- <module name="sys_rst" kind="altera_reset_bridge" version="15.0" enabled="1">
+ <module name="sys_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
   <parameter name="ACTIVE_LOW_RESET" value="0" />
-  <parameter name="AUTO_CLK_CLOCK_RATE" value="1000000000" />
+  <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
   <parameter name="NUM_RESET_OUTPUTS" value="1" />
-  <parameter name="SYNCHRONOUS_EDGES" value="deassert" />
+  <parameter name="SYNCHRONOUS_EDGES" value="none" />
   <parameter name="USE_RESET_REQUEST" value="0" />
  </module>
- <module name="sys_spi" kind="altera_avalon_spi" version="15.0" enabled="1">
+ <module name="sys_spi" kind="altera_avalon_spi" version="15.1" enabled="1">
   <parameter name="avalonSpec" value="2.0" />
   <parameter name="clockPhase" value="0" />
   <parameter name="clockPolarity" value="0" />
   <parameter name="dataWidth" value="8" />
   <parameter name="disableAvalonFlowControl" value="false" />
-  <parameter name="inputClockRate" value="1000000000" />
+  <parameter name="inputClockRate" value="100000000" />
   <parameter name="insertDelayBetweenSlaveSelectAndSClk" value="false" />
   <parameter name="insertSync" value="false" />
   <parameter name="lsbOrderedFirst" value="false" />
@@ -1513,10 +1669,39 @@
   <parameter name="targetClockRate" value="128000" />
   <parameter name="targetSlaveSelectToSClkDelay" value="0.0" />
  </module>
+ <module
+   name="sys_tcm_mem"
+   kind="altera_avalon_onchip_memory2"
+   version="15.1"
+   enabled="1">
+  <parameter name="allowInSystemMemoryContentEditor" value="false" />
+  <parameter name="autoInitializationFileName">$${FILENAME}_sys_tcm_mem</parameter>
+  <parameter name="blockType" value="AUTO" />
+  <parameter name="copyInitFile" value="false" />
+  <parameter name="dataWidth" value="32" />
+  <parameter name="deviceFamily" value="Arria V" />
+  <parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
+  <parameter name="dualPort" value="true" />
+  <parameter name="ecc_enabled" value="false" />
+  <parameter name="initMemContent" value="true" />
+  <parameter name="initializationFileName" value="onchip_mem.hex" />
+  <parameter name="instanceID" value="NONE" />
+  <parameter name="memorySize" value="4096" />
+  <parameter name="readDuringWriteMode" value="DONT_CARE" />
+  <parameter name="resetrequest_enabled" value="true" />
+  <parameter name="simAllowMRAMContentsFile" value="false" />
+  <parameter name="simMemInitOnlyFilename" value="0" />
+  <parameter name="singleClockOperation" value="false" />
+  <parameter name="slave1Latency" value="1" />
+  <parameter name="slave2Latency" value="1" />
+  <parameter name="useNonDefaultInitFile" value="false" />
+  <parameter name="useShallowMemBlocks" value="false" />
+  <parameter name="writable" value="true" />
+ </module>
  <module
    name="sys_timer"
    kind="altera_avalon_timer"
-   version="15.0"
+   version="15.1"
    enabled="1">
   <parameter name="alwaysRun" value="false" />
   <parameter name="counterSize" value="32" />
@@ -1525,18 +1710,34 @@
   <parameter name="periodUnits" value="MSEC" />
   <parameter name="resetOutput" value="false" />
   <parameter name="snapshot" value="true" />
-  <parameter name="systemFrequency" value="1000000000" />
+  <parameter name="systemFrequency" value="100000000" />
+  <parameter name="timeoutPulseOutput" value="false" />
+  <parameter name="watchdogPulse" value="2" />
+ </module>
+ <module
+   name="sys_timer_2nd"
+   kind="altera_avalon_timer"
+   version="15.1"
+   enabled="1">
+  <parameter name="alwaysRun" value="false" />
+  <parameter name="counterSize" value="32" />
+  <parameter name="fixedPeriod" value="false" />
+  <parameter name="period" value="1" />
+  <parameter name="periodUnits" value="MSEC" />
+  <parameter name="resetOutput" value="false" />
+  <parameter name="snapshot" value="true" />
+  <parameter name="systemFrequency" value="100000000" />
   <parameter name="timeoutPulseOutput" value="false" />
   <parameter name="watchdogPulse" value="2" />
  </module>
  <module
    name="sys_uart"
    kind="altera_avalon_jtag_uart"
-   version="15.0"
+   version="15.1"
    enabled="1">
   <parameter name="allowMultipleConnections" value="false" />
   <parameter name="avalonSpec" value="2.0" />
-  <parameter name="clkFreq" value="1000000000" />
+  <parameter name="clkFreq" value="100000000" />
   <parameter name="hubInstanceID" value="0" />
   <parameter name="readBufferDepth" value="64" />
   <parameter name="readIRQThreshold" value="8" />
@@ -1550,97 +1751,97 @@
  </module>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.data_master"
    end="sys_uart.avalon_jtag_slave">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x214014f0" />
+  <parameter name="baseAddress" value="0x1520e4e0" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.data_master"
    end="sys_ddr3_cntrl.avl">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10000000" />
+  <parameter name="baseAddress" value="0x0000" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.data_master"
    end="sys_ethernet.control_port">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x21401000" />
+  <parameter name="baseAddress" value="0x1520e000" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.data_master"
    end="sys_id.control_slave">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x214014e8" />
+  <parameter name="baseAddress" value="0x1520e4d8" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.data_master"
    end="sys_ethernet_dma_tx.csr">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x214014a0" />
+  <parameter name="baseAddress" value="0x1520e400" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.data_master"
    end="sys_ethernet_dma_rx.csr">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x21401480" />
+  <parameter name="baseAddress" value="0x1520e440" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.data_master"
    end="sys_cpu.debug_mem_slave">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x21400800" />
+  <parameter name="baseAddress" value="0x1520d800" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.data_master"
    end="sys_ethernet_dma_rx.descriptor_slave">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x21401460" />
+  <parameter name="baseAddress" value="0x1520e460" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.data_master"
    end="sys_ethernet_dma_tx.descriptor_slave">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x21401440" />
+  <parameter name="baseAddress" value="0x1520e420" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.data_master"
    end="sys_ethernet_dma_rx.response">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x214014e0" />
+  <parameter name="baseAddress" value="0x1520e480" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.data_master"
    end="sys_cpu_interconnect.s0">
   <parameter name="arbitrationPriority" value="1" />
@@ -1649,391 +1850,474 @@
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.data_master"
    end="sys_int_mem.s1">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x21200000" />
+  <parameter name="baseAddress" value="0x15000000" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.data_master"
    end="sys_gpio.s1">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x214014d0" />
+  <parameter name="baseAddress" value="0x1520e4c0" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.data_master"
    end="sys_timer.s1">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x21401420" />
+  <parameter name="baseAddress" value="0x1520e4a0" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.data_master"
    end="sys_gpio_bd.s1">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x214014c0" />
+  <parameter name="baseAddress" value="0x1520e520" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
+   start="sys_cpu.data_master"
+   end="sys_timer_2nd.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x1520e540" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
    start="sys_cpu.data_master"
    end="sys_spi.spi_control_port">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x21401400" />
+  <parameter name="baseAddress" value="0x1520e500" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.instruction_master"
    end="sys_ddr3_cntrl.avl">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10000000" />
+  <parameter name="baseAddress" value="0x0000" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.instruction_master"
    end="sys_cpu.debug_mem_slave">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x21400800" />
+  <parameter name="baseAddress" value="0x1520d800" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.instruction_master"
-   end="sys_int_mem.s1">
+   end="sys_int_mem.s2">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x21200000" />
+  <parameter name="baseAddress" value="0x15000000" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="sys_mem_interconnect.m0"
    end="sys_ddr3_cntrl.avl">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10000000" />
+  <parameter name="baseAddress" value="0x0000" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="sys_ethernet_dma_tx.mm_read"
    end="sys_ddr3_cntrl.avl">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10000000" />
+  <parameter name="baseAddress" value="0x0000" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="sys_ethernet_dma_rx.mm_write"
    end="sys_ddr3_cntrl.avl">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x10000000" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="sys_cpu.tightly_coupled_data_master_0"
+   end="sys_tcm_mem.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x1520c000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="sys_cpu.tightly_coupled_instruction_master_0"
+   end="sys_tcm_mem.s2">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x1520c000" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
    kind="avalon_streaming"
-   version="15.0"
+   version="15.1"
    start="sys_ethernet.receive"
    end="sys_ethernet_dma_rx.st_sink" />
  <connection
    kind="avalon_streaming"
-   version="15.0"
+   version="15.1"
    start="sys_ethernet_dma_tx.st_source"
    end="sys_ethernet.transmit" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_ddr3_cntrl.afi_clk"
    end="sys_mem_interconnect.clk" />
  <connection
    kind="clock"
-   version="15.0"
-   start="sys_ddr3_cntrl.afi_clk"
-   end="mem_rst.clk" />
- <connection
-   kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_ddr3_cntrl.afi_clk"
    end="mem_clk.in_clk" />
- <connection kind="clock" version="15.0" start="sys_clk.out_clk" end="sys_rst.clk" />
- <connection kind="clock" version="15.0" start="sys_clk.out_clk" end="sys_cpu.clk" />
  <connection
    kind="clock"
-   version="15.0"
-   start="sys_clk.out_clk"
-   end="sys_uart.clk" />
- <connection
-   kind="clock"
-   version="15.0"
-   start="sys_clk.out_clk"
-   end="sys_timer.clk" />
- <connection kind="clock" version="15.0" start="sys_clk.out_clk" end="sys_id.clk" />
- <connection
-   kind="clock"
-   version="15.0"
-   start="sys_clk.out_clk"
-   end="sys_gpio_bd.clk" />
- <connection
-   kind="clock"
-   version="15.0"
-   start="sys_clk.out_clk"
-   end="sys_gpio.clk" />
- <connection kind="clock" version="15.0" start="sys_clk.out_clk" end="sys_spi.clk" />
- <connection
-   kind="clock"
-   version="15.0"
-   start="sys_clk.out_clk"
-   end="sys_cpu_interconnect.clk" />
- <connection
-   kind="clock"
-   version="15.0"
-   start="sys_clk.out_clk"
-   end="sys_intr.clk" />
- <connection
-   kind="clock"
-   version="15.0"
-   start="sys_clk.out_clk"
-   end="sys_int_mem.clk1" />
- <connection
-   kind="clock"
-   version="15.0"
-   start="sys_clk.out_clk"
-   end="sys_ethernet_dma_rx.clock" />
- <connection
-   kind="clock"
-   version="15.0"
-   start="sys_clk.out_clk"
-   end="sys_ethernet_dma_tx.clock" />
- <connection
-   kind="clock"
-   version="15.0"
-   start="sys_clk.out_clk"
-   end="sys_ethernet.control_port_clock_connection" />
- <connection
-   kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
    end="sys_ddr3_cntrl.pll_ref_clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
+   end="sys_pll.refclk" />
+ <connection kind="clock" version="15.1" start="sys_pll.outclk3" end="sys_cpu.clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_pll.outclk3"
+   end="sys_timer.clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_pll.outclk3"
+   end="sys_timer_2nd.clk" />
+ <connection kind="clock" version="15.1" start="sys_pll.outclk3" end="sys_id.clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_pll.outclk3"
+   end="sys_gpio.clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_pll.outclk3"
+   end="sys_gpio_bd.clk" />
+ <connection kind="clock" version="15.1" start="sys_pll.outclk3" end="sys_spi.clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_pll.outclk3"
+   end="sys_cpu_interconnect.clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_pll.outclk3"
+   end="sys_uart.clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_pll.outclk3"
+   end="sys_intr.clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_pll.outclk3"
+   end="sys_int_mem.clk1" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_pll.outclk3"
+   end="sys_tcm_mem.clk1" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_pll.outclk3"
+   end="sys_int_mem.clk2" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_pll.outclk3"
+   end="sys_tcm_mem.clk2" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_pll.outclk3"
+   end="sys_ethernet_dma_rx.clock" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_pll.outclk3"
+   end="sys_ethernet_dma_tx.clock" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_pll.outclk3"
+   end="sys_ethernet.control_port_clock_connection" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_pll.outclk3"
+   end="cpu_clk.in_clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_pll.outclk3"
    end="sys_ethernet.receive_clock_connection" />
  <connection
    kind="clock"
-   version="15.0"
-   start="sys_clk.out_clk"
-   end="sys_pll.refclk" />
- <connection
-   kind="clock"
-   version="15.0"
-   start="sys_clk.out_clk"
+   version="15.1"
+   start="sys_pll.outclk3"
    end="sys_ethernet.transmit_clock_connection" />
  <connection
    kind="interrupt"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.irq"
    end="sys_ethernet_dma_rx.csr_irq">
-  <parameter name="irqNumber" value="0" />
+  <parameter name="irqNumber" value="3" />
  </connection>
  <connection
    kind="interrupt"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.irq"
    end="sys_ethernet_dma_tx.csr_irq">
   <parameter name="irqNumber" value="1" />
  </connection>
  <connection
    kind="interrupt"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.irq"
    end="sys_uart.irq">
-  <parameter name="irqNumber" value="4" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.0"
-   start="sys_cpu.irq"
-   end="sys_timer.irq">
-  <parameter name="irqNumber" value="5" />
- </connection>
- <connection kind="interrupt" version="15.0" start="sys_cpu.irq" end="sys_spi.irq">
-  <parameter name="irqNumber" value="6" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.0"
-   start="sys_cpu.irq"
-   end="sys_gpio.irq">
-  <parameter name="irqNumber" value="7" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.0"
-   start="sys_cpu.irq"
-   end="sys_gpio_bd.irq">
-  <parameter name="irqNumber" value="8" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.0"
-   start="sys_cpu.irq"
-   end="sys_intr.sender0_irq">
   <parameter name="irqNumber" value="2" />
  </connection>
  <connection
    kind="interrupt"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.irq"
-   end="sys_intr.sender1_irq">
-  <parameter name="irqNumber" value="3" />
+   end="sys_timer.irq">
+  <parameter name="irqNumber" value="0" />
+ </connection>
+ <connection kind="interrupt" version="15.1" start="sys_cpu.irq" end="sys_spi.irq">
+  <parameter name="irqNumber" value="4" />
  </connection>
  <connection
    kind="interrupt"
-   version="15.0"
+   version="15.1"
+   start="sys_cpu.irq"
+   end="sys_gpio.irq">
+  <parameter name="irqNumber" value="6" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="15.1"
+   start="sys_cpu.irq"
+   end="sys_gpio_bd.irq">
+  <parameter name="irqNumber" value="5" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="15.1"
+   start="sys_cpu.irq"
+   end="sys_timer_2nd.irq">
+  <parameter name="irqNumber" value="7" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="15.1"
+   start="sys_cpu.irq"
+   end="sys_intr.sender0_irq">
+  <parameter name="irqNumber" value="15" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="15.1"
+   start="sys_cpu.irq"
+   end="sys_intr.sender1_irq">
+  <parameter name="irqNumber" value="8" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="15.1"
    start="sys_cpu.irq"
    end="sys_intr.sender2_irq">
   <parameter name="irqNumber" value="9" />
  </connection>
  <connection
    kind="interrupt"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.irq"
    end="sys_intr.sender3_irq">
   <parameter name="irqNumber" value="10" />
  </connection>
  <connection
    kind="interrupt"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.irq"
    end="sys_intr.sender4_irq">
   <parameter name="irqNumber" value="11" />
  </connection>
  <connection
    kind="interrupt"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.irq"
    end="sys_intr.sender5_irq">
   <parameter name="irqNumber" value="12" />
  </connection>
  <connection
    kind="interrupt"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.irq"
    end="sys_intr.sender6_irq">
   <parameter name="irqNumber" value="13" />
  </connection>
  <connection
    kind="interrupt"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.irq"
    end="sys_intr.sender7_irq">
   <parameter name="irqNumber" value="14" />
  </connection>
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_ddr3_cntrl.afi_reset"
    end="mem_rst.in_reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_ddr3_cntrl.afi_reset"
    end="sys_mem_interconnect.reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
+   start="sys_cpu.debug_reset_request"
+   end="sys_cpu.reset" />
+ <connection
+   kind="reset"
+   version="15.1"
    start="sys_rst.out_reset"
    end="sys_intr.clk_reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="sys_ddr3_cntrl.global_reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="cpu_reset.in_reset" />
+ <connection
+   kind="reset"
+   version="15.1"
    start="sys_rst.out_reset"
    end="sys_pll.reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="sys_cpu.reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="sys_uart.reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="sys_timer.reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="sys_id.reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="sys_gpio_bd.reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="sys_gpio.reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="sys_spi.reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="sys_cpu_interconnect.reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="sys_timer_2nd.reset" />
+ <connection
+   kind="reset"
+   version="15.1"
    start="sys_rst.out_reset"
    end="sys_int_mem.reset1" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="sys_tcm_mem.reset1" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="sys_int_mem.reset2" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="sys_tcm_mem.reset2" />
+ <connection
+   kind="reset"
+   version="15.1"
    start="sys_rst.out_reset"
    end="sys_ethernet.reset_connection" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="sys_ethernet_dma_rx.reset_n" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="sys_ethernet_dma_tx.reset_n" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="sys_ddr3_cntrl.soft_reset" />
  <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
diff --git a/projects/fmcjesdadc1/a5gt/system_bd.qsys b/projects/fmcjesdadc1/a5gt/system_bd.qsys
index fa7810f69..482a3db95 100644
--- a/projects/fmcjesdadc1/a5gt/system_bd.qsys
+++ b/projects/fmcjesdadc1/a5gt/system_bd.qsys
@@ -9,14 +9,6 @@
    categories="System" />
  <parameter name="bonusData"><![CDATA[bonusData 
 {
-   element $${FILENAME}
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria V";
-         type = "String";
-      }
-   }
    element a5gt_base
    {
       datum _sortIndex
@@ -73,6 +65,14 @@
          type = "String";
       }
    }
+   element fmcjesdadc1.axi_jesd204_rx_avs
+   {
+      datum baseAddress
+      {
+         value = "262144";
+         type = "String";
+      }
+   }
    element fmcjesdadc1.axi_jesd_xcvr_s_axi
    {
       datum baseAddress
@@ -169,6 +169,22 @@
          type = "String";
       }
    }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria V";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria V";
+         type = "String";
+      }
+   }
 }
 ]]></parameter>
  <parameter name="clockCrossingAdapter" value="FIFO" />
@@ -308,26 +324,26 @@
   <parameter name="AUTO_UNIQUE_ID">$${FILENAME}_a5gt_base</parameter>
  </module>
  <module name="fmcjesdadc1" kind="fmcjesdadc1_bd" version="1.0" enabled="1">
-  <parameter name="AUTO_AXI_DMAC_0_M_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a5gt_base_sys_ddr3_cntrl.avl' start='0x10000000' end='0x20000000' /></address-map>]]></parameter>
-  <parameter name="AUTO_AXI_DMAC_0_M_AXI_ADDRESS_WIDTH" value="AddressWidth = 29" />
-  <parameter name="AUTO_AXI_DMAC_1_M_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a5gt_base_sys_ddr3_cntrl.avl' start='0x10000000' end='0x20000000' /></address-map>]]></parameter>
-  <parameter name="AUTO_AXI_DMAC_1_M_AXI_ADDRESS_WIDTH" value="AddressWidth = 29" />
+  <parameter name="AUTO_AXI_DMAC_0_M_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a5gt_base_sys_ddr3_cntrl.avl' start='0x0' end='0x10000000' /></address-map>]]></parameter>
+  <parameter name="AUTO_AXI_DMAC_0_M_AXI_ADDRESS_WIDTH" value="AddressWidth = 28" />
+  <parameter name="AUTO_AXI_DMAC_1_M_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a5gt_base_sys_ddr3_cntrl.avl' start='0x0' end='0x10000000' /></address-map>]]></parameter>
+  <parameter name="AUTO_AXI_DMAC_1_M_AXI_ADDRESS_WIDTH" value="AddressWidth = 28" />
+  <parameter name="AUTO_CPU_CLK_CLOCK_DOMAIN" value="9" />
+  <parameter name="AUTO_CPU_CLK_CLOCK_RATE" value="100000000" />
+  <parameter name="AUTO_CPU_CLK_RESET_DOMAIN" value="9" />
   <parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" />
   <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
   <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
   <parameter name="AUTO_GENERATION_ID" value="0" />
-  <parameter name="AUTO_MEM_CLK_CLOCK_DOMAIN" value="9" />
+  <parameter name="AUTO_MEM_CLK_CLOCK_DOMAIN" value="10" />
   <parameter name="AUTO_MEM_CLK_CLOCK_RATE" value="100000000" />
-  <parameter name="AUTO_MEM_CLK_RESET_DOMAIN" value="9" />
+  <parameter name="AUTO_MEM_CLK_RESET_DOMAIN" value="10" />
   <parameter name="AUTO_RX_REF_CLK_CLOCK_DOMAIN" value="6" />
   <parameter name="AUTO_RX_REF_CLK_CLOCK_RATE" value="0" />
   <parameter name="AUTO_RX_REF_CLK_RESET_DOMAIN" value="6" />
-  <parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="7" />
-  <parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="100000000" />
-  <parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="7" />
   <parameter name="AUTO_UNIQUE_ID">$${FILENAME}_fmcjesdadc1</parameter>
  </module>
- <module name="sys_clk" kind="clock_source" version="15.0" enabled="1">
+ <module name="sys_clk" kind="clock_source" version="15.1" enabled="1">
   <parameter name="clockFrequency" value="100000000" />
   <parameter name="clockFrequencyKnown" value="true" />
   <parameter name="inputClockFrequency" value="0" />
@@ -335,7 +351,7 @@
  </module>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="fmcjesdadc1.axi_dmac_0_m_axi"
    end="a5gt_base.sys_mem_interconnect_s0">
   <parameter name="arbitrationPriority" value="1" />
@@ -344,7 +360,7 @@
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="fmcjesdadc1.axi_dmac_1_m_axi"
    end="a5gt_base.sys_mem_interconnect_s0">
   <parameter name="arbitrationPriority" value="1" />
@@ -353,7 +369,7 @@
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="a5gt_base.sys_cpu_interconnect_m0"
    end="fmcjesdadc1.axi_ad9250_0_s_axi">
   <parameter name="arbitrationPriority" value="1" />
@@ -362,7 +378,7 @@
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="a5gt_base.sys_cpu_interconnect_m0"
    end="fmcjesdadc1.axi_ad9250_1_s_axi">
   <parameter name="arbitrationPriority" value="1" />
@@ -371,7 +387,7 @@
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="a5gt_base.sys_cpu_interconnect_m0"
    end="fmcjesdadc1.axi_dmac_0_s_axi">
   <parameter name="arbitrationPriority" value="1" />
@@ -380,7 +396,7 @@
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="a5gt_base.sys_cpu_interconnect_m0"
    end="fmcjesdadc1.axi_dmac_1_s_axi">
   <parameter name="arbitrationPriority" value="1" />
@@ -389,7 +405,7 @@
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="a5gt_base.sys_cpu_interconnect_m0"
    end="fmcjesdadc1.axi_jesd_xcvr_s_axi">
   <parameter name="arbitrationPriority" value="1" />
@@ -398,46 +414,46 @@
  </connection>
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.clk"
    end="a5gt_base.sys_clk" />
  <connection
    kind="clock"
-   version="15.0"
-   start="sys_clk.clk"
-   end="fmcjesdadc1.sys_clk" />
+   version="15.1"
+   start="a5gt_base.cpu_clk"
+   end="fmcjesdadc1.cpu_clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="a5gt_base.mem_clk"
    end="fmcjesdadc1.mem_clk" />
  <connection
    kind="interrupt"
-   version="15.0"
+   version="15.1"
    start="a5gt_base.sys_intr"
    end="fmcjesdadc1.axi_dmac_0_intr">
   <parameter name="irqNumber" value="1" />
  </connection>
  <connection
    kind="interrupt"
-   version="15.0"
+   version="15.1"
    start="a5gt_base.sys_intr"
    end="fmcjesdadc1.axi_dmac_1_intr">
   <parameter name="irqNumber" value="0" />
  </connection>
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_clk.clk_reset"
    end="a5gt_base.sys_rst" />
  <connection
    kind="reset"
-   version="15.0"
-   start="sys_clk.clk_reset"
-   end="fmcjesdadc1.sys_rst" />
+   version="15.1"
+   start="a5gt_base.cpu_rst"
+   end="fmcjesdadc1.cpu_rst" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="a5gt_base.mem_rst"
    end="fmcjesdadc1.mem_rst" />
  <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
diff --git a/projects/fmcjesdadc1/a5gt/system_constr.sdc b/projects/fmcjesdadc1/a5gt/system_constr.sdc
index 9a557c5e2..ce12d1393 100644
--- a/projects/fmcjesdadc1/a5gt/system_constr.sdc
+++ b/projects/fmcjesdadc1/a5gt/system_constr.sdc
@@ -9,6 +9,9 @@ derive_clock_uncertainty
 set_clock_groups -exclusive \
   -group [get_clocks {i_system_bd|a5gt_base|sys_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \
   -group [get_clocks {i_system_bd|a5gt_base|sys_pll|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] \
-  -group [get_clocks {i_system_bd|a5gt_base|sys_pll|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] \
-
+  -group [get_clocks {i_system_bd|a5gt_base|sys_pll|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}]
 
+set_clock_groups -asynchronous \
+  -group {ref_clk_250mhz} \
+  -group [get_clocks {i_system_bd|fmcjesdadc1|xcvr_rx_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \
+  -group [get_clocks {i_system_bd|a5gt_base|sys_pll|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}]
diff --git a/projects/fmcjesdadc1/a5gt/system_project.tcl b/projects/fmcjesdadc1/a5gt/system_project.tcl
index 041cc6132..d554fce31 100755
--- a/projects/fmcjesdadc1/a5gt/system_project.tcl
+++ b/projects/fmcjesdadc1/a5gt/system_project.tcl
@@ -5,8 +5,8 @@ source ../../scripts/adi_env.tcl
 project_new fmcjesdadc1_a5gt -overwrite
 
 source "../../common/a5gt/a5gt_system_assign.tcl"
-set_global_assignment -name IP_SEARCH_PATHS "../common/;../../common/a5gt;../../../library/**/*"
-set_user_option -name USER_IP_SEARCH_PATHS "../common/;../../common/a5gt/;../../../library/**/*"
+set_global_assignment -name IP_SEARCH_PATHS "../common/;../../common/**/*;../../../library/**/*"
+set_user_option -name USER_IP_SEARCH_PATHS "../common/;../../common/**/*;../../../library/**/*"
 set_global_assignment -name QSYS_FILE system_bd.qsys
 
 set_global_assignment -name VERILOG_FILE "../../../library/common/ad_iobuf.v"
diff --git a/projects/fmcjesdadc1/common/fmcjesdadc1_bd.qsys b/projects/fmcjesdadc1/common/fmcjesdadc1_bd.qsys
index 28591481d..c3abb1886 100644
--- a/projects/fmcjesdadc1/common/fmcjesdadc1_bd.qsys
+++ b/projects/fmcjesdadc1/common/fmcjesdadc1_bd.qsys
@@ -9,14 +9,6 @@
    categories="System" />
  <parameter name="bonusData"><![CDATA[bonusData 
 {
-   element $${FILENAME}
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria V";
-         type = "String";
-      }
-   }
    element axi_ad9250_0
    {
       datum _sortIndex
@@ -434,11 +426,18 @@
    internal="axi_dmac_1.s_axi"
    type="axi4lite"
    dir="end" />
+ <interface
+   name="axi_jesd204_rx_avs"
+   internal="xcvr_core.jesd204_rx_avs"
+   type="avalon"
+   dir="end" />
  <interface
    name="axi_jesd_xcvr_s_axi"
    internal="axi_jesd_xcvr.s_axi"
    type="axi4lite"
    dir="end" />
+ <interface name="cpu_clk" internal="sys_clk.in_clk" type="clock" dir="end" />
+ <interface name="cpu_rst" internal="sys_rst.in_reset" type="reset" dir="end" />
  <interface name="mem_clk" internal="mem_clk.in_clk" type="clock" dir="end" />
  <interface name="mem_rst" internal="mem_rst.in_reset" type="reset" dir="end" />
  <interface
@@ -457,8 +456,6 @@
    internal="axi_jesd_xcvr.if_rx_ext_sysref_out"
    type="conduit"
    dir="end" />
- <interface name="sys_clk" internal="sys_clk.in_clk" type="clock" dir="end" />
- <interface name="sys_rst" internal="sys_rst.in_reset" type="reset" dir="end" />
  <interface name="tx_ref_clk" internal="axi_jesd_xcvr.if_tx_ref_clk" />
  <module name="axi_ad9250_0" kind="axi_ad9250" version="1.0" enabled="1">
   <parameter name="DEVICE_TYPE" value="0" />
@@ -474,14 +471,14 @@
   <parameter name="ASYNC_CLK_SRC_DEST" value="1" />
   <parameter name="AXI_SLICE_DEST" value="0" />
   <parameter name="AXI_SLICE_SRC" value="0" />
-  <parameter name="CYCLIC" value="1" />
-  <parameter name="DMA_2D_TRANSFER" value="1" />
-  <parameter name="DMA_DATA_WIDTH_DEST" value="64" />
+  <parameter name="CYCLIC" value="0" />
+  <parameter name="DMA_2D_TRANSFER" value="0" />
+  <parameter name="DMA_DATA_WIDTH_DEST" value="256" />
   <parameter name="DMA_DATA_WIDTH_SRC" value="64" />
-  <parameter name="DMA_LENGTH_WIDTH" value="14" />
+  <parameter name="DMA_LENGTH_WIDTH" value="24" />
   <parameter name="DMA_TYPE_DEST" value="0" />
   <parameter name="DMA_TYPE_SRC" value="2" />
-  <parameter name="FIFO_SIZE" value="4" />
+  <parameter name="FIFO_SIZE" value="64" />
   <parameter name="ID" value="0" />
   <parameter name="SYNC_TRANSFER_START" value="0" />
  </module>
@@ -491,14 +488,14 @@
   <parameter name="ASYNC_CLK_SRC_DEST" value="1" />
   <parameter name="AXI_SLICE_DEST" value="0" />
   <parameter name="AXI_SLICE_SRC" value="0" />
-  <parameter name="CYCLIC" value="1" />
-  <parameter name="DMA_2D_TRANSFER" value="1" />
-  <parameter name="DMA_DATA_WIDTH_DEST" value="64" />
+  <parameter name="CYCLIC" value="0" />
+  <parameter name="DMA_2D_TRANSFER" value="0" />
+  <parameter name="DMA_DATA_WIDTH_DEST" value="256" />
   <parameter name="DMA_DATA_WIDTH_SRC" value="64" />
-  <parameter name="DMA_LENGTH_WIDTH" value="14" />
+  <parameter name="DMA_LENGTH_WIDTH" value="24" />
   <parameter name="DMA_TYPE_DEST" value="0" />
   <parameter name="DMA_TYPE_SRC" value="2" />
-  <parameter name="FIFO_SIZE" value="4" />
+  <parameter name="FIFO_SIZE" value="64" />
   <parameter name="ID" value="0" />
   <parameter name="SYNC_TRANSFER_START" value="0" />
  </module>
@@ -508,37 +505,37 @@
   <parameter name="RX_NUM_OF_LANES" value="4" />
   <parameter name="TX_NUM_OF_LANES" value="4" />
  </module>
- <module name="mem_clk" kind="altera_clock_bridge" version="15.0" enabled="1">
+ <module name="mem_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
   <parameter name="DERIVED_CLOCK_RATE" value="0" />
   <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
   <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
  </module>
- <module name="mem_rst" kind="altera_reset_bridge" version="15.0" enabled="1">
+ <module name="mem_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
   <parameter name="ACTIVE_LOW_RESET" value="0" />
-  <parameter name="AUTO_CLK_CLOCK_RATE" value="0" />
+  <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
   <parameter name="NUM_RESET_OUTPUTS" value="1" />
-  <parameter name="SYNCHRONOUS_EDGES" value="deassert" />
+  <parameter name="SYNCHRONOUS_EDGES" value="none" />
   <parameter name="USE_RESET_REQUEST" value="0" />
  </module>
  <module
    name="rx_ref_clk"
    kind="altera_clock_bridge"
-   version="15.0"
+   version="15.1"
    enabled="1">
   <parameter name="DERIVED_CLOCK_RATE" value="0" />
   <parameter name="EXPLICIT_CLOCK_RATE" value="250000000" />
   <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
  </module>
- <module name="sys_clk" kind="altera_clock_bridge" version="15.0" enabled="1">
+ <module name="sys_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
   <parameter name="DERIVED_CLOCK_RATE" value="0" />
   <parameter name="EXPLICIT_CLOCK_RATE" value="100000000" />
   <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
  </module>
- <module name="sys_rst" kind="altera_reset_bridge" version="15.0" enabled="1">
+ <module name="sys_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
   <parameter name="ACTIVE_LOW_RESET" value="0" />
-  <parameter name="AUTO_CLK_CLOCK_RATE" value="100000000" />
+  <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
   <parameter name="NUM_RESET_OUTPUTS" value="1" />
-  <parameter name="SYNCHRONOUS_EDGES" value="deassert" />
+  <parameter name="SYNCHRONOUS_EDGES" value="none" />
   <parameter name="USE_RESET_REQUEST" value="0" />
  </module>
  <module name="util_bsplit" kind="util_bsplit" version="1.0" enabled="1">
@@ -553,7 +550,7 @@
   <parameter name="CHANNEL_DATA_WIDTH" value="32" />
   <parameter name="NUM_OF_CHANNELS" value="2" />
  </module>
- <module name="xcvr_core" kind="altera_jesd204" version="15.0" enabled="1">
+ <module name="xcvr_core" kind="altera_jesd204" version="15.1" enabled="1">
   <parameter name="ADJCNT" value="0" />
   <parameter name="ADJDIR" value="0" />
   <parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" />
@@ -566,6 +563,13 @@
   <parameter name="DID" value="0" />
   <parameter name="DLB_TEST" value="0" />
   <parameter name="ECC_EN" value="0" />
+  <parameter name="ED_DEV_KIT" value="NONE" />
+  <parameter name="ED_FILESET_SIM" value="false" />
+  <parameter name="ED_FILESET_SYNTH" value="false" />
+  <parameter name="ED_GENERIC_5SERIES" value="No" />
+  <parameter name="ED_GENERIC_A10" value="No" />
+  <parameter name="ED_HDL_FORMAT_SIM" value="VERILOG" />
+  <parameter name="ED_HDL_FORMAT_SYNTH" value="VERILOG" />
   <parameter name="GUI_CFG_F" value="4" />
   <parameter name="GUI_EN_CFG_F" value="false" />
   <parameter name="HD" value="0" />
@@ -612,13 +616,13 @@
  <module
    name="xcvr_rst_cntrl"
    kind="altera_xcvr_reset_control"
-   version="15.0"
+   version="15.1"
    enabled="1">
   <parameter name="CHANNELS" value="4" />
   <parameter name="PLLS" value="1" />
   <parameter name="REDUCED_SIM_TIME" value="1" />
   <parameter name="RX_ENABLE" value="1" />
-  <parameter name="RX_PER_CHANNEL" value="0" />
+  <parameter name="RX_PER_CHANNEL" value="1" />
   <parameter name="SYNCHRONIZE_PLL_RESET" value="0" />
   <parameter name="SYNCHRONIZE_RESET" value="1" />
   <parameter name="SYS_CLK_IN_MHZ" value="100" />
@@ -627,8 +631,9 @@
   <parameter name="TX_PLL_ENABLE" value="0" />
   <parameter name="T_PLL_LOCK_HYST" value="0" />
   <parameter name="T_PLL_POWERDOWN" value="1000" />
-  <parameter name="T_RX_ANALOGRESET" value="40" />
-  <parameter name="T_RX_DIGITALRESET" value="4000" />
+  <parameter name="T_RX_ANALOGRESET" value="80" />
+  <parameter name="T_RX_DIGITALRESET" value="8000" />
+  <parameter name="T_TX_ANALOGRESET" value="0" />
   <parameter name="T_TX_DIGITALRESET" value="20" />
   <parameter name="device_family" value="Arria V" />
   <parameter name="gui_pll_cal_busy" value="0" />
@@ -636,7 +641,7 @@
   <parameter name="gui_split_interfaces" value="0" />
   <parameter name="gui_tx_auto_reset" value="1" />
  </module>
- <module name="xcvr_rx_pll" kind="altera_pll" version="15.0" enabled="1">
+ <module name="xcvr_rx_pll" kind="altera_pll" version="15.1" enabled="1">
   <parameter name="debug_print_output" value="false" />
   <parameter name="debug_use_rbc_taf_method" value="false" />
   <parameter name="device" value="5AGTFD7K3F40I3" />
@@ -699,7 +704,7 @@
   <parameter name="gui_cascade_outclk_index" value="0" />
   <parameter name="gui_channel_spacing" value="0.0" />
   <parameter name="gui_clk_bad" value="false" />
-  <parameter name="gui_device_speed_grade" value="1" />
+  <parameter name="gui_device_speed_grade" value="2" />
   <parameter name="gui_divide_factor_c0" value="1" />
   <parameter name="gui_divide_factor_c1" value="1" />
   <parameter name="gui_divide_factor_c10" value="1" />
@@ -841,114 +846,112 @@
  </module>
  <connection
    kind="avalon_streaming"
-   version="15.0"
+   version="15.1"
    start="xcvr_core.jesd204_rx_link"
    end="axi_jesd_xcvr.if_rx_ip_avl" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="axi_ad9250_0.if_adc_clk"
    end="util_cpack_0.if_adc_clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="axi_ad9250_1.if_adc_clk"
    end="util_cpack_1.if_adc_clk" />
- <connection kind="clock" version="15.0" start="sys_clk.out_clk" end="sys_rst.clk" />
- <connection kind="clock" version="15.0" start="mem_clk.out_clk" end="mem_rst.clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
+   start="axi_ad9250_1.if_adc_clk"
+   end="axi_dmac_1.if_fifo_wr_clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="axi_ad9250_0.if_adc_clk"
+   end="axi_dmac_0.if_fifo_wr_clk" />
+ <connection
+   kind="clock"
+   version="15.1"
    start="sys_clk.out_clk"
    end="xcvr_rst_cntrl.clock" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
    end="xcvr_core.jesd204_rx_avs_clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="mem_clk.out_clk"
    end="axi_dmac_1.m_dest_axi_clock" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="mem_clk.out_clk"
    end="axi_dmac_0.m_dest_axi_clock" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="rx_ref_clk.out_clk"
    end="xcvr_core.pll_ref_clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="rx_ref_clk.out_clk"
    end="xcvr_rx_pll.refclk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
    end="axi_ad9250_1.s_axi_clock" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
    end="axi_dmac_0.s_axi_clock" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
    end="axi_dmac_1.s_axi_clock" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
    end="axi_jesd_xcvr.s_axi_clock" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
    end="axi_ad9250_0.s_axi_clock" />
  <connection
    kind="clock"
-   version="15.0"
-   start="xcvr_rx_pll.outclk0"
-   end="axi_dmac_1.if_fifo_wr_clk" />
- <connection
-   kind="clock"
-   version="15.0"
-   start="xcvr_rx_pll.outclk0"
-   end="axi_dmac_0.if_fifo_wr_clk" />
- <connection
-   kind="clock"
-   version="15.0"
+   version="15.1"
    start="xcvr_rx_pll.outclk0"
    end="axi_ad9250_1.if_rx_clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="xcvr_rx_pll.outclk0"
    end="axi_ad9250_0.if_rx_clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="xcvr_rx_pll.outclk0"
    end="axi_jesd_xcvr.if_rx_clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="xcvr_rx_pll.outclk0"
    end="axi_jesd_xcvr.if_tx_clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="xcvr_rx_pll.outclk0"
    end="xcvr_core.rxlink_clk" />
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="xcvr_core.dev_lane_aligned"
    end="xcvr_core.alldev_lane_aligned">
   <parameter name="endPort" value="" />
@@ -959,7 +962,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="axi_ad9250_0.fifo_ch_0_in"
    end="util_cpack_0.fifo_ch_0">
   <parameter name="endPort" value="" />
@@ -970,7 +973,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="axi_ad9250_1.fifo_ch_0_in"
    end="util_cpack_1.fifo_ch_0">
   <parameter name="endPort" value="" />
@@ -981,7 +984,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="axi_ad9250_0.fifo_ch_1_in"
    end="util_cpack_0.fifo_ch_1">
   <parameter name="endPort" value="" />
@@ -992,7 +995,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="axi_ad9250_1.fifo_ch_1_in"
    end="util_cpack_1.fifo_ch_1">
   <parameter name="endPort" value="" />
@@ -1003,7 +1006,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="util_cpack_0.if_adc_data"
    end="axi_dmac_0.if_fifo_wr_din">
   <parameter name="endPort" value="" />
@@ -1014,7 +1017,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="util_cpack_1.if_adc_data"
    end="axi_dmac_1.if_fifo_wr_din">
   <parameter name="endPort" value="" />
@@ -1025,7 +1028,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="util_cpack_0.if_adc_sync"
    end="axi_dmac_0.if_fifo_wr_sync">
   <parameter name="endPort" value="" />
@@ -1036,7 +1039,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="util_cpack_1.if_adc_sync"
    end="axi_dmac_1.if_fifo_wr_sync">
   <parameter name="endPort" value="" />
@@ -1047,7 +1050,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="axi_dmac_0.if_fifo_wr_en"
    end="util_cpack_0.if_adc_valid">
   <parameter name="endPort" value="" />
@@ -1058,7 +1061,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="axi_dmac_1.if_fifo_wr_en"
    end="util_cpack_1.if_adc_valid">
   <parameter name="endPort" value="" />
@@ -1069,7 +1072,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="axi_dmac_0.if_fifo_wr_overflow"
    end="axi_ad9250_0.if_adc_dovf">
   <parameter name="endPort" value="" />
@@ -1080,7 +1083,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="axi_dmac_1.if_fifo_wr_overflow"
    end="axi_ad9250_1.if_adc_dovf">
   <parameter name="endPort" value="" />
@@ -1091,7 +1094,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="axi_jesd_xcvr.if_rx_data"
    end="util_bsplit.if_data">
   <parameter name="endPort" value="" />
@@ -1102,7 +1105,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="axi_ad9250_0.if_rx_data"
    end="util_bsplit.if_split_data_0">
   <parameter name="endPort" value="" />
@@ -1113,7 +1116,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="axi_jesd_xcvr.if_rx_ip_sync"
    end="xcvr_core.dev_sync_n">
   <parameter name="endPort" value="" />
@@ -1124,7 +1127,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="axi_jesd_xcvr.if_rx_ip_sysref"
    end="xcvr_core.sysref">
   <parameter name="endPort" value="" />
@@ -1135,7 +1138,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="util_bsplit.if_split_data_1"
    end="axi_ad9250_1.if_rx_data">
   <parameter name="endPort" value="" />
@@ -1146,7 +1149,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="xcvr_rst_cntrl.rx_analogreset"
    end="xcvr_core.rx_analogreset">
   <parameter name="endPort" value="" />
@@ -1157,7 +1160,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="xcvr_core.rx_cal_busy"
    end="xcvr_rst_cntrl.rx_cal_busy">
   <parameter name="endPort" value="" />
@@ -1168,7 +1171,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="xcvr_core.rx_digitalreset"
    end="xcvr_rst_cntrl.rx_digitalreset">
   <parameter name="endPort" value="" />
@@ -1179,7 +1182,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="xcvr_rst_cntrl.rx_is_lockedtodata"
    end="xcvr_core.rx_islockedtodata">
   <parameter name="endPort" value="" />
@@ -1190,7 +1193,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="xcvr_rst_cntrl.rx_ready"
    end="axi_jesd_xcvr.if_rx_ready">
   <parameter name="endPort" value="" />
@@ -1201,7 +1204,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="xcvr_core.sof"
    end="axi_jesd_xcvr.if_rx_ip_sof">
   <parameter name="endPort" value="" />
@@ -1212,72 +1215,67 @@
  </connection>
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="axi_ad9250_1.if_adc_rst"
    end="util_cpack_1.if_adc_rst" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="axi_ad9250_0.if_adc_rst"
    end="util_cpack_0.if_adc_rst" />
  <connection
    kind="reset"
-   version="15.0"
-   start="axi_jesd_xcvr.if_rst"
-   end="xcvr_rst_cntrl.reset" />
- <connection
-   kind="reset"
-   version="15.0"
+   version="15.1"
    start="axi_jesd_xcvr.if_rst"
    end="xcvr_rx_pll.reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="axi_jesd_xcvr.if_rx_rstn"
    end="xcvr_core.rxlink_rst_n" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="xcvr_core.jesd204_rx_avs_rst_n" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="mem_rst.out_reset"
    end="axi_dmac_1.m_dest_axi_reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="mem_rst.out_reset"
    end="axi_dmac_0.m_dest_axi_reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="xcvr_rst_cntrl.reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="axi_ad9250_1.s_axi_reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="axi_dmac_0.s_axi_reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="axi_dmac_1.s_axi_reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="axi_jesd_xcvr.s_axi_reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="axi_ad9250_0.s_axi_reset" />
  <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />