diff --git a/projects/ad9081_fmca_ebz/a10soc/Makefile b/projects/ad9081_fmca_ebz/a10soc/Makefile new file mode 100644 index 000000000..548b205ee --- /dev/null +++ b/projects/ad9081_fmca_ebz/a10soc/Makefile @@ -0,0 +1,24 @@ +#################################################################################### +## Copyright 2018(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := ad9081_fmca_ebz_a10soc + +M_DEPS += ../common/ad9081_fmca_ebz_qsys.tcl +M_DEPS += ../../scripts/adi_pd.tcl +M_DEPS += ../../common/a10soc/a10soc_system_qsys.tcl +M_DEPS += ../../common/a10soc/a10soc_system_assign.tcl +M_DEPS += ../../common/intel/dacfifo_qsys.tcl +M_DEPS += ../../common/intel/adcfifo_qsys.tcl + +LIB_DEPS += axi_dmac +LIB_DEPS += axi_sysid +LIB_DEPS += intel/adi_jesd204 +LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc +LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac +LIB_DEPS += sysid_rom +LIB_DEPS += util_pack/util_cpack2 +LIB_DEPS += util_pack/util_upack2 + +include ../../scripts/project-intel.mk diff --git a/projects/ad9081_fmca_ebz/a10soc/system_constr.sdc b/projects/ad9081_fmca_ebz/a10soc/system_constr.sdc new file mode 100755 index 000000000..768890a56 --- /dev/null +++ b/projects/ad9081_fmca_ebz/a10soc/system_constr.sdc @@ -0,0 +1,12 @@ + +create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}] +create_clock -period "4.000 ns" -name ref_clk [get_ports {fpga_refclk_in}] +create_clock -period "4.000 ns" -name device_clk [get_ports {clkin6}] + +derive_pll_clocks +derive_clock_uncertainty + +set_false_path -to [get_registers *sys_gpio_bd|readdata[12]*] +set_false_path -to [get_registers *sys_gpio_bd|readdata[13]*] + +set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*] diff --git a/projects/ad9081_fmca_ebz/a10soc/system_project.tcl b/projects/ad9081_fmca_ebz/a10soc/system_project.tcl new file mode 100755 index 000000000..7bae59555 --- /dev/null +++ b/projects/ad9081_fmca_ebz/a10soc/system_project.tcl @@ -0,0 +1,203 @@ + +source ../../scripts/adi_env.tcl +source ../../scripts/adi_project_intel.tcl + +# get_env_param retrieves parameter value from the environment if exists, +# other case use the default value +# +# Use over-writable parameters from the environment. +# +# e.g. +# make RX_JESD_L=4 RX_JESD_M=8 RX_JESD_S=1 RX_JESD_NP=16 TX_JESD_L=4 TX_JESD_M=8 TX_JESD_S=1 TX_JESD_NP=16 SAMPLE_RATE=250 +# make RX_JESD_L=8 RX_JESD_M=4 RX_JESD_S=1 RX_JESD_NP=16 TX_JESD_L=8 TX_JESD_M=4 TX_JESD_S=1 TX_JESD_NP=16 SAMPLE_RATE=250 + +adi_project ad9081_fmca_ebz_a10soc [list \ + SAMPLE_RATE [get_env_param SAMPLE_RATE 250] \ + RX_JESD_M [get_env_param RX_JESD_M 8 ] \ + RX_JESD_L [get_env_param RX_JESD_L 4 ] \ + RX_JESD_S [get_env_param RX_JESD_S 1 ] \ + RX_JESD_NP [get_env_param RX_JESD_NP 16 ] \ + RX_NUM_LINKS [get_env_param RX_NUM_LINKS 1 ] \ + TX_JESD_M [get_env_param TX_JESD_M 8 ] \ + TX_JESD_L [get_env_param TX_JESD_L 4 ] \ + TX_JESD_S [get_env_param TX_JESD_S 1 ] \ + TX_JESD_NP [get_env_param TX_JESD_NP 16 ] \ + TX_NUM_LINKS [get_env_param TX_NUM_LINKS 1 ] \ + RX_KS_PER_CHANNEL [get_env_param RX_KS_PER_CHANNEL 32 ] \ + TX_KS_PER_CHANNEL [get_env_param TX_KS_PER_CHANNEL 32 ] \ +] + +source $ad_hdl_dir/projects/common/a10soc/a10soc_system_assign.tcl + + +# files + +set_global_assignment -name VERILOG_FILE ../../../library/common/ad_3w_spi.v + + +# Note: This projects requires a hardware rework to function correctly. +# The rework connects FMC header pins directly to the FPGA so that they can be +# accessed by the fabric. +# +# Changes required: +# R610: DNI -> R0 PIN_E12 +# R611: DNI -> R0 PIN_E13 +# R612: R0 -> DNI +# R613: R0 -> DNI +# R620: DNI -> R0 PIN_F13 +# R632: DNI -> R0 PIN_F14 +# R621: R0 -> DNI +# R633: R0 -> DNI + +set_location_assignment PIN_F9 -to "agc0[0]" ; ## D20 LA17_CC_P +set_location_assignment PIN_G9 -to "agc0[1]" ; ## D21 LA17_CC_N +set_location_assignment PIN_G7 -to "agc1[0]" ; ## C22 LA18_CC_P +set_location_assignment PIN_H7 -to "agc1[1]" ; ## C23 LA18_CC_N +set_location_assignment PIN_C3 -to "agc2[0]" ; ## G21 LA20_P +set_location_assignment PIN_C4 -to "agc2[1]" ; ## G22 LA20_N +set_location_assignment PIN_C2 -to "agc3[0]" ; ## H25 LA21_P +set_location_assignment PIN_D3 -to "agc3[1]" ; ## H26 LA21_N +set_location_assignment PIN_W6 -to "clkin6(n)" ; ## G03 CLK1_M2C_N +set_location_assignment PIN_W5 -to "clkin6" ; ## G02 CLK1_M2C_P +set_location_assignment PIN_N28 -to "fpga_refclk_in(n)" ; ## D05 GBTCLK0_M2C_N +set_location_assignment PIN_N29 -to "fpga_refclk_in" ; ## D04 GBTCLK0_M2C_P +set_location_assignment PIN_P34 -to "rx_data[2](n)" ; ## A07 DP2_M2C_N +set_location_assignment PIN_P35 -to "rx_data[2]" ; ## A06 DP2_M2C_P +set_location_assignment PIN_T30 -to "rx_data[0](n)" ; ## C07 DP0_M2C_N +set_location_assignment PIN_T31 -to "rx_data[0]" ; ## C06 DP0_M2C_P +set_location_assignment PIN_L32 -to "rx_data[7](n)" ; ## B13 DP7_M2C_N +set_location_assignment PIN_L33 -to "rx_data[7]" ; ## B12 DP7_M2C_P +set_location_assignment PIN_M30 -to "rx_data[6](n)" ; ## B17 DP6_M2C_N +set_location_assignment PIN_M31 -to "rx_data[6]" ; ## B16 DP6_M2C_P +set_location_assignment PIN_M34 -to "rx_data[5](n)" ; ## A19 DP5_M2C_N +set_location_assignment PIN_M35 -to "rx_data[5]" ; ## A18 DP5_M2C_P +set_location_assignment PIN_N32 -to "rx_data[4](n)" ; ## A15 DP4_M2C_N +set_location_assignment PIN_N33 -to "rx_data[4]" ; ## A14 DP4_M2C_P +set_location_assignment PIN_P30 -to "rx_data[3](n)" ; ## A11 DP3_M2C_N +set_location_assignment PIN_P31 -to "rx_data[3]" ; ## A10 DP3_M2C_P +set_location_assignment PIN_R32 -to "rx_data[1](n)" ; ## A03 DP1_M2C_N +set_location_assignment PIN_R33 -to "rx_data[1]" ; ## A02 DP1_M2C_P +set_location_assignment PIN_N36 -to "tx_data[0](n)" ; ## C03 DP0_C2M_N +set_location_assignment PIN_N37 -to "tx_data[0]" ; ## C02 DP0_C2M_P +set_location_assignment PIN_L36 -to "tx_data[2](n)" ; ## A27 DP2_C2M_N +set_location_assignment PIN_L37 -to "tx_data[2]" ; ## A26 DP2_C2M_P +set_location_assignment PIN_F38 -to "tx_data[7](n)" ; ## B33 DP7_C2M_N +set_location_assignment PIN_F39 -to "tx_data[7]" ; ## B32 DP7_C2M_P +set_location_assignment PIN_G36 -to "tx_data[6](n)" ; ## B37 DP6_C2M_N +set_location_assignment PIN_G37 -to "tx_data[6]" ; ## B36 DP6_C2M_P +set_location_assignment PIN_M38 -to "tx_data[1](n)" ; ## A23 DP1_C2M_N +set_location_assignment PIN_M39 -to "tx_data[1]" ; ## A22 DP1_C2M_P +set_location_assignment PIN_H38 -to "tx_data[5](n)" ; ## A39 DP5_C2M_N +set_location_assignment PIN_H39 -to "tx_data[5]" ; ## A38 DP5_C2M_P +set_location_assignment PIN_J36 -to "tx_data[4](n)" ; ## A35 DP4_C2M_N +set_location_assignment PIN_J37 -to "tx_data[4]" ; ## A34 DP4_C2M_P +set_location_assignment PIN_K38 -to "tx_data[3](n)" ; ## A31 DP3_C2M_N +set_location_assignment PIN_K39 -to "tx_data[3]" ; ## A30 DP3_C2M_P +set_location_assignment PIN_D13 -to "fpga_syncin[0](n)" ; ## H08 LA02_N +set_location_assignment PIN_C13 -to "fpga_syncin[0]" ; ## H07 LA02_P +set_location_assignment PIN_D14 -to "fpga_syncin[1](n)" ; ## G10 LA03_N +set_location_assignment PIN_C14 -to "fpga_syncin[1]" ; ## G09 LA03_P +set_location_assignment PIN_E13 -to "fpga_syncout[0](n)" ; ## D09 LA01_CC_N +set_location_assignment PIN_E12 -to "fpga_syncout[0]" ; ## D08 LA01_CC_P +set_location_assignment PIN_B10 -to "fpga_syncout[1](n)" ; ## C11 LA06_N +set_location_assignment PIN_A10 -to "fpga_syncout[1]" ; ## C10 LA06_P +set_location_assignment PIN_D4 -to "gpio[0]" ; ## H19 LA15_P +set_location_assignment PIN_D5 -to "gpio[1]" ; ## H20 LA15_N +set_location_assignment PIN_G5 -to "gpio[2]" ; ## H22 LA19_P +set_location_assignment PIN_G6 -to "gpio[3]" ; ## H23 LA19_N +set_location_assignment PIN_J11 -to "gpio[4]" ; ## D17 LA13_P +set_location_assignment PIN_K11 -to "gpio[5]" ; ## D18 LA13_N +set_location_assignment PIN_J9 -to "gpio[6]" ; ## C18 LA14_P +set_location_assignment PIN_J10 -to "gpio[7]" ; ## C19 LA14_N +set_location_assignment PIN_D6 -to "gpio[8]" ; ## G18 LA16_P +set_location_assignment PIN_E6 -to "gpio[9]" ; ## G19 LA16_N +set_location_assignment PIN_G4 -to "gpio[10]" ; ## G25 LA22_N +set_location_assignment PIN_D9 -to "hmc_gpio1" ; ## H17 LA11_N +set_location_assignment PIN_B9 -to "hmc_sync" ; ## H14 LA07_N +set_location_assignment PIN_B11 -to "irqb[0]" ; ## G12 LA08_P +set_location_assignment PIN_B12 -to "irqb[1]" ; ## G13 LA08_N +set_location_assignment PIN_A9 -to "rstb" ; ## H13 LA07_P +set_location_assignment PIN_A7 -to "rxen[0]" ; ## C14 LA10_P +set_location_assignment PIN_A8 -to "rxen[1]" ; ## C15 LA10_N +set_location_assignment PIN_F13 -to "spi0_csb" ; ## D11 LA05_P +set_location_assignment PIN_F14 -to "spi0_miso" ; ## D12 LA05_N +set_location_assignment PIN_H12 -to "spi0_mosi" ; ## H10 LA04_P +set_location_assignment PIN_H13 -to "spi0_sclk" ; ## H11 LA04_N +set_location_assignment PIN_M12 -to "spi1_csb" ; ## G15 LA12_P +set_location_assignment PIN_C9 -to "spi1_sclk" ; ## H16 LA11_P +set_location_assignment PIN_N13 -to "spi1_sdio" ; ## G16 LA12_N +set_location_assignment PIN_F5 -to "sysref2(n)" ; ## H05 CLK0_M2C_N +set_location_assignment PIN_E5 -to "sysref2" ; ## H04 CLK0_M2C_P +set_location_assignment PIN_A12 -to "txen[0]" ; ## D14 LA09_P +set_location_assignment PIN_A13 -to "txen[1]" ; ## D15 LA09_N + + +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to rx_data +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to tx_data + +set_instance_assignment -name IO_STANDARD LVDS -to fpga_refclk_in +set_instance_assignment -name IO_STANDARD LVDS -to clkin6 +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data + +set common_lanes 0 +set common_lanes [get_env_param RX_JESD_L 4] +if {$common_lanes > [get_env_param TX_JESD_L 4]} { + set common_lanes [get_env_param TX_JESD_L 4] +} + +# Merge RX and TX into single transceiver +for {set i 0} {$i < $common_lanes} {incr i} { + set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_${i} -to rx_data[${i}] + set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_${i} -to tx_data[${i}] +} + +set_instance_assignment -name IO_STANDARD LVDS -to fpga_syncin[0] +set_instance_assignment -name IO_STANDARD LVDS -to fpga_syncin[1] +set_instance_assignment -name IO_STANDARD LVDS -to fpga_syncout[0] +set_instance_assignment -name IO_STANDARD LVDS -to fpga_syncout[1] +set_instance_assignment -name IO_STANDARD LVDS -to sysref2 +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to fpga_syncin[0] +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to fpga_syncin[1] +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to sysref2 + +set_instance_assignment -name IO_STANDARD "1.8 V" -to agc0[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to agc0[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to agc1[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to agc1[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to agc2[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to agc2[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to agc3[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to agc3[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio[4] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio[5] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio[6] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio[7] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio[8] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio[9] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio[10] +set_instance_assignment -name IO_STANDARD "1.8 V" -to hmc_gpio1 +set_instance_assignment -name IO_STANDARD "1.8 V" -to hmc_sync +set_instance_assignment -name IO_STANDARD "1.8 V" -to irqb[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to irqb[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to rstb +set_instance_assignment -name IO_STANDARD "1.8 V" -to rxen[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to rxen[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to spi0_csb +set_instance_assignment -name IO_STANDARD "1.8 V" -to spi0_miso +set_instance_assignment -name IO_STANDARD "1.8 V" -to spi0_mosi +set_instance_assignment -name IO_STANDARD "1.8 V" -to spi0_sclk +set_instance_assignment -name IO_STANDARD "1.8 V" -to spi1_csb +set_instance_assignment -name IO_STANDARD "1.8 V" -to spi1_sclk +set_instance_assignment -name IO_STANDARD "1.8 V" -to spi1_sdio +set_instance_assignment -name IO_STANDARD "1.8 V" -to txen[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to txen[1] + +# set optimization to get a better timing closure +set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT" + +execute_flow -compile diff --git a/projects/ad9081_fmca_ebz/a10soc/system_qsys.tcl b/projects/ad9081_fmca_ebz/a10soc/system_qsys.tcl new file mode 100755 index 000000000..d368de94b --- /dev/null +++ b/projects/ad9081_fmca_ebz/a10soc/system_qsys.tcl @@ -0,0 +1,20 @@ + +## ADC FIFO depth in samples per converter +set adc_fifo_samples_per_converter [expr $ad_project_params(RX_KS_PER_CHANNEL)*1024] +## DAC FIFO depth in samples per converter +set dac_fifo_samples_per_converter [expr $ad_project_params(TX_KS_PER_CHANNEL)*1024] + +source $ad_hdl_dir/projects/scripts/adi_pd.tcl +source $ad_hdl_dir/projects/common/a10soc/a10soc_system_qsys.tcl +source $ad_hdl_dir/projects/common/intel/dacfifo_qsys.tcl +source $ad_hdl_dir/projects/common/intel/adcfifo_qsys.tcl +source ../common/ad9081_fmca_ebz_qsys.tcl + +#system ID +set_instance_parameter_value axi_sysid_0 {ROM_ADDR_BITS} {9} +set_instance_parameter_value rom_sys_0 {ROM_ADDR_BITS} {9} + +set_instance_parameter_value rom_sys_0 {PATH_TO_FILE} "[pwd]/mem_init_sys.txt" + +sysid_gen_sys_init_file; + diff --git a/projects/ad9081_fmca_ebz/a10soc/system_top.v b/projects/ad9081_fmca_ebz/a10soc/system_top.v new file mode 100755 index 000000000..263ffc765 --- /dev/null +++ b/projects/ad9081_fmca_ebz/a10soc/system_top.v @@ -0,0 +1,330 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top #( + // Dummy parameters to workaround critical warning + parameter SAMPLE_RATE = 250, + parameter RX_JESD_M = 8, + parameter RX_JESD_L = 4, + parameter RX_JESD_S = 1, + parameter RX_JESD_NP = 16, + parameter RX_NUM_LINKS = 1, + parameter TX_JESD_M = 8, + parameter TX_JESD_L = 4, + parameter TX_JESD_S = 1, + parameter TX_JESD_NP = 16, + parameter TX_NUM_LINKS = 1, + parameter RX_KS_PER_CHANNEL = 32, + parameter TX_KS_PER_CHANNEL = 32 +) ( + + // clock and resets + + input sys_clk, + input sys_resetn, + + // hps-ddr4 (32) + + input hps_ddr_ref_clk, + output [ 0:0] hps_ddr_clk_p, + output [ 0:0] hps_ddr_clk_n, + output [ 16:0] hps_ddr_a, + output [ 1:0] hps_ddr_ba, + output [ 0:0] hps_ddr_bg, + output [ 0:0] hps_ddr_cke, + output [ 0:0] hps_ddr_cs_n, + output [ 0:0] hps_ddr_odt, + output [ 0:0] hps_ddr_reset_n, + output [ 0:0] hps_ddr_act_n, + output [ 0:0] hps_ddr_par, + input [ 0:0] hps_ddr_alert_n, + inout [ 3:0] hps_ddr_dqs_p, + inout [ 3:0] hps_ddr_dqs_n, + inout [ 31:0] hps_ddr_dq, + inout [ 3:0] hps_ddr_dbi_n, + input hps_ddr_rzq, + + // hps-ethernet + + input [ 0:0] hps_eth_rxclk, + input [ 0:0] hps_eth_rxctl, + input [ 3:0] hps_eth_rxd, + output [ 0:0] hps_eth_txclk, + output [ 0:0] hps_eth_txctl, + output [ 3:0] hps_eth_txd, + output [ 0:0] hps_eth_mdc, + inout [ 0:0] hps_eth_mdio, + + // hps-sdio + + output [ 0:0] hps_sdio_clk, + inout [ 0:0] hps_sdio_cmd, + inout [ 7:0] hps_sdio_d, + + // hps-usb + + input [ 0:0] hps_usb_clk, + input [ 0:0] hps_usb_dir, + input [ 0:0] hps_usb_nxt, + output [ 0:0] hps_usb_stp, + inout [ 7:0] hps_usb_d, + + // hps-uart + + input [ 0:0] hps_uart_rx, + output [ 0:0] hps_uart_tx, + + // hps-i2c (shared w fmc-a, fmc-b) + + inout [ 0:0] hps_i2c_sda, + inout [ 0:0] hps_i2c_scl, + + // hps-gpio (max-v-u16) + + inout [ 3:0] hps_gpio, + + // gpio (max-v-u21) + + input [ 7:0] gpio_bd_i, + output [ 3:0] gpio_bd_o, + + // FMC HPC IOs + + // lane interface + input clkin6, + input fpga_refclk_in, + input [7:0] rx_data, + output [7:0] tx_data, + input [1:0] fpga_syncin, + output [1:0] fpga_syncout, + input sysref2, + + // spi + output spi0_csb, + input spi0_miso, + output spi0_mosi, + output spi0_sclk, + output spi1_csb, + output spi1_sclk, + inout spi1_sdio, + + // gpio + input [1:0] agc0, + input [1:0] agc1, + input [1:0] agc2, + input [1:0] agc3, + inout [10:0] gpio, + inout hmc_gpio1, + output hmc_sync, + input [1:0] irqb, + output rstb, + output [1:0] rxen, + output [1:0] txen + + ); + + // internal signals + + wire sys_hps_resetn; + wire sys_resetn_s; + wire [ 63:0] gpio_i; + wire [ 63:0] gpio_o; + wire [ 7:0] spi_csn_s; + wire dac_fifo_bypass; + + // assignments + + assign spi0_csb = spi_csn_s[0]; + assign spi1_csb = spi_csn_s[1]; + + assign spi0_sclk = spi_clk; + assign spi1_sclk = spi_clk; + + assign spi0_mosi = spi_mosi; + + ad_3w_spi #(.NUM_OF_SLAVES(1)) i_spi_hmc ( + .spi_csn (spi_csn_s[1]), + .spi_clk (spi_clk), + .spi_mosi (spi_mosi), + .spi_miso (spi_hmc_miso), + .spi_sdio (spi1_sdio), + .spi_dir ()); + + assign spi_miso = ~spi_csn_s[0] ? spi0_miso : + ~spi_csn_s[1] ? spi_hmc_miso : + 1'b0; + + // gpio + + // TODO output only for now + assign hmc_gpio1 = gpio_o[43]; + + assign gpio_i[44] = agc0[0]; + assign gpio_i[45] = agc0[1]; + assign gpio_i[46] = agc1[0]; + assign gpio_i[47] = agc1[1]; + assign gpio_i[48] = agc2[0]; + assign gpio_i[49] = agc2[1]; + assign gpio_i[50] = agc3[0]; + assign gpio_i[51] = agc3[1]; + assign gpio_i[52] = irqb[0]; + assign gpio_i[53] = irqb[1]; + + assign hmc_sync = gpio_o[54]; + assign rstb = gpio_o[55]; + assign rxen[0] = gpio_o[56]; + assign rxen[1] = gpio_o[57]; + assign txen[0] = gpio_o[58]; + assign txen[1] = gpio_o[59]; + assign dac_fifo_bypass = gpio_o[60]; + + // board stuff (max-v-u21) + + assign gpio_i[31:14] = gpio_o[31:14]; + assign gpio_i[13:13] = 1'b1; + assign gpio_i[12:12] = 1'b0; + assign gpio_i[11: 4] = gpio_bd_i; + assign gpio_i[ 3: 0] = gpio_o[3:0]; + + assign gpio_bd_o = gpio_o[3:0]; + + // Unused GPIOs + assign gpio_i[63:60] = gpio_o[63:60]; + + // peripheral reset + + assign sys_resetn_s = sys_resetn & sys_hps_resetn; + + // instantiations + + system_bd i_system_bd ( + .mxfe_gpio_export (gpio), + .sys_clk_clk (sys_clk), + .sys_gpio_bd_in_port (gpio_i[31:0]), + .sys_gpio_bd_out_port (gpio_o[31:0]), + .sys_gpio_in_export (gpio_i[63:32]), + .sys_gpio_out_export (gpio_o[63:32]), + .sys_hps_ddr_mem_ck (hps_ddr_clk_p), + .sys_hps_ddr_mem_ck_n (hps_ddr_clk_n), + .sys_hps_ddr_mem_a (hps_ddr_a), + .sys_hps_ddr_mem_act_n (hps_ddr_act_n), + .sys_hps_ddr_mem_ba (hps_ddr_ba), + .sys_hps_ddr_mem_bg (hps_ddr_bg), + .sys_hps_ddr_mem_cke (hps_ddr_cke), + .sys_hps_ddr_mem_cs_n (hps_ddr_cs_n), + .sys_hps_ddr_mem_odt (hps_ddr_odt), + .sys_hps_ddr_mem_reset_n (hps_ddr_reset_n), + .sys_hps_ddr_mem_par (hps_ddr_par), + .sys_hps_ddr_mem_alert_n (hps_ddr_alert_n), + .sys_hps_ddr_mem_dqs (hps_ddr_dqs_p), + .sys_hps_ddr_mem_dqs_n (hps_ddr_dqs_n), + .sys_hps_ddr_mem_dq (hps_ddr_dq), + .sys_hps_ddr_mem_dbi_n (hps_ddr_dbi_n), + .sys_hps_ddr_oct_oct_rzqin (hps_ddr_rzq), + .sys_hps_ddr_ref_clk_clk (hps_ddr_ref_clk), + .sys_hps_ddr_rstn_reset_n (sys_resetn), + .sys_hps_io_hps_io_phery_emac0_TX_CLK (hps_eth_txclk), + .sys_hps_io_hps_io_phery_emac0_TXD0 (hps_eth_txd[0]), + .sys_hps_io_hps_io_phery_emac0_TXD1 (hps_eth_txd[1]), + .sys_hps_io_hps_io_phery_emac0_TXD2 (hps_eth_txd[2]), + .sys_hps_io_hps_io_phery_emac0_TXD3 (hps_eth_txd[3]), + .sys_hps_io_hps_io_phery_emac0_RX_CTL (hps_eth_rxctl), + .sys_hps_io_hps_io_phery_emac0_TX_CTL (hps_eth_txctl), + .sys_hps_io_hps_io_phery_emac0_RX_CLK (hps_eth_rxclk), + .sys_hps_io_hps_io_phery_emac0_RXD0 (hps_eth_rxd[0]), + .sys_hps_io_hps_io_phery_emac0_RXD1 (hps_eth_rxd[1]), + .sys_hps_io_hps_io_phery_emac0_RXD2 (hps_eth_rxd[2]), + .sys_hps_io_hps_io_phery_emac0_RXD3 (hps_eth_rxd[3]), + .sys_hps_io_hps_io_phery_emac0_MDIO (hps_eth_mdio), + .sys_hps_io_hps_io_phery_emac0_MDC (hps_eth_mdc), + .sys_hps_io_hps_io_phery_sdmmc_CMD (hps_sdio_cmd), + .sys_hps_io_hps_io_phery_sdmmc_D0 (hps_sdio_d[0]), + .sys_hps_io_hps_io_phery_sdmmc_D1 (hps_sdio_d[1]), + .sys_hps_io_hps_io_phery_sdmmc_D2 (hps_sdio_d[2]), + .sys_hps_io_hps_io_phery_sdmmc_D3 (hps_sdio_d[3]), + .sys_hps_io_hps_io_phery_sdmmc_D4 (hps_sdio_d[4]), + .sys_hps_io_hps_io_phery_sdmmc_D5 (hps_sdio_d[5]), + .sys_hps_io_hps_io_phery_sdmmc_D6 (hps_sdio_d[6]), + .sys_hps_io_hps_io_phery_sdmmc_D7 (hps_sdio_d[7]), + .sys_hps_io_hps_io_phery_sdmmc_CCLK (hps_sdio_clk), + .sys_hps_io_hps_io_phery_usb0_DATA0 (hps_usb_d[0]), + .sys_hps_io_hps_io_phery_usb0_DATA1 (hps_usb_d[1]), + .sys_hps_io_hps_io_phery_usb0_DATA2 (hps_usb_d[2]), + .sys_hps_io_hps_io_phery_usb0_DATA3 (hps_usb_d[3]), + .sys_hps_io_hps_io_phery_usb0_DATA4 (hps_usb_d[4]), + .sys_hps_io_hps_io_phery_usb0_DATA5 (hps_usb_d[5]), + .sys_hps_io_hps_io_phery_usb0_DATA6 (hps_usb_d[6]), + .sys_hps_io_hps_io_phery_usb0_DATA7 (hps_usb_d[7]), + .sys_hps_io_hps_io_phery_usb0_CLK (hps_usb_clk), + .sys_hps_io_hps_io_phery_usb0_STP (hps_usb_stp), + .sys_hps_io_hps_io_phery_usb0_DIR (hps_usb_dir), + .sys_hps_io_hps_io_phery_usb0_NXT (hps_usb_nxt), + .sys_hps_io_hps_io_phery_uart1_RX (hps_uart_rx), + .sys_hps_io_hps_io_phery_uart1_TX (hps_uart_tx), + .sys_hps_io_hps_io_phery_i2c1_SDA (hps_i2c_sda), + .sys_hps_io_hps_io_phery_i2c1_SCL (hps_i2c_scl), + .sys_hps_io_hps_io_gpio_gpio1_io5 (hps_gpio[0]), + .sys_hps_io_hps_io_gpio_gpio1_io14 (hps_gpio[1]), + .sys_hps_io_hps_io_gpio_gpio1_io16 (hps_gpio[2]), + .sys_hps_io_hps_io_gpio_gpio1_io17 (hps_gpio[3]), + .sys_hps_out_rstn_reset_n (sys_hps_resetn), + .sys_hps_rstn_reset_n (sys_resetn), + .sys_rstn_reset_n (sys_resetn_s), + .pr_rom_data_nc_rom_data('h0), + // FMC HPC + .sys_spi_MISO (spi_miso), + .sys_spi_MOSI (spi_mosi), + .sys_spi_SCLK (spi_clk), + .sys_spi_SS_n (spi_csn_s), + .tx_serial_data_tx_serial_data (tx_data[7:0]), + .tx_ref_clk_clk (fpga_refclk_in), + .tx_sync_export (fpga_syncin), + .tx_sysref_export (sysref2), + .tx_device_clk_clk (clkin6), + .rx_serial_data_rx_serial_data (rx_data[7:0]), + .rx_ref_clk_clk (fpga_refclk_in), + .rx_sync_export (fpga_syncout), + .rx_sysref_export (sysref2), + .rx_device_clk_clk (clkin6), + .tx_fifo_bypass_bypass (dac_fifo_bypass) + + ); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_qsys.tcl b/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_qsys.tcl new file mode 100644 index 000000000..846af336e --- /dev/null +++ b/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_qsys.tcl @@ -0,0 +1,358 @@ +# Common parameter for TX and RX +set SAMPLE_RATE $ad_project_params(SAMPLE_RATE) + +# RX parameters +set RX_NUM_OF_LINKS $ad_project_params(RX_NUM_LINKS) + +# RX JESD parameter per link +set RX_JESD_M $ad_project_params(RX_JESD_M) +set RX_JESD_L $ad_project_params(RX_JESD_L) +set RX_JESD_S $ad_project_params(RX_JESD_S) +set RX_JESD_NP $ad_project_params(RX_JESD_NP) + +set RX_TPL_DATA_PATH_WIDTH 4 + +set RX_NUM_OF_LANES [expr $RX_JESD_L * $RX_NUM_OF_LINKS] +set RX_NUM_OF_CONVERTERS [expr $RX_JESD_M * $RX_NUM_OF_LINKS] +set RX_SAMPLES_PER_FRAME $RX_JESD_S +set RX_SAMPLE_WIDTH $RX_JESD_NP +set RX_DMA_SAMPLE_WIDTH 16 + +set RX_SAMPLES_PER_CHANNEL [expr $RX_NUM_OF_LANES * 8*$RX_TPL_DATA_PATH_WIDTH / \ + ($RX_NUM_OF_CONVERTERS * $RX_SAMPLE_WIDTH)] + +# TX parameters +set TX_NUM_OF_LINKS $ad_project_params(TX_NUM_LINKS) + +# TX JESD parameter per link +set TX_JESD_M $ad_project_params(TX_JESD_M) +set TX_JESD_L $ad_project_params(TX_JESD_L) +set TX_JESD_S $ad_project_params(TX_JESD_S) +set TX_JESD_NP $ad_project_params(TX_JESD_NP) + +set TX_TPL_DATA_PATH_WIDTH 4 + +set TX_NUM_OF_LANES [expr $TX_JESD_L * $TX_NUM_OF_LINKS] +set TX_NUM_OF_CONVERTERS [expr $TX_JESD_M * $TX_NUM_OF_LINKS] +set TX_SAMPLES_PER_FRAME $TX_JESD_S +set TX_SAMPLE_WIDTH $TX_JESD_NP +set TX_DMA_SAMPLE_WIDTH 16 + +set TX_SAMPLES_PER_CHANNEL [expr $TX_NUM_OF_LANES * 8*$TX_TPL_DATA_PATH_WIDTH / \ + ($TX_NUM_OF_CONVERTERS * $TX_SAMPLE_WIDTH)] + +#Lane Rate = I/Q Sample Rate x M x N' x (10 \ 8) \ L +set TX_LANE_RATE [expr ($SAMPLE_RATE*$TX_NUM_OF_CONVERTERS*$TX_SAMPLE_WIDTH*10)/(8*$TX_NUM_OF_LANES)] +set RX_LANE_RATE [expr ($SAMPLE_RATE*$RX_NUM_OF_CONVERTERS*$RX_SAMPLE_WIDTH*10)/(8*$RX_NUM_OF_LANES)] + +set adc_fifo_name mxfe_adc_fifo +set adc_data_width [expr 8*$RX_TPL_DATA_PATH_WIDTH*$RX_NUM_OF_LANES*$RX_DMA_SAMPLE_WIDTH/$RX_SAMPLE_WIDTH] +set adc_dma_data_width $adc_data_width +set adc_fifo_address_width [expr int(ceil(log(($adc_fifo_samples_per_converter*$RX_NUM_OF_CONVERTERS) / ($adc_data_width/$RX_DMA_SAMPLE_WIDTH))/log(2)))] + +set dac_fifo_name mxfe_dac_fifo +set dac_data_width [expr 8*$TX_TPL_DATA_PATH_WIDTH*$TX_NUM_OF_LANES*$TX_DMA_SAMPLE_WIDTH/$TX_SAMPLE_WIDTH] +set dac_dma_data_width $dac_data_width +set dac_fifo_address_width [expr int(ceil(log(($dac_fifo_samples_per_converter*$TX_NUM_OF_CONVERTERS) / ($dac_data_width/$TX_DMA_SAMPLE_WIDTH))/log(2)))] + +# JESD204B clock bridges + +add_instance tx_device_clk altera_clock_bridge 19.1 +set_instance_parameter_value tx_device_clk {EXPLICIT_CLOCK_RATE} {250000000} + +add_instance rx_device_clk altera_clock_bridge 19.1 +set_instance_parameter_value rx_device_clk {EXPLICIT_CLOCK_RATE} {250000000} + +# +## IP instantions and configuration +# + +# RX JESD204 PHY-Link layer + +add_instance mxfe_rx_jesd204 adi_jesd204 +set_instance_parameter_value mxfe_rx_jesd204 {ID} {0} +set_instance_parameter_value mxfe_rx_jesd204 {TX_OR_RX_N} {0} +set_instance_parameter_value mxfe_rx_jesd204 {SOFT_PCS} {true} +set_instance_parameter_value mxfe_rx_jesd204 {LANE_RATE} $RX_LANE_RATE +set_instance_parameter_value mxfe_rx_jesd204 {SYSCLK_FREQUENCY} {100.0} +set_instance_parameter_value mxfe_rx_jesd204 {REFCLK_FREQUENCY} {250.0} +set_instance_parameter_value mxfe_rx_jesd204 {INPUT_PIPELINE_STAGES} {2} +set_instance_parameter_value mxfe_rx_jesd204 {NUM_OF_LANES} $RX_NUM_OF_LANES +set_instance_parameter_value mxfe_rx_jesd204 {EXT_DEVICE_CLK_EN} {1} + +add_instance mxfe_rx_tpl ad_ip_jesd204_tpl_adc +set_instance_parameter_value mxfe_rx_tpl {ID} {0} +set_instance_parameter_value mxfe_rx_tpl {NUM_CHANNELS} $RX_NUM_OF_CONVERTERS +set_instance_parameter_value mxfe_rx_tpl {NUM_LANES} $RX_NUM_OF_LANES +set_instance_parameter_value mxfe_rx_tpl {BITS_PER_SAMPLE} $RX_SAMPLE_WIDTH +set_instance_parameter_value mxfe_rx_tpl {CONVERTER_RESOLUTION} $RX_SAMPLE_WIDTH +set_instance_parameter_value mxfe_rx_tpl {TWOS_COMPLEMENT} {1} + +# TX JESD204 PHY+Link + +add_instance mxfe_tx_jesd204 adi_jesd204 +set_instance_parameter_value mxfe_tx_jesd204 {ID} {0} +set_instance_parameter_value mxfe_tx_jesd204 {TX_OR_RX_N} {1} +set_instance_parameter_value mxfe_tx_jesd204 {SOFT_PCS} {true} +set_instance_parameter_value mxfe_tx_jesd204 {LANE_RATE} $TX_LANE_RATE +set_instance_parameter_value mxfe_tx_jesd204 {SYSCLK_FREQUENCY} {100.0} +set_instance_parameter_value mxfe_tx_jesd204 {REFCLK_FREQUENCY} {250.0} +set_instance_parameter_value mxfe_tx_jesd204 {NUM_OF_LANES} $TX_NUM_OF_LANES +set_instance_parameter_value mxfe_tx_jesd204 {EXT_DEVICE_CLK_EN} {1} + +add_instance mxfe_tx_tpl ad_ip_jesd204_tpl_dac +set_instance_parameter_value mxfe_tx_tpl {ID} {0} +set_instance_parameter_value mxfe_tx_tpl {NUM_CHANNELS} $TX_NUM_OF_CONVERTERS +set_instance_parameter_value mxfe_tx_tpl {NUM_LANES} $TX_NUM_OF_LANES +set_instance_parameter_value mxfe_tx_tpl {BITS_PER_SAMPLE} $TX_SAMPLE_WIDTH +set_instance_parameter_value mxfe_tx_tpl {CONVERTER_RESOLUTION} $TX_SAMPLE_WIDTH + +# pack(s) & unpack(s) + +add_instance mxfe_tx_upack util_upack2 +set_instance_parameter_value mxfe_tx_upack {NUM_OF_CHANNELS} $TX_NUM_OF_CONVERTERS +set_instance_parameter_value mxfe_tx_upack {SAMPLES_PER_CHANNEL} $TX_SAMPLES_PER_CHANNEL +set_instance_parameter_value mxfe_tx_upack {SAMPLE_DATA_WIDTH} $TX_DMA_SAMPLE_WIDTH +set_instance_parameter_value mxfe_tx_upack {INTERFACE_TYPE} {1} + +add_instance mxfe_rx_cpack util_cpack2 +set_instance_parameter_value mxfe_rx_cpack {NUM_OF_CHANNELS} $RX_NUM_OF_CONVERTERS +set_instance_parameter_value mxfe_rx_cpack {SAMPLES_PER_CHANNEL} $RX_SAMPLES_PER_CHANNEL +set_instance_parameter_value mxfe_rx_cpack {SAMPLE_DATA_WIDTH} $RX_DMA_SAMPLE_WIDTH + +# RX and TX data offload buffers + +ad_adcfifo_create $adc_fifo_name $adc_data_width $adc_dma_data_width $adc_fifo_address_width +ad_dacfifo_create $dac_fifo_name $dac_data_width $dac_dma_data_width $dac_fifo_address_width + +# RX and TX DMA instance and connections + +add_instance mxfe_tx_dma axi_dmac +set_instance_parameter_value mxfe_tx_dma {ID} {0} +set_instance_parameter_value mxfe_tx_dma {DMA_DATA_WIDTH_SRC} {128} +set_instance_parameter_value mxfe_tx_dma {DMA_DATA_WIDTH_DEST} $dac_dma_data_width +set_instance_parameter_value mxfe_tx_dma {DMA_LENGTH_WIDTH} {24} +set_instance_parameter_value mxfe_tx_dma {DMA_2D_TRANSFER} {0} +set_instance_parameter_value mxfe_tx_dma {AXI_SLICE_DEST} {0} +set_instance_parameter_value mxfe_tx_dma {AXI_SLICE_SRC} {0} +set_instance_parameter_value mxfe_tx_dma {SYNC_TRANSFER_START} {0} +set_instance_parameter_value mxfe_tx_dma {CYCLIC} {1} +set_instance_parameter_value mxfe_tx_dma {DMA_TYPE_DEST} {1} +set_instance_parameter_value mxfe_tx_dma {DMA_TYPE_SRC} {0} +set_instance_parameter_value mxfe_tx_dma {FIFO_SIZE} {16} +set_instance_parameter_value mxfe_tx_dma {HAS_AXIS_TLAST} {1} +set_instance_parameter_value mxfe_tx_dma {DMA_AXI_PROTOCOL_SRC} {0} +set_instance_parameter_value mxfe_tx_dma {MAX_BYTES_PER_BURST} {4096} + +add_instance mxfe_rx_dma axi_dmac +set_instance_parameter_value mxfe_rx_dma {ID} {0} +set_instance_parameter_value mxfe_rx_dma {DMA_DATA_WIDTH_SRC} $adc_dma_data_width +set_instance_parameter_value mxfe_rx_dma {DMA_DATA_WIDTH_DEST} {128} +set_instance_parameter_value mxfe_rx_dma {DMA_LENGTH_WIDTH} {24} +set_instance_parameter_value mxfe_rx_dma {DMA_2D_TRANSFER} {0} +set_instance_parameter_value mxfe_rx_dma {AXI_SLICE_DEST} {0} +set_instance_parameter_value mxfe_rx_dma {AXI_SLICE_SRC} {0} +set_instance_parameter_value mxfe_rx_dma {SYNC_TRANSFER_START} {0} +set_instance_parameter_value mxfe_rx_dma {CYCLIC} {0} +set_instance_parameter_value mxfe_rx_dma {DMA_TYPE_DEST} {0} +set_instance_parameter_value mxfe_rx_dma {DMA_TYPE_SRC} {1} +set_instance_parameter_value mxfe_rx_dma {FIFO_SIZE} {16} +set_instance_parameter_value mxfe_rx_dma {DMA_AXI_PROTOCOL_DEST} {0} +set_instance_parameter_value mxfe_rx_dma {MAX_BYTES_PER_BURST} {4096} + +# mxfe gpio + +add_instance avl_mxfe_gpio altera_avalon_pio +set_instance_parameter_value avl_mxfe_gpio {direction} {Bidir} +set_instance_parameter_value avl_mxfe_gpio {generateIRQ} {1} +set_instance_parameter_value avl_mxfe_gpio {width} {19} +add_connection sys_clk.clk avl_mxfe_gpio.clk +add_connection sys_clk.clk_reset avl_mxfe_gpio.reset +add_interface mxfe_gpio conduit end +set_interface_property mxfe_gpio EXPORT_OF avl_mxfe_gpio.external_connection + +# +## clocks and resets +# + +# system clock and reset + +add_connection sys_clk.clk mxfe_rx_jesd204.sys_clk +add_connection sys_clk.clk mxfe_rx_tpl.s_axi_clock +add_connection sys_clk.clk mxfe_rx_dma.s_axi_clock +add_connection sys_clk.clk mxfe_tx_jesd204.sys_clk +add_connection sys_clk.clk mxfe_tx_tpl.s_axi_clock +add_connection sys_clk.clk mxfe_tx_dma.s_axi_clock + +add_connection sys_clk.clk_reset mxfe_rx_jesd204.sys_resetn +add_connection sys_clk.clk_reset mxfe_rx_tpl.s_axi_reset +add_connection sys_clk.clk_reset mxfe_rx_dma.s_axi_reset +add_connection sys_clk.clk_reset mxfe_tx_jesd204.sys_resetn +add_connection sys_clk.clk_reset mxfe_tx_tpl.s_axi_reset +add_connection sys_clk.clk_reset mxfe_tx_dma.s_axi_reset + +# device clock and reset + +add_connection rx_device_clk.out_clk mxfe_rx_jesd204.device_clk +add_connection rx_device_clk.out_clk mxfe_rx_tpl.link_clk +add_connection rx_device_clk.out_clk mxfe_rx_cpack.clk +add_connection rx_device_clk.out_clk $adc_fifo_name.if_adc_clk + +add_connection tx_device_clk.out_clk mxfe_tx_jesd204.device_clk +add_connection tx_device_clk.out_clk mxfe_tx_tpl.link_clk +add_connection tx_device_clk.out_clk mxfe_tx_upack.clk +add_connection tx_device_clk.out_clk $dac_fifo_name.if_dac_clk + +add_connection mxfe_rx_jesd204.link_reset mxfe_rx_cpack.reset +add_connection mxfe_rx_jesd204.link_reset $adc_fifo_name.if_adc_rst + +add_connection mxfe_tx_jesd204.link_reset mxfe_tx_upack.reset +add_connection mxfe_tx_jesd204.link_reset $dac_fifo_name.if_dac_rst + +# dma clock and reset + +add_connection sys_dma_clk.clk $adc_fifo_name.if_dma_clk +add_connection sys_dma_clk.clk mxfe_rx_dma.if_s_axis_aclk +add_connection sys_dma_clk.clk mxfe_rx_dma.m_dest_axi_clock + +add_connection sys_dma_clk.clk_reset mxfe_rx_dma.m_dest_axi_reset + +add_connection sys_dma_clk.clk $dac_fifo_name.if_dma_clk +add_connection sys_dma_clk.clk mxfe_tx_dma.if_m_axis_aclk +add_connection sys_dma_clk.clk mxfe_tx_dma.m_src_axi_clock + +add_connection sys_dma_clk.clk_reset mxfe_tx_dma.m_src_axi_reset +add_connection sys_dma_clk.clk_reset $dac_fifo_name.if_dma_rst + +# +## Exported signals +# + +add_interface rx_ref_clk clock sink +add_interface rx_sysref conduit end +add_interface rx_sync conduit end +add_interface rx_serial_data conduit end +add_interface tx_ref_clk clock sink +add_interface rx_device_clk clock sink +add_interface tx_serial_data conduit end +add_interface tx_sysref conduit end +add_interface tx_sync conduit end +add_interface tx_fifo_bypass conduit end +add_interface tx_device_clk clock sink + +set_interface_property rx_ref_clk EXPORT_OF mxfe_rx_jesd204.ref_clk +set_interface_property rx_sysref EXPORT_OF mxfe_rx_jesd204.sysref +set_interface_property rx_sync EXPORT_OF mxfe_rx_jesd204.sync +set_interface_property rx_serial_data EXPORT_OF mxfe_rx_jesd204.serial_data +set_interface_property rx_device_clk EXPORT_OF rx_device_clk.in_clk + +set_interface_property tx_ref_clk EXPORT_OF mxfe_tx_jesd204.ref_clk +set_interface_property tx_sysref EXPORT_OF mxfe_tx_jesd204.sysref +set_interface_property tx_sync EXPORT_OF mxfe_tx_jesd204.sync +set_interface_property tx_serial_data EXPORT_OF mxfe_tx_jesd204.serial_data +set_interface_property tx_fifo_bypass EXPORT_OF $dac_fifo_name.if_bypass +set_interface_property tx_device_clk EXPORT_OF tx_device_clk.in_clk + +# +## Data interface / data path +# + +# RX link to tpl +add_connection mxfe_rx_jesd204.link_sof mxfe_rx_tpl.if_link_sof +add_connection mxfe_rx_jesd204.link_data mxfe_rx_tpl.link_data +# RX tpl to cpack +for {set i 0} {$i < $RX_NUM_OF_CONVERTERS} {incr i} { + add_connection mxfe_rx_tpl.adc_ch_$i mxfe_rx_cpack.adc_ch_$i +} +add_connection mxfe_rx_tpl.if_adc_dovf $adc_fifo_name.if_adc_wovf +# RX cpack to offload +add_connection mxfe_rx_cpack.if_packed_fifo_wr_en $adc_fifo_name.if_adc_wr +add_connection mxfe_rx_cpack.if_packed_fifo_wr_data $adc_fifo_name.if_adc_wdata +# RX offload to dma +add_connection $adc_fifo_name.if_dma_xfer_req mxfe_rx_dma.if_s_axis_xfer_req +add_connection $adc_fifo_name.m_axis mxfe_rx_dma.s_axis +# RX dma to HPS +ad_dma_interconnect mxfe_rx_dma.m_dest_axi + +# TX link to tpl +add_connection mxfe_tx_tpl.link_data mxfe_tx_jesd204.link_data +# TX tpl to pack +for {set i 0} {$i < $TX_NUM_OF_CONVERTERS} {incr i} { + add_connection mxfe_tx_upack.dac_ch_$i mxfe_tx_tpl.dac_ch_$i +} +# TX pack to offload +add_connection mxfe_tx_upack.if_packed_fifo_rd_en $dac_fifo_name.if_dac_valid +add_connection $dac_fifo_name.if_dac_data mxfe_tx_upack.if_packed_fifo_rd_data +add_connection $dac_fifo_name.if_dac_dunf mxfe_tx_tpl.if_dac_dunf +# TX offload to dma +add_connection mxfe_tx_dma.if_m_axis_xfer_req $dac_fifo_name.if_dma_xfer_req +add_connection mxfe_tx_dma.m_axis $dac_fifo_name.s_axis +# TX dma to HPS +ad_dma_interconnect mxfe_tx_dma.m_src_axi + +# reconfiguration interface sharing + +set MAX_NUM_OF_LANES $TX_NUM_OF_LANES +if {$RX_NUM_OF_LANES > $TX_NUM_OF_LANES} { + set MAX_NUM_OF_LANES $RX_NUM_OF_LANES +} +for {set i 0} {$i < $MAX_NUM_OF_LANES} {incr i} { + add_instance avl_adxcfg_${i} avl_adxcfg + add_connection sys_clk.clk avl_adxcfg_${i}.rcfg_clk + add_connection sys_clk.clk_reset avl_adxcfg_${i}.rcfg_reset_n + add_connection avl_adxcfg_${i}.rcfg_m0 mxfe_tx_jesd204.phy_reconfig_${i} + add_connection avl_adxcfg_${i}.rcfg_m1 mxfe_rx_jesd204.phy_reconfig_${i} + + set_instance_parameter_value avl_adxcfg_${i} {ADDRESS_WIDTH} $xcvr_reconfig_addr_width + +} + +# +## address map +# + +## NOTE: if bridge is used, the address will be bridge_base_addr + peripheral_base_addr +# + +ad_cpu_interconnect 0x00020000 mxfe_rx_jesd204.link_pll_reconfig "avl_mm_bridge_0" 0x00040000 +if {$RX_NUM_OF_LANES > 0} {ad_cpu_interconnect 0x00000000 avl_adxcfg_0.rcfg_s0 "avl_mm_bridge_0"} +if {$RX_NUM_OF_LANES > 1} {ad_cpu_interconnect 0x00002000 avl_adxcfg_1.rcfg_s0 "avl_mm_bridge_0"} +if {$RX_NUM_OF_LANES > 2} {ad_cpu_interconnect 0x00004000 avl_adxcfg_2.rcfg_s0 "avl_mm_bridge_0"} +if {$RX_NUM_OF_LANES > 3} {ad_cpu_interconnect 0x00006000 avl_adxcfg_3.rcfg_s0 "avl_mm_bridge_0"} +if {$RX_NUM_OF_LANES > 4} {ad_cpu_interconnect 0x00008000 avl_adxcfg_4.rcfg_s0 "avl_mm_bridge_0"} +if {$RX_NUM_OF_LANES > 5} {ad_cpu_interconnect 0x0000A000 avl_adxcfg_5.rcfg_s0 "avl_mm_bridge_0"} +if {$RX_NUM_OF_LANES > 6} {ad_cpu_interconnect 0x0000C000 avl_adxcfg_6.rcfg_s0 "avl_mm_bridge_0"} +if {$RX_NUM_OF_LANES > 7} {ad_cpu_interconnect 0x0000E000 avl_adxcfg_7.rcfg_s0 "avl_mm_bridge_0"} + +ad_cpu_interconnect 0x00020000 mxfe_tx_jesd204.link_pll_reconfig "avl_mm_bridge_1" 0x00080000 +if {$TX_NUM_OF_LANES > 0} {ad_cpu_interconnect 0x00000000 avl_adxcfg_0.rcfg_s1 "avl_mm_bridge_1"} +if {$TX_NUM_OF_LANES > 1} {ad_cpu_interconnect 0x00002000 avl_adxcfg_1.rcfg_s1 "avl_mm_bridge_1"} +if {$TX_NUM_OF_LANES > 2} {ad_cpu_interconnect 0x00004000 avl_adxcfg_2.rcfg_s1 "avl_mm_bridge_1"} +if {$TX_NUM_OF_LANES > 3} {ad_cpu_interconnect 0x00006000 avl_adxcfg_3.rcfg_s1 "avl_mm_bridge_1"} +if {$TX_NUM_OF_LANES > 4} {ad_cpu_interconnect 0x00008000 avl_adxcfg_4.rcfg_s1 "avl_mm_bridge_1"} +if {$TX_NUM_OF_LANES > 5} {ad_cpu_interconnect 0x0000A000 avl_adxcfg_5.rcfg_s1 "avl_mm_bridge_1"} +if {$TX_NUM_OF_LANES > 6} {ad_cpu_interconnect 0x0000C000 avl_adxcfg_6.rcfg_s1 "avl_mm_bridge_1"} +if {$TX_NUM_OF_LANES > 7} {ad_cpu_interconnect 0x0000E000 avl_adxcfg_7.rcfg_s1 "avl_mm_bridge_1"} + +ad_cpu_interconnect 0x000C0000 mxfe_rx_jesd204.link_reconfig +ad_cpu_interconnect 0x000C4000 mxfe_rx_jesd204.link_management +ad_cpu_interconnect 0x000C8000 mxfe_tx_jesd204.link_reconfig +ad_cpu_interconnect 0x000CC000 mxfe_tx_jesd204.link_management +ad_cpu_interconnect 0x000D0000 mxfe_tx_jesd204.lane_pll_reconfig +ad_cpu_interconnect 0x000D2000 mxfe_rx_tpl.s_axi +ad_cpu_interconnect 0x000D4000 mxfe_tx_tpl.s_axi +ad_cpu_interconnect 0x000D8000 mxfe_rx_dma.s_axi +ad_cpu_interconnect 0x000DC000 mxfe_tx_dma.s_axi +ad_cpu_interconnect 0x000E0000 avl_mxfe_gpio.s1 + +# +## interrupts +# + +ad_cpu_interrupt 11 mxfe_rx_dma.interrupt_sender +ad_cpu_interrupt 12 mxfe_tx_dma.interrupt_sender +ad_cpu_interrupt 13 mxfe_rx_jesd204.interrupt +ad_cpu_interrupt 14 mxfe_tx_jesd204.interrupt +ad_cpu_interrupt 15 avl_mxfe_gpio.irq + +