From 0ffbe50163ac964d9c16708a626324d800274a92 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Wed, 19 Apr 2017 15:47:21 +0200 Subject: [PATCH] m2k: zed: Run video DMA at higher clock rate For the M2K standalone version we run the interface clock at a lower rate to reduce the power consumption. While this is not necessary on the ZED board we also run the interface at a lower rate for consistency. Currently the video DMA on the ZED board uses the interface clock for the data path as well. This is now too slow to support 1080p@60Hz so move it over to a faster clock. Signed-off-by: Lars-Peter Clausen --- projects/m2k/zed/system_bd.tcl | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/projects/m2k/zed/system_bd.tcl b/projects/m2k/zed/system_bd.tcl index dc673a39d..b15bd3115 100644 --- a/projects/m2k/zed/system_bd.tcl +++ b/projects/m2k/zed/system_bd.tcl @@ -2,3 +2,37 @@ source ../../common/zed/zed_system_bd.tcl source ../common/m2k_bd.tcl +# Use the 100 MHz clock for video DMA, the AXI interface clock is to slow for +# this in this project. + +set video_dma_clocks [list \ + axi_hp0_interconnect/ACLK \ + axi_hp0_interconnect/M00_ACLK \ + axi_hp0_interconnect/S00_ACLK \ + sys_ps7/S_AXI_HP0_ACLK \ + axi_hdmi_dma/m_axi_mm2s_aclk \ + axi_hdmi_dma/m_axis_mm2s_aclk \ + axi_hdmi_core/vdma_clk +] + +set video_dma_resets [list \ + axi_hp0_interconnect/ARESETN \ + axi_hp0_interconnect/M00_ARESETN \ + axi_hp0_interconnect/S00_ARESETN \ +] + +ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ 100.0 + +ad_ip_instance proc_sys_reset video_dma_reset +ad_connect sys_ps7/FCLK_CLK1 video_dma_reset/slowest_sync_clk +ad_connect sys_rstgen/peripheral_aresetn video_dma_reset/ext_reset_in + +foreach clk $video_dma_clocks { + ad_disconnect /sys_cpu_clk $clk + ad_connect $clk sys_ps7/FCLK_CLK1 +} + +foreach rst $video_dma_resets { + ad_disconnect /sys_cpu_resetn $rst + ad_connect $rst video_dma_reset/peripheral_aresetn +}