From 104e9dfcdcf1eb0084c111de9621500cbe811440 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Tue, 28 Feb 2017 13:30:50 -0500 Subject: [PATCH] adc/dac-fifo altera cores --- library/util_adcfifo/util_adcfifo_hw.tcl | 76 +++++--------- library/util_dacfifo/util_dacfifo_constr.sdc | 4 + library/util_dacfifo/util_dacfifo_hw.tcl | 34 +++++++ .../xilinx/axi_dacfifo/axi_dacfifo_constr.sdc | 14 +++ library/xilinx/axi_dacfifo/axi_dacfifo_hw.tcl | 99 +++++++++++++++++++ library/xilinx/axi_dacfifo/axi_dacfifo_ip.tcl | 1 - 6 files changed, 174 insertions(+), 54 deletions(-) create mode 100644 library/util_dacfifo/util_dacfifo_constr.sdc create mode 100755 library/util_dacfifo/util_dacfifo_hw.tcl create mode 100644 library/xilinx/axi_dacfifo/axi_dacfifo_constr.sdc create mode 100644 library/xilinx/axi_dacfifo/axi_dacfifo_hw.tcl diff --git a/library/util_adcfifo/util_adcfifo_hw.tcl b/library/util_adcfifo/util_adcfifo_hw.tcl index 73784bf58..6bccd23bd 100755 --- a/library/util_adcfifo/util_adcfifo_hw.tcl +++ b/library/util_adcfifo/util_adcfifo_hw.tcl @@ -4,63 +4,33 @@ package require -exact qsys 15.0 source ../scripts/adi_env.tcl source ../scripts/adi_ip_alt.tcl - -set_module_property NAME util_adcfifo -set_module_property DESCRIPTION "ADC FIFO utility" -set_module_property VERSION 1.0 -set_module_property GROUP "Analog Devices" -set_module_property DISPLAY_NAME util_adcfifo - -# files - -add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis" -set_fileset_property quartus_synth TOP_LEVEL util_adcfifo - -add_fileset_file ad_axis_inf_rx.v VERILOG PATH ../common/ad_axis_inf_rx.v -add_fileset_file ad_mem_asym.v VERILOG PATH ../common/ad_mem_asym.v -add_fileset_file util_adcfifo.v VERILOG PATH util_adcfifo.v TOP_LEVEL_FILE -add_fileset_file util_adcfifo_constr.sdc SDC PATH util_adcfifo_constr.sdc +ad_ip_create util_adcfifo {UTIL ADC FIFO Interface} +ad_ip_files util_adcfifo [list\ + $ad_hdl_dir/library/common/ad_mem_asym.v \ + $ad_hdl_dir/library/common/ad_axis_inf_rx.v \ + util_adcfifo.v \ + util_adcfifo_constr.sdc] # parameters -add_parameter ADC_DATA_WIDTH INTEGER 0 -set_parameter_property ADC_DATA_WIDTH DEFAULT_VALUE 256 -set_parameter_property ADC_DATA_WIDTH DISPLAY_NAME ADC_DATA_WIDTH -set_parameter_property ADC_DATA_WIDTH TYPE INTEGER -set_parameter_property ADC_DATA_WIDTH UNITS None -set_parameter_property ADC_DATA_WIDTH HDL_PARAMETER true +ad_ip_parameter DEVICE_FAMILY STRING {Arria 10} +ad_ip_parameter ADC_DATA_WIDTH INTEGER 256 +ad_ip_parameter DMA_DATA_WIDTH INTEGER 64 +ad_ip_parameter DMA_READY_ENABLE INTEGER 1 +ad_ip_parameter DMA_ADDRESS_WIDTH INTEGER 10 -add_parameter DMA_DATA_WIDTH INTEGER 0 -set_parameter_property DMA_DATA_WIDTH DEFAULT_VALUE 64 -set_parameter_property DMA_DATA_WIDTH DISPLAY_NAME DMA_DATA_WIDTH -set_parameter_property DMA_DATA_WIDTH TYPE INTEGER -set_parameter_property DMA_DATA_WIDTH UNITS None -set_parameter_property DMA_DATA_WIDTH HDL_PARAMETER true +# interfaces -add_parameter DMA_READY_ENABLE INTEGER 0 -set_parameter_property DMA_READY_ENABLE DEFAULT_VALUE 1 -set_parameter_property DMA_READY_ENABLE DISPLAY_NAME DMA_READY_ENABLE -set_parameter_property DMA_READY_ENABLE TYPE INTEGER -set_parameter_property DMA_READY_ENABLE UNITS None -set_parameter_property DMA_READY_ENABLE HDL_PARAMETER true +ad_alt_intf clock adc_clk input 1 adc_clk +ad_alt_intf reset adc_rst input 1 if_adc_clk +ad_alt_intf signal adc_wr input 1 valid +ad_alt_intf signal adc_wdata input ADC_DATA_WIDTH data +ad_alt_intf signal adc_wovf output 1 ovf -add_parameter DMA_ADDRESS_WIDTH INTEGER 0 -set_parameter_property DMA_ADDRESS_WIDTH DEFAULT_VALUE 10 -set_parameter_property DMA_ADDRESS_WIDTH DISPLAY_NAME DMA_ADDRESS_WIDTH -set_parameter_property DMA_ADDRESS_WIDTH TYPE INTEGER -set_parameter_property DMA_ADDRESS_WIDTH UNITS None -set_parameter_property DMA_ADDRESS_WIDTH HDL_PARAMETER true +ad_alt_intf clock dma_clk input 1 clk +ad_alt_intf signal dma_wr output 1 valid +ad_alt_intf signal dma_wdata output DMA_DATA_WIDTH data +ad_alt_intf signal dma_wready input 1 ready +ad_alt_intf signal dma_xfer_req input 1 xfer_req +ad_alt_intf signal dma_xfer_status output 4 xfer_status -# defaults - -ad_alt_intf clock adc_clk input 1 adc_clk -ad_alt_intf reset adc_rst input 1 if_adc_clk -ad_alt_intf signal adc_wr input 1 valid -ad_alt_intf signal adc_wdata input ADC_DATA_WIDTH data -ad_alt_intf signal adc_wovf output 1 ovf - -ad_alt_intf clock dma_clk input 1 clk -ad_alt_intf signal dma_wr output 1 valid -ad_alt_intf signal dma_wdata output DMA_DATA_WIDTH data -ad_alt_intf signal dma_wready input 1 ready -ad_alt_intf signal dma_xfer_req input 1 xfer_req diff --git a/library/util_dacfifo/util_dacfifo_constr.sdc b/library/util_dacfifo/util_dacfifo_constr.sdc new file mode 100644 index 000000000..d4df2aa2b --- /dev/null +++ b/library/util_dacfifo/util_dacfifo_constr.sdc @@ -0,0 +1,4 @@ + +set_false_path -from [get_registers *dma_lastaddr_reg*] -to [get_registers *dac_lastaddr_d_reg*] +set_false_path -to [get_registers *dac_xfer_out_m_reg[0]*] + diff --git a/library/util_dacfifo/util_dacfifo_hw.tcl b/library/util_dacfifo/util_dacfifo_hw.tcl new file mode 100755 index 000000000..7d40fb6e4 --- /dev/null +++ b/library/util_dacfifo/util_dacfifo_hw.tcl @@ -0,0 +1,34 @@ + +package require -exact qsys 13.0 +source ../scripts/adi_env.tcl +source ../scripts/adi_ip_alt.tcl + +ad_ip_create util_dacfifo {UTIL DAC FIFO Interface} +ad_ip_files util_dacfifo [list\ + $ad_hdl_dir/library/common/ad_mem.v \ + util_dacfifo.v \ + util_dacfifo_constr.sdc] + +# parameters + +ad_ip_parameter DEVICE_FAMILY STRING {Arria 10} +ad_ip_parameter ADDRESS_WIDTH INTEGER 6 +ad_ip_parameter DATA_WIDTH INTEGER 128 + +# interfaces + +ad_alt_intf clock dma_clk input 1 clk +ad_alt_intf reset dma_rst input 1 if_dma_clk +ad_alt_intf signal dma_valid input 1 valid +ad_alt_intf signal dma_data input DATA_WIDTH data +ad_alt_intf signal dma_ready output 1 ready +ad_alt_intf signal dma_xfer_req input 1 xfer_req +ad_alt_intf signal dma_xfer_last input 1 last + +ad_alt_intf clock dac_clk input 1 +ad_alt_intf signal dac_valid input 1 valid +ad_alt_intf signal dac_data output DATA_WIDTH data +ad_alt_intf signal dac_xfer_out output 1 xfer_req + +ad_alt_intf signal bypass input 1 bypass + diff --git a/library/xilinx/axi_dacfifo/axi_dacfifo_constr.sdc b/library/xilinx/axi_dacfifo/axi_dacfifo_constr.sdc new file mode 100644 index 000000000..49ef19dbb --- /dev/null +++ b/library/xilinx/axi_dacfifo/axi_dacfifo_constr.sdc @@ -0,0 +1,14 @@ + +set_false_path -to [get_registers *_xfer_req_m*[0]*] +set_false_path -to [get_registers *_xfer_last_m*[0]*] +set_false_path -to [get_registers *dac_xfer_out_m1*] +set_false_path -to [get_registers *_bypass_m1*] +set_false_path -to [get_registers *dma_rst_m1*] + +set_false_path -from [get_registers *dma_*] -to [get_registers *axi_*_m*] +set_false_path -from [get_registers *axi_*] -to [get_registers *dma_*_m*] +set_false_path -from [get_registers *dac_*] -to [get_registers *axi_*_m*] +set_false_path -from [get_registers *axi_*] -to [get_registers *dac_*_m*] +set_false_path -from [get_registers *dac_*] -to [get_registers *dma_*_m*] +set_false_path -from [get_registers *dma_*] -to [get_registers *dac_*_m*] + diff --git a/library/xilinx/axi_dacfifo/axi_dacfifo_hw.tcl b/library/xilinx/axi_dacfifo/axi_dacfifo_hw.tcl new file mode 100644 index 000000000..9db720356 --- /dev/null +++ b/library/xilinx/axi_dacfifo/axi_dacfifo_hw.tcl @@ -0,0 +1,99 @@ + +package require -exact qsys 13.0 +source ../../scripts/adi_env.tcl +source ../../scripts/adi_ip_alt.tcl + +ad_ip_create axi_dacfifo {AXI DAC FIFO Interface} +ad_ip_files axi_dacfifo [list\ + $ad_hdl_dir/library/common/ad_mem_asym.v \ + $ad_hdl_dir/library/common/ad_axis_inf_rx.v \ + axi_dacfifo_dac.v \ + axi_dacfifo_wr.v \ + axi_dacfifo_rd.v \ + axi_dacfifo_bypass.v \ + axi_dacfifo.v \ + axi_dacfifo_constr.sdc] + +# parameters + +ad_ip_parameter DEVICE_FAMILY STRING {Arria 10} +ad_ip_parameter DAC_DATA_WIDTH INTEGER 64 +ad_ip_parameter DMA_DATA_WIDTH INTEGER 64 +ad_ip_parameter AXI_DATA_WIDTH INTEGER 512 +ad_ip_parameter AXI_SIZE INTEGER 2 +ad_ip_parameter AXI_LENGTH INTEGER 15 +ad_ip_parameter AXI_ADDRESS INTEGER 0 +ad_ip_parameter AXI_ADDRESS_LIMIT INTEGER -1 + +# interfaces + +ad_alt_intf clock dma_clk input 1 clk +ad_alt_intf signal dma_valid input 1 valid +ad_alt_intf signal dma_data input DMA_DATA_WIDTH data +ad_alt_intf signal dma_ready output 1 ready +ad_alt_intf signal dma_xfer_req input 1 xfer_req +ad_alt_intf signal dma_xfer_last input 1 last + +ad_alt_intf clock dac_clk input 1 +ad_alt_intf reset dac_rst input 1 if_dac_clk +ad_alt_intf signal dac_valid input 1 valid +ad_alt_intf signal dac_data output DAC_DATA_WIDTH data +ad_alt_intf signal dac_dunf output 1 unf +ad_alt_intf signal dac_xfer_out output 1 xfer_req + +ad_alt_intf signal bypass input 1 bypass + +add_interface axi_clock clock end +add_interface_port axi_clock axi_clk clk input 1 + +add_interface axi_reset_n reset end +set_interface_property axi_reset_n associatedclock axi_clock +add_interface_port axi_reset_n axi_resetn reset_n input 1 + +add_interface m_axi axi4 start +add_interface_port m_axi axi_awvalid awvalid output 1 +add_interface_port m_axi axi_awid awid output 4 +add_interface_port m_axi axi_awburst awburst output 2 +add_interface_port m_axi axi_awlock awlock output 1 +add_interface_port m_axi axi_awcache awcache output 4 +add_interface_port m_axi axi_awprot awprot output 3 +add_interface_port m_axi axi_awqos awqos output 4 +add_interface_port m_axi axi_awuser awuser output 4 +add_interface_port m_axi axi_awlen awlen output 8 +add_interface_port m_axi axi_awsize awsize output 3 +add_interface_port m_axi axi_awaddr awaddr output 32 +add_interface_port m_axi axi_awready awready input 1 +add_interface_port m_axi axi_wvalid wvalid output 1 +add_interface_port m_axi axi_wdata wdata output AXI_DATA_WIDTH +add_interface_port m_axi axi_wstrb wstrb output AXI_DATA_WIDTH/8 +add_interface_port m_axi axi_wlast wlast output 1 +add_interface_port m_axi axi_wready wready input 1 +add_interface_port m_axi axi_bvalid bvalid input 1 +add_interface_port m_axi axi_bid bid input 4 +add_interface_port m_axi axi_bresp bresp input 2 +add_interface_port m_axi axi_buser buser input 4 +add_interface_port m_axi axi_bready bready output 1 +add_interface_port m_axi axi_arvalid arvalid output 1 +add_interface_port m_axi axi_arid arid output 4 +add_interface_port m_axi axi_arburst arburst output 2 +add_interface_port m_axi axi_arlock arlock output 1 +add_interface_port m_axi axi_arcache arcache output 4 +add_interface_port m_axi axi_arprot arprot output 3 +add_interface_port m_axi axi_arqos arqos output 4 +add_interface_port m_axi axi_aruser aruser output 4 +add_interface_port m_axi axi_arlen arlen output 8 +add_interface_port m_axi axi_arsize arsize output 3 +add_interface_port m_axi axi_araddr araddr output 32 +add_interface_port m_axi axi_arready arready input 1 +add_interface_port m_axi axi_rvalid rvalid input 1 +add_interface_port m_axi axi_rid rid input 4 +add_interface_port m_axi axi_ruser ruser input 4 +add_interface_port m_axi axi_rresp rresp input 2 +add_interface_port m_axi axi_rlast rlast input 1 +add_interface_port m_axi axi_rdata rdata input AXI_DATA_WIDTH +add_interface_port m_axi axi_rready rready output 1 + +set_interface_property m_axi associatedclock axi_clock +set_interface_property m_axi associatedreset axi_reset_n + + diff --git a/library/xilinx/axi_dacfifo/axi_dacfifo_ip.tcl b/library/xilinx/axi_dacfifo/axi_dacfifo_ip.tcl index 0bb293baa..1241c24ea 100644 --- a/library/xilinx/axi_dacfifo/axi_dacfifo_ip.tcl +++ b/library/xilinx/axi_dacfifo/axi_dacfifo_ip.tcl @@ -8,7 +8,6 @@ adi_ip_create axi_dacfifo adi_ip_files axi_dacfifo [list \ "$ad_hdl_dir/library/common/ad_mem_asym.v" \ "$ad_hdl_dir/library/common/ad_axis_inf_rx.v" \ - "$ad_hdl_dir/library/util_axis_resize/util_axis_resize.v" \ "axi_dacfifo_constr.xdc" \ "axi_dacfifo_dac.v" \ "axi_dacfifo_wr.v" \