adc/dac-fifo altera cores
Rejeesh Kutty
parent
59dda01419
commit
104e9dfcdc
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@ -4,54 +4,22 @@ package require -exact qsys 15.0
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source ../scripts/adi_env.tcl
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source ../scripts/adi_ip_alt.tcl
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set_module_property NAME util_adcfifo
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set_module_property DESCRIPTION "ADC FIFO utility"
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set_module_property VERSION 1.0
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set_module_property GROUP "Analog Devices"
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set_module_property DISPLAY_NAME util_adcfifo
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# files
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add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
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set_fileset_property quartus_synth TOP_LEVEL util_adcfifo
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add_fileset_file ad_axis_inf_rx.v VERILOG PATH ../common/ad_axis_inf_rx.v
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add_fileset_file ad_mem_asym.v VERILOG PATH ../common/ad_mem_asym.v
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add_fileset_file util_adcfifo.v VERILOG PATH util_adcfifo.v TOP_LEVEL_FILE
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add_fileset_file util_adcfifo_constr.sdc SDC PATH util_adcfifo_constr.sdc
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ad_ip_create util_adcfifo {UTIL ADC FIFO Interface}
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ad_ip_files util_adcfifo [list\
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$ad_hdl_dir/library/common/ad_mem_asym.v \
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$ad_hdl_dir/library/common/ad_axis_inf_rx.v \
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util_adcfifo.v \
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util_adcfifo_constr.sdc]
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# parameters
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add_parameter ADC_DATA_WIDTH INTEGER 0
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set_parameter_property ADC_DATA_WIDTH DEFAULT_VALUE 256
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set_parameter_property ADC_DATA_WIDTH DISPLAY_NAME ADC_DATA_WIDTH
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set_parameter_property ADC_DATA_WIDTH TYPE INTEGER
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set_parameter_property ADC_DATA_WIDTH UNITS None
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set_parameter_property ADC_DATA_WIDTH HDL_PARAMETER true
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ad_ip_parameter DEVICE_FAMILY STRING {Arria 10}
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ad_ip_parameter ADC_DATA_WIDTH INTEGER 256
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ad_ip_parameter DMA_DATA_WIDTH INTEGER 64
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ad_ip_parameter DMA_READY_ENABLE INTEGER 1
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ad_ip_parameter DMA_ADDRESS_WIDTH INTEGER 10
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add_parameter DMA_DATA_WIDTH INTEGER 0
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set_parameter_property DMA_DATA_WIDTH DEFAULT_VALUE 64
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set_parameter_property DMA_DATA_WIDTH DISPLAY_NAME DMA_DATA_WIDTH
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set_parameter_property DMA_DATA_WIDTH TYPE INTEGER
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set_parameter_property DMA_DATA_WIDTH UNITS None
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set_parameter_property DMA_DATA_WIDTH HDL_PARAMETER true
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add_parameter DMA_READY_ENABLE INTEGER 0
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set_parameter_property DMA_READY_ENABLE DEFAULT_VALUE 1
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set_parameter_property DMA_READY_ENABLE DISPLAY_NAME DMA_READY_ENABLE
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set_parameter_property DMA_READY_ENABLE TYPE INTEGER
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set_parameter_property DMA_READY_ENABLE UNITS None
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set_parameter_property DMA_READY_ENABLE HDL_PARAMETER true
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add_parameter DMA_ADDRESS_WIDTH INTEGER 0
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set_parameter_property DMA_ADDRESS_WIDTH DEFAULT_VALUE 10
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set_parameter_property DMA_ADDRESS_WIDTH DISPLAY_NAME DMA_ADDRESS_WIDTH
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set_parameter_property DMA_ADDRESS_WIDTH TYPE INTEGER
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set_parameter_property DMA_ADDRESS_WIDTH UNITS None
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set_parameter_property DMA_ADDRESS_WIDTH HDL_PARAMETER true
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# defaults
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# interfaces
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ad_alt_intf clock adc_clk input 1 adc_clk
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ad_alt_intf reset adc_rst input 1 if_adc_clk
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@ -64,3 +32,5 @@ ad_alt_intf signal dma_wr output 1 valid
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ad_alt_intf signal dma_wdata output DMA_DATA_WIDTH data
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ad_alt_intf signal dma_wready input 1 ready
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ad_alt_intf signal dma_xfer_req input 1 xfer_req
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ad_alt_intf signal dma_xfer_status output 4 xfer_status
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@ -0,0 +1,4 @@
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set_false_path -from [get_registers *dma_lastaddr_reg*] -to [get_registers *dac_lastaddr_d_reg*]
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set_false_path -to [get_registers *dac_xfer_out_m_reg[0]*]
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@ -0,0 +1,34 @@
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package require -exact qsys 13.0
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source ../scripts/adi_env.tcl
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source ../scripts/adi_ip_alt.tcl
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ad_ip_create util_dacfifo {UTIL DAC FIFO Interface}
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ad_ip_files util_dacfifo [list\
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$ad_hdl_dir/library/common/ad_mem.v \
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util_dacfifo.v \
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util_dacfifo_constr.sdc]
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# parameters
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ad_ip_parameter DEVICE_FAMILY STRING {Arria 10}
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ad_ip_parameter ADDRESS_WIDTH INTEGER 6
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ad_ip_parameter DATA_WIDTH INTEGER 128
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# interfaces
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ad_alt_intf clock dma_clk input 1 clk
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ad_alt_intf reset dma_rst input 1 if_dma_clk
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ad_alt_intf signal dma_valid input 1 valid
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ad_alt_intf signal dma_data input DATA_WIDTH data
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ad_alt_intf signal dma_ready output 1 ready
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ad_alt_intf signal dma_xfer_req input 1 xfer_req
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ad_alt_intf signal dma_xfer_last input 1 last
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ad_alt_intf clock dac_clk input 1
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ad_alt_intf signal dac_valid input 1 valid
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ad_alt_intf signal dac_data output DATA_WIDTH data
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ad_alt_intf signal dac_xfer_out output 1 xfer_req
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ad_alt_intf signal bypass input 1 bypass
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@ -0,0 +1,14 @@
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set_false_path -to [get_registers *_xfer_req_m*[0]*]
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set_false_path -to [get_registers *_xfer_last_m*[0]*]
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set_false_path -to [get_registers *dac_xfer_out_m1*]
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set_false_path -to [get_registers *_bypass_m1*]
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set_false_path -to [get_registers *dma_rst_m1*]
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set_false_path -from [get_registers *dma_*] -to [get_registers *axi_*_m*]
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set_false_path -from [get_registers *axi_*] -to [get_registers *dma_*_m*]
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set_false_path -from [get_registers *dac_*] -to [get_registers *axi_*_m*]
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set_false_path -from [get_registers *axi_*] -to [get_registers *dac_*_m*]
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set_false_path -from [get_registers *dac_*] -to [get_registers *dma_*_m*]
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set_false_path -from [get_registers *dma_*] -to [get_registers *dac_*_m*]
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@ -0,0 +1,99 @@
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package require -exact qsys 13.0
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source ../../scripts/adi_env.tcl
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source ../../scripts/adi_ip_alt.tcl
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ad_ip_create axi_dacfifo {AXI DAC FIFO Interface}
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ad_ip_files axi_dacfifo [list\
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$ad_hdl_dir/library/common/ad_mem_asym.v \
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$ad_hdl_dir/library/common/ad_axis_inf_rx.v \
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axi_dacfifo_dac.v \
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axi_dacfifo_wr.v \
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axi_dacfifo_rd.v \
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axi_dacfifo_bypass.v \
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axi_dacfifo.v \
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axi_dacfifo_constr.sdc]
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# parameters
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ad_ip_parameter DEVICE_FAMILY STRING {Arria 10}
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ad_ip_parameter DAC_DATA_WIDTH INTEGER 64
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ad_ip_parameter DMA_DATA_WIDTH INTEGER 64
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ad_ip_parameter AXI_DATA_WIDTH INTEGER 512
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ad_ip_parameter AXI_SIZE INTEGER 2
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ad_ip_parameter AXI_LENGTH INTEGER 15
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ad_ip_parameter AXI_ADDRESS INTEGER 0
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ad_ip_parameter AXI_ADDRESS_LIMIT INTEGER -1
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# interfaces
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ad_alt_intf clock dma_clk input 1 clk
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ad_alt_intf signal dma_valid input 1 valid
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ad_alt_intf signal dma_data input DMA_DATA_WIDTH data
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ad_alt_intf signal dma_ready output 1 ready
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ad_alt_intf signal dma_xfer_req input 1 xfer_req
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ad_alt_intf signal dma_xfer_last input 1 last
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ad_alt_intf clock dac_clk input 1
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ad_alt_intf reset dac_rst input 1 if_dac_clk
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ad_alt_intf signal dac_valid input 1 valid
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ad_alt_intf signal dac_data output DAC_DATA_WIDTH data
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ad_alt_intf signal dac_dunf output 1 unf
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ad_alt_intf signal dac_xfer_out output 1 xfer_req
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ad_alt_intf signal bypass input 1 bypass
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add_interface axi_clock clock end
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add_interface_port axi_clock axi_clk clk input 1
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add_interface axi_reset_n reset end
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set_interface_property axi_reset_n associatedclock axi_clock
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add_interface_port axi_reset_n axi_resetn reset_n input 1
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add_interface m_axi axi4 start
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add_interface_port m_axi axi_awvalid awvalid output 1
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add_interface_port m_axi axi_awid awid output 4
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add_interface_port m_axi axi_awburst awburst output 2
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add_interface_port m_axi axi_awlock awlock output 1
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add_interface_port m_axi axi_awcache awcache output 4
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add_interface_port m_axi axi_awprot awprot output 3
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add_interface_port m_axi axi_awqos awqos output 4
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add_interface_port m_axi axi_awuser awuser output 4
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add_interface_port m_axi axi_awlen awlen output 8
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add_interface_port m_axi axi_awsize awsize output 3
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add_interface_port m_axi axi_awaddr awaddr output 32
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add_interface_port m_axi axi_awready awready input 1
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add_interface_port m_axi axi_wvalid wvalid output 1
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add_interface_port m_axi axi_wdata wdata output AXI_DATA_WIDTH
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add_interface_port m_axi axi_wstrb wstrb output AXI_DATA_WIDTH/8
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add_interface_port m_axi axi_wlast wlast output 1
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add_interface_port m_axi axi_wready wready input 1
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add_interface_port m_axi axi_bvalid bvalid input 1
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add_interface_port m_axi axi_bid bid input 4
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add_interface_port m_axi axi_bresp bresp input 2
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add_interface_port m_axi axi_buser buser input 4
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add_interface_port m_axi axi_bready bready output 1
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add_interface_port m_axi axi_arvalid arvalid output 1
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add_interface_port m_axi axi_arid arid output 4
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add_interface_port m_axi axi_arburst arburst output 2
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add_interface_port m_axi axi_arlock arlock output 1
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add_interface_port m_axi axi_arcache arcache output 4
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add_interface_port m_axi axi_arprot arprot output 3
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add_interface_port m_axi axi_arqos arqos output 4
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add_interface_port m_axi axi_aruser aruser output 4
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add_interface_port m_axi axi_arlen arlen output 8
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add_interface_port m_axi axi_arsize arsize output 3
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add_interface_port m_axi axi_araddr araddr output 32
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add_interface_port m_axi axi_arready arready input 1
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add_interface_port m_axi axi_rvalid rvalid input 1
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add_interface_port m_axi axi_rid rid input 4
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add_interface_port m_axi axi_ruser ruser input 4
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add_interface_port m_axi axi_rresp rresp input 2
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add_interface_port m_axi axi_rlast rlast input 1
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add_interface_port m_axi axi_rdata rdata input AXI_DATA_WIDTH
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add_interface_port m_axi axi_rready rready output 1
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set_interface_property m_axi associatedclock axi_clock
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set_interface_property m_axi associatedreset axi_reset_n
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@ -8,7 +8,6 @@ adi_ip_create axi_dacfifo
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adi_ip_files axi_dacfifo [list \
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"$ad_hdl_dir/library/common/ad_mem_asym.v" \
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"$ad_hdl_dir/library/common/ad_axis_inf_rx.v" \
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"$ad_hdl_dir/library/util_axis_resize/util_axis_resize.v" \
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"axi_dacfifo_constr.xdc" \
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"axi_dacfifo_dac.v" \
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"axi_dacfifo_wr.v" \
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