axi_dmac: Add Cache Coherency support

This commit implements Cache Coherency through dedicated parameters.

The AxCACHE/AxPROT parameters are automatically set to the most commonly
used values unless otherwise specified. Their default values are:
AxCACHE = CACHE_COHERENT ? 4'b1111 : 4'b0011
AxPROT  = CACHE_COHERENT ? 3'b010  : 3'b000

If Cache Coherency is enabled, the AxCACHE/AxPROT values can be changed
to support systems with different caching policies.

Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>

library/axi_dmac/address_generator.v

@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -43,7 +43,8 @@ module address_generator #(
   parameter BEATS_PER_BURST_WIDTH = 4,
   parameter BYTES_PER_BEAT_WIDTH = $clog2(DMA_DATA_WIDTH/8),
   parameter LENGTH_WIDTH = 8,
-  parameter CACHE_COHERENT = 0
+  parameter [3:0] AXI_AXCACHE = 4'b0011,
+  parameter [2:0] AXI_AXPROT = 3'b000
 ) (
   input                        clk,
   input                        resetn,
@@ -80,10 +81,8 @@ module address_generator #(
 `include "inc_id.vh"
 
   assign burst = 2'b01;
-  assign prot = 3'b000;
+  assign prot = AXI_AXPROT;
-  // If CACHE_COHERENT is set, signal downstream that this transaction must be
+  assign cache = AXI_AXCACHE;
-  // looked up in cache. Otherwise default to "normal non-cachable bufferable".
-  assign cache = CACHE_COHERENT ? 4'b1110 : 4'b0011;
   assign size = DMA_DATA_WIDTH == 1024 ? 3'b111 :
                 DMA_DATA_WIDTH ==  512 ? 3'b110 :
                 DMA_DATA_WIDTH ==  256 ? 3'b101 :

library/axi_dmac/axi_dmac.v

@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -70,7 +70,9 @@ module axi_dmac #(
   parameter DISABLE_DEBUG_REGISTERS = 0,
   parameter ENABLE_DIAGNOSTICS_IF = 0,
   parameter ALLOW_ASYM_MEM = 0,
-  parameter CACHE_COHERENT_DEST = 0
+  parameter CACHE_COHERENT = 0,
+  parameter [3:0] AXI_AXCACHE = 4'b0011,
+  parameter [2:0] AXI_AXPROT = 3'b000
 ) (
 
   // Slave AXI interface
@@ -447,7 +449,9 @@ module axi_dmac #(
     .DMA_2D_TRANSFER(DMA_2D_TRANSFER),
     .DMA_SG_TRANSFER(DMA_SG_TRANSFER),
     .SYNC_TRANSFER_START(SYNC_TRANSFER_START),
-    .CACHE_COHERENT_DEST(CACHE_COHERENT_DEST)
+    .CACHE_COHERENT(CACHE_COHERENT),
+    .AXI_AXCACHE(AXI_AXCACHE),
+    .AXI_AXPROT(AXI_AXPROT)
   ) i_regmap (
     .s_axi_aclk(s_axi_aclk),
     .s_axi_aresetn(s_axi_aresetn),
@@ -537,7 +541,8 @@ module axi_dmac #(
     .AXI_LENGTH_WIDTH_SG(8-(4*DMA_AXI_PROTOCOL_SG)),
     .ENABLE_DIAGNOSTICS_IF(ENABLE_DIAGNOSTICS_IF),
     .ALLOW_ASYM_MEM(ALLOW_ASYM_MEM),
-    .CACHE_COHERENT_DEST(CACHE_COHERENT_DEST)
+    .AXI_AXCACHE(AXI_AXCACHE),
+    .AXI_AXPROT(AXI_AXPROT)
   ) i_transfer (
     .ctrl_clk(s_axi_aclk),
     .ctrl_resetn(s_axi_aresetn),

library/axi_dmac/axi_dmac_hw.tcl

@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
@@ -92,6 +92,46 @@ set_parameter_property DMA_AXI_ADDR_WIDTH HDL_PARAMETER true
 set_parameter_property DMA_AXI_ADDR_WIDTH ALLOWED_RANGES {16:64}
 set_parameter_property DMA_AXI_ADDR_WIDTH GROUP $group
 
+add_parameter AXI_AXCACHE_AUTO BOOLEAN 1
+set_parameter_property AXI_AXCACHE_AUTO DISPLAY_NAME "ARCACHE/AWCACHE Automatically Set"
+set_parameter_property AXI_AXCACHE_AUTO HDL_PARAMETER false
+set_parameter_property AXI_AXCACHE_AUTO GROUP $group
+
+add_parameter AXI_AXPROT_AUTO BOOLEAN 1
+set_parameter_property AXI_AXPROT_AUTO DISPLAY_NAME "ARPROT/AWPROT Automatically Set"
+set_parameter_property AXI_AXPROT_AUTO HDL_PARAMETER false
+set_parameter_property AXI_AXPROT_AUTO GROUP $group
+
+add_parameter AXI_AXCACHE_MANUAL STD_LOGIC_VECTOR
+set_parameter_property AXI_AXCACHE_MANUAL WIDTH 4
+set_parameter_property AXI_AXCACHE_MANUAL DISPLAY_NAME "ARCACHE/AWCACHE"
+set_parameter_property AXI_AXCACHE_MANUAL HDL_PARAMETER false
+set_parameter_property AXI_AXCACHE_MANUAL ALLOWED_RANGES {0x0:0xF}
+set_parameter_property AXI_AXCACHE_MANUAL GROUP $group
+
+add_parameter AXI_AXPROT_MANUAL STD_LOGIC_VECTOR
+set_parameter_property AXI_AXPROT_MANUAL WIDTH 3
+set_parameter_property AXI_AXPROT_MANUAL DISPLAY_NAME "ARPROT/AWPROT"
+set_parameter_property AXI_AXPROT_MANUAL HDL_PARAMETER false
+set_parameter_property AXI_AXPROT_MANUAL ALLOWED_RANGES {0x0:0x7}
+set_parameter_property AXI_AXPROT_MANUAL GROUP $group
+
+add_parameter AXI_AXCACHE STD_LOGIC_VECTOR
+set_parameter_property AXI_AXCACHE WIDTH 4
+set_parameter_property AXI_AXCACHE DISPLAY_NAME "ARCACHE/AWCACHE"
+set_parameter_property AXI_AXCACHE HDL_PARAMETER true
+set_parameter_property AXI_AXCACHE ALLOWED_RANGES {0x0:0xF}
+set_parameter_property AXI_AXCACHE DERIVED true
+set_parameter_property AXI_AXCACHE GROUP $group
+
+add_parameter AXI_AXPROT STD_LOGIC_VECTOR
+set_parameter_property AXI_AXPROT WIDTH 3
+set_parameter_property AXI_AXPROT DISPLAY_NAME "ARPROT/AWPROT"
+set_parameter_property AXI_AXPROT HDL_PARAMETER true
+set_parameter_property AXI_AXPROT ALLOWED_RANGES {0x0:0x7}
+set_parameter_property AXI_AXPROT DERIVED true
+set_parameter_property AXI_AXPROT GROUP $group
+
 foreach {suffix group} { \
     "SRC" "Source" \
     "DEST" "Destination" \
@@ -153,24 +193,31 @@ set_parameter_property CYCLIC DISPLAY_HINT boolean
 set_parameter_property CYCLIC HDL_PARAMETER true
 set_parameter_property CYCLIC GROUP $group
 
-add_parameter DMA_2D_TRANSFER INTEGER 0
-set_parameter_property DMA_2D_TRANSFER DISPLAY_NAME "2D Transfer Support"
-set_parameter_property DMA_2D_TRANSFER DISPLAY_HINT boolean
-set_parameter_property DMA_2D_TRANSFER HDL_PARAMETER true
-set_parameter_property DMA_2D_TRANSFER GROUP $group
-
 add_parameter DMA_SG_TRANSFER INTEGER 0
 set_parameter_property DMA_SG_TRANSFER DISPLAY_NAME "SG Transfer Support"
 set_parameter_property DMA_SG_TRANSFER DISPLAY_HINT boolean
 set_parameter_property DMA_SG_TRANSFER HDL_PARAMETER true
 set_parameter_property DMA_SG_TRANSFER GROUP $group
 
+add_parameter DMA_2D_TRANSFER INTEGER 0
+set_parameter_property DMA_2D_TRANSFER DISPLAY_NAME "2D Transfer Support"
+set_parameter_property DMA_2D_TRANSFER DISPLAY_HINT boolean
+set_parameter_property DMA_2D_TRANSFER HDL_PARAMETER true
+set_parameter_property DMA_2D_TRANSFER GROUP $group
+
 add_parameter SYNC_TRANSFER_START INTEGER 0
 set_parameter_property SYNC_TRANSFER_START DISPLAY_NAME "Transfer Start Synchronization Support"
 set_parameter_property SYNC_TRANSFER_START DISPLAY_HINT boolean
 set_parameter_property SYNC_TRANSFER_START HDL_PARAMETER true
 set_parameter_property SYNC_TRANSFER_START GROUP $group
 
+add_parameter CACHE_COHERENT BOOLEAN 0
+set_parameter_property CACHE_COHERENT DISPLAY_NAME "Cache Coherent"
+set_parameter_property CACHE_COHERENT DESCRIPTION "Assume DMA ports ensure cache coherence"
+set_parameter_property CACHE_COHERENT DISPLAY_HINT boolean
+set_parameter_property CACHE_COHERENT HDL_PARAMETER true
+set_parameter_property CACHE_COHERENT GROUP $group
+
 set group "Clock Domain Configuration"
 
 add_parameter AUTO_ASYNC_CLK BOOLEAN 1
@@ -328,6 +375,26 @@ proc axi_dmac_validate {} {
   }
 
   set_parameter_property MAX_BYTES_PER_BURST ALLOWED_RANGES "1:$max_burst"
+
+  set cache_coherent [get_parameter_value CACHE_COHERENT]
+  set axcache_auto [get_parameter_value AXI_AXCACHE_AUTO]
+  set axprot_auto [get_parameter_value AXI_AXPROT_AUTO]
+  set axcache_manual [get_parameter_value AXI_AXCACHE_MANUAL]
+  set axprot_manual [get_parameter_value AXI_AXPROT_MANUAL]
+  set axcache_default [expr {$cache_coherent == true} ? 0xF : 0x3]
+  set axprot_default [expr {$cache_coherent == true} ? 0x2 : 0x0]
+
+  set_parameter_property AXI_AXCACHE_AUTO ENABLED $cache_coherent
+  set_parameter_property AXI_AXPROT_AUTO ENABLED $cache_coherent
+  set_parameter_property AXI_AXCACHE_MANUAL ENABLED $cache_coherent
+  set_parameter_property AXI_AXPROT_MANUAL ENABLED $cache_coherent
+  set_parameter_property AXI_AXCACHE_MANUAL VISIBLE [expr {$cache_coherent == true} ? [expr {$axcache_auto == true} ? false : true] : false]
+  set_parameter_property AXI_AXPROT_MANUAL VISIBLE [expr {$cache_coherent == true} ? [expr {$axprot_auto == true} ? false : true] : false]
+  set_parameter_property AXI_AXCACHE VISIBLE [expr {$cache_coherent == true} ? $axcache_auto : true]
+  set_parameter_property AXI_AXPROT VISIBLE [expr {$cache_coherent == true} ? $axprot_auto : true]
+
+  set_parameter_value AXI_AXCACHE [expr {$cache_coherent == true} ? [expr {$axcache_auto == true} ? $axcache_default : $axcache_manual] : $axcache_default]
+  set_parameter_value AXI_AXPROT [expr {$cache_coherent == true} ? [expr {$axprot_auto == true} ? $axprot_default : $axprot_manual]  : $axprot_default]
 }
 
 # conditional interfaces

library/axi_dmac/axi_dmac_ip.tcl

@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
@@ -274,14 +274,14 @@ foreach {k v} { \
         "ASYNC_CLK_SRC_SG" "true" \
         "ASYNC_CLK_DEST_SG" "true" \
         "CYCLIC" "false" \
-        "DMA_2D_TRANSFER" "false" \
         "DMA_SG_TRANSFER" "false" \
+        "DMA_2D_TRANSFER" "false" \
         "SYNC_TRANSFER_START" "false" \
         "AXI_SLICE_SRC" "false" \
         "AXI_SLICE_DEST" "false" \
         "DISABLE_DEBUG_REGISTERS" "false" \
         "ENABLE_DIAGNOSTICS_IF" "false" \
-        "CACHE_COHERENT_DEST" "false" \
+        "CACHE_COHERENT" "false" \
 	} { \
 	set_property -dict [list \
 			"value_format" "bool" \
@@ -369,18 +369,6 @@ set_property -dict [list \
 	"enablement_tcl_expr" "\$DMA_TYPE_SRC != 0" \
 ] [ipx::get_user_parameters SYNC_TRANSFER_START -of_objects $cc]
 
-set p [ipgui::get_guiparamspec -name "CACHE_COHERENT_DEST" -component $cc]
-ipgui::move_param -component $cc -order 4 $p -parent $dest_group
-set_property -dict [list \
-	"tooltip" "Assume destination port ensures cache coherency (e.g. Ultrascale HPC port)" \
-] $p
-set_property -dict [list \
-	"display_name" "Assume cache coherent" \
-	"enablement_tcl_expr" "\$DMA_TYPE_DEST == 0 && \$DMA_AXI_PROTOCOL_DEST == 0" \
-	"value_tcl_expr" "\$DMA_TYPE_DEST == 0 && \$DMA_AXI_PROTOCOL_DEST == 0" \
-	"enablement_value" "false" \
-] [ipx::get_user_parameters CACHE_COHERENT_DEST -of_objects $cc]
-
 set p [ipgui::get_guiparamspec -name "DMA_AXI_PROTOCOL_SG" -component $cc]
 ipgui::move_param -component $cc -order 0 $p -parent $sg_group
 set_property -dict [list \
@@ -441,6 +429,24 @@ set_property -dict [list \
 	"display_name" "DMA AXI Address Width" \
 ] $p
 
+set p [ipgui::get_guiparamspec -name "AXI_AXCACHE" -component $cc]
+ipgui::move_param -component $cc -order 5 $p -parent $general_group
+set_property -dict [list \
+        "display_name" "ARCACHE/AWCACHE" \
+] $p
+set_property -dict [list \
+        "enablement_tcl_expr" "\$CACHE_COHERENT == true" \
+] [ipx::get_user_parameters AXI_AXCACHE -of_objects $cc]
+
+set p [ipgui::get_guiparamspec -name "AXI_AXPROT" -component $cc]
+ipgui::move_param -component $cc -order 6 $p -parent $general_group
+set_property -dict [list \
+        "display_name" "ARPROT/AWPROT" \
+] $p
+set_property -dict [list \
+        "enablement_tcl_expr" "\$CACHE_COHERENT == true" \
+] [ipx::get_user_parameters AXI_AXPROT -of_objects $cc]
+
 set feature_group [ipgui::add_group -name "Features" -component $cc \
 		-parent $page0 -display_name "Features"]
 
@@ -450,17 +456,27 @@ set_property -dict [list \
 	"display_name" "Cyclic Transfer Support" \
 ] $p
 
-set p [ipgui::get_guiparamspec -name "DMA_2D_TRANSFER" -component $cc]
+set p [ipgui::get_guiparamspec -name "DMA_SG_TRANSFER" -component $cc]
 ipgui::move_param -component $cc -order 1 $p -parent $feature_group
+set_property -dict [list \
+	"display_name" "SG Transfer Support" \
+] $p
+
+set p [ipgui::get_guiparamspec -name "DMA_2D_TRANSFER" -component $cc]
+ipgui::move_param -component $cc -order 2 $p -parent $feature_group
 set_property -dict [list \
 	"display_name" "2D Transfer Support" \
 ] $p
 
-set p [ipgui::get_guiparamspec -name "DMA_SG_TRANSFER" -component $cc]
+set p [ipgui::get_guiparamspec -name "CACHE_COHERENT" -component $cc]
-ipgui::move_param -component $cc -order 2 $p -parent $feature_group
+ipgui::move_param -component $cc -order 3 $p -parent $feature_group
 set_property -dict [list \
-	"display_name" "SG Transfer Support" \
+	"tooltip" "Assume DMA ports ensure cache coherence (e.g. Ultrascale HPC port)" \
 ] $p
+set_property -dict [list \
+	"display_name" "Cache Coherent" \
+	"enablement_tcl_expr" "\$DMA_TYPE_SRC == 0 || \$DMA_TYPE_DEST == 0" \
+] [ipx::get_user_parameters CACHE_COHERENT -of_objects $cc]
 
 set clk_group [ipgui::add_group -name {Clock Domain Configuration} -component $cc \
 		-parent $page0 -display_name {Clock Domain Configuration}]

library/axi_dmac/axi_dmac_regmap.v

@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -53,7 +53,9 @@ module axi_dmac_regmap #(
   parameter DMA_2D_TRANSFER = 0,
   parameter DMA_SG_TRANSFER = 0,
   parameter SYNC_TRANSFER_START = 0,
-  parameter CACHE_COHERENT_DEST = 0
+  parameter CACHE_COHERENT = 0,
+  parameter [3:0] AXI_AXCACHE = 4'b0011,
+  parameter [2:0] AXI_AXPROT = 3'b000
 ) (
 
   // Slave AXI interface
@@ -121,7 +123,7 @@ module axi_dmac_regmap #(
   input [31:0] dbg_ids1
 );
 
-  localparam PCORE_VERSION = 'h00040561;
+  localparam PCORE_VERSION = 'h00040562;
   localparam HAS_ADDR_HIGH = DMA_AXI_ADDR_WIDTH > 32;
   localparam ADDR_LOW_MSB = HAS_ADDR_HIGH ? 31 : DMA_AXI_ADDR_WIDTH-1;
 
@@ -223,7 +225,10 @@ module axi_dmac_regmap #(
                            4'b0,BYTES_PER_BURST_WIDTH[3:0],
                            2'b0,DMA_TYPE_SRC[1:0],BYTES_PER_BEAT_WIDTH_SRC[3:0],
                            2'b0,DMA_TYPE_DEST[1:0],BYTES_PER_BEAT_WIDTH_DEST[3:0]};
-      9'h005: up_rdata <= {31'd0, CACHE_COHERENT_DEST};
+      9'h005: up_rdata <= {20'b0,
+                           1'b0,AXI_AXPROT,
+                           AXI_AXCACHE,
+                           3'b0,CACHE_COHERENT};
       9'h020: up_rdata <= up_irq_mask;
       9'h021: up_rdata <= up_irq_pending;
       9'h022: up_rdata <= up_irq_source;

library/axi_dmac/axi_dmac_transfer.v

@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -64,7 +64,8 @@ module axi_dmac_transfer #(
   parameter AXI_LENGTH_WIDTH_SG = 8,
   parameter ENABLE_DIAGNOSTICS_IF = 0,
   parameter ALLOW_ASYM_MEM = 0,
-  parameter CACHE_COHERENT_DEST = 0
+  parameter [3:0] AXI_AXCACHE = 4'b0011,
+  parameter [2:0] AXI_AXPROT = 3'b000
 ) (
   input ctrl_clk,
   input ctrl_resetn,
@@ -321,7 +322,9 @@ module axi_dmac_transfer #(
     .BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT_WIDTH_DEST),
     .BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC),
     .BYTES_PER_BEAT_WIDTH_SG(BYTES_PER_BEAT_WIDTH_SG),
-    .ASYNC_CLK_REQ_SG(ASYNC_CLK_REQ_SG)
+    .ASYNC_CLK_REQ_SG(ASYNC_CLK_REQ_SG),
+    .AXI_AXCACHE(AXI_AXCACHE),
+    .AXI_AXPROT(AXI_AXPROT)
   ) i_dmac_sg (
     .req_clk(req_clk),
     .req_resetn(req_resetn),
@@ -500,7 +503,8 @@ module axi_dmac_transfer #(
     .AXI_LENGTH_WIDTH_SRC (AXI_LENGTH_WIDTH_SRC),
     .ENABLE_DIAGNOSTICS_IF(ENABLE_DIAGNOSTICS_IF),
     .ALLOW_ASYM_MEM (ALLOW_ASYM_MEM),
-    .CACHE_COHERENT_DEST(CACHE_COHERENT_DEST)
+    .AXI_AXCACHE(AXI_AXCACHE),
+    .AXI_AXPROT(AXI_AXPROT)
   ) i_request_arb (
     .req_clk (req_clk),
     .req_resetn (req_resetn),

library/axi_dmac/bd/bd.tcl

@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2015-2024 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
@@ -203,4 +203,11 @@ proc post_propagate {cellpath otherinfo} {
 	}
 
 	set_property "CONFIG.DMA_AXI_ADDR_WIDTH" $addr_width $ip
+
+	# AXCACHE/AXPROT configuration
+        set cache_coherent [get_property "CONFIG.CACHE_COHERENT" $ip]
+        set axcache [expr {$cache_coherent == true} ? 0b1111 : 0b0011]
+        set axprot [expr {$cache_coherent == true} ? 0b010 : 0b000]
+        set_property "CONFIG.AXI_AXCACHE" $axcache $ip
+        set_property "CONFIG.AXI_AXPROT" $axprot $ip
 }

library/axi_dmac/dest_axi_mm.v

@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -45,7 +45,8 @@ module dest_axi_mm #(
   parameter MAX_BYTES_PER_BURST = 128,
   parameter BYTES_PER_BURST_WIDTH = $clog2(MAX_BYTES_PER_BURST),
   parameter AXI_LENGTH_WIDTH = 8,
-  parameter CACHE_COHERENT = 0
+  parameter [3:0] AXI_AXCACHE = 4'b0011,
+  parameter [2:0] AXI_AXPROT = 3'b000
 ) (
   input                               m_axi_aclk,
   input                               m_axi_aresetn,
@@ -117,7 +118,8 @@ module dest_axi_mm #(
     .DMA_DATA_WIDTH(DMA_DATA_WIDTH),
     .LENGTH_WIDTH(AXI_LENGTH_WIDTH),
     .DMA_ADDR_WIDTH(DMA_ADDR_WIDTH),
-    .CACHE_COHERENT(CACHE_COHERENT)
+    .AXI_AXCACHE(AXI_AXCACHE),
+    .AXI_AXPROT(AXI_AXPROT)
   ) i_addr_gen (
     .clk(m_axi_aclk),
     .resetn(m_axi_aresetn),

library/axi_dmac/dmac_sg.v

@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -43,7 +43,9 @@ module dmac_sg #(
   parameter BYTES_PER_BEAT_WIDTH_DEST = 3,
   parameter BYTES_PER_BEAT_WIDTH_SRC = 3,
   parameter BYTES_PER_BEAT_WIDTH_SG = 3,
-  parameter ASYNC_CLK_REQ_SG = 1
+  parameter ASYNC_CLK_REQ_SG = 1,
+  parameter [3:0] AXI_AXCACHE = 4'b0011,
+  parameter [2:0] AXI_AXPROT = 3'b000
 ) (
   input req_clk,
   input req_resetn,
@@ -147,8 +149,8 @@ module dmac_sg #(
 
   assign m_axi_arsize  = 3'h3;
   assign m_axi_arburst = 2'h1;
-  assign m_axi_arprot  = 3'h0;
+  assign m_axi_arprot  = AXI_AXPROT;
-  assign m_axi_arcache = 4'h3;
+  assign m_axi_arcache = AXI_AXCACHE;
   assign m_axi_arlen   = 'h5;
   assign m_axi_araddr  = {next_desc_addr, {BYTES_PER_BEAT_WIDTH_SG{1'b0}}};
 

library/axi_dmac/request_arb.v

@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -58,7 +58,8 @@ module request_arb #(
   parameter AXI_LENGTH_WIDTH_DEST = 8,
   parameter ENABLE_DIAGNOSTICS_IF = 0,
   parameter ALLOW_ASYM_MEM = 0,
-  parameter CACHE_COHERENT_DEST = 0
+  parameter [3:0] AXI_AXCACHE = 4'b0011,
+  parameter [2:0] AXI_AXPROT = 3'b000
 ) (
   input req_clk,
   input req_resetn,
@@ -357,7 +358,8 @@ module request_arb #(
     .MAX_BYTES_PER_BURST(MAX_BYTES_PER_BURST),
     .BYTES_PER_BURST_WIDTH(BYTES_PER_BURST_WIDTH),
     .AXI_LENGTH_WIDTH(AXI_LENGTH_WIDTH_DEST),
-    .CACHE_COHERENT(CACHE_COHERENT_DEST)
+    .AXI_AXCACHE(AXI_AXCACHE),
+    .AXI_AXPROT(AXI_AXPROT)
   ) i_dest_dma_mm (
     .m_axi_aclk(m_dest_axi_aclk),
     .m_axi_aresetn(dest_resetn),
@@ -619,7 +621,9 @@ module request_arb #(
     .DMA_ADDR_WIDTH(DMA_AXI_ADDR_WIDTH),
     .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_SRC),
     .BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH_SRC),
-    .AXI_LENGTH_WIDTH(AXI_LENGTH_WIDTH_SRC)
+    .AXI_LENGTH_WIDTH(AXI_LENGTH_WIDTH_SRC),
+    .AXI_AXCACHE(AXI_AXCACHE),
+    .AXI_AXPROT(AXI_AXPROT)
   ) i_src_dma_mm (
     .m_axi_aclk(m_src_axi_aclk),
     .m_axi_aresetn(src_resetn),

library/axi_dmac/src_axi_mm.v

@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -42,7 +42,9 @@ module src_axi_mm #(
   parameter DMA_ADDR_WIDTH = 32,
   parameter BYTES_PER_BEAT_WIDTH = 3,
   parameter BEATS_PER_BURST_WIDTH = 4,
-  parameter AXI_LENGTH_WIDTH = 8
+  parameter AXI_LENGTH_WIDTH = 8,
+  parameter [3:0] AXI_AXCACHE = 4'b0011,
+  parameter [2:0] AXI_AXPROT = 3'b000
 ) (
   input                           m_axi_aclk,
   input                           m_axi_aresetn,
@@ -148,7 +150,9 @@ module src_axi_mm #(
     .BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH),
     .DMA_DATA_WIDTH(DMA_DATA_WIDTH),
     .LENGTH_WIDTH(AXI_LENGTH_WIDTH),
-    .DMA_ADDR_WIDTH(DMA_ADDR_WIDTH)
+    .DMA_ADDR_WIDTH(DMA_ADDR_WIDTH),
+    .AXI_AXCACHE(AXI_AXCACHE),
+    .AXI_AXPROT(AXI_AXPROT)
   ) i_addr_gen (
     .clk(m_axi_aclk),
     .resetn(m_axi_aresetn),