From 10c99562cf9ad51985ae56a7c012f1d89d276a9c Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Tue, 15 Oct 2019 10:36:57 +0300 Subject: [PATCH] axi_logic_analyzer: Add extra reg pipe to avoid latch --- library/axi_logic_analyzer/axi_logic_analyzer.v | 5 ++--- library/axi_logic_analyzer/axi_logic_analyzer_trigger.v | 2 +- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/library/axi_logic_analyzer/axi_logic_analyzer.v b/library/axi_logic_analyzer/axi_logic_analyzer.v index b8bf7a66b..1575743b8 100644 --- a/library/axi_logic_analyzer/axi_logic_analyzer.v +++ b/library/axi_logic_analyzer/axi_logic_analyzer.v @@ -52,7 +52,7 @@ module axi_logic_analyzer #( input [ 1:0] trigger_i, output adc_valid, - output [15:0] adc_data, + output reg [15:0] adc_data, input [15:0] dac_data, input dac_valid, @@ -161,8 +161,6 @@ module axi_logic_analyzer #( assign trigger_out = trigger_delay == 32'h0 ? trigger_out_s | streaming_on : trigger_out_delayed | streaming_on; assign trigger_out_delayed = delay_counter == 32'h0 ? 1 : 0; - assign adc_data = adc_data_mn; - always @(posedge clk_out) begin if (trigger_delay == 0) begin if (streaming == 1'b1 && sample_valid_la == 1'b1 && trigger_out_s == 1'b1) begin @@ -250,6 +248,7 @@ module axi_logic_analyzer #( always @(posedge clk_out) begin if (sample_valid_la == 1'b1) begin adc_data_mn <= data_m[ADC_PATH_DELAY-2]; + adc_data <= adc_data_mn; end end endgenerate diff --git a/library/axi_logic_analyzer/axi_logic_analyzer_trigger.v b/library/axi_logic_analyzer/axi_logic_analyzer_trigger.v index c1df58da2..8368edfff 100644 --- a/library/axi_logic_analyzer/axi_logic_analyzer_trigger.v +++ b/library/axi_logic_analyzer/axi_logic_analyzer_trigger.v @@ -96,7 +96,7 @@ module axi_logic_analyzer_trigger ( // 0 OR // 1 AND - always @(*) begin + always @(posedge clk) begin if (data_valid == 1'b1) begin case (trigger_logic[0]) 0: trigger_active = |(({ext_t_edge_detect_hold, edge_detect_m} & edge_detect_enable) |