zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

axi_jesd_gt: move master/slave control to a util module

main
Rejeesh Kutty 2015-08-03 16:35:51 -04:00
parent 3ed350efbc
commit 10d4da64dd
5 changed files with 554 additions and 237 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

620
library/axi_jesd_gt/axi_jesd_gt.v
View File

File diff suppressed because it is too large Load Diff

4
library/axi_jesd_gt/axi_jesd_gt_constr.xdc
View File

@ -1,3 +1,3 @@
set_false_path -from [get_cells -hier *preset* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier *rst* -filter {primitive_subgroup == flop}]
set_false_path -from [get_cells -hier *up_*_preset* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier *_rst* -filter {primitive_subgroup == flop}]

65
library/common/ad_gt_channel.v
View File

@ -51,7 +51,7 @@ module ad_gt_channel (
// receive
rx_rst,
rx_gt_rst_m,
rx_p,
rx_n,
@ -59,12 +59,8 @@ module ad_gt_channel (
rx_out_clk_sel,
rx_out_clk,
rx_rst_done,
rx_rst_done_in,
rx_rst_done_out,
rx_pll_locked,
rx_pll_locked_in,
rx_pll_locked_out,
rx_user_ready,
rx_user_ready_m,
rx_clk,
rx_gt_charisk,
@ -80,7 +76,7 @@ module ad_gt_channel (
// transmit
tx_rst,
tx_gt_rst_m,
tx_p,
tx_n,
@ -88,12 +84,8 @@ module ad_gt_channel (
tx_out_clk_sel,
tx_out_clk,
tx_rst_done,
tx_rst_done_in,
tx_rst_done_out,
tx_pll_locked,
tx_pll_locked_in,
tx_pll_locked_out,
tx_user_ready,
tx_user_ready_m,
tx_clk,
tx_gt_charisk,
@ -118,12 +110,10 @@ module ad_gt_channel (
parameter integer RX_OUT_DIV = 1;
parameter integer RX_CLK25_DIV = 10;
parameter integer RX_CLKBUF_ENABLE = 0;
parameter integer RX_PRIMARY = 0;
parameter [72:0] RX_CDR_CFG = 72'h03000023ff20400020;
parameter integer TX_OUT_DIV = 1;
parameter integer TX_CLK25_DIV = 10;
parameter integer TX_CLKBUF_ENABLE = 0;
parameter integer TX_PRIMARY = 0;
// rst and clocks
@ -137,7 +127,7 @@ module ad_gt_channel (
// receive
input rx_rst;
input rx_gt_rst_m;
input rx_p;
input rx_n;
@ -145,12 +135,8 @@ module ad_gt_channel (
input [ 2:0] rx_out_clk_sel;
output rx_out_clk;
output rx_rst_done;
input rx_rst_done_in;
output rx_rst_done_out;
output rx_pll_locked;
input rx_pll_locked_in;
output rx_pll_locked_out;
input rx_user_ready;
input rx_user_ready_m;
input rx_clk;
output [ 3:0] rx_gt_charisk;
@ -166,7 +152,7 @@ module ad_gt_channel (
// transmit
input tx_rst;
input tx_gt_rst_m;
output tx_p;
output tx_n;
@ -174,12 +160,8 @@ module ad_gt_channel (
input [ 2:0] tx_out_clk_sel;
output tx_out_clk;
output tx_rst_done;
input tx_rst_done_in;
output tx_rst_done_out;
output tx_pll_locked;
input tx_pll_locked_in;
output tx_pll_locked_out;
input tx_user_ready;
input tx_user_ready_m;
input tx_clk;
input [ 3:0] tx_gt_charisk;
@ -252,20 +234,7 @@ module ad_gt_channel (
// pll locked
assign rx_pll_locked = (rx_sys_clk_sel == 2'd3) ? qpll_locked : cpll_locked_s;
assign rx_pll_locked_out = (RX_PRIMARY == 1) ? rx_pll_locked :
(rx_pll_locked & rx_pll_locked_in);
assign tx_pll_locked = (tx_sys_clk_sel == 2'd3) ? qpll_locked : cpll_locked_s;
assign tx_pll_locked_out = (TX_PRIMARY == 1) ? tx_pll_locked :
(tx_pll_locked & tx_pll_locked_in);
// reset done
assign rx_rst_done_out = (RX_PRIMARY == 1) ? rx_rst_done :
(rx_rst_done & rx_rst_done_in);
assign tx_rst_done_out = (TX_PRIMARY == 1) ? tx_rst_done :
(tx_rst_done & tx_rst_done_in);
// instantiations
@ -544,7 +513,7 @@ module ad_gt_channel (
.TXPD (2'b00),
.SETERRSTATUS (1'd0),
.EYESCANRESET (1'd0),
.RXUSERRDY (rx_user_ready),
.RXUSERRDY (rx_user_ready_m),
.EYESCANDATAERROR (),
.EYESCANMODE (1'd0),
.EYESCANTRIGGER (1'd0),
@ -637,7 +606,7 @@ module ad_gt_channel (
.RXHEADERVALID (),
.RXSTARTOFSEQ (),
.RXGEARBOXSLIP (1'd0),
.GTRXRESET (rx_rst),
.GTRXRESET (rx_gt_rst_m),
.RXOOBRESET (1'd0),
.RXPCSRESET (1'd0),
.RXPMARESET (1'd0),
@ -665,9 +634,9 @@ module ad_gt_channel (
.TXQPISTRONGPDOWN (1'd0),
.TXQPIWEAKPUP (1'd0),
.CFGRESET (1'd0),
.GTTXRESET (tx_rst),
.GTTXRESET (tx_gt_rst_m),
.PCSRSVDOUT (),
.TXUSERRDY (tx_user_ready),
.TXUSERRDY (tx_user_ready_m),
.GTRESETSEL (1'd0),
.RESETOVRD (1'd0),
.TXCHARDISPMODE (8'd0),
@ -1172,10 +1141,10 @@ module ad_gt_channel (
.GTREFCLK1 (1'd0),
.GTRESETSEL (1'd0),
.GTRSVD (15'd0),
.GTRXRESET (rx_rst),
.GTRXRESET (rx_gt_rst_m),
.GTSOUTHREFCLK0 (1'd0),
.GTSOUTHREFCLK1 (1'd0),
.GTTXRESET (tx_rst),
.GTTXRESET (tx_gt_rst_m),
.LOOPBACK (3'd0),
.LPBKRXTXSEREN (1'd0),
.LPBKTXRXSEREN (1'd0),
@ -1297,7 +1266,7 @@ module ad_gt_channel (
.RXSYNCIN (1'd0),
.RXSYNCMODE (1'd0),
.RXSYSCLKSEL (rx_sys_clk_sel_s),
.RXUSERRDY (rx_user_ready),
.RXUSERRDY (rx_user_ready_m),
.RXUSRCLK (rx_clk),
.RXUSRCLK2 (rx_clk),
.RX8B10BEN (1'd1),
@ -1354,7 +1323,7 @@ module ad_gt_channel (
.TXPRBSSEL (4'd0),
.TXPRECURSOR (5'd0),
.TXPRECURSORINV (1'd0),
.TXPROGDIVRESET (tx_rst),
.TXPROGDIVRESET (tx_gt_rst_m),
.TXQPIBIASEN (1'd0),
.TXQPISTRONGPDOWN (1'd0),
.TXQPIWEAKPUP (1'd0),
@ -1366,7 +1335,7 @@ module ad_gt_channel (
.TXSYNCIN (1'd0),
.TXSYNCMODE (1'd0),
.TXSYSCLKSEL (tx_sys_clk_sel_s),
.TXUSERRDY (tx_user_ready),
.TXUSERRDY (tx_user_ready_m),
.TXUSRCLK (tx_clk),
.TXUSRCLK2 (tx_clk),
.TX8B10BBYPASS (8'd0),

94
library/common/ad_gt_channel_1.v
View File

@ -41,12 +41,12 @@ module ad_gt_channel_1 (
// channel interface (pll)
cpll_rst_m,
cpll_ref_clk_in,
qpll_ref_clk,
qpll_locked,
qpll_clk,
pll_rst,
pll_rst_m,
// channel interface (rx)
@ -82,17 +82,13 @@ module ad_gt_channel_1 (
rx_ip_sync,
rx_ip_rst_done,
rx_pll_locked,
rx_user_ready,
rx_rst_done_m,
rx_rst_done,
rx_pll_locked_m,
rx_user_ready_m,
// channel interface (rx-daisy-chain)
rx_rst_done_in,
rx_rst_done_out,
rx_pll_locked_in,
rx_pll_locked_out,
rx_rst_done_m,
// channel interface (tx)
@ -118,17 +114,13 @@ module ad_gt_channel_1 (
tx_ip_sync,
tx_ip_rst_done,
tx_pll_locked,
tx_user_ready,
tx_rst_done_m,
tx_rst_done,
tx_pll_locked_m,
tx_user_ready_m,
// channel interface (tx-daisy-chain)
tx_rst_done_in,
tx_rst_done_out,
tx_pll_locked_in,
tx_pll_locked_out,
tx_rst_done_m,
// dma interface
@ -160,21 +152,19 @@ module ad_gt_channel_1 (
parameter integer RX_OUT_DIV = 1;
parameter integer RX_CLK25_DIV = 10;
parameter integer RX_CLKBUF_ENABLE = 0;
parameter integer RX_PRIMARY = 0;
parameter [72:0] RX_CDR_CFG = 72'h03000023ff20400020;
parameter integer TX_OUT_DIV = 1;
parameter integer TX_CLK25_DIV = 10;
parameter integer TX_CLKBUF_ENABLE = 0;
parameter integer TX_PRIMARY = 0;
// channel interface (pll)
input cpll_rst_m;
input cpll_ref_clk_in;
input qpll_ref_clk;
input qpll_locked;
input qpll_clk;
output pll_rst;
input pll_rst_m;
// channel interface (rx)
@ -210,17 +200,13 @@ module ad_gt_channel_1 (
input rx_ip_sync;
output rx_ip_rst_done;
output rx_pll_locked;
output rx_user_ready;
input rx_rst_done_m;
output rx_rst_done;
input rx_pll_locked_m;
input rx_user_ready_m;
// channel interface (rx-daisy-chain)
input rx_rst_done_in;
output rx_rst_done_out;
input rx_pll_locked_in;
output rx_pll_locked_out;
input rx_rst_done_m;
// channel interface (tx)
@ -246,17 +232,13 @@ module ad_gt_channel_1 (
output tx_ip_sync;
output tx_ip_rst_done;
output tx_pll_locked;
output tx_user_ready;
input tx_rst_done_m;
output tx_rst_done;
input tx_pll_locked_m;
input tx_user_ready_m;
// channel interface (tx-daisy-chain)
input tx_rst_done_in;
output tx_rst_done_out;
input tx_pll_locked_in;
output tx_pll_locked_out;
input tx_rst_done_m;
// dma interface
@ -285,12 +267,8 @@ module ad_gt_channel_1 (
wire cpll_pd_s;
wire [ 1:0] rx_sys_clk_sel_s;
wire [ 2:0] rx_out_clk_sel_s;
wire rx_rst_done_s;
wire rx_pll_locked_s;
wire [ 1:0] tx_sys_clk_sel_s;
wire [ 2:0] tx_out_clk_sel_s;
wire tx_rst_done_s;
wire tx_pll_locked_s;
wire up_drp_sel_s;
wire up_drp_wr_s;
wire [11:0] up_drp_addr_s;
@ -351,30 +329,24 @@ module ad_gt_channel_1 (
.TX_CLK25_DIV (TX_CLK25_DIV),
.RX_CLKBUF_ENABLE (RX_CLKBUF_ENABLE),
.TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE),
.RX_PRIMARY (RX_PRIMARY),
.TX_PRIMARY (TX_PRIMARY),
.RX_CDR_CFG (RX_CDR_CFG))
i_gt (
.lpm_dfe_n (lpm_dfe_n_s),
.cpll_ref_clk_in (cpll_ref_clk_in),
.cpll_pd (cpll_pd_s),
.cpll_rst (pll_rst_m),
.cpll_rst (cpll_rst_m),
.qpll_clk (qpll_clk),
.qpll_ref_clk (qpll_ref_clk),
.qpll_locked (qpll_locked),
.rx_rst (rx_rst_m),
.rx_gt_rst_m (rx_gt_rst_m),
.rx_p (rx_p),
.rx_n (rx_n),
.rx_sys_clk_sel (rx_sys_clk_sel_s),
.rx_out_clk_sel (rx_out_clk_sel_s),
.rx_out_clk (rx_out_clk),
.rx_rst_done (rx_rst_done_s),
.rx_rst_done_in (rx_rst_done_in),
.rx_rst_done_out (rx_rst_done_out),
.rx_pll_locked (rx_pll_locked_s),
.rx_pll_locked_in (rx_pll_locked_in),
.rx_pll_locked_out (rx_pll_locked_out),
.rx_user_ready (rx_user_ready_m),
.rx_rst_done (rx_rst_done),
.rx_pll_locked (rx_pll_locked),
.rx_user_ready_m (rx_user_ready_m),
.rx_clk (rx_clk),
.rx_gt_charisk (rx_gt_charisk),
.rx_gt_disperr (rx_gt_disperr),
@ -386,19 +358,15 @@ module ad_gt_channel_1 (
.rx_gt_ilas_a (rx_gt_ilas_a),
.rx_gt_ilas_r (rx_gt_ilas_r),
.rx_gt_cgs_k (rx_gt_cgs_k),
.tx_rst (tx_rst_m),
.tx_gt_rst_m (tx_gt_rst_m),
.tx_p (tx_p),
.tx_n (tx_n),
.tx_sys_clk_sel (tx_sys_clk_sel_s),
.tx_out_clk_sel (tx_out_clk_sel_s),
.tx_out_clk (tx_out_clk),
.tx_rst_done (tx_rst_done_s),
.tx_rst_done_in (tx_rst_done_in),
.tx_rst_done_out (tx_rst_done_out),
.tx_pll_locked (tx_pll_locked_s),
.tx_pll_locked_in (tx_pll_locked_in),
.tx_pll_locked_out (tx_pll_locked_out),
.tx_user_ready (tx_user_ready_m),
.tx_rst_done (tx_rst_done),
.tx_pll_locked (tx_pll_locked),
.tx_user_ready_m (tx_user_ready_m),
.tx_clk (tx_clk),
.tx_gt_charisk (tx_gt_charisk),
.tx_gt_data (tx_gt_data),
@ -469,9 +437,9 @@ module ad_gt_channel_1 (
.rx_ip_sysref (rx_ip_sysref),
.rx_ip_sync (rx_ip_sync),
.rx_sync (rx_sync),
.rx_rst_done (rx_rst_done_s),
.rx_rst_done (rx_rst_done),
.rx_rst_done_m (rx_rst_done_m),
.rx_pll_locked (rx_pll_locked_s),
.rx_pll_locked (rx_pll_locked),
.rx_pll_locked_m (rx_pll_locked_m),
.rx_user_ready (rx_user_ready),
.rx_ip_rst_done (rx_ip_rst_done),
@ -486,9 +454,9 @@ module ad_gt_channel_1 (
.tx_ip_sysref (tx_ip_sysref),
.tx_sync (tx_sync),
.tx_ip_sync (tx_ip_sync),
.tx_rst_done (tx_rst_done_s),
.tx_rst_done (tx_rst_done),
.tx_rst_done_m (tx_rst_done_m),
.tx_pll_locked (tx_pll_locked_s),
.tx_pll_locked (tx_pll_locked),
.tx_pll_locked_m (tx_pll_locked_m),
.tx_user_ready (tx_user_ready),
.tx_ip_rst_done (tx_ip_rst_done),

8
library/common/up_gt_channel.v
View File

@ -613,8 +613,8 @@ module up_gt_channel (
8'h0b: up_rdata <= {30'd0, up_rx_sysref_sel, up_rx_sysref};
8'h0c: up_rdata <= {31'd0, up_rx_sync};
8'h0d: up_rdata <= {15'd0, up_rx_status,
6'hcf, up_rx_rst_done_m, up_rx_rst_done,
6'hcf, up_rx_pll_locked_m, up_rx_pll_locked};
6'h3f, up_rx_rst_done_m, up_rx_rst_done,
6'h3f, up_rx_pll_locked_m, up_rx_pll_locked};
8'h0e: up_rdata <= {31'd0, up_rx_user_ready};
8'h18: up_rdata <= {31'd0, up_tx_gt_resetn};
8'h19: up_rdata <= {31'd0, up_tx_resetn};
@ -622,8 +622,8 @@ module up_gt_channel (
8'h1b: up_rdata <= {30'd0, up_tx_sysref_sel, up_tx_sysref};
8'h1c: up_rdata <= {31'd0, up_tx_sync};
8'h1d: up_rdata <= {15'd0, up_tx_status,
6'hcf, up_tx_rst_done_m, up_tx_rst_done,
6'hcf, up_tx_pll_locked_m, up_tx_pll_locked};
6'h3f, up_tx_rst_done_m, up_tx_rst_done,
6'h3f, up_tx_pll_locked_m, up_tx_pll_locked};
8'h1e: up_rdata <= {31'd0, up_tx_user_ready};
8'h24: up_rdata <= {3'd0, up_drp_rwn, up_drp_addr_int, up_drp_wdata_int};
8'h25: up_rdata <= {15'd0, up_drp_status, up_drp_rdata_int};