axi_ad9361/tdd: Update the synchronization logic
The master will regenerate a sync pulse periodically. The period can be defined by software.main
parent
bcee3e04d4
commit
10d9de39a1
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@ -113,8 +113,8 @@ module axi_ad9361 (
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enable,
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txnrx,
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tdd_sync_req,
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tdd_sync_ack,
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tdd_sync_out,
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tdd_sync_in,
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// axi interface
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@ -232,8 +232,8 @@ module axi_ad9361 (
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output enable;
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output txnrx;
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inout tdd_sync_req;
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inout tdd_sync_ack;
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output tdd_sync_out;
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input tdd_sync_in;
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// axi interface
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@ -409,8 +409,8 @@ module axi_ad9361 (
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.tdd_tx_rf_en(tdd_tx_rf_en_s),
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.tdd_enabled (tdd_enabled),
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.tdd_status(tdd_status_s),
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.tdd_sync_req(tdd_sync_req),
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.tdd_sync_ack(tdd_sync_ack),
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.tdd_sync_out(tdd_sync_out),
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.tdd_sync_in(tdd_sync_in),
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.tx_valid_i0(dac_valid_i0_s),
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.tx_valid_q0(dac_valid_q0_s),
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.tx_valid_i1(dac_valid_i1_s),
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@ -60,8 +60,8 @@ module axi_ad9361_tdd (
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// sync signals
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tdd_sync_req,
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tdd_sync_ack,
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tdd_sync_out,
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tdd_sync_in,
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// tx/rx data flow control
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@ -114,8 +114,8 @@ module axi_ad9361_tdd (
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output tdd_enabled;
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input [ 7:0] tdd_status;
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inout tdd_sync_req;
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inout tdd_sync_ack;
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output tdd_sync_out;
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input tdd_sync_in;
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// tx data flow control
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@ -157,7 +157,6 @@ module axi_ad9361_tdd (
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output [41:0] tdd_dbg;
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reg tdd_slave_synced = 1'b0;
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reg tdd_sync_o = 1'b0;
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// internal signals
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@ -174,6 +173,7 @@ module axi_ad9361_tdd (
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wire [23:0] tdd_frame_length_s;
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wire tdd_terminal_type_s;
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wire tdd_sync_enable_s;
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wire [31:0] tdd_sync_period_s;
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wire [23:0] tdd_vco_rx_on_1_s;
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wire [23:0] tdd_vco_rx_off_1_s;
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wire [23:0] tdd_vco_tx_on_1_s;
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@ -194,12 +194,13 @@ module axi_ad9361_tdd (
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wire [23:0] tdd_tx_off_2_s;
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wire [23:0] tdd_tx_dp_on_2_s;
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wire [23:0] tdd_tx_dp_off_2_s;
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wire tdd_resync_s;
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wire [23:0] tdd_counter_status;
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wire tdd_tx_dp_en_s;
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assign tdd_dbg = {tdd_counter_status, tdd_enable_s, tdd_tx_dp_en_s,
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assign tdd_dbg = {tdd_counter_status, tdd_enable_s, tdd_enable_synced_s, tdd_tx_dp_en_s,
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tdd_rx_vco_en, tdd_tx_vco_en, tdd_rx_rf_en, tdd_tx_rf_en};
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// tx/rx data flow control
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@ -240,6 +241,7 @@ module axi_ad9361_tdd (
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.tdd_frame_length(tdd_frame_length_s),
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.tdd_terminal_type(tdd_terminal_type_s),
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.tdd_sync_enable(tdd_sync_enable_s),
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.tdd_sync_period(tdd_sync_period_s),
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.tdd_vco_rx_on_1(tdd_vco_rx_on_1_s),
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.tdd_vco_rx_off_1(tdd_vco_rx_off_1_s),
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.tdd_vco_tx_on_1(tdd_vco_tx_on_1_s),
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@ -282,6 +284,7 @@ module axi_ad9361_tdd (
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.tdd_burst_count(tdd_burst_count_s),
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.tdd_rx_only(tdd_rx_only_s),
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.tdd_tx_only(tdd_tx_only_s),
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.tdd_resync (tdd_resync_s),
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.tdd_vco_rx_on_1(tdd_vco_rx_on_1_s),
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.tdd_vco_rx_off_1(tdd_vco_rx_off_1_s),
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.tdd_vco_tx_on_1(tdd_vco_tx_on_1_s),
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@ -312,13 +315,14 @@ module axi_ad9361_tdd (
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ad_tdd_sync i_tdd_sync (
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.clk(clk),
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.rst(rst),
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.tdd_sync_en(tdd_sync_enable_s),
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.tdd_term_type(tdd_terminal_type_s),
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.tdd_enable_in(tdd_enable_s),
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.tdd_enable_out(tdd_enable_synced_s),
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.sync_req(tdd_sync_req),
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.sync_ack(tdd_sync_ack),
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.sync_dbg(tdd_sync_dbg)
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.sync_en(tdd_sync_enable_s),
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.device_type(tdd_terminal_type_s),
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.sync_period(tdd_sync_period_s),
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.enable_in(tdd_enable_s),
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.enable_out(tdd_enable_synced_s),
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.sync_out(tdd_sync_out),
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.sync_in(tdd_sync_in),
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.resync(tdd_resync_s)
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);
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endmodule
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@ -75,6 +75,7 @@ module ad_tdd_control(
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tdd_tx_off_2,
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tdd_tx_dp_on_2,
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tdd_tx_dp_off_2,
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tdd_resync,
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// TDD control signals
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@ -123,6 +124,7 @@ module ad_tdd_control(
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input [23:0] tdd_tx_off_2;
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input [23:0] tdd_tx_dp_on_2;
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input [23:0] tdd_tx_dp_off_2;
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input tdd_resync;
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output tdd_tx_dp_en; // initiate vco tx2rx switch
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output tdd_rx_vco_en; // initiate vco rx2tx switch
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@ -207,6 +209,11 @@ module ad_tdd_control(
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tdd_counter_state <= ON;
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end else
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// resync slave to master
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if (tdd_resync == 1'b1) begin
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tdd_counter <= 24'b0;
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end
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// free running counter
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if (tdd_counter_state == ON) begin
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if (tdd_counter == tdd_frame_length) begin
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@ -47,123 +47,96 @@ module ad_tdd_sync (
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// control signals
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tdd_sync_en, // synchronization enabled
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tdd_term_type, // master or slave
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tdd_enable_in, // tdd_enable signal asserted by software
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tdd_enable_out, // synchronized tdd_enable
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sync_en, // synchronization enabled
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device_type, // master or slave
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sync_period, // periodicity of the sync pulse,
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enable_in, // tdd enable signal asserted by software
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enable_out, // synchronized tdd_enable
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// sync interface
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sync_req, // sync request generated by master
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sync_ack, // sync acknowledge generated by slave
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sync_out, // sync output for slave
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sync_in, // sync input
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// debug
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sync_dbg
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resync // resync pulse for slave device
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);
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input clk;
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input rst;
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input clk;
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input rst;
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input tdd_sync_en;
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input tdd_term_type;
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input tdd_enable_in;
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output tdd_enable_out;
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input sync_en;
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input device_type;
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input [31:0] sync_period;
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inout sync_req;
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inout sync_ack;
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input enable_in;
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output enable_out;
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output [5:0] sync_dbg;
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output sync_out;
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input sync_in;
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reg tdd_enable_out = 1'b0;
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reg tdd_enable_synced = 1'b0;
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reg tdd_enable_d = 1'b0;
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reg sync_req_i = 1'b0;
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reg sync_ack_i = 1'b0;
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output resync;
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reg [2:0] pulse_width = 3'h7;
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// internal registers
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wire sync_ack_o_s;
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wire sync_req_o_s;
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wire sync_req_t_s;
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wire sync_ack_t_s;
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reg enable_out = 1'b0;
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reg enable_synced = 1'b0;
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reg sync_in_d = 1'b0;
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reg sync_out = 1'b0;
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reg resync = 1'b0;
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reg [ 2:0] pulse_width = 3'h7;
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reg [31:0] pulse_counter = 32'h0;
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// the sync module can be bypassed
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always @(posedge clk) begin
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if (rst == 1) begin
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tdd_enable_out <= 1'b0;
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enable_out <= 1'b0;
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end else begin
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tdd_enable_out <= (tdd_sync_en) ? tdd_enable_synced : tdd_enable_in;
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enable_out <= (sync_en) ? enable_synced : enable_in;
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end
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end
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// iobuffers for the syncronization lines
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assign sync_req_t_s = ~tdd_term_type;
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assign sync_ack_t_s = tdd_term_type;
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assign sync_dbg = {sync_ack_i_s,
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sync_ack_o_s,
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sync_ack_t_s,
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sync_req_i,
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sync_req_o_s,
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sync_req_t_s};
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ad_iobuf #(
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.DATA_WIDTH(1)
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) i_sync_req_iobuf (
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.dio_t (sync_req_t_s),
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.dio_i (sync_req_i),
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.dio_o (sync_req_o_s),
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.dio_p (sync_req)
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);
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ad_iobuf #(
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.DATA_WIDTH(1)
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) i_sync_ack_iobuf (
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.dio_t (sync_ack_i_s),
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.dio_i (sync_ack_i),
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.dio_o (sync_ack_o_s),
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.dio_p (sync_ack)
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);
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// generate sync pulse
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always @(posedge clk) begin
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if (rst == 1) begin
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tdd_enable_d <= 1'b0;
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sync_req_i <= 1'b0;
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sync_ack_i <= 1'b0;
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if(rst == 1) begin
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pulse_counter <= 0;
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pulse_width <= 3'h7;
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sync_out <= 1'h0;
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end else begin
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tdd_enable_d <= tdd_enable_in;
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// device is master
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if (tdd_term_type == 1) begin
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if (~tdd_enable_d & tdd_enable_in == 1'b1) begin // generate sync request
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sync_req_i <= 1'b1;
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pulse_width <= 1'b0;
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if (device_type == 1) begin
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pulse_counter <= (pulse_counter < sync_period) ? pulse_counter + 1 : 32'h0;
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if(pulse_counter == sync_period) begin
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sync_out <= enable_in;
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pulse_width <= 3'h0;
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end else begin
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pulse_width <= (pulse_width < 3'h7) ? pulse_width + 1 : pulse_width;
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sync_req_i <= (pulse_width == 3'h7) ? 1'b0 : 1'b1;
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end
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if (sync_ack_o_s == 1'b1) begin // sync acknowledge arrived
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tdd_enable_synced <= tdd_enable_in;
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end else begin
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tdd_enable_synced <= (tdd_enable_in == 1'b0) ? 1'b0 : tdd_enable_synced;
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end
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// device is slave
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end else begin
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if (sync_req_o_s == 1'b1) begin
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tdd_enable_synced <= tdd_enable_in;
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sync_ack_i <= 1'b1;
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end else begin
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tdd_enable_synced <= (tdd_enable_in == 1'b0) ? 1'b0 : tdd_enable_synced;
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sync_ack_i <= 1'b0;
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sync_out <= (pulse_width == 3'h7) ? 0 : enable_in;
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end
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end
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end
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end
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// syncronize enalbe_in and generate resync for slave
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always @(posedge clk) begin
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sync_in_d <= sync_in;
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if(device_type == 1'b1) begin
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enable_synced <= enable_in;
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resync <= 1'b0;
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end else begin
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if (~sync_in_d & sync_in) begin
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enable_synced <= enable_in;
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resync <= 1'b1;
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end else begin
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resync <= 1'b0;
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end
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end
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end
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endmodule
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@ -56,6 +56,7 @@ module up_tdd_cntrl (
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tdd_frame_length,
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tdd_terminal_type,
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tdd_sync_enable,
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tdd_sync_period,
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tdd_vco_rx_on_1,
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tdd_vco_rx_off_1,
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tdd_vco_tx_on_1,
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@ -111,6 +112,7 @@ module up_tdd_cntrl (
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output [23:0] tdd_frame_length;
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output tdd_terminal_type;
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output tdd_sync_enable;
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output [31:0] tdd_sync_period;
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output [23:0] tdd_vco_rx_on_1;
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output [23:0] tdd_vco_rx_off_1;
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output [23:0] tdd_vco_tx_on_1;
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@ -162,6 +164,7 @@ module up_tdd_cntrl (
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reg up_tdd_gated_rx_dmapath = 1'h0;
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reg up_tdd_terminal_type = 1'h0;
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reg up_tdd_sync_enable = 1'h0;
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reg [31:0] up_tdd_sync_period = 32'h0;
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reg [ 7:0] up_tdd_burst_count = 8'h0;
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reg [23:0] up_tdd_counter_init = 24'h0;
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@ -214,6 +217,7 @@ module up_tdd_cntrl (
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up_tdd_gated_rx_dmapath <= 1'h0;
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up_tdd_terminal_type <= 1'h0;
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up_tdd_sync_enable <= 1'h0;
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up_tdd_sync_period <= 32'h0;
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up_tdd_counter_init <= 24'h0;
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up_tdd_frame_length <= 24'h0;
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up_tdd_burst_count <= 8'h0;
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@ -258,6 +262,9 @@ module up_tdd_cntrl (
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up_tdd_terminal_type <= up_wdata[1];
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up_tdd_sync_enable <= up_wdata[0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h15)) begin
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up_tdd_sync_period <= up_wdata;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h20)) begin
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up_tdd_vco_rx_on_1 <= up_wdata[23:0];
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end
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@ -342,6 +349,7 @@ module up_tdd_cntrl (
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8'h13: up_rdata <= { 8'h0, up_tdd_frame_length};
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8'h14: up_rdata <= {30'h0, up_tdd_terminal_type,
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up_tdd_sync_enable};
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8'h15: up_rdata <= up_tdd_sync_period;
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8'h18: up_rdata <= {24'h0, up_tdd_status_s};
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8'h20: up_rdata <= { 8'h0, up_tdd_vco_rx_on_1};
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8'h21: up_rdata <= { 8'h0, up_tdd_vco_rx_off_1};
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@ -371,7 +379,7 @@ module up_tdd_cntrl (
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// rf tdd control signal CDC
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up_xfer_cntrl #(.DATA_WIDTH(16)) i_tdd_control (
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up_xfer_cntrl #(.DATA_WIDTH(48)) i_tdd_control (
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.up_rstn(up_rstn),
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.up_clk(up_clk),
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.up_data_cntrl({up_tdd_enable,
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@ -382,7 +390,8 @@ module up_tdd_cntrl (
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up_tdd_gated_tx_dmapath,
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up_tdd_burst_count,
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up_tdd_terminal_type,
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up_tdd_sync_enable
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up_tdd_sync_enable,
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up_tdd_sync_period
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}),
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.up_xfer_done(),
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.d_rst(rst),
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@ -395,7 +404,8 @@ module up_tdd_cntrl (
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tdd_gated_tx_dmapath,
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tdd_burst_count,
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tdd_terminal_type,
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tdd_sync_enable
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tdd_sync_enable,
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tdd_sync_period
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}));
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up_xfer_cntrl #(.DATA_WIDTH(528)) i_tdd_counter_values (
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@ -19,8 +19,8 @@ create_bd_port -dir O enable
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create_bd_port -dir O txnrx
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create_bd_port -dir O tdd_enabled
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create_bd_port -dir IO tdd_sync_req
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create_bd_port -dir IO tdd_sync_ack
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create_bd_port -dir O tdd_sync_out
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create_bd_port -dir I tdd_sync_in
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# ad9361 core
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@ -139,8 +139,8 @@ ad_connect util_ad9361_dac_upack/dac_data_3 axi_ad9361/dac_data_q1
|
|||
ad_connect util_ad9361_dac_upack/dac_valid axi_ad9361_dac_dma/fifo_rd_en
|
||||
ad_connect util_ad9361_dac_upack/dac_data axi_ad9361_dac_dma/fifo_rd_dout
|
||||
ad_connect axi_ad9361_dac_dma/fifo_rd_underflow axi_ad9361/dac_dunf
|
||||
ad_connect tdd_sync_req axi_ad9361/tdd_sync_req
|
||||
ad_connect tdd_sync_ack axi_ad9361/tdd_sync_ack
|
||||
ad_connect tdd_sync_out axi_ad9361/tdd_sync_out
|
||||
ad_connect tdd_sync_in axi_ad9361/tdd_sync_in
|
||||
|
||||
ad_connect tdd_enabled axi_ad9361/tdd_enabled
|
||||
|
||||
|
|
|
@ -36,9 +36,8 @@ set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVDS} [get_ports tx_data_o
|
|||
set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVDS} [get_ports tx_data_out_n[5]] ; ## IO_L18N_T2_AD13N_35
|
||||
set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS18} [get_ports enable] ; ## IO_L11P_T1_SRCC_35
|
||||
set_property -dict {PACKAGE_PIN F14 IOSTANDARD LVCMOS18} [get_ports txnrx] ; ## IO_L11N_T1_SRCC_35
|
||||
set_property -dict {PACKAGE_PIN AA18 IOSTANDARD LVCMOS25} [get_ports tdd_sync_req] ; ## IO_L24_13_JX2_N
|
||||
set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS25} [get_ports tdd_sync_ack] ; ## IO_L23_13_JX2_N
|
||||
|
||||
set_property -dict {PACKAGE_PIN AA18 IOSTANDARD LVCMOS25} [get_ports tdd_sync_out] ; ## IO_L24_13_JX2_N
|
||||
set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS25} [get_ports tdd_sync_in] ; ## IO_L23_13_JX2_N
|
||||
|
||||
set_property -dict {PACKAGE_PIN D13 IOSTANDARD LVCMOS18} [get_ports gpio_status[0]] ; ## IO_L19P_T3_35
|
||||
set_property -dict {PACKAGE_PIN C13 IOSTANDARD LVCMOS18} [get_ports gpio_status[1]] ; ## IO_L19N_T3_VREF_35
|
||||
|
|
|
@ -109,8 +109,8 @@ module system_top (
|
|||
tx_data_out_n,
|
||||
enable,
|
||||
txnrx,
|
||||
tdd_sync_req,
|
||||
tdd_sync_ack,
|
||||
tdd_sync_out,
|
||||
tdd_sync_in,
|
||||
|
||||
gpio_rf0,
|
||||
gpio_rf1,
|
||||
|
@ -198,8 +198,8 @@ module system_top (
|
|||
output [ 5:0] tx_data_out_n;
|
||||
output enable;
|
||||
output txnrx;
|
||||
inout tdd_sync_req;
|
||||
inout tdd_sync_ack;
|
||||
output tdd_sync_out;
|
||||
input tdd_sync_in;
|
||||
|
||||
inout gpio_rf0;
|
||||
inout gpio_rf1;
|
||||
|
@ -364,8 +364,8 @@ module system_top (
|
|||
.tx_frame_out_p (tx_frame_out_p),
|
||||
.txnrx (txnrx_s),
|
||||
.tdd_enabled (tdd_enabled_s),
|
||||
.tdd_sync_req (tdd_sync_req),
|
||||
.tdd_sync_ack (tdd_sync_ack));
|
||||
.tdd_sync_out (tdd_sync_out),
|
||||
.tdd_sync_in (tdd_sync_in));
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
|
@ -36,8 +36,8 @@ set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVDS_25} [get_ports tx_data_o
|
|||
set_property -dict {PACKAGE_PIN AB14 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[5]] ; ## H20 FMC_LPC_LA15_N
|
||||
set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS25} [get_ports enable] ; ## G18 FMC_LPC_LA16_P
|
||||
set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVCMOS25} [get_ports txnrx] ; ## G19 FMC_LPC_LA16_N
|
||||
set_property -dict {PACKAGE_PIN AC19 IOSTANDARD LVCMOS25} [get_ports tdd_sync_req] ; ## PMOD1_7_LS
|
||||
set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVCMOS25} [get_ports tdd_sync_ack] ; ## PMOD1_5_LS
|
||||
set_property -dict {PACKAGE_PIN AC19 IOSTANDARD LVCMOS25} [get_ports tdd_sync_out] ; ## PMOD1_7_LS
|
||||
set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVCMOS25} [get_ports tdd_sync_in] ; ## PMOD1_5_LS
|
||||
|
||||
set_property -dict {PACKAGE_PIN AG26 IOSTANDARD LVCMOS25} [get_ports gpio_status[0]] ; ## G21 FMC_LPC_LA20_P
|
||||
set_property -dict {PACKAGE_PIN AG27 IOSTANDARD LVCMOS25} [get_ports gpio_status[1]] ; ## G22 FMC_LPC_LA20_N
|
||||
|
|
|
@ -92,8 +92,8 @@ module system_top (
|
|||
|
||||
enable,
|
||||
txnrx,
|
||||
tdd_sync_req,
|
||||
tdd_sync_ack,
|
||||
tdd_sync_out,
|
||||
tdd_sync_in,
|
||||
|
||||
gpio_muxout_tx,
|
||||
gpio_muxout_rx,
|
||||
|
@ -164,8 +164,8 @@ module system_top (
|
|||
|
||||
output enable;
|
||||
output txnrx;
|
||||
inout tdd_sync_req;
|
||||
inout tdd_sync_ack;
|
||||
output tdd_sync_out;
|
||||
input tdd_sync_in;
|
||||
|
||||
inout gpio_muxout_tx;
|
||||
inout gpio_muxout_rx;
|
||||
|
@ -243,6 +243,11 @@ module system_top (
|
|||
.dio_o (gpio_i[14:0]),
|
||||
.dio_p (gpio_bd));
|
||||
|
||||
//========================================================
|
||||
// debug syncronization pulses
|
||||
|
||||
//========================================================
|
||||
|
||||
system_wrapper i_system_wrapper (
|
||||
.ddr_addr (ddr_addr),
|
||||
.ddr_ba (ddr_ba),
|
||||
|
@ -321,8 +326,8 @@ module system_top (
|
|||
.tx_frame_out_p (tx_frame_out_p),
|
||||
.txnrx (txnrx_s),
|
||||
.tdd_enabled (tdd_enabled_s),
|
||||
.tdd_sync_req(tdd_sync_req),
|
||||
.tdd_sync_ack(tdd_sync_ack));
|
||||
.tdd_sync_out(tdd_sync_out),
|
||||
.tdd_sync_in(tdd_sync_in));
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
Loading…
Reference in New Issue