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fmcomms1: Updated common and ZC706 project to the latest flow

main
Adrian Costina 2015-03-25 17:41:14 +02:00
parent 037484e1d0
commit 10f3ac4d22
5 changed files with 220 additions and 277 deletions
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290
projects/fmcomms1/common/fmcomms1_bd.tcl
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@ -1,57 +1,49 @@
source $ad_hdl_dir/projects/common/xilinx/sys_wfifo.tcl
# dac interface
set dac_clk_in_p [create_bd_port -dir I dac_clk_in_p]
set dac_clk_in_n [create_bd_port -dir I dac_clk_in_n]
set dac_clk_out_p [create_bd_port -dir O dac_clk_out_p]
set dac_clk_out_n [create_bd_port -dir O dac_clk_out_n]
set dac_frame_out_p [create_bd_port -dir O dac_frame_out_p]
set dac_frame_out_n [create_bd_port -dir O dac_frame_out_n]
set dac_data_out_p [create_bd_port -dir O -from 15 -to 0 dac_data_out_p]
set dac_data_out_n [create_bd_port -dir O -from 15 -to 0 dac_data_out_n]
create_bd_port -dir I dac_clk_in_p
create_bd_port -dir I dac_clk_in_n
create_bd_port -dir O dac_clk_out_p
create_bd_port -dir O dac_clk_out_n
create_bd_port -dir O dac_frame_out_p
create_bd_port -dir O dac_frame_out_n
create_bd_port -dir O -from 15 -to 0 dac_data_out_p
create_bd_port -dir O -from 15 -to 0 dac_data_out_n
# adc interface
set adc_clk_in_p [create_bd_port -dir I adc_clk_in_p]
set adc_clk_in_n [create_bd_port -dir I adc_clk_in_n]
set adc_or_in_p [create_bd_port -dir I adc_or_in_p]
set adc_or_in_n [create_bd_port -dir I adc_or_in_n]
set adc_data_in_p [create_bd_port -dir I -from 13 -to 0 adc_data_in_p]
set adc_data_in_n [create_bd_port -dir I -from 13 -to 0 adc_data_in_n]
create_bd_port -dir I adc_clk_in_p
create_bd_port -dir I adc_clk_in_n
create_bd_port -dir I adc_or_in_p
create_bd_port -dir I adc_or_in_n
create_bd_port -dir I -from 13 -to 0 adc_data_in_p
create_bd_port -dir I -from 13 -to 0 adc_data_in_n
# reference clock
set ref_clk [create_bd_port -dir O ref_clk]
create_bd_port -dir O ref_clk
# dma interface
set dac_clk [create_bd_port -dir O dac_clk]
set dac_valid_0 [create_bd_port -dir O dac_valid_0]
set dac_enable_0 [create_bd_port -dir O dac_enable_0]
set dac_ddata_0 [create_bd_port -dir I -from 63 -to 0 dac_ddata_0]
set dac_valid_1 [create_bd_port -dir O dac_valid_1]
set dac_enable_1 [create_bd_port -dir O dac_enable_1]
set dac_ddata_1 [create_bd_port -dir I -from 63 -to 0 dac_ddata_1]
set dac_dma_rd [create_bd_port -dir I dac_dma_rd]
set dac_dma_rdata [create_bd_port -dir O -from 63 -to 0 dac_dma_rdata]
create_bd_port -dir O dac_clk
create_bd_port -dir O dac_valid_0
create_bd_port -dir O dac_enable_0
create_bd_port -dir I -from 63 -to 0 dac_ddata_0
create_bd_port -dir O dac_valid_1
create_bd_port -dir O dac_enable_1
create_bd_port -dir I -from 63 -to 0 dac_ddata_1
create_bd_port -dir I dac_dma_rd
create_bd_port -dir O -from 63 -to 0 dac_dma_rdata
set adc_clk [create_bd_port -dir O adc_clk]
set adc_valid_0 [create_bd_port -dir O adc_valid_0]
set adc_enable_0 [create_bd_port -dir O adc_enable_0]
set adc_data_0 [create_bd_port -dir O -from 15 -to 0 adc_data_0]
set adc_valid_1 [create_bd_port -dir O adc_valid_1]
set adc_enable_1 [create_bd_port -dir O adc_enable_1]
set adc_data_1 [create_bd_port -dir O -from 15 -to 0 adc_data_1]
set adc_dma_wr [create_bd_port -dir I adc_dma_wr]
set adc_dma_sync [create_bd_port -dir I adc_dma_sync]
set adc_dma_wdata [create_bd_port -dir I -from 31 -to 0 adc_dma_wdata]
# interrupts
set ad9122_dma_irq [create_bd_port -dir O ad9122_dma_irq]
set ad9643_dma_irq [create_bd_port -dir O ad9643_dma_irq]
create_bd_port -dir O adc_clk
create_bd_port -dir O adc_valid_0
create_bd_port -dir O adc_enable_0
create_bd_port -dir O -from 15 -to 0 adc_data_0
create_bd_port -dir O adc_valid_1
create_bd_port -dir O adc_enable_1
create_bd_port -dir O -from 15 -to 0 adc_data_1
create_bd_port -dir I adc_dma_wr
create_bd_port -dir I -from 31 -to 0 adc_dma_wdata
# dac peripherals
@ -67,10 +59,6 @@
set_property -dict [list CONFIG.C_AXI_SLICE_SRC {1}] $axi_ad9122_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9122_dma
if {$sys_zynq == 1} {
set_property -dict [list CONFIG.C_DMA_AXI_PROTOCOL_SRC {1}] $axi_ad9122_dma
}
# adc peripherals
set axi_ad9643 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9643:1.0 axi_ad9643]
@ -85,146 +73,100 @@ if {$sys_zynq == 1} {
set_property -dict [list CONFIG.C_AXI_SLICE_SRC {1}] $axi_ad9643_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9643_dma
if {$sys_zynq == 1} {
set_property -dict [list CONFIG.C_DMA_AXI_PROTOCOL_DEST {1}] $axi_ad9643_dma
}
# reference clock
if {$sys_zynq == 0} {
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9643_dma
}
set refclk_clkgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 refclk_clkgen]
set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {30} ] [get_bd_cells refclk_clkgen]
set_property -dict [list CONFIG.USE_PHASE_ALIGNMENT {false} ] [get_bd_cells refclk_clkgen]
set_property -dict [list CONFIG.JITTER_SEL {Min_O_Jitter} ] [get_bd_cells refclk_clkgen]
set_property -dict [list CONFIG.USE_LOCKED {false} ] [get_bd_cells refclk_clkgen]
set_property -dict [list CONFIG.USE_RESET {false} ] [get_bd_cells refclk_clkgen]
# additions to default configuration
# connections (dac)
set_property -dict [list CONFIG.NUM_MI {11}] $axi_cpu_interconnect
ad_connect dac_clk axi_ad9122/dac_div_clk
ad_connect dac_clk axi_ad9122_dma/fifo_rd_clk
if {$sys_zynq == 0} {
set_property -dict [list CONFIG.NUM_SI {10}] $axi_mem_interconnect
}
ad_connect dac_clk_in_p axi_ad9122/dac_clk_in_p
ad_connect dac_clk_in_n axi_ad9122/dac_clk_in_n
ad_connect dac_clk_out_p axi_ad9122/dac_clk_out_p
ad_connect dac_clk_out_n axi_ad9122/dac_clk_out_n
ad_connect dac_frame_out_p axi_ad9122/dac_frame_out_p
ad_connect dac_frame_out_n axi_ad9122/dac_frame_out_n
ad_connect dac_data_out_p axi_ad9122/dac_data_out_p
ad_connect dac_data_out_n axi_ad9122/dac_data_out_n
if {$sys_zynq == 1} {
set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $sys_ps7
}
ad_connect axi_ad9122/dac_valid_0 dac_valid_0
ad_connect axi_ad9122/dac_enable_0 dac_enable_0
ad_connect axi_ad9122/dac_ddata_0 dac_ddata_0
ad_connect axi_ad9122/dac_valid_1 dac_valid_1
ad_connect axi_ad9122/dac_enable_1 dac_enable_1
ad_connect axi_ad9122/dac_ddata_1 dac_ddata_1
ad_connect axi_ad9122/dac_dunf axi_ad9122_dma/fifo_rd_underflow
# reference clock shared with audio clock
set_property -dict [list CONFIG.CLKOUT2_USED {true}] $sys_audio_clkgen
set_property -dict [list CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {30.3030}] $sys_audio_clkgen
# connections (dac)
connect_bd_net -net dac_div_clk [get_bd_ports dac_clk] [get_bd_pins axi_ad9122/dac_div_clk]
connect_bd_net -net dac_div_clk [get_bd_pins axi_ad9122_dma/fifo_rd_clk]
connect_bd_net -net axi_ad9122_dac_clk_in_p [get_bd_ports dac_clk_in_p] [get_bd_pins axi_ad9122/dac_clk_in_p]
connect_bd_net -net axi_ad9122_dac_clk_in_n [get_bd_ports dac_clk_in_n] [get_bd_pins axi_ad9122/dac_clk_in_n]
connect_bd_net -net axi_ad9122_dac_clk_out_p [get_bd_ports dac_clk_out_p] [get_bd_pins axi_ad9122/dac_clk_out_p]
connect_bd_net -net axi_ad9122_dac_clk_out_n [get_bd_ports dac_clk_out_n] [get_bd_pins axi_ad9122/dac_clk_out_n]
connect_bd_net -net axi_ad9122_dac_frame_out_p [get_bd_ports dac_frame_out_p] [get_bd_pins axi_ad9122/dac_frame_out_p]
connect_bd_net -net axi_ad9122_dac_frame_out_n [get_bd_ports dac_frame_out_n] [get_bd_pins axi_ad9122/dac_frame_out_n]
connect_bd_net -net axi_ad9122_dac_data_out_p [get_bd_ports dac_data_out_p] [get_bd_pins axi_ad9122/dac_data_out_p]
connect_bd_net -net axi_ad9122_dac_data_out_n [get_bd_ports dac_data_out_n] [get_bd_pins axi_ad9122/dac_data_out_n]
connect_bd_net -net axi_ad9122_dac_valid_0 [get_bd_pins axi_ad9122/dac_valid_0] [get_bd_ports dac_valid_0]
connect_bd_net -net axi_ad9122_dac_enable_0 [get_bd_pins axi_ad9122/dac_enable_0] [get_bd_ports dac_enable_0]
connect_bd_net -net axi_ad9122_dac_ddata_0 [get_bd_pins axi_ad9122/dac_ddata_0] [get_bd_ports dac_ddata_0]
connect_bd_net -net axi_ad9122_dac_valid_1 [get_bd_pins axi_ad9122/dac_valid_1] [get_bd_ports dac_valid_1]
connect_bd_net -net axi_ad9122_dac_enable_1 [get_bd_pins axi_ad9122/dac_enable_1] [get_bd_ports dac_enable_1]
connect_bd_net -net axi_ad9122_dac_ddata_1 [get_bd_pins axi_ad9122/dac_ddata_1] [get_bd_ports dac_ddata_1]
connect_bd_net -net axi_ad9122_dac_dunf [get_bd_pins axi_ad9122/dac_dunf] [get_bd_pins axi_ad9122_dma/fifo_rd_underflow]
connect_bd_net -net axi_ad9122_dma_drd [get_bd_pins axi_ad9122_dma/fifo_rd_en] [get_bd_ports dac_dma_rd]
connect_bd_net -net axi_ad9122_dma_ddata [get_bd_pins axi_ad9122_dma/fifo_rd_dout] [get_bd_ports dac_dma_rdata]
connect_bd_net -net axi_ad9122_dma_irq [get_bd_pins axi_ad9122_dma/irq] [get_bd_ports ad9122_dma_irq]
ad_connect dac_dma_rd axi_ad9122_dma/fifo_rd_en
ad_connect dac_dma_rdata axi_ad9122_dma/fifo_rd_dout
# connections (adc)
p_sys_wfifo [current_bd_instance .] sys_wfifo 32 64
connect_bd_net -net adc_clk [get_bd_ports adc_clk] [get_bd_pins axi_ad9643/adc_clk] [get_bd_pins sys_wfifo/m_clk]
connect_bd_net -net sys_200m_clk [get_bd_pins sys_wfifo/s_clk] [get_bd_pins axi_ad9643_dma/fifo_wr_clk] [get_bd_pins axi_ad9643/delay_clk]
connect_bd_net -net sys_100m_resetn [get_bd_pins sys_wfifo/rstn] $sys_100m_resetn_source
ad_connect adc_clk axi_ad9643/adc_clk
ad_connect adc_clk sys_wfifo/adc_clk
ad_connect sys_200m_clk sys_wfifo/dma_clk
ad_connect sys_200m_clk axi_ad9643_dma/fifo_wr_clk
ad_connect sys_200m_clk axi_ad9643/delay_clk
ad_connect sys_cpu_reset sys_wfifo/adc_rst
connect_bd_net -net axi_ad9643_adc_clk_in_p [get_bd_ports adc_clk_in_p] [get_bd_pins axi_ad9643/adc_clk_in_p]
connect_bd_net -net axi_ad9643_adc_clk_in_n [get_bd_ports adc_clk_in_n] [get_bd_pins axi_ad9643/adc_clk_in_n]
connect_bd_net -net axi_ad9643_adc_or_in_p [get_bd_ports adc_or_in_p] [get_bd_pins axi_ad9643/adc_or_in_p]
connect_bd_net -net axi_ad9643_adc_or_in_n [get_bd_ports adc_or_in_n] [get_bd_pins axi_ad9643/adc_or_in_n]
connect_bd_net -net axi_ad9643_adc_data_in_p [get_bd_ports adc_data_in_p] [get_bd_pins axi_ad9643/adc_data_in_p]
connect_bd_net -net axi_ad9643_adc_data_in_n [get_bd_ports adc_data_in_n] [get_bd_pins axi_ad9643/adc_data_in_n]
ad_connect adc_clk_in_p axi_ad9643/adc_clk_in_p
ad_connect adc_clk_in_n axi_ad9643/adc_clk_in_n
ad_connect adc_or_in_p axi_ad9643/adc_or_in_p
ad_connect adc_or_in_n axi_ad9643/adc_or_in_n
ad_connect adc_data_in_p axi_ad9643/adc_data_in_p
ad_connect adc_data_in_n axi_ad9643/adc_data_in_n
connect_bd_net -net axi_ad9643_adc_valid_0 [get_bd_ports adc_valid_0] [get_bd_pins axi_ad9643/adc_valid_0]
connect_bd_net -net axi_ad9643_adc_enable_0 [get_bd_ports adc_enable_0] [get_bd_pins axi_ad9643/adc_enable_0]
connect_bd_net -net axi_ad9643_adc_data_0 [get_bd_ports adc_data_0] [get_bd_pins axi_ad9643/adc_data_0]
connect_bd_net -net axi_ad9643_adc_valid_1 [get_bd_ports adc_valid_1] [get_bd_pins axi_ad9643/adc_valid_1]
connect_bd_net -net axi_ad9643_adc_enable_1 [get_bd_ports adc_enable_1] [get_bd_pins axi_ad9643/adc_enable_1]
connect_bd_net -net axi_ad9643_adc_data_1 [get_bd_ports adc_data_1] [get_bd_pins axi_ad9643/adc_data_1]
connect_bd_net -net axi_ad9643_adc_dovf [get_bd_pins axi_ad9643/adc_dovf] [get_bd_pins sys_wfifo/m_wovf]
ad_connect adc_valid_0 axi_ad9643/adc_valid_0
ad_connect adc_enable_0 axi_ad9643/adc_enable_0
ad_connect adc_data_0 axi_ad9643/adc_data_0
ad_connect adc_valid_1 axi_ad9643/adc_valid_1
ad_connect adc_enable_1 axi_ad9643/adc_enable_1
ad_connect adc_data_1 axi_ad9643/adc_data_1
ad_connect axi_ad9643/adc_dovf sys_wfifo/adc_wovf
connect_bd_net -net axi_ad9643_fifo_wr [get_bd_ports adc_dma_wr] [get_bd_pins sys_wfifo/m_wr]
connect_bd_net -net axi_ad9643_fifo_wdata [get_bd_ports adc_dma_wdata] [get_bd_pins sys_wfifo/m_wdata]
ad_connect adc_dma_wr sys_wfifo/adc_wr
ad_connect adc_dma_wdata sys_wfifo/adc_wdata
connect_bd_net -net axi_ad9643_dma_dwr [get_bd_pins sys_wfifo/s_wr] [get_bd_pins axi_ad9643_dma/fifo_wr_en]
connect_bd_net -net axi_ad9643_dma_dsync [get_bd_ports adc_dma_sync] [get_bd_pins axi_ad9643_dma/fifo_wr_sync]
connect_bd_net -net axi_ad9643_dma_ddata [get_bd_pins sys_wfifo/s_wdata] [get_bd_pins axi_ad9643_dma/fifo_wr_din]
connect_bd_net -net axi_ad9643_dma_dovf [get_bd_pins sys_wfifo/s_wovf] [get_bd_pins axi_ad9643_dma/fifo_wr_overflow]
connect_bd_net -net axi_ad9643_dma_irq [get_bd_pins axi_ad9643_dma/irq] [get_bd_ports ad9643_dma_irq]
ad_connect sys_wfifo/dma_wr axi_ad9643_dma/fifo_wr_en
ad_connect sys_wfifo/dma_wdata axi_ad9643_dma/fifo_wr_din
ad_connect sys_wfifo/dma_wovf axi_ad9643_dma/fifo_wr_overflow
# interconnect (cpu)
ad_connect sys_cpu_resetn axi_ad9122_dma/m_src_axi_aresetn
ad_connect sys_cpu_resetn axi_ad9643_dma/m_dest_axi_aresetn
connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_ad9122/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_ad9643/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_ad9643_dma/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_ad9122_dma/s_axi]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M09_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M10_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9122/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9122_dma/s_axi_aclk]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9122/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9122_dma/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M10_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9643/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9643_dma/s_axi_aclk]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9643/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9643_dma/s_axi_aresetn]
# reference clock
# interconnect (mem/dac)
ad_connect sys_200m_clk refclk_clkgen/clk_in1
ad_connect ref_clk refclk_clkgen/clk_out1
if {$sys_zynq == 0 } {
connect_bd_intf_net -intf_net axi_mem_interconnect_s08_axi [get_bd_intf_pins axi_mem_interconnect/S08_AXI] [get_bd_intf_pins axi_ad9122_dma/m_src_axi]
connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/S08_ACLK] $sys_200m_clk_source
connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9122_dma/m_src_axi_aclk]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S08_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9122_dma/m_src_axi_aresetn]
} else {
connect_bd_intf_net -intf_net axi_ad9122_dma_axi [get_bd_intf_pins sys_ps7/S_AXI_HP2] [get_bd_intf_pins axi_ad9122_dma/m_src_axi]
connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9122_dma/m_src_axi_aclk]
connect_bd_net -net sys_200m_clk [get_bd_pins sys_ps7/S_AXI_HP2_ACLK]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9122_dma/m_src_axi_aresetn]
}
# address map
# interconnect (mem/adc)
ad_cpu_interconnect 0x74200000 axi_ad9122
ad_cpu_interconnect 0x79020000 axi_ad9643
ad_cpu_interconnect 0x7c400000 axi_ad9643_dma
ad_cpu_interconnect 0x7c420000 axi_ad9122_dma
ad_mem_hp1_interconnect sys_200m_clk sys_ps7/S_AXI_HP1
ad_mem_hp1_interconnect sys_200m_clk axi_ad9643_dma/m_dest_axi
ad_mem_hp2_interconnect sys_200m_clk sys_ps7/S_AXI_HP2
ad_mem_hp2_interconnect sys_200m_clk axi_ad9122_dma/m_src_axi
if {$sys_zynq == 0 } {
connect_bd_intf_net -intf_net axi_mem_interconnect_s09_axi [get_bd_intf_pins axi_mem_interconnect/S09_AXI] [get_bd_intf_pins axi_ad9643_dma/m_dest_axi]
connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/S09_ACLK] $sys_200m_clk_source
connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9643_dma/m_dest_axi_aclk]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S09_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9643_dma/m_dest_axi_aresetn]
} else {
connect_bd_intf_net -intf_net axi_ad9643_dma_axi [get_bd_intf_pins sys_ps7/S_AXI_HP1] [get_bd_intf_pins axi_ad9643_dma/m_dest_axi]
connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9643_dma/m_dest_axi_aclk]
connect_bd_net -net sys_200m_clk [get_bd_pins sys_ps7/S_AXI_HP1_ACLK]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9643_dma/m_dest_axi_aresetn]
}
# interrupts
# ila (adc)
ad_cpu_interrupt ps-12 mb-12 axi_ad9122_dma/irq
ad_cpu_interrupt ps-13 mb-13 axi_ad9643_dma/irq
set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_adc]
# ila (adc)
set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.0 ila_adc]
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc
set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_adc
set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_adc
@ -232,25 +174,7 @@ if {$sys_zynq == 0 } {
set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc
set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc
connect_bd_net -net sys_200m_clk [get_bd_pins ila_adc/clk]
connect_bd_net -net axi_ad9643_dma_dwr [get_bd_pins ila_adc/PROBE0]
connect_bd_net -net axi_ad9643_dma_ddata [get_bd_pins ila_adc/PROBE1]
ad_connect sys_200m_clk ila_adc/clk
ad_connect sys_wfifo/dma_wr ila_adc/PROBE0
ad_connect sys_wfifo/dma_wdata ila_adc/PROBE1
# reference clock
connect_bd_net -net fmcomms1_ref_clk [get_bd_pins sys_audio_clkgen/clk_out2] [get_bd_ports ref_clk]
# address map
create_bd_addr_seg -range 0x00010000 -offset 0x74200000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9122/s_axi/axi_lite] SEG_data_ad9122
create_bd_addr_seg -range 0x00010000 -offset 0x79020000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9643/s_axi/axi_lite] SEG_data_ad9643
create_bd_addr_seg -range 0x00010000 -offset 0x7c400000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9643_dma/s_axi/axi_lite] SEG_data_ad9122_dma
create_bd_addr_seg -range 0x00010000 -offset 0x7c420000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9122_dma/s_axi/axi_lite] SEG_data_ad9643_dma
if {$sys_zynq == 0} {
create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9643_dma/m_dest_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl
create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9122_dma/m_src_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl
} else {
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9643_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9122_dma/m_src_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_sys_ps7_hp2_ddr_lowocm
}

1
projects/fmcomms1/zc706/system_bd.tcl
View File

@ -1,4 +1,5 @@
source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/sys_wfifo.tcl
source ../common/fmcomms1_bd.tcl

3
projects/fmcomms1/zc706/system_constr.xdc
View File

@ -85,6 +85,3 @@ set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_
create_clock -name dac_clk_in -period 2.00 [get_ports dac_clk_in_p]
create_clock -name adc_clk_in -period 4.00 [get_ports adc_clk_in_p]
create_clock -name dac_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/axi_ad9122/dac_div_clk]
set_false_path -from [get_pins i_system_wrapper/system_i/axi_ad9643_dma/inst/i_request_arb/i_src_dma_fifo/overflow_reg/C] \
-to [get_pins i_system_wrapper/system_i/sys_wfifo/wfifo_ctl/inst/m_wovf_m1_reg/D]

1
projects/fmcomms1/zc706/system_project.tcl
View File

@ -1,6 +1,7 @@
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project_create fmcomms1_zc706
adi_project_files fmcomms1_zc706 [list \

202
projects/fmcomms1/zc706/system_top.v
View File

@ -41,28 +41,28 @@
module system_top (
DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
ddr_addr,
ddr_ba,
ddr_cas_n,
ddr_ck_n,
ddr_ck_p,
ddr_cke,
ddr_cs_n,
ddr_dm,
ddr_dq,
ddr_dqs_n,
ddr_dqs_p,
ddr_odt,
ddr_ras_n,
ddr_reset_n,
ddr_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
fixed_io_ddr_vrn,
fixed_io_ddr_vrp,
fixed_io_mio,
fixed_io_ps_clk,
fixed_io_ps_porb,
fixed_io_ps_srstb,
gpio_bd,
@ -96,28 +96,28 @@ module system_top (
iic_scl,
iic_sda);
inout [14:0] DDR_addr;
inout [ 2:0] DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [ 3:0] DDR_dm;
inout [31:0] DDR_dq;
inout [ 3:0] DDR_dqs_n;
inout [ 3:0] DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout [14:0] ddr_addr;
inout [ 2:0] ddr_ba;
inout ddr_cas_n;
inout ddr_ck_n;
inout ddr_ck_p;
inout ddr_cke;
inout ddr_cs_n;
inout [ 3:0] ddr_dm;
inout [31:0] ddr_dq;
inout [ 3:0] ddr_dqs_n;
inout [ 3:0] ddr_dqs_p;
inout ddr_odt;
inout ddr_ras_n;
inout ddr_reset_n;
inout ddr_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0] FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
inout fixed_io_ddr_vrn;
inout fixed_io_ddr_vrp;
inout [53:0] fixed_io_mio;
inout fixed_io_ps_clk;
inout fixed_io_ps_porb;
inout fixed_io_ps_srstb;
inout [14:0] gpio_bd;
@ -162,9 +162,17 @@ module system_top (
// internal signals
wire [14:0] gpio_i;
wire [14:0] gpio_o;
wire [14:0] gpio_t;
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [ 2:0] spi0_csn;
wire spi0_clk;
wire spi0_mosi;
wire spi0_miso;
wire [ 2:0] spi1_csn;
wire spi1_clk;
wire spi1_mosi;
wire spi1_miso;
wire dac_clk;
wire dac_valid_0;
wire dac_enable_0;
@ -180,7 +188,6 @@ module system_top (
wire [15:0] adc_data_1;
wire ref_clk;
wire oddr_ref_clk;
wire [15:0] ps_intrs;
// instantiations
@ -205,9 +212,9 @@ module system_top (
ad_iobuf #(
.DATA_WIDTH(15))
i_gpio_bd (
.dt(gpio_t),
.di(gpio_o),
.do(gpio_i),
.dt(gpio_t[14:0]),
.di(gpio_o[14:0]),
.do(gpio_i[14:0]),
.dio(gpio_bd));
always @(posedge dac_clk) begin
@ -241,30 +248,30 @@ module system_top (
end
system_wrapper i_system_wrapper (
.DDR_addr (DDR_addr),
.DDR_ba (DDR_ba),
.DDR_cas_n (DDR_cas_n),
.DDR_ck_n (DDR_ck_n),
.DDR_ck_p (DDR_ck_p),
.DDR_cke (DDR_cke),
.DDR_cs_n (DDR_cs_n),
.DDR_dm (DDR_dm),
.DDR_dq (DDR_dq),
.DDR_dqs_n (DDR_dqs_n),
.DDR_dqs_p (DDR_dqs_p),
.DDR_odt (DDR_odt),
.DDR_ras_n (DDR_ras_n),
.DDR_reset_n (DDR_reset_n),
.DDR_we_n (DDR_we_n),
.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp),
.FIXED_IO_mio (FIXED_IO_mio),
.FIXED_IO_ps_clk (FIXED_IO_ps_clk),
.FIXED_IO_ps_porb (FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb),
.GPIO_I (gpio_i),
.GPIO_O (gpio_o),
.GPIO_T (gpio_t),
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.adc_clk (adc_clk),
.adc_clk_in_n (adc_clk_in_n),
.adc_clk_in_p (adc_clk_in_p),
@ -272,7 +279,6 @@ module system_top (
.adc_data_1 (adc_data_1),
.adc_data_in_n (adc_data_in_n),
.adc_data_in_p (adc_data_in_p),
.adc_dma_sync (1'b1),
.adc_dma_wdata (adc_dma_wdata),
.adc_dma_wr (adc_dma_wr),
.adc_enable_0 (adc_enable_0),
@ -305,24 +311,38 @@ module system_top (
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.ps_intr_0 (ps_intrs[0]),
.ps_intr_1 (ps_intrs[1]),
.ps_intr_10 (ps_intrs[10]),
.ps_intr_11 (ps_intrs[11]),
.ps_intr_12 (ps_intrs[12]),
.ps_intr_13 (ps_intrs[13]),
.ps_intr_2 (ps_intrs[2]),
.ps_intr_3 (ps_intrs[3]),
.ps_intr_4 (ps_intrs[4]),
.ps_intr_5 (ps_intrs[5]),
.ps_intr_6 (ps_intrs[6]),
.ps_intr_7 (ps_intrs[7]),
.ps_intr_8 (ps_intrs[8]),
.ps_intr_9 (ps_intrs[9]),
.ad9122_dma_irq (ps_intrs[12]),
.ad9643_dma_irq (ps_intrs[13]),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.ps_intr_10 (1'b0),
.ps_intr_11 (1'b0),
.ref_clk (ref_clk),
.spdif (spdif));
.spdif (spdif),
.spi0_clk_i (spi0_clk),
.spi0_clk_o (spi0_clk),
.spi0_csn_0_o (spi0_csn[0]),
.spi0_csn_1_o (spi0_csn[1]),
.spi0_csn_2_o (spi0_csn[2]),
.spi0_csn_i (1'b1),
.spi0_sdi_i (spi0_miso),
.spi0_sdo_i (spi0_mosi),
.spi0_sdo_o (spi0_mosi),
.spi1_clk_i (spi1_clk),
.spi1_clk_o (spi1_clk),
.spi1_csn_0_o (spi1_csn[0]),
.spi1_csn_1_o (spi1_csn[1]),
.spi1_csn_2_o (spi1_csn[2]),
.spi1_csn_i (1'b1),
.spi1_sdi_i (1'b1),
.spi1_sdo_i (spi1_mosi),
.spi1_sdo_o (spi1_mosi));
endmodule