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ad_rst: Update all the modules, which instantiate the ad_rst

main
Istvan Csomortani 2018-07-18 15:21:33 +01:00 committed by István Csomortáni
parent 472b12feb7
commit 11071516d1
10 changed files with 20 additions and 16 deletions
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3
library/axi_gpreg/axi_gpreg_clock_mon.v
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@ -122,8 +122,9 @@ module axi_gpreg_clock_mon #(
.d_clk (d_clk_g));
ad_rst i_d_rst_reg (
.preset (up_d_preset),
.rst_async (up_d_preset),
.clk (d_clk_g),
.rstn (),
.rst (d_rst));
generate

6
library/axi_logic_analyzer/axi_logic_analyzer_reg.v
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@ -57,9 +57,9 @@ module axi_logic_analyzer_reg (
output [15:0] overwrite_data,
input [15:0] input_data,
output [15:0] od_pp_n,
input triggered,
output streaming,
// bus interface
@ -220,7 +220,7 @@ module axi_logic_analyzer_reg (
end
end
ad_rst i_core_rst_reg (.preset(!up_rstn), .clk(clk), .rst(reset));
ad_rst i_core_rst_reg (.rst_async(~up_rstn), .clk(clk), .rstn(), .rst(reset));
up_xfer_cntrl #(.DATA_WIDTH(285)) i_xfer_cntrl (
.up_rstn (up_rstn),

4
library/common/up_adc_common.v
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@ -403,8 +403,8 @@ module up_adc_common #(
// resets
ad_rst i_mmcm_rst_reg (.preset(up_mmcm_preset), .clk(up_clk), .rst(mmcm_rst));
ad_rst i_core_rst_reg (.preset(up_core_preset), .clk(adc_clk), .rst(adc_rst));
ad_rst i_mmcm_rst_reg (.rst_async(up_mmcm_preset), .clk(up_clk), .rstn(), .rst(mmcm_rst));
ad_rst i_core_rst_reg (.rst_async(up_core_preset), .clk(adc_clk), .rstn(), .rst(adc_rst));
// adc control & status

2
library/common/up_clkgen.v
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@ -176,7 +176,7 @@ module up_clkgen #(
// resets
ad_rst i_mmcm_rst_reg (.preset(up_mmcm_preset), .clk(up_clk), .rst(mmcm_rst));
ad_rst i_mmcm_rst_reg (.rst_async(up_mmcm_preset), .clk(up_clk), .rstn(), .rst(mmcm_rst));
endmodule

4
library/common/up_dac_common.v
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@ -407,8 +407,8 @@ module up_dac_common #(
// resets
ad_rst i_mmcm_rst_reg (.preset(up_mmcm_preset), .clk(up_clk), .rst(mmcm_rst));
ad_rst i_core_rst_reg (.preset(up_core_preset), .clk(dac_clk), .rst(dac_rst));
ad_rst i_mmcm_rst_reg (.rst_async(up_mmcm_preset), .clk(up_clk), .rstn(), .rst(mmcm_rst));
ad_rst i_core_rst_reg (.rst_async(up_core_preset), .clk(dac_clk), .rstn(), .rst(dac_rst));
// dac control & status

3
library/common/up_delay_cntrl.v
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@ -205,8 +205,9 @@ module up_delay_cntrl #(
assign delay_rst = delay_rst_s;
ad_rst i_delay_rst_reg (
.preset (up_preset),
.rst_async (up_preset),
.clk (delay_clk),
.rstn (),
.rst (delay_rst_s));
end
endgenerate

3
library/common/up_hdmi_rx.v
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@ -221,8 +221,9 @@ module up_hdmi_rx #(
// resets
ad_rst i_hdmi_rst_reg (
.preset (up_core_preset),
.rst_async (up_core_preset),
.clk (hdmi_clk),
.rstn (),
.rst (hdmi_rst));
// hdmi control & status

6
library/common/up_hdmi_tx.v
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@ -267,8 +267,8 @@ module up_hdmi_tx #(
// resets
ad_rst i_core_rst_reg (.preset(up_core_preset), .clk(hdmi_clk), .rst(hdmi_rst));
ad_rst i_vdma_rst_reg (.preset(up_core_preset), .clk(vdma_clk), .rst(vdma_rst));
ad_rst i_core_rst_reg (.rst_async(up_core_preset), .clk(hdmi_clk), .rstn(), .rst(hdmi_rst));
ad_rst i_vdma_rst_reg (.rst_async(up_core_preset), .clk(vdma_clk), .rstn(), .rst(vdma_rst));
// hdmi control & status
@ -340,7 +340,7 @@ module up_hdmi_tx #(
up_vdma_tpm_oos_s}),
.d_rst (vdma_rst),
.d_clk (vdma_clk),
.d_data_status ({ vdma_ovf,
.d_data_status ({ vdma_ovf,
vdma_unf,
vdma_tpm_oos}));

2
library/common/up_pmod.v
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@ -118,7 +118,7 @@ module up_pmod #(
// resets
ad_rst i_adc_rst_reg (.preset(up_preset_s), .clk(pmod_clk), .rst(pmod_rst));
ad_rst i_adc_rst_reg (.rst_async(up_preset_s), .clk(pmod_clk), .rstn(), .rst(pmod_rst));
// adc control & status

3
library/spi_engine/axi_spi_engine/axi_spi_engine.v
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@ -333,8 +333,9 @@ generate if (ASYNC_SPI_CLK) begin
wire spi_reset;
ad_rst i_spi_resetn (
.preset(up_sw_reset),
.rst_async(up_sw_reset),
.clk(spi_clk),
.rstn(),
.rst(spi_reset)
);
assign spi_resetn = ~spi_reset;