From 11822e2824030e49549bab715b9db3c4144447f7 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Fri, 2 Oct 2020 08:09:23 +0100 Subject: [PATCH] cn0540/coraz7s: Set and input delay of one spi_clk cycle for the MISO line Note, the current SCLK to spi_clk ratio is four. That means, the input delay in the MISO line is 25% of the SCLK period. If the SCLK to spi_clk ratio is changing, this constraint must be updated. --- projects/cn0540/coraz7s/system_constr.xdc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/projects/cn0540/coraz7s/system_constr.xdc b/projects/cn0540/coraz7s/system_constr.xdc index 20f0e1ffc..961e4a90d 100755 --- a/projects/cn0540/coraz7s/system_constr.xdc +++ b/projects/cn0540/coraz7s/system_constr.xdc @@ -35,6 +35,6 @@ create_generated_clock -name spi_clk -source [get_pins -filter name=~*CLKIN1 -of create_generated_clock -name SCLK_clk -source [get_pins -hier -filter name=~*sclk_reg/C] -edges {1 3 5} [get_ports cn0540_spi_sclk] # input delays for MISO lines (SDO for the device) -set_input_delay -clock [get_clocks SCLK_clk] -max 0.6 [get_ports cn0540_spi_miso] -clock_fall -set_input_delay -clock [get_clocks SCLK_clk] -min 0.1 [get_ports cn0540_spi_miso] -clock_fall +set_input_delay -clock [get_clocks spi_clk] [get_property PERIOD [get_clocks spi_clk]] \ + [get_ports -filter {NAME =~ "cn0540_spi_miso"}]