ad7616_sdz: Add support for parallel interface
parent
fbb0d368bf
commit
118577f64f
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@ -10,6 +10,7 @@ create_bd_port -dir I sdi_1
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create_bd_port -dir O -from 15 -to 0 db_o
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create_bd_port -dir O -from 15 -to 0 db_o
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create_bd_port -dir I -from 15 -to 0 db_i
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create_bd_port -dir I -from 15 -to 0 db_i
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create_bd_port -dir O db_t
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create_bd_port -dir O rd_n
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create_bd_port -dir O rd_n
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create_bd_port -dir O wr_n
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create_bd_port -dir O wr_n
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@ -46,10 +47,22 @@ if {$ad7616_if == 0} {
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} else {
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} else {
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ad_connect db_o axi_ad7616/db_o
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ad_connect db_i axi_ad7616/db_i
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ad_connect db_t axi_ad7616/db_t
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ad_connect rd_n axi_ad7616/rd_n
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ad_connect wr_n axi_ad7616/wr_n
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ad_connect cs_n axi_ad7616/cs_n
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ad_connect cnvst axi_ad7616/cnvst
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ad_connect busy axi_ad7616/busy
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}
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}
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ad_connect axi_ad7616/m_axis axi_ad7616_dma/s_axis
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ad_connect sys_cpu_clk axi_ad7616_dma/s_axis_aclk
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ad_connect sys_cpu_clk axi_ad7616_dma/s_axis_aclk
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ad_connect axi_ad7616/m_axis axi_ad7616_dma/s_axis
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ad_connect axi_ad7616/m_axis_xfer_req axi_ad7616_dma/s_axis_xfer_req
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# interconnect
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# interconnect
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@ -1,36 +1,36 @@
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# ad7616
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# ad7616
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set_property -dict {PACKAGE_PIN AC14 IOSTANDARD LVCMOS25} [get_ports db[0] ] ; ## FMC_LPC_LA10_P
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set_property -dict {PACKAGE_PIN AC14 IOSTANDARD LVCMOS25} [get_ports adc_db[0] ] ; ## FMC_LPC_LA10_P
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set_property -dict {PACKAGE_PIN AJ15 IOSTANDARD LVCMOS25} [get_ports db[1] ] ; ## FMC_LPC_LA04_P
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set_property -dict {PACKAGE_PIN AJ15 IOSTANDARD LVCMOS25} [get_ports adc_db[1] ] ; ## FMC_LPC_LA04_P
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set_property -dict {PACKAGE_PIN AH14 IOSTANDARD LVCMOS25} [get_ports db[2] ] ; ## FMC_LPC_LA09_P
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set_property -dict {PACKAGE_PIN AH14 IOSTANDARD LVCMOS25} [get_ports adc_db[2] ] ; ## FMC_LPC_LA09_P
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set_property -dict {PACKAGE_PIN AG12 IOSTANDARD LVCMOS25} [get_ports db[3] ] ; ## FMC_LPC_LA03_P
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set_property -dict {PACKAGE_PIN AG12 IOSTANDARD LVCMOS25} [get_ports adc_db[3] ] ; ## FMC_LPC_LA03_P
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set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVCMOS25} [get_ports db[4] ] ; ## FMC_LPC_LA05_N
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set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVCMOS25} [get_ports adc_db[4] ] ; ## FMC_LPC_LA05_N
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set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVCMOS25} [get_ports db[5] ] ; ## FMC_LPC_LA02_N
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set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVCMOS25} [get_ports adc_db[5] ] ; ## FMC_LPC_LA02_N
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set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVCMOS25} [get_ports db[6] ] ; ## FMC_LPC_LA06_N
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set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVCMOS25} [get_ports adc_db[6] ] ; ## FMC_LPC_LA06_N
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set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVCMOS25} [get_ports db[7] ] ; ## FMC_LPC_LA00_CC_N
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set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVCMOS25} [get_ports adc_db[7] ] ; ## FMC_LPC_LA00_CC_N
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set_property -dict {PACKAGE_PIN AE16 IOSTANDARD LVCMOS25} [get_ports db[8] ] ; ## FMC_LPC_LA05_P
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set_property -dict {PACKAGE_PIN AE16 IOSTANDARD LVCMOS25} [get_ports adc_db[8] ] ; ## FMC_LPC_LA05_P
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set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVCMOS25} [get_ports db[9] ] ; ## FMC_LPC_LA02_P
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set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVCMOS25} [get_ports adc_db[9] ] ; ## FMC_LPC_LA02_P
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set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVCMOS25} [get_ports db[10]] ; ## FMC_LPC_LA16_N
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set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVCMOS25} [get_ports adc_db[10]] ; ## FMC_LPC_LA16_N
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set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS25} [get_ports db[11]] ; ## FMC_LPC_LA00_CC_P
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set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS25} [get_ports adc_db[11]] ; ## FMC_LPC_LA00_CC_P
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set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVCMOS25} [get_ports db[12]] ; ## FMC_LPC_LA01_CC_N
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set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVCMOS25} [get_ports adc_db[12]] ; ## FMC_LPC_LA01_CC_N
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set_property -dict {PACKAGE_PIN AG16 IOSTANDARD LVCMOS25} [get_ports db[13]] ; ## FMC_LPC_CLK0_M2C_N
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set_property -dict {PACKAGE_PIN AG16 IOSTANDARD LVCMOS25} [get_ports adc_db[13]] ; ## FMC_LPC_CLK0_M2C_N
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set_property -dict {PACKAGE_PIN AG17 IOSTANDARD LVCMOS25} [get_ports db[14]] ; ## FMC_LPC_CLK0_M2C_P
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set_property -dict {PACKAGE_PIN AG17 IOSTANDARD LVCMOS25} [get_ports adc_db[14]] ; ## FMC_LPC_CLK0_M2C_P
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set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVCMOS25} [get_ports db[15]] ; ## FMC_LPC_LA01_CC_P
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set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVCMOS25} [get_ports adc_db[15]] ; ## FMC_LPC_LA01_CC_P
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set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVCMOS25} [get_ports rd_n] ; ## FMC_LPC_LA03_N
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set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVCMOS25} [get_ports adc_rd_n] ; ## FMC_LPC_LA03_N
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set_property -dict {PACKAGE_PIN AH13 IOSTANDARD LVCMOS25} [get_ports wr_n] ; ## FMC_LPC_LA09_N
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set_property -dict {PACKAGE_PIN AH13 IOSTANDARD LVCMOS25} [get_ports adc_wr_n] ; ## FMC_LPC_LA09_N
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# control lines
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# control lines
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set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVCOMS25} [get_ports convst] ; ## FMC_LPC_LA24_P
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set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVCMOS25} [get_ports adc_convst] ; ## FMC_LPC_LA24_P
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set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVCOMS25} [get_ports chsel[0]] ; ## FMC_LPC_LA21_N
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set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVCMOS25} [get_ports adc_chsel[0]] ; ## FMC_LPC_LA21_N
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set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVCOMS25} [get_ports chsel[1]] ; ## FMC_LPC_LA26_N
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set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVCMOS25} [get_ports adc_chsel[1]] ; ## FMC_LPC_LA26_N
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set_property -dict {PACKAGE_PIN AF29 IOSTANDARD LVCOMS25} [get_ports chsel[2]] ; ## FMC_LPC_LA25_P
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set_property -dict {PACKAGE_PIN AF29 IOSTANDARD LVCMOS25} [get_ports adc_chsel[2]] ; ## FMC_LPC_LA25_P
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set_property -dict {PACKAGE_PIN AH28 IOSTANDARD LVCOMS25} [get_ports hw_rngsel[0]] ; ## FMC_LPC_LA21_P
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set_property -dict {PACKAGE_PIN AH28 IOSTANDARD LVCMOS25} [get_ports adc_hw_rngsel[0]] ; ## FMC_LPC_LA21_P
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set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD LVCOMS25} [get_ports hw_rngsel[1]] ; ## FMC_LPC_LA26_P
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set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD LVCMOS25} [get_ports adc_hw_rngsel[1]] ; ## FMC_LPC_LA26_P
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set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVCOMS25} [get_ports busy] ; ## FMC_LPC_LA10_N
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set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVCMOS25} [get_ports adc_busy] ; ## FMC_LPC_LA10_N
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set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVCOMS25} [get_ports seq_en] ; ## FMC_LPC_LA27_P
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set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVCMOS25} [get_ports adc_seq_en] ; ## FMC_LPC_LA27_P
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set_property -dict {PACKAGE_PIN AK28 IOSTANDARD LVCOMS25} [get_ports reset_n] ; ## FMC_LPC_LA22_N
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set_property -dict {PACKAGE_PIN AK28 IOSTANDARD LVCMOS25} [get_ports adc_reset_n] ; ## FMC_LPC_LA22_N
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set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVCOMS25} [get_ports cs_n] ; ## FMC_LPC_LA04_N
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set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVCMOS25} [get_ports adc_cs_n] ; ## FMC_LPC_LA04_N
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@ -6,12 +6,9 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
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##--------------------------------------------------------------
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##--------------------------------------------------------------
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# IMPORTANT: Set AD7616 operation and interface mode
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# IMPORTANT: Set AD7616 operation and interface mode
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#
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#
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# ad7616_opm - Defines the operation mode (software OR hardware)
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# ad7616_if - Defines the interface type (serial OR parallel)
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# ad7616_if - Defines the interface type (serial OR parallel)
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#
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#
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# LEGEND: Software - 0
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# LEGEND: Serial - 0
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# Hardware - 1
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# Serial - 0
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# Parallel - 1
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# Parallel - 1
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#
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#
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# NOTE : These switches are 'hardware' switches. User needs to
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# NOTE : These switches are 'hardware' switches. User needs to
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@ -28,7 +25,7 @@ if { $ad7616_if == 0 } {
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adi_project_files ad7616_sdz_zc706 [list \
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adi_project_files ad7616_sdz_zc706 [list \
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"$ad_hdl_dir/library/common/ad_iobuf.v" \
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"$ad_hdl_dir/library/common/ad_iobuf.v" \
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"system_top.v" \
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"system_top_si.v" \
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"serial_if_constr.xdc" \
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"serial_if_constr.xdc" \
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"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc"]
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"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc"]
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@ -36,7 +33,7 @@ if { $ad7616_if == 0 } {
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adi_project_files ad7616_sdz_zc706 [list \
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adi_project_files ad7616_sdz_zc706 [list \
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"$ad_hdl_dir/library/common/ad_iobuf.v" \
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"$ad_hdl_dir/library/common/ad_iobuf.v" \
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"system_top.v" \
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"system_top_pi.v" \
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"parallel_if_constr.xdc" \
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"parallel_if_constr.xdc" \
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"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc"]
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"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc"]
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@ -0,0 +1,248 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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ddr_addr,
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ddr_ba,
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ddr_cas_n,
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ddr_ck_n,
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ddr_ck_p,
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ddr_cke,
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ddr_cs_n,
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ddr_dm,
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ddr_dq,
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ddr_dqs_n,
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ddr_dqs_p,
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ddr_odt,
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ddr_ras_n,
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ddr_reset_n,
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ddr_we_n,
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fixed_io_ddr_vrn,
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fixed_io_ddr_vrp,
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fixed_io_mio,
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fixed_io_ps_clk,
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fixed_io_ps_porb,
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fixed_io_ps_srstb,
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gpio_bd,
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hdmi_out_clk,
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hdmi_vsync,
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hdmi_hsync,
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hdmi_data_e,
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hdmi_data,
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spdif,
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iic_scl,
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iic_sda,
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adc_db,
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adc_rd_n,
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adc_wr_n,
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adc_cs_n,
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adc_reset_n,
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adc_convst,
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adc_busy,
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adc_seq_en,
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adc_hw_rngsel,
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adc_chsel,
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adc_crcen,
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adc_burst,
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adc_os);
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inout [14:0] ddr_addr;
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inout [ 2:0] ddr_ba;
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inout ddr_cas_n;
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inout ddr_ck_n;
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inout ddr_ck_p;
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inout ddr_cke;
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inout ddr_cs_n;
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inout [ 3:0] ddr_dm;
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inout [31:0] ddr_dq;
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inout [ 3:0] ddr_dqs_n;
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inout [ 3:0] ddr_dqs_p;
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inout ddr_odt;
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inout ddr_ras_n;
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inout ddr_reset_n;
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inout ddr_we_n;
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inout fixed_io_ddr_vrn;
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inout fixed_io_ddr_vrp;
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inout [53:0] fixed_io_mio;
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inout fixed_io_ps_clk;
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inout fixed_io_ps_porb;
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inout fixed_io_ps_srstb;
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inout [14:0] gpio_bd;
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output hdmi_out_clk;
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output hdmi_vsync;
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output hdmi_hsync;
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output hdmi_data_e;
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output [23:0] hdmi_data;
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output spdif;
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inout iic_scl;
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inout iic_sda;
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inout [15:0] adc_db;
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output adc_rd_n;
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output adc_wr_n;
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output adc_cs_n;
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output adc_reset_n;
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output adc_convst;
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output adc_busy;
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output adc_seq_en;
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output [ 1:0] adc_hw_rngsel;
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output [ 2:0] adc_chsel;
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output adc_crcen;
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output adc_burst;
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output [ 2:0] adc_os;
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// internal signals
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wire [63:0] gpio_i;
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wire [63:0] gpio_o;
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wire [63:0] gpio_t;
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wire adc_db_t;
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wire [15:0] adc_db_o;
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wire [15:0] adc_db_i;
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genvar i;
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// instantiations
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ad_iobuf #(.DATA_WIDTH(12)) i_iobuf (
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.dio_t (gpio_t[43:32]),
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.dio_i (gpio_o[43:32]),
|
||||||
|
.dio_o (gpio_i[43:32]),
|
||||||
|
.dio_p ({adc_reset_n, // 43
|
||||||
|
adc_hw_rngsel, // 42:41
|
||||||
|
adc_os, // 40:38
|
||||||
|
adc_seq_en, // 37
|
||||||
|
adc_burst, // 36
|
||||||
|
adc_chsel, // 35:33
|
||||||
|
adc_crcen})); // 32
|
||||||
|
|
||||||
|
generate
|
||||||
|
for (i = 0; i < 16; i = i + 1) begin: adc_db_io
|
||||||
|
ad_iobuf i_adc_db (
|
||||||
|
.dio_t(adc_db_t),
|
||||||
|
.dio_i(adc_db_o[i]),
|
||||||
|
.dio_o(adc_db_i[i]),
|
||||||
|
.dio_p(adc_db[i]));
|
||||||
|
end
|
||||||
|
endgenerate
|
||||||
|
|
||||||
|
ad_iobuf #(
|
||||||
|
.DATA_WIDTH(15)
|
||||||
|
) i_gpio_bd (
|
||||||
|
.dio_t(gpio_t[14:0]),
|
||||||
|
.dio_i(gpio_o[14:0]),
|
||||||
|
.dio_o(gpio_i[14:0]),
|
||||||
|
.dio_p(gpio_bd));
|
||||||
|
|
||||||
|
system_wrapper i_system_wrapper (
|
||||||
|
.ddr_addr (ddr_addr),
|
||||||
|
.ddr_ba (ddr_ba),
|
||||||
|
.ddr_cas_n (ddr_cas_n),
|
||||||
|
.ddr_ck_n (ddr_ck_n),
|
||||||
|
.ddr_ck_p (ddr_ck_p),
|
||||||
|
.ddr_cke (ddr_cke),
|
||||||
|
.ddr_cs_n (ddr_cs_n),
|
||||||
|
.ddr_dm (ddr_dm),
|
||||||
|
.ddr_dq (ddr_dq),
|
||||||
|
.ddr_dqs_n (ddr_dqs_n),
|
||||||
|
.ddr_dqs_p (ddr_dqs_p),
|
||||||
|
.ddr_odt (ddr_odt),
|
||||||
|
.ddr_ras_n (ddr_ras_n),
|
||||||
|
.ddr_reset_n (ddr_reset_n),
|
||||||
|
.ddr_we_n (ddr_we_n),
|
||||||
|
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
|
||||||
|
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
|
||||||
|
.fixed_io_mio (fixed_io_mio),
|
||||||
|
.fixed_io_ps_clk (fixed_io_ps_clk),
|
||||||
|
.fixed_io_ps_porb (fixed_io_ps_porb),
|
||||||
|
.fixed_io_ps_srstb (fixed_io_ps_srstb),
|
||||||
|
.gpio_i (gpio_i),
|
||||||
|
.gpio_o (gpio_o),
|
||||||
|
.gpio_t (gpio_t),
|
||||||
|
.hdmi_data (hdmi_data),
|
||||||
|
.hdmi_data_e (hdmi_data_e),
|
||||||
|
.hdmi_hsync (hdmi_hsync),
|
||||||
|
.hdmi_out_clk (hdmi_out_clk),
|
||||||
|
.hdmi_vsync (hdmi_vsync),
|
||||||
|
.iic_main_scl_io (iic_scl),
|
||||||
|
.iic_main_sda_io (iic_sda),
|
||||||
|
.ps_intr_00 (1'b0),
|
||||||
|
.ps_intr_01 (1'b0),
|
||||||
|
.ps_intr_02 (1'b0),
|
||||||
|
.ps_intr_03 (1'b0),
|
||||||
|
.ps_intr_04 (1'b0),
|
||||||
|
.ps_intr_05 (1'b0),
|
||||||
|
.ps_intr_06 (1'b0),
|
||||||
|
.ps_intr_07 (1'b0),
|
||||||
|
.ps_intr_08 (1'b0),
|
||||||
|
.ps_intr_09 (1'b0),
|
||||||
|
.ps_intr_10 (1'b0),
|
||||||
|
.ps_intr_11 (1'b0),
|
||||||
|
.spdif (spdif),
|
||||||
|
.cnvst (adc_convst),
|
||||||
|
.cs_n (adc_cs_n),
|
||||||
|
.busy (adc_busy),
|
||||||
|
.db_o (adc_db_o),
|
||||||
|
.db_i (adc_db_i),
|
||||||
|
.db_t (adc_db_t),
|
||||||
|
.rd_n (adc_rd_n),
|
||||||
|
.wr_n (adc_wr_n)
|
||||||
|
);
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
// ***************************************************************************
|
||||||
|
// ***************************************************************************
|
Loading…
Reference in New Issue