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zynq_plddr3: Fix PLDDR3's Reset Generator 

Reset generator's external reset signal was active low, but the GT reset is active high, and both the DDR controller and FIFO2S were in reset.
Therefore the external reset active state is changed to active high. This setup in general is made by the tool automatically, in order to do it correctly, need to
set this two property of the reset generator.
main
Istvan Csomortani 2014-12-04 15:39:17 +02:00
parent 324c0528c2
commit 11f41d1dff
1 changed files with 2 additions and 1 deletions
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3
projects/common/zc706/zc706_system_plddr3.tcl
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@ -36,7 +36,8 @@ proc p_plddr3_fifo {p_name m_name adc_data_width} {
set_property -dict [list CONFIG.XML_INPUT_FILE {zc706_system_mig.prj}] $axi_ddr_cntrl
set axi_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 axi_rstgen]
set_property -dict [list CONFIG.USE_BOARD_FLOW {true}] $axi_rstgen
set_property -dict [list CONFIG.RESET_BOARD_INTERFACE {reset}] $axi_rstgen
set axi_fifo2s [create_bd_cell -type ip -vlnv analog.com:user:axi_fifo2s:1.0 axi_fifo2s]
set_property -dict [list CONFIG.ADC_DATA_WIDTH $adc_data_width] $axi_fifo2s