fmcomms7: daq2 copy
Rejeesh Kutty
parent
50ce2e30be
commit
12896c7624
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@ -0,0 +1,542 @@
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# daq2
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if {$sys_zynq == 1} {
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set spi_csn_2_o [create_bd_port -dir O spi_csn_2_o]
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set spi_csn_1_o [create_bd_port -dir O spi_csn_1_o]
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set spi_csn_0_o [create_bd_port -dir O spi_csn_0_o]
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set spi_csn_i [create_bd_port -dir I spi_csn_i]
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} else {
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set spi_csn_o [create_bd_port -dir O -from 2 -to 0 spi_csn_o]
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set spi_csn_i [create_bd_port -dir I -from 2 -to 0 spi_csn_i]
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}
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set spi_clk_i [create_bd_port -dir I spi_clk_i]
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set spi_clk_o [create_bd_port -dir O spi_clk_o]
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set spi_sdo_i [create_bd_port -dir I spi_sdo_i]
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set spi_sdo_o [create_bd_port -dir O spi_sdo_o]
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set spi_sdi_i [create_bd_port -dir I spi_sdi_i]
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set rx_ref_clk [create_bd_port -dir I rx_ref_clk]
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set rx_sync [create_bd_port -dir O rx_sync]
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set rx_sysref [create_bd_port -dir I rx_sysref]
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set rx_data_p [create_bd_port -dir I -from 3 -to 0 rx_data_p]
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set rx_data_n [create_bd_port -dir I -from 3 -to 0 rx_data_n]
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set tx_ref_clk [create_bd_port -dir I tx_ref_clk]
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set tx_sync [create_bd_port -dir I tx_sync]
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set tx_sysref [create_bd_port -dir I tx_sysref]
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set tx_data_p [create_bd_port -dir O -from 3 -to 0 tx_data_p]
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set tx_data_n [create_bd_port -dir O -from 3 -to 0 tx_data_n]
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if {$sys_zynq == 0} {
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set gpio_ctl_i [create_bd_port -dir I -from 5 -to 0 gpio_ctl_i]
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set gpio_ctl_o [create_bd_port -dir O -from 5 -to 0 gpio_ctl_o]
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set gpio_ctl_t [create_bd_port -dir O -from 5 -to 0 gpio_ctl_t]
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set gpio_status_i [create_bd_port -dir I -from 4 -to 0 gpio_status_i]
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set gpio_status_o [create_bd_port -dir O -from 4 -to 0 gpio_status_o]
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set gpio_status_t [create_bd_port -dir O -from 4 -to 0 gpio_status_t]
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}
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set dac_clk [create_bd_port -dir O dac_clk]
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set dac_valid_0 [create_bd_port -dir O dac_valid_0]
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set dac_enable_0 [create_bd_port -dir O dac_enable_0]
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set dac_ddata_0 [create_bd_port -dir I -from 63 -to 0 dac_ddata_0]
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set dac_valid_1 [create_bd_port -dir O dac_valid_1]
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set dac_enable_1 [create_bd_port -dir O dac_enable_1]
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set dac_ddata_1 [create_bd_port -dir I -from 63 -to 0 dac_ddata_1]
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set dac_valid_2 [create_bd_port -dir O dac_valid_2]
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set dac_enable_2 [create_bd_port -dir O dac_enable_2]
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set dac_ddata_2 [create_bd_port -dir I -from 63 -to 0 dac_ddata_2]
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set dac_valid_3 [create_bd_port -dir O dac_valid_3]
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set dac_enable_3 [create_bd_port -dir O dac_enable_3]
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set dac_ddata_3 [create_bd_port -dir I -from 63 -to 0 dac_ddata_3]
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set dac_drd [create_bd_port -dir I dac_drd]
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set dac_ddata [create_bd_port -dir O -from 127 -to 0 dac_ddata]
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set adc_clk [create_bd_port -dir O adc_clk]
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set adc_enable_0 [create_bd_port -dir O adc_enable_0]
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set adc_valid_0 [create_bd_port -dir O adc_valid_0]
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set adc_data_0 [create_bd_port -dir O -from 63 -to 0 adc_data_0]
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set adc_enable_1 [create_bd_port -dir O adc_enable_1]
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set adc_valid_1 [create_bd_port -dir O adc_valid_1]
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set adc_data_1 [create_bd_port -dir O -from 63 -to 0 adc_data_1]
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set adc_dwr [create_bd_port -dir I adc_dwr]
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set adc_dsync [create_bd_port -dir I adc_dsync]
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set adc_ddata [create_bd_port -dir I -from 127 -to 0 adc_ddata]
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if {$sys_zynq == 1} {
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set DDR3 [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR3]
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set sys_clk [create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk]
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}
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set axi_ad9144_dma_intr [create_bd_port -dir O axi_ad9144_dma_intr]
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set axi_ad9680_dma_intr [create_bd_port -dir O axi_ad9680_dma_intr]
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set axi_daq2_spi_intr [create_bd_port -dir O axi_daq2_spi_intr ]
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set axi_daq2_gpio_intr [create_bd_port -dir O axi_daq2_gpio_intr ]
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# dac peripherals
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set axi_ad9144_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9144:1.0 axi_ad9144_core]
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set_property -dict [list CONFIG.PCORE_QUAD_DUAL_N {0}] $axi_ad9144_core
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set axi_ad9144_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:5.2 axi_ad9144_jesd]
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set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9144_jesd
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set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9144_jesd
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set axi_ad9144_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9144_dma]
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set_property -dict [list CONFIG.C_DMA_TYPE_SRC {0}] $axi_ad9144_dma
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set_property -dict [list CONFIG.C_DMA_TYPE_DEST {2}] $axi_ad9144_dma
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set_property -dict [list CONFIG.PCORE_ID {1}] $axi_ad9144_dma
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set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9144_dma
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set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9144_dma
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set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_ad9144_dma
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set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9144_dma
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set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9144_dma
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set_property -dict [list CONFIG.C_CYCLIC {1}] $axi_ad9144_dma
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {128}] $axi_ad9144_dma
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9144_dma
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if {$sys_zynq == 1} {
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set axi_ad9144_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9144_dma_interconnect]
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set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9144_dma_interconnect
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}
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# adc peripherals
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set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core]
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set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:5.2 axi_ad9680_jesd]
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set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd
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set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9680_jesd
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set axi_ad9680_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9680_dma]
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set_property -dict [list CONFIG.C_DMA_TYPE_SRC {1}] $axi_ad9680_dma
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set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9680_dma
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set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad9680_dma
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set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9680_dma
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set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9680_dma
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set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9680_dma
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set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad9680_dma
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set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9680_dma
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set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9680_dma
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set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9680_dma
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9680_dma
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9680_dma
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if {$sys_zynq == 1} {
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p_plddr3_fifo [current_bd_instance .] axi_ad9680_fifo 128
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} else {
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p_sys_dmafifo [current_bd_instance .] axi_ad9680_fifo 128
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}
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if {$sys_zynq == 1} {
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set axi_ad9680_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9680_dma_interconnect]
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set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9680_dma_interconnect
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}
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# dac/adc common gt/gpio
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set axi_daq2_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_daq2_gt]
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set_property -dict [list CONFIG.PCORE_NUM_OF_LANES {4}] $axi_daq2_gt
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set_property -dict [list CONFIG.PCORE_TX_LANE_SEL_0 {0}] $axi_daq2_gt
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set_property -dict [list CONFIG.PCORE_TX_LANE_SEL_1 {3}] $axi_daq2_gt
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set_property -dict [list CONFIG.PCORE_TX_LANE_SEL_2 {1}] $axi_daq2_gt
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set_property -dict [list CONFIG.PCORE_TX_LANE_SEL_3 {2}] $axi_daq2_gt
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if {$sys_zynq == 1} {
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set axi_daq2_gt_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_daq2_gt_interconnect]
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set_property -dict [list CONFIG.NUM_MI {1}] $axi_daq2_gt_interconnect
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}
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# gpio and spi
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if {$sys_zynq == 0} {
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set axi_daq2_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_daq2_spi]
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set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_daq2_spi
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set_property -dict [list CONFIG.C_NUM_SS_BITS {3}] $axi_daq2_spi
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set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_daq2_spi
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set axi_daq2_gpio [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_daq2_gpio]
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set_property -dict [list CONFIG.C_IS_DUAL {1}] $axi_daq2_gpio
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set_property -dict [list CONFIG.C_GPIO_WIDTH {5}] $axi_daq2_gpio
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set_property -dict [list CONFIG.C_GPIO2_WIDTH {6}] $axi_daq2_gpio
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set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_daq2_gpio
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}
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# additions to default configuration
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if {$sys_zynq == 0} {
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set_property -dict [list CONFIG.NUM_MI {16}] $axi_cpu_interconnect
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} else {
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set_property -dict [list CONFIG.NUM_MI {14}] $axi_cpu_interconnect
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}
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if {$sys_zynq == 0} {
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set_property -dict [list CONFIG.NUM_SI {11}] $axi_mem_interconnect
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}
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if {$sys_zynq == 1} {
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set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_USE_S_AXI_HP3 {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
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set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {44}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
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set_property LEFT 43 [get_bd_ports GPIO_I]
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set_property LEFT 43 [get_bd_ports GPIO_O]
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set_property LEFT 43 [get_bd_ports GPIO_T]
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}
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# connections (pl ddr3)
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if {$sys_zynq == 1} {
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connect_bd_intf_net -intf_net DDR3 [get_bd_intf_ports DDR3] [get_bd_intf_pins axi_ad9680_fifo/DDR3]
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connect_bd_intf_net -intf_net sys_clk [get_bd_intf_ports sys_clk] [get_bd_intf_pins axi_ad9680_fifo/sys_clk]
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}
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# connections (spi and gpio)
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if {$sys_zynq == 0} {
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connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins axi_daq2_spi/ss_i]
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connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins axi_daq2_spi/ss_o]
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connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins axi_daq2_spi/sck_i]
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connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins axi_daq2_spi/sck_o]
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connect_bd_net -net spi_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins axi_daq2_spi/io0_i]
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connect_bd_net -net spi_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins axi_daq2_spi/io0_o]
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connect_bd_net -net spi_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins axi_daq2_spi/io1_i]
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} else {
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connect_bd_net -net spi_csn_2_o [get_bd_ports spi_csn_2_o] [get_bd_pins sys_ps7/SPI0_SS2_O]
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connect_bd_net -net spi_csn_1_o [get_bd_ports spi_csn_1_o] [get_bd_pins sys_ps7/SPI0_SS1_O]
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connect_bd_net -net spi_csn_0_o [get_bd_ports spi_csn_0_o] [get_bd_pins sys_ps7/SPI0_SS_O]
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connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins sys_ps7/SPI0_SS_I]
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connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins sys_ps7/SPI0_SCLK_I]
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connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins sys_ps7/SPI0_SCLK_O]
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connect_bd_net -net spi_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins sys_ps7/SPI0_MOSI_I]
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connect_bd_net -net spi_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins sys_ps7/SPI0_MOSI_O]
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connect_bd_net -net spi_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins sys_ps7/SPI0_MISO_I]
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}
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if {$sys_zynq == 0} {
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connect_bd_net -net gpio_status_i [get_bd_ports gpio_status_i] [get_bd_pins axi_daq2_gpio/gpio_io_i]
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connect_bd_net -net gpio_status_o [get_bd_ports gpio_status_o] [get_bd_pins axi_daq2_gpio/gpio_io_o]
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connect_bd_net -net gpio_status_t [get_bd_ports gpio_status_t] [get_bd_pins axi_daq2_gpio/gpio_io_t]
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connect_bd_net -net gpio_ctl_i [get_bd_ports gpio_ctl_i] [get_bd_pins axi_daq2_gpio/gpio2_io_i]
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connect_bd_net -net gpio_ctl_o [get_bd_ports gpio_ctl_o] [get_bd_pins axi_daq2_gpio/gpio2_io_o]
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connect_bd_net -net gpio_ctl_t [get_bd_ports gpio_ctl_t] [get_bd_pins axi_daq2_gpio/gpio2_io_t]
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}
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# connections (gt)
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connect_bd_net -net axi_daq2_gt_ref_clk_q [get_bd_pins axi_daq2_gt/ref_clk_q] [get_bd_ports rx_ref_clk]
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connect_bd_net -net axi_daq2_gt_ref_clk_c [get_bd_pins axi_daq2_gt/ref_clk_c] [get_bd_ports tx_ref_clk]
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connect_bd_net -net axi_daq2_gt_rx_data_p [get_bd_pins axi_daq2_gt/rx_data_p] [get_bd_ports rx_data_p]
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connect_bd_net -net axi_daq2_gt_rx_data_n [get_bd_pins axi_daq2_gt/rx_data_n] [get_bd_ports rx_data_n]
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connect_bd_net -net axi_daq2_gt_rx_sync [get_bd_pins axi_daq2_gt/rx_sync] [get_bd_ports rx_sync]
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connect_bd_net -net axi_daq2_gt_rx_ext_sysref [get_bd_pins axi_daq2_gt/rx_ext_sysref] [get_bd_ports rx_sysref]
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connect_bd_net -net axi_daq2_gt_tx_data_p [get_bd_pins axi_daq2_gt/tx_data_p] [get_bd_ports tx_data_p]
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connect_bd_net -net axi_daq2_gt_tx_data_n [get_bd_pins axi_daq2_gt/tx_data_n] [get_bd_ports tx_data_n]
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connect_bd_net -net axi_daq2_gt_tx_sync [get_bd_pins axi_daq2_gt/tx_sync] [get_bd_ports tx_sync]
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connect_bd_net -net axi_daq2_gt_tx_ext_sysref [get_bd_pins axi_daq2_gt/tx_ext_sysref] [get_bd_ports tx_sysref]
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# connections (dac)
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connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins axi_daq2_gt/tx_clk_g]
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connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins axi_daq2_gt/tx_clk]
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connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins axi_ad9144_core/tx_clk]
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connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins axi_ad9144_jesd/tx_core_clk]
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|
||||
connect_bd_net -net axi_daq2_gt_tx_rst [get_bd_pins axi_daq2_gt/tx_rst] [get_bd_pins axi_ad9144_jesd/tx_reset]
|
||||
connect_bd_net -net axi_daq2_gt_tx_sysref [get_bd_pins axi_daq2_gt/tx_sysref] [get_bd_pins axi_ad9144_jesd/tx_sysref]
|
||||
connect_bd_net -net axi_daq2_gt_tx_gt_charisk [get_bd_pins axi_daq2_gt/tx_gt_charisk] [get_bd_pins axi_ad9144_jesd/gt_txcharisk_out]
|
||||
connect_bd_net -net axi_daq2_gt_tx_gt_data [get_bd_pins axi_daq2_gt/tx_gt_data] [get_bd_pins axi_ad9144_jesd/gt_txdata_out]
|
||||
connect_bd_net -net axi_daq2_gt_tx_rst_done [get_bd_pins axi_daq2_gt/tx_rst_done] [get_bd_pins axi_ad9144_jesd/tx_reset_done]
|
||||
connect_bd_net -net axi_daq2_gt_tx_ip_sync [get_bd_pins axi_daq2_gt/tx_ip_sync] [get_bd_pins axi_ad9144_jesd/tx_sync]
|
||||
connect_bd_net -net axi_daq2_gt_tx_ip_sof [get_bd_pins axi_daq2_gt/tx_ip_sof] [get_bd_pins axi_ad9144_jesd/tx_start_of_frame]
|
||||
connect_bd_net -net axi_daq2_gt_tx_ip_data [get_bd_pins axi_daq2_gt/tx_ip_data] [get_bd_pins axi_ad9144_jesd/tx_tdata]
|
||||
connect_bd_net -net axi_daq2_gt_tx_data [get_bd_pins axi_daq2_gt/tx_data] [get_bd_pins axi_ad9144_core/tx_data]
|
||||
connect_bd_net -net axi_ad9144_dac_clk [get_bd_pins axi_ad9144_core/dac_clk] [get_bd_pins axi_ad9144_dma/fifo_rd_clk]
|
||||
connect_bd_net -net axi_ad9144_dac_valid_0 [get_bd_pins axi_ad9144_core/dac_valid_0] [get_bd_ports dac_valid_0]
|
||||
connect_bd_net -net axi_ad9144_dac_enable_0 [get_bd_pins axi_ad9144_core/dac_enable_0] [get_bd_ports dac_enable_0]
|
||||
connect_bd_net -net axi_ad9144_dac_ddata_0 [get_bd_pins axi_ad9144_core/dac_ddata_0] [get_bd_ports dac_ddata_0]
|
||||
connect_bd_net -net axi_ad9144_dac_valid_1 [get_bd_pins axi_ad9144_core/dac_valid_1] [get_bd_ports dac_valid_1]
|
||||
connect_bd_net -net axi_ad9144_dac_enable_1 [get_bd_pins axi_ad9144_core/dac_enable_1] [get_bd_ports dac_enable_1]
|
||||
connect_bd_net -net axi_ad9144_dac_ddata_1 [get_bd_pins axi_ad9144_core/dac_ddata_1] [get_bd_ports dac_ddata_1]
|
||||
connect_bd_net -net axi_ad9144_dac_valid_2 [get_bd_pins axi_ad9144_core/dac_valid_2] [get_bd_ports dac_valid_2]
|
||||
connect_bd_net -net axi_ad9144_dac_enable_2 [get_bd_pins axi_ad9144_core/dac_enable_2] [get_bd_ports dac_enable_2]
|
||||
connect_bd_net -net axi_ad9144_dac_ddata_2 [get_bd_pins axi_ad9144_core/dac_ddata_2] [get_bd_ports dac_ddata_2]
|
||||
connect_bd_net -net axi_ad9144_dac_valid_3 [get_bd_pins axi_ad9144_core/dac_valid_3] [get_bd_ports dac_valid_3]
|
||||
connect_bd_net -net axi_ad9144_dac_enable_3 [get_bd_pins axi_ad9144_core/dac_enable_3] [get_bd_ports dac_enable_3]
|
||||
connect_bd_net -net axi_ad9144_dac_ddata_3 [get_bd_pins axi_ad9144_core/dac_ddata_3] [get_bd_ports dac_ddata_3]
|
||||
connect_bd_net -net axi_ad9144_dac_drd [get_bd_ports dac_drd] [get_bd_pins axi_ad9144_dma/fifo_rd_en]
|
||||
connect_bd_net -net axi_ad9144_dac_ddata [get_bd_ports dac_ddata] [get_bd_pins axi_ad9144_dma/fifo_rd_dout]
|
||||
connect_bd_net -net axi_ad9144_dac_dunf [get_bd_pins axi_ad9144_core/dac_dunf] [get_bd_pins axi_ad9144_dma/fifo_rd_underflow]
|
||||
connect_bd_net -net axi_ad9144_dma_intr [get_bd_pins axi_ad9144_dma/irq] [get_bd_ports axi_ad9144_dma_intr]
|
||||
|
||||
# connections (adc)
|
||||
|
||||
connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins axi_daq2_gt/rx_clk_g]
|
||||
connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins axi_daq2_gt/rx_clk]
|
||||
connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins axi_ad9680_core/rx_clk]
|
||||
connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins axi_ad9680_jesd/rx_core_clk]
|
||||
|
||||
connect_bd_net -net axi_daq2_gt_rx_rst [get_bd_pins axi_daq2_gt/rx_rst] [get_bd_pins axi_ad9680_jesd/rx_reset]
|
||||
connect_bd_net -net axi_daq2_gt_rx_sysref [get_bd_pins axi_daq2_gt/rx_sysref] [get_bd_pins axi_ad9680_jesd/rx_sysref]
|
||||
connect_bd_net -net axi_daq2_gt_rx_gt_charisk [get_bd_pins axi_daq2_gt/rx_gt_charisk] [get_bd_pins axi_ad9680_jesd/gt_rxcharisk_in]
|
||||
connect_bd_net -net axi_daq2_gt_rx_gt_disperr [get_bd_pins axi_daq2_gt/rx_gt_disperr] [get_bd_pins axi_ad9680_jesd/gt_rxdisperr_in]
|
||||
connect_bd_net -net axi_daq2_gt_rx_gt_notintable [get_bd_pins axi_daq2_gt/rx_gt_notintable] [get_bd_pins axi_ad9680_jesd/gt_rxnotintable_in]
|
||||
connect_bd_net -net axi_daq2_gt_rx_gt_data [get_bd_pins axi_daq2_gt/rx_gt_data] [get_bd_pins axi_ad9680_jesd/gt_rxdata_in]
|
||||
connect_bd_net -net axi_daq2_gt_rx_rst_done [get_bd_pins axi_daq2_gt/rx_rst_done] [get_bd_pins axi_ad9680_jesd/rx_reset_done]
|
||||
connect_bd_net -net axi_daq2_gt_rx_ip_comma_align [get_bd_pins axi_daq2_gt/rx_ip_comma_align] [get_bd_pins axi_ad9680_jesd/rxencommaalign_out]
|
||||
connect_bd_net -net axi_daq2_gt_rx_ip_sync [get_bd_pins axi_daq2_gt/rx_ip_sync] [get_bd_pins axi_ad9680_jesd/rx_sync]
|
||||
connect_bd_net -net axi_daq2_gt_rx_ip_sof [get_bd_pins axi_daq2_gt/rx_ip_sof] [get_bd_pins axi_ad9680_jesd/rx_start_of_frame]
|
||||
connect_bd_net -net axi_daq2_gt_rx_ip_data [get_bd_pins axi_daq2_gt/rx_ip_data] [get_bd_pins axi_ad9680_jesd/rx_tdata]
|
||||
connect_bd_net -net axi_daq2_gt_rx_data [get_bd_pins axi_daq2_gt/rx_data] [get_bd_pins axi_ad9680_core/rx_data]
|
||||
|
||||
connect_bd_net -net axi_daq2_gt_rx_rst [get_bd_pins axi_ad9680_fifo/adc_rst] [get_bd_pins axi_daq2_gt/rx_rst]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_fifo/dma_rstn] $sys_100m_resetn_source
|
||||
|
||||
connect_bd_net -net axi_ad9680_adc_clk [get_bd_pins axi_ad9680_core/adc_clk] [get_bd_pins axi_ad9680_fifo/adc_clk]
|
||||
connect_bd_net -net axi_ad9680_adc_dovf [get_bd_pins axi_ad9680_core/adc_dovf] [get_bd_pins axi_ad9680_fifo/adc_wovf]
|
||||
connect_bd_net -net axi_ad9680_adc_enable_0 [get_bd_pins axi_ad9680_core/adc_enable_0] [get_bd_ports adc_enable_0]
|
||||
connect_bd_net -net axi_ad9680_adc_valid_0 [get_bd_pins axi_ad9680_core/adc_valid_0] [get_bd_ports adc_valid_0]
|
||||
connect_bd_net -net axi_ad9680_adc_data_0 [get_bd_pins axi_ad9680_core/adc_data_0] [get_bd_ports adc_data_0]
|
||||
connect_bd_net -net axi_ad9680_adc_enable_1 [get_bd_pins axi_ad9680_core/adc_enable_1] [get_bd_ports adc_enable_1]
|
||||
connect_bd_net -net axi_ad9680_adc_valid_1 [get_bd_pins axi_ad9680_core/adc_valid_1] [get_bd_ports adc_valid_1]
|
||||
connect_bd_net -net axi_ad9680_adc_data_1 [get_bd_pins axi_ad9680_core/adc_data_1] [get_bd_ports adc_data_1]
|
||||
connect_bd_net -net axi_ad9680_adc_dwr [get_bd_ports adc_dwr] [get_bd_pins axi_ad9680_fifo/adc_wr]
|
||||
connect_bd_net -net axi_ad9680_adc_ddata [get_bd_ports adc_ddata] [get_bd_pins axi_ad9680_fifo/adc_wdata]
|
||||
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_fifo/dma_clk] [get_bd_pins axi_ad9680_dma/s_axis_aclk]
|
||||
connect_bd_net -net axi_ad9680_dma_dvalid [get_bd_pins axi_ad9680_fifo/dma_wvalid] [get_bd_pins axi_ad9680_dma/s_axis_valid]
|
||||
connect_bd_net -net axi_ad9680_dma_dready [get_bd_pins axi_ad9680_fifo/dma_wready] [get_bd_pins axi_ad9680_dma/s_axis_ready]
|
||||
connect_bd_net -net axi_ad9680_dma_ddata [get_bd_pins axi_ad9680_fifo/dma_wdata] [get_bd_pins axi_ad9680_dma/s_axis_data]
|
||||
connect_bd_net -net axi_ad9680_dma_xfer_req [get_bd_pins axi_ad9680_fifo/axi_xfer_req] [get_bd_pins axi_ad9680_dma/s_axis_xfer_req]
|
||||
connect_bd_net -net axi_ad9680_dma_intr [get_bd_pins axi_ad9680_dma/irq] [get_bd_ports axi_ad9680_dma_intr]
|
||||
|
||||
# dac/adc clocks
|
||||
|
||||
connect_bd_net -net axi_ad9144_dac_clk [get_bd_ports dac_clk]
|
||||
connect_bd_net -net axi_ad9680_adc_clk [get_bd_ports adc_clk]
|
||||
|
||||
if {$sys_zynq == 0} {
|
||||
|
||||
connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9680_fifo/axi_clk] $sys_200m_clk_source
|
||||
}
|
||||
|
||||
# interconnect (cpu)
|
||||
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_ad9144_dma/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_ad9144_core/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_ad9144_jesd/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_ad9680_dma/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m11_axi [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins axi_ad9680_core/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m12_axi [get_bd_intf_pins axi_cpu_interconnect/M12_AXI] [get_bd_intf_pins axi_ad9680_jesd/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m13_axi [get_bd_intf_pins axi_cpu_interconnect/M13_AXI] [get_bd_intf_pins axi_daq2_gt/s_axi]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M09_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M10_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M11_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M12_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M13_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9144_core/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9144_jesd/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9144_dma/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_core/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_jesd/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_dma/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M10_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M11_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M12_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M13_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gt/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9144_core/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9144_jesd/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9144_dma/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_core/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_jesd/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_dma/s_axi_aresetn]
|
||||
|
||||
if {$sys_zynq == 0} {
|
||||
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m14_axi [get_bd_intf_pins axi_cpu_interconnect/M14_AXI] [get_bd_intf_pins axi_daq2_spi/axi_lite]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m15_axi [get_bd_intf_pins axi_cpu_interconnect/M15_AXI] [get_bd_intf_pins axi_daq2_gpio/s_axi]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M14_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M15_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_spi/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_spi/ext_spi_clk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gpio/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M14_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M15_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_spi/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gpio/s_axi_aresetn]
|
||||
|
||||
connect_bd_net -net axi_daq2_spi_intr [get_bd_pins axi_daq2_spi/ip2intc_irpt] [get_bd_ports axi_daq2_spi_intr]
|
||||
connect_bd_net -net axi_daq2_gpio_intr [get_bd_pins axi_daq2_gpio/ip2intc_irpt] [get_bd_ports axi_daq2_gpio_intr]
|
||||
}
|
||||
|
||||
# gt uses hp3, and 100MHz clock for both DRP and AXI4
|
||||
|
||||
if {$sys_zynq == 0} {
|
||||
|
||||
connect_bd_intf_net -intf_net axi_mem_interconnect_s08_axi [get_bd_intf_pins axi_mem_interconnect/S08_AXI] [get_bd_intf_pins axi_daq2_gt/m_axi]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S08_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt/m_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt/drp_clk]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S08_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gt/m_axi_aresetn]
|
||||
|
||||
} else {
|
||||
|
||||
connect_bd_intf_net -intf_net axi_daq2_gt_interconnect_m00_axi [get_bd_intf_pins axi_daq2_gt_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP3]
|
||||
connect_bd_intf_net -intf_net axi_daq2_gt_interconnect_s00_axi [get_bd_intf_pins axi_daq2_gt_interconnect/S00_AXI] [get_bd_intf_pins axi_daq2_gt/m_axi]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt_interconnect/ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt_interconnect/M00_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt_interconnect/S00_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP3_ACLK]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt/m_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt/drp_clk]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gt_interconnect/ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gt_interconnect/M00_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gt_interconnect/S00_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gt/m_axi_aresetn]
|
||||
}
|
||||
|
||||
# memory interconnects share the same clock (fclk2)
|
||||
|
||||
# interconnect (mem/dac)
|
||||
|
||||
if {$sys_zynq == 0} {
|
||||
|
||||
connect_bd_intf_net -intf_net axi_mem_interconnect_s09_axi [get_bd_intf_pins axi_mem_interconnect/S09_AXI] [get_bd_intf_pins axi_ad9144_dma/m_src_axi]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S09_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9144_dma/m_src_axi_aclk]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S09_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9144_dma/m_src_axi_aresetn]
|
||||
|
||||
connect_bd_intf_net -intf_net axi_mem_interconnect_s10_axi [get_bd_intf_pins axi_mem_interconnect/S10_AXI] [get_bd_intf_pins axi_ad9680_dma/m_dest_axi]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S10_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_dma/m_dest_axi_aclk]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S10_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_dma/m_dest_axi_aresetn]
|
||||
|
||||
} else {
|
||||
|
||||
connect_bd_intf_net -intf_net axi_ad9144_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9144_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP1]
|
||||
connect_bd_intf_net -intf_net axi_ad9144_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9144_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9144_dma/m_src_axi]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9144_dma_interconnect/ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9144_dma_interconnect/M00_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9144_dma_interconnect/S00_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP1_ACLK]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9144_dma/m_src_axi_aclk]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9144_dma_interconnect/ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9144_dma_interconnect/M00_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9144_dma_interconnect/S00_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9144_dma/m_src_axi_aresetn]
|
||||
|
||||
connect_bd_intf_net -intf_net axi_ad9680_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9680_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP2]
|
||||
connect_bd_intf_net -intf_net axi_ad9680_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9680_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9680_dma/m_dest_axi]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_dma_interconnect/ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_dma_interconnect/M00_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_dma_interconnect/S00_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP2_ACLK]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_dma/m_dest_axi_aclk]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_dma_interconnect/ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_dma_interconnect/M00_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_dma_interconnect/S00_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_dma/m_dest_axi_aresetn]
|
||||
}
|
||||
|
||||
# ila
|
||||
|
||||
if {$sys_zynq == 1} {
|
||||
|
||||
set ila_jesd_rx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_jesd_rx_mon]
|
||||
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_jesd_rx_mon
|
||||
set_property -dict [list CONFIG.C_NUM_OF_PROBES {3}] $ila_jesd_rx_mon
|
||||
set_property -dict [list CONFIG.C_PROBE0_WIDTH {334}] $ila_jesd_rx_mon
|
||||
set_property -dict [list CONFIG.C_PROBE1_WIDTH {6}] $ila_jesd_rx_mon
|
||||
set_property -dict [list CONFIG.C_PROBE2_WIDTH {128}] $ila_jesd_rx_mon
|
||||
|
||||
connect_bd_net -net axi_daq2_gt_rx_mon_data [get_bd_pins axi_daq2_gt/rx_mon_data]
|
||||
connect_bd_net -net axi_daq2_gt_rx_mon_trigger [get_bd_pins axi_daq2_gt/rx_mon_trigger]
|
||||
connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins ila_jesd_rx_mon/CLK]
|
||||
connect_bd_net -net axi_daq2_gt_rx_mon_data [get_bd_pins ila_jesd_rx_mon/PROBE0]
|
||||
connect_bd_net -net axi_daq2_gt_rx_mon_trigger [get_bd_pins ila_jesd_rx_mon/PROBE1]
|
||||
connect_bd_net -net axi_daq2_gt_rx_data [get_bd_pins ila_jesd_rx_mon/PROBE2]
|
||||
|
||||
set ila_jesd_tx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_jesd_tx_mon]
|
||||
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_jesd_tx_mon
|
||||
set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_jesd_tx_mon
|
||||
set_property -dict [list CONFIG.C_PROBE0_WIDTH {150}] $ila_jesd_tx_mon
|
||||
set_property -dict [list CONFIG.C_PROBE1_WIDTH {6}] $ila_jesd_tx_mon
|
||||
|
||||
connect_bd_net -net axi_daq2_gt_tx_mon_data [get_bd_pins axi_daq2_gt/tx_mon_data]
|
||||
connect_bd_net -net axi_daq2_gt_tx_mon_trigger [get_bd_pins axi_daq2_gt/tx_mon_trigger]
|
||||
connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins ila_jesd_tx_mon/CLK]
|
||||
connect_bd_net -net axi_daq2_gt_tx_mon_data [get_bd_pins ila_jesd_tx_mon/PROBE0]
|
||||
connect_bd_net -net axi_daq2_gt_tx_mon_trigger [get_bd_pins ila_jesd_tx_mon/PROBE1]
|
||||
}
|
||||
|
||||
# address map
|
||||
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9144_core/s_axi/axi_lite] SEG_data_ad9144_core
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x44A10000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9680_core/s_axi/axi_lite] SEG_data_ad9680_core
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x44A60000 $sys_addr_cntrl_space [get_bd_addr_segs axi_daq2_gt/s_axi/axi_lite] SEG_data_daq2_gt
|
||||
create_bd_addr_seg -range 0x00001000 -offset 0x44A90000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9144_jesd/s_axi/Reg] SEG_data_ad9144_jesd
|
||||
create_bd_addr_seg -range 0x00001000 -offset 0x44A91000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9680_jesd/s_axi/Reg] SEG_data_ad9680_jesd
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x7c400000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9680_dma/s_axi/axi_lite] SEG_data_ad9680_dma
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x7c420000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9144_dma/s_axi/axi_lite] SEG_data_ad9144_dma
|
||||
|
||||
if {$sys_zynq == 0} {
|
||||
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x40000000 $sys_addr_cntrl_space [get_bd_addr_segs axi_daq2_gpio/S_AXI/Reg] SEG_data_daq2_gpio
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x44A70000 $sys_addr_cntrl_space [get_bd_addr_segs axi_daq2_spi/axi_lite/Reg] SEG_data_daq2_spi
|
||||
}
|
||||
|
||||
if {$sys_zynq == 0} {
|
||||
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9144_dma/m_src_axi] $sys_addr_mem_seg SEG_axi_ddr_cntrl
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9680_dma/m_dest_axi] $sys_addr_mem_seg SEG_axi_ddr_cntrl
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_daq2_gt/m_axi] $sys_addr_mem_seg SEG_axi_ddr_cntrl
|
||||
|
||||
} else {
|
||||
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9144_dma/m_src_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9680_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_sys_ps7_hp2_ddr_lowocm
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_daq2_gt/m_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_sys_ps7_hp3_ddr_lowocm
|
||||
|
||||
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_ad9680_fifo/axi_fifo2s/axi] [get_bd_addr_segs axi_ad9680_fifo/axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl_memaddr
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,112 @@
|
|||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2011(c) Analog Devices, Inc.
|
||||
//
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without modification,
|
||||
// are permitted provided that the following conditions are met:
|
||||
// - Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// - Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in
|
||||
// the documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
// - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
// contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
// - The use of this software may or may not infringe the patent rights
|
||||
// of one or more patent holders. This license does not release you
|
||||
// from the requirement that you obtain separate licenses from these
|
||||
// patent holders to use this software.
|
||||
// - Use of the software either in source or binary form, must be run
|
||||
// on or directly connected to an Analog Devices Inc. component.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
|
||||
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
|
||||
// PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
//
|
||||
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
|
||||
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module daq2_spi (
|
||||
|
||||
spi_csn,
|
||||
spi_clk,
|
||||
spi_mosi,
|
||||
spi_miso,
|
||||
|
||||
spi_sdio,
|
||||
spi_dir);
|
||||
|
||||
// 4 wire
|
||||
|
||||
input [ 2:0] spi_csn;
|
||||
input spi_clk;
|
||||
input spi_mosi;
|
||||
output spi_miso;
|
||||
|
||||
// 3 wire
|
||||
|
||||
inout spi_sdio;
|
||||
output spi_dir;
|
||||
|
||||
// internal registers
|
||||
|
||||
reg [ 5:0] spi_count = 'd0;
|
||||
reg spi_rd_wr_n = 'd0;
|
||||
reg spi_enable = 'd0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire spi_csn_s;
|
||||
wire spi_enable_s;
|
||||
|
||||
// check on rising edge and change on falling edge
|
||||
|
||||
assign spi_csn_s = & spi_csn;
|
||||
assign spi_dir = ~spi_enable_s;
|
||||
assign spi_enable_s = spi_enable & ~spi_csn_s;
|
||||
|
||||
always @(posedge spi_clk or posedge spi_csn_s) begin
|
||||
if (spi_csn_s == 1'b1) begin
|
||||
spi_count <= 6'd0;
|
||||
spi_rd_wr_n <= 1'd0;
|
||||
end else begin
|
||||
spi_count <= spi_count + 1'b1;
|
||||
if (spi_count == 6'd0) begin
|
||||
spi_rd_wr_n <= spi_mosi;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(negedge spi_clk or posedge spi_csn_s) begin
|
||||
if (spi_csn_s == 1'b1) begin
|
||||
spi_enable <= 1'b0;
|
||||
end else begin
|
||||
if (spi_count == 6'd16) begin
|
||||
spi_enable <= spi_rd_wr_n;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// io butter
|
||||
|
||||
IOBUF i_iobuf_sdio (
|
||||
.T (spi_enable_s),
|
||||
.I (spi_mosi),
|
||||
.O (spi_miso),
|
||||
.IO (spi_sdio));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
|
||||
source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
|
||||
source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3.tcl
|
||||
source ../common/daq2_bd.tcl
|
||||
|
||||
|
|
@ -0,0 +1,61 @@
|
|||
|
||||
# daq2
|
||||
|
||||
set_property -dict {PACKAGE_PIN AA8 } [get_ports rx_ref_clk_p] ; ## B20 FMC_HPC_GBTCLK1_M2C_P
|
||||
set_property -dict {PACKAGE_PIN AA7 } [get_ports rx_ref_clk_n] ; ## B21 FMC_HPC_GBTCLK1_M2C_N
|
||||
set_property -dict {PACKAGE_PIN AE8 } [get_ports rx_data_p[0]] ; ## A10 FMC_HPC_DP3_M2C_P
|
||||
set_property -dict {PACKAGE_PIN AE7 } [get_ports rx_data_n[0]] ; ## A11 FMC_HPC_DP3_M2C_N
|
||||
set_property -dict {PACKAGE_PIN AH10} [get_ports rx_data_p[1]] ; ## C06 FMC_HPC_DP0_M2C_P
|
||||
set_property -dict {PACKAGE_PIN AH9 } [get_ports rx_data_n[1]] ; ## C07 FMC_HPC_DP0_M2C_N
|
||||
set_property -dict {PACKAGE_PIN AG8 } [get_ports rx_data_p[2]] ; ## A06 FMC_HPC_DP2_M2C_P
|
||||
set_property -dict {PACKAGE_PIN AG7 } [get_ports rx_data_n[2]] ; ## A07 FMC_HPC_DP2_M2C_N
|
||||
set_property -dict {PACKAGE_PIN AJ8 } [get_ports rx_data_p[3]] ; ## A02 FMC_HPC_DP1_M2C_P
|
||||
set_property -dict {PACKAGE_PIN AJ7 } [get_ports rx_data_n[3]] ; ## A03 FMC_HPC_DP1_M2C_N
|
||||
set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVDS_25} [get_ports rx_sync_p] ; ## D08 FMC_HPC_LA01_CC_P
|
||||
set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVDS_25} [get_ports rx_sync_n] ; ## D09 FMC_HPC_LA01_CC_N
|
||||
set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_p] ; ## G09 FMC_HPC_LA03_P
|
||||
set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_n] ; ## G10 FMC_HPC_LA03_N
|
||||
|
||||
set_property -dict {PACKAGE_PIN AD10} [get_ports tx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P
|
||||
set_property -dict {PACKAGE_PIN AD9 } [get_ports tx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N
|
||||
set_property -dict {PACKAGE_PIN AK2 } [get_ports tx_data_p[0]] ; ## A30 FMC_HPC_DP3_C2M_P (tx_data_p[0])
|
||||
set_property -dict {PACKAGE_PIN AK1 } [get_ports tx_data_n[0]] ; ## A31 FMC_HPC_DP3_C2M_N (tx_data_n[0])
|
||||
set_property -dict {PACKAGE_PIN AK10} [get_ports tx_data_p[1]] ; ## C02 FMC_HPC_DP0_C2M_P (tx_data_p[3])
|
||||
set_property -dict {PACKAGE_PIN AK9 } [get_ports tx_data_n[1]] ; ## C03 FMC_HPC_DP0_C2M_N (tx_data_n[3])
|
||||
set_property -dict {PACKAGE_PIN AJ4 } [get_ports tx_data_p[2]] ; ## A26 FMC_HPC_DP2_C2M_P (tx_data_p[1])
|
||||
set_property -dict {PACKAGE_PIN AJ3 } [get_ports tx_data_n[2]] ; ## A27 FMC_HPC_DP2_C2M_N (tx_data_n[1])
|
||||
set_property -dict {PACKAGE_PIN AK6 } [get_ports tx_data_p[3]] ; ## A22 FMC_HPC_DP1_C2M_P (tx_data_p[2])
|
||||
set_property -dict {PACKAGE_PIN AK5 } [get_ports tx_data_n[3]] ; ## A23 FMC_HPC_DP1_C2M_N (tx_data_n[2])
|
||||
set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_p] ; ## H07 FMC_HPC_LA02_P
|
||||
set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_n] ; ## H08 FMC_HPC_LA02_N
|
||||
set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sysref_p] ; ## H10 FMC_HPC_LA04_P
|
||||
set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sysref_n] ; ## H11 FMC_HPC_LA04_N
|
||||
|
||||
set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVCMOS25} [get_ports spi_csn_clk] ; ## D11 FMC_HPC_LA05_P
|
||||
set_property -dict {PACKAGE_PIN AG24 IOSTANDARD LVCMOS25} [get_ports spi_csn_dac] ; ## C14 FMC_HPC_LA10_P
|
||||
set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports spi_csn_adc] ; ## D15 FMC_HPC_LA09_N
|
||||
set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D12 FMC_HPC_LA05_N
|
||||
set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS25} [get_ports spi_sdio] ; ## D14 FMC_HPC_LA09_P
|
||||
set_property -dict {PACKAGE_PIN AG19 IOSTANDARD LVCMOS25} [get_ports spi_dir] ; ## G13 FMC_HPC_LA08_N
|
||||
|
||||
set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25} [get_ports clkd_sync] ; ## G12 FMC_HPC_LA08_P
|
||||
set_property -dict {PACKAGE_PIN AG25 IOSTANDARD LVCMOS25} [get_ports dac_reset] ; ## C15 FMC_HPC_LA10_N
|
||||
set_property -dict {PACKAGE_PIN AF24 IOSTANDARD LVCMOS25} [get_ports dac_txen] ; ## G16 FMC_HPC_LA12_N
|
||||
set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVCMOS25} [get_ports adc_pd] ; ## C10 FMC_HPC_LA06_P
|
||||
|
||||
set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS25} [get_ports clkd_status[0]] ; ## D17 FMC_HPC_LA13_P
|
||||
set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS25} [get_ports clkd_status[1]] ; ## D18 FMC_HPC_LA13_N
|
||||
set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS25} [get_ports dac_irq] ; ## G15 FMC_HPC_LA12_P
|
||||
set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS25} [get_ports adc_fda] ; ## H16 FMC_HPC_LA11_P
|
||||
set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS25} [get_ports adc_fdb] ; ## H17 FMC_HPC_LA11_N
|
||||
|
||||
set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports trig_p] ; ## H13 FMC_HPC_LA07_P
|
||||
set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports trig_n] ; ## H14 FMC_HPC_LA07_N
|
||||
|
||||
# clocks
|
||||
|
||||
create_clock -name tx_ref_clk -period 2.00 [get_ports tx_ref_clk_p]
|
||||
create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p]
|
||||
create_clock -name tx_div_clk -period 4.00 [get_nets i_system_wrapper/system_i/axi_daq2_gt_tx_clk]
|
||||
create_clock -name rx_div_clk -period 4.00 [get_nets i_system_wrapper/system_i/axi_daq2_gt_rx_clk]
|
||||
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
|
||||
|
||||
|
||||
source ../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/projects/scripts/adi_project.tcl
|
||||
|
||||
adi_project_create daq2_zc706
|
||||
adi_project_files daq2_zc706 [list \
|
||||
"../common/daq2_spi.v" \
|
||||
"system_top.v" \
|
||||
"system_constr.xdc"\
|
||||
"$ad_hdl_dir/library/common/ad_iobuf.v" \
|
||||
"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
|
||||
|
||||
set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc]
|
||||
set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
|
||||
|
||||
adi_project_run daq2_zc706
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,550 @@
|
|||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2011(c) Analog Devices, Inc.
|
||||
//
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without modification,
|
||||
// are permitted provided that the following conditions are met:
|
||||
// - Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// - Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in
|
||||
// the documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
// - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
// contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
// - The use of this software may or may not infringe the patent rights
|
||||
// of one or more patent holders. This license does not release you
|
||||
// from the requirement that you obtain separate licenses from these
|
||||
// patent holders to use this software.
|
||||
// - Use of the software either in source or binary form, must be run
|
||||
// on or directly connected to an Analog Devices Inc. component.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
|
||||
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
|
||||
// PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
//
|
||||
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
|
||||
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module system_top (
|
||||
|
||||
sys_clk_p,
|
||||
sys_clk_n,
|
||||
|
||||
DDR3_addr,
|
||||
DDR3_ba,
|
||||
DDR3_cas_n,
|
||||
DDR3_ck_n,
|
||||
DDR3_ck_p,
|
||||
DDR3_cke,
|
||||
DDR3_cs_n,
|
||||
DDR3_dm,
|
||||
DDR3_dq,
|
||||
DDR3_dqs_n,
|
||||
DDR3_dqs_p,
|
||||
DDR3_odt,
|
||||
DDR3_ras_n,
|
||||
DDR3_reset_n,
|
||||
DDR3_we_n,
|
||||
|
||||
DDR_addr,
|
||||
DDR_ba,
|
||||
DDR_cas_n,
|
||||
DDR_ck_n,
|
||||
DDR_ck_p,
|
||||
DDR_cke,
|
||||
DDR_cs_n,
|
||||
DDR_dm,
|
||||
DDR_dq,
|
||||
DDR_dqs_n,
|
||||
DDR_dqs_p,
|
||||
DDR_odt,
|
||||
DDR_ras_n,
|
||||
DDR_reset_n,
|
||||
DDR_we_n,
|
||||
|
||||
FIXED_IO_ddr_vrn,
|
||||
FIXED_IO_ddr_vrp,
|
||||
FIXED_IO_mio,
|
||||
FIXED_IO_ps_clk,
|
||||
FIXED_IO_ps_porb,
|
||||
FIXED_IO_ps_srstb,
|
||||
|
||||
gpio_bd,
|
||||
|
||||
hdmi_out_clk,
|
||||
hdmi_vsync,
|
||||
hdmi_hsync,
|
||||
hdmi_data_e,
|
||||
hdmi_data,
|
||||
|
||||
spdif,
|
||||
|
||||
iic_scl,
|
||||
iic_sda,
|
||||
|
||||
rx_ref_clk_p,
|
||||
rx_ref_clk_n,
|
||||
rx_sysref_p,
|
||||
rx_sysref_n,
|
||||
rx_sync_p,
|
||||
rx_sync_n,
|
||||
rx_data_p,
|
||||
rx_data_n,
|
||||
|
||||
tx_ref_clk_p,
|
||||
tx_ref_clk_n,
|
||||
tx_sysref_p,
|
||||
tx_sysref_n,
|
||||
tx_sync_p,
|
||||
tx_sync_n,
|
||||
tx_data_p,
|
||||
tx_data_n,
|
||||
|
||||
trig_p,
|
||||
trig_n,
|
||||
|
||||
adc_fdb,
|
||||
adc_fda,
|
||||
dac_irq,
|
||||
clkd_status,
|
||||
|
||||
adc_pd,
|
||||
dac_txen,
|
||||
dac_reset,
|
||||
clkd_sync,
|
||||
|
||||
spi_csn_clk,
|
||||
spi_csn_dac,
|
||||
spi_csn_adc,
|
||||
spi_clk,
|
||||
spi_sdio,
|
||||
spi_dir);
|
||||
|
||||
input sys_clk_p;
|
||||
input sys_clk_n;
|
||||
|
||||
output [13:0] DDR3_addr;
|
||||
output [ 2:0] DDR3_ba;
|
||||
output DDR3_cas_n;
|
||||
output [ 0:0] DDR3_ck_n;
|
||||
output [ 0:0] DDR3_ck_p;
|
||||
output [ 0:0] DDR3_cke;
|
||||
output [ 0:0] DDR3_cs_n;
|
||||
output [ 7:0] DDR3_dm;
|
||||
inout [63:0] DDR3_dq;
|
||||
inout [ 7:0] DDR3_dqs_n;
|
||||
inout [ 7:0] DDR3_dqs_p;
|
||||
output [ 0:0] DDR3_odt;
|
||||
output DDR3_ras_n;
|
||||
output DDR3_reset_n;
|
||||
output DDR3_we_n;
|
||||
|
||||
inout [14:0] DDR_addr;
|
||||
inout [ 2:0] DDR_ba;
|
||||
inout DDR_cas_n;
|
||||
inout DDR_ck_n;
|
||||
inout DDR_ck_p;
|
||||
inout DDR_cke;
|
||||
inout DDR_cs_n;
|
||||
inout [ 3:0] DDR_dm;
|
||||
inout [31:0] DDR_dq;
|
||||
inout [ 3:0] DDR_dqs_n;
|
||||
inout [ 3:0] DDR_dqs_p;
|
||||
inout DDR_odt;
|
||||
inout DDR_ras_n;
|
||||
inout DDR_reset_n;
|
||||
inout DDR_we_n;
|
||||
|
||||
inout FIXED_IO_ddr_vrn;
|
||||
inout FIXED_IO_ddr_vrp;
|
||||
inout [53:0] FIXED_IO_mio;
|
||||
inout FIXED_IO_ps_clk;
|
||||
inout FIXED_IO_ps_porb;
|
||||
inout FIXED_IO_ps_srstb;
|
||||
|
||||
inout [14:0] gpio_bd;
|
||||
|
||||
output hdmi_out_clk;
|
||||
output hdmi_vsync;
|
||||
output hdmi_hsync;
|
||||
output hdmi_data_e;
|
||||
output [23:0] hdmi_data;
|
||||
|
||||
output spdif;
|
||||
|
||||
inout iic_scl;
|
||||
inout iic_sda;
|
||||
|
||||
input rx_ref_clk_p;
|
||||
input rx_ref_clk_n;
|
||||
input rx_sysref_p;
|
||||
input rx_sysref_n;
|
||||
output rx_sync_p;
|
||||
output rx_sync_n;
|
||||
input [ 3:0] rx_data_p;
|
||||
input [ 3:0] rx_data_n;
|
||||
|
||||
input tx_ref_clk_p;
|
||||
input tx_ref_clk_n;
|
||||
input tx_sysref_p;
|
||||
input tx_sysref_n;
|
||||
input tx_sync_p;
|
||||
input tx_sync_n;
|
||||
output [ 3:0] tx_data_p;
|
||||
output [ 3:0] tx_data_n;
|
||||
|
||||
input trig_p;
|
||||
input trig_n;
|
||||
|
||||
inout adc_fdb;
|
||||
inout adc_fda;
|
||||
inout dac_irq;
|
||||
inout [ 1:0] clkd_status;
|
||||
|
||||
inout adc_pd;
|
||||
inout dac_txen;
|
||||
inout dac_reset;
|
||||
inout clkd_sync;
|
||||
|
||||
output spi_csn_clk;
|
||||
output spi_csn_dac;
|
||||
output spi_csn_adc;
|
||||
output spi_clk;
|
||||
inout spi_sdio;
|
||||
output spi_dir;
|
||||
|
||||
// internal registers
|
||||
|
||||
reg dac_drd = 'd0;
|
||||
reg [63:0] dac_ddata_0 = 'd0;
|
||||
reg [63:0] dac_ddata_1 = 'd0;
|
||||
reg [63:0] dac_ddata_2 = 'd0;
|
||||
reg [63:0] dac_ddata_3 = 'd0;
|
||||
reg adc_dsync = 'd0;
|
||||
reg adc_dwr = 'd0;
|
||||
reg [127:0] adc_ddata = 'd0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire trig;
|
||||
wire [43:0] gpio_i;
|
||||
wire [43:0] gpio_o;
|
||||
wire [43:0] gpio_t;
|
||||
wire rx_ref_clk;
|
||||
wire rx_sysref;
|
||||
wire rx_sync;
|
||||
wire tx_ref_clk;
|
||||
wire tx_sysref;
|
||||
wire tx_sync;
|
||||
wire [ 2:0] spi_csn;
|
||||
wire spi_mosi;
|
||||
wire spi_miso;
|
||||
wire dac_clk;
|
||||
wire [127:0] dac_ddata;
|
||||
wire dac_enable_0;
|
||||
wire dac_enable_1;
|
||||
wire dac_enable_2;
|
||||
wire dac_enable_3;
|
||||
wire dac_valid_0;
|
||||
wire dac_valid_1;
|
||||
wire dac_valid_2;
|
||||
wire dac_valid_3;
|
||||
wire adc_clk;
|
||||
wire [63:0] adc_data_0;
|
||||
wire [63:0] adc_data_1;
|
||||
wire adc_enable_0;
|
||||
wire adc_enable_1;
|
||||
wire adc_valid_0;
|
||||
wire adc_valid_1;
|
||||
|
||||
// adc-dac data
|
||||
|
||||
always @(posedge dac_clk) begin
|
||||
case ({dac_enable_1, dac_enable_0})
|
||||
2'b11: begin
|
||||
dac_drd <= dac_valid_0 & dac_valid_1;
|
||||
dac_ddata_0[63:48] <= dac_ddata[111: 96];
|
||||
dac_ddata_0[47:32] <= dac_ddata[ 79: 64];
|
||||
dac_ddata_0[31:16] <= dac_ddata[ 47: 32];
|
||||
dac_ddata_0[15: 0] <= dac_ddata[ 15: 0];
|
||||
dac_ddata_1[63:48] <= dac_ddata[127:112];
|
||||
dac_ddata_1[47:32] <= dac_ddata[ 95: 80];
|
||||
dac_ddata_1[31:16] <= dac_ddata[ 63: 48];
|
||||
dac_ddata_1[15: 0] <= dac_ddata[ 31: 16];
|
||||
dac_ddata_2 <= 64'd0;
|
||||
dac_ddata_3 <= 64'd0;
|
||||
end
|
||||
2'b10: begin
|
||||
dac_drd <= dac_valid_1 & ~dac_drd;
|
||||
dac_ddata_0 <= 64'd0;
|
||||
if (dac_drd == 1'b1) begin
|
||||
dac_ddata_1[63:48] <= dac_ddata[127:112];
|
||||
dac_ddata_1[47:32] <= dac_ddata[111: 96];
|
||||
dac_ddata_1[31:16] <= dac_ddata[ 95: 80];
|
||||
dac_ddata_1[15: 0] <= dac_ddata[ 79: 64];
|
||||
end else begin
|
||||
dac_ddata_1[63:48] <= dac_ddata[ 63: 48];
|
||||
dac_ddata_1[47:32] <= dac_ddata[ 47: 32];
|
||||
dac_ddata_1[31:16] <= dac_ddata[ 31: 16];
|
||||
dac_ddata_1[15: 0] <= dac_ddata[ 15: 0];
|
||||
end
|
||||
dac_ddata_2 <= 64'd0;
|
||||
dac_ddata_3 <= 64'd0;
|
||||
end
|
||||
2'b01: begin
|
||||
dac_drd <= dac_valid_0 & ~dac_drd;
|
||||
if (dac_drd == 1'b1) begin
|
||||
dac_ddata_0[63:48] <= dac_ddata[127:112];
|
||||
dac_ddata_0[47:32] <= dac_ddata[111: 96];
|
||||
dac_ddata_0[31:16] <= dac_ddata[ 95: 80];
|
||||
dac_ddata_0[15: 0] <= dac_ddata[ 79: 64];
|
||||
end else begin
|
||||
dac_ddata_0[63:48] <= dac_ddata[ 63: 48];
|
||||
dac_ddata_0[47:32] <= dac_ddata[ 47: 32];
|
||||
dac_ddata_0[31:16] <= dac_ddata[ 31: 16];
|
||||
dac_ddata_0[15: 0] <= dac_ddata[ 15: 0];
|
||||
end
|
||||
dac_ddata_1 <= 64'd0;
|
||||
dac_ddata_2 <= 64'd0;
|
||||
dac_ddata_3 <= 64'd0;
|
||||
end
|
||||
default: begin
|
||||
dac_drd <= 1'b0;
|
||||
dac_ddata_0 <= 64'd0;
|
||||
dac_ddata_1 <= 64'd0;
|
||||
dac_ddata_2 <= 64'd0;
|
||||
dac_ddata_3 <= 64'd0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge adc_clk) begin
|
||||
case ({adc_enable_1, adc_enable_0})
|
||||
2'b11: begin
|
||||
adc_dsync <= 1'b1;
|
||||
adc_dwr <= adc_valid_1 & adc_valid_0;
|
||||
adc_ddata[127:112] <= adc_data_1[63:48];
|
||||
adc_ddata[111: 96] <= adc_data_0[63:48];
|
||||
adc_ddata[ 95: 80] <= adc_data_1[47:32];
|
||||
adc_ddata[ 79: 64] <= adc_data_0[47:32];
|
||||
adc_ddata[ 63: 48] <= adc_data_1[31:16];
|
||||
adc_ddata[ 47: 32] <= adc_data_0[31:16];
|
||||
adc_ddata[ 31: 16] <= adc_data_1[15: 0];
|
||||
adc_ddata[ 15: 0] <= adc_data_0[15: 0];
|
||||
end
|
||||
2'b10: begin
|
||||
adc_dsync <= 1'b1;
|
||||
adc_dwr <= adc_valid_1 & ~adc_dwr;
|
||||
adc_ddata[127:112] <= adc_data_1[63:48];
|
||||
adc_ddata[111: 96] <= adc_data_1[47:32];
|
||||
adc_ddata[ 95: 80] <= adc_data_1[31:16];
|
||||
adc_ddata[ 79: 64] <= adc_data_1[15: 0];
|
||||
adc_ddata[ 63: 48] <= adc_ddata[127:112];
|
||||
adc_ddata[ 47: 32] <= adc_ddata[111: 96];
|
||||
adc_ddata[ 31: 16] <= adc_ddata[ 95: 80];
|
||||
adc_ddata[ 15: 0] <= adc_ddata[ 79: 64];
|
||||
end
|
||||
2'b01: begin
|
||||
adc_dsync <= 1'b1;
|
||||
adc_dwr <= adc_valid_0 & ~adc_dwr;
|
||||
adc_ddata[127:112] <= adc_data_0[63:48];
|
||||
adc_ddata[111: 96] <= adc_data_0[47:32];
|
||||
adc_ddata[ 95: 80] <= adc_data_0[31:16];
|
||||
adc_ddata[ 79: 64] <= adc_data_0[15: 0];
|
||||
adc_ddata[ 63: 48] <= adc_ddata[127:112];
|
||||
adc_ddata[ 47: 32] <= adc_ddata[111: 96];
|
||||
adc_ddata[ 31: 16] <= adc_ddata[ 95: 80];
|
||||
adc_ddata[ 15: 0] <= adc_ddata[ 79: 64];
|
||||
end
|
||||
default: begin
|
||||
adc_dsync <= 1'b0;
|
||||
adc_dwr <= 1'b0;
|
||||
adc_ddata <= 128'd0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
// spi
|
||||
|
||||
assign spi_csn_adc = spi_csn[2];
|
||||
assign spi_csn_dac = spi_csn[1];
|
||||
assign spi_csn_clk = spi_csn[0];
|
||||
|
||||
// instantiations
|
||||
|
||||
IBUFDS_GTE2 i_ibufds_rx_ref_clk (
|
||||
.CEB (1'd0),
|
||||
.I (rx_ref_clk_p),
|
||||
.IB (rx_ref_clk_n),
|
||||
.O (rx_ref_clk),
|
||||
.ODIV2 ());
|
||||
|
||||
IBUFDS i_ibufds_rx_sysref (
|
||||
.I (rx_sysref_p),
|
||||
.IB (rx_sysref_n),
|
||||
.O (rx_sysref));
|
||||
|
||||
OBUFDS i_obufds_rx_sync (
|
||||
.I (rx_sync),
|
||||
.O (rx_sync_p),
|
||||
.OB (rx_sync_n));
|
||||
|
||||
IBUFDS_GTE2 i_ibufds_tx_ref_clk (
|
||||
.CEB (1'd0),
|
||||
.I (tx_ref_clk_p),
|
||||
.IB (tx_ref_clk_n),
|
||||
.O (tx_ref_clk),
|
||||
.ODIV2 ());
|
||||
|
||||
IBUFDS i_ibufds_tx_sysref (
|
||||
.I (tx_sysref_p),
|
||||
.IB (tx_sysref_n),
|
||||
.O (tx_sysref));
|
||||
|
||||
IBUFDS i_ibufds_tx_sync (
|
||||
.I (tx_sync_p),
|
||||
.IB (tx_sync_n),
|
||||
.O (tx_sync));
|
||||
|
||||
daq2_spi i_spi (
|
||||
.spi_csn (spi_csn),
|
||||
.spi_clk (spi_clk),
|
||||
.spi_mosi (spi_mosi),
|
||||
.spi_miso (spi_miso),
|
||||
.spi_sdio (spi_sdio),
|
||||
.spi_dir (spi_dir));
|
||||
|
||||
IBUFDS i_ibufds_trig (
|
||||
.I (trig_p),
|
||||
.IB (trig_n),
|
||||
.O (trig));
|
||||
|
||||
assign gpio_i[43] = trig;
|
||||
|
||||
ad_iobuf #(.DATA_WIDTH(24)) i_iobuf (
|
||||
.dt ({gpio_t[42:40], gpio_t[38], gpio_t[36:32], gpio_t[14:0]}),
|
||||
.di ({gpio_o[42:40], gpio_o[38], gpio_o[36:32], gpio_o[14:0]}),
|
||||
.do ({gpio_i[42:40], gpio_i[38], gpio_i[36:32], gpio_i[14:0]}),
|
||||
.dio ({ adc_pd, // 42
|
||||
dac_txen, // 41
|
||||
dac_reset, // 40
|
||||
clkd_sync, // 38
|
||||
adc_fdb, // 36
|
||||
adc_fda, // 35
|
||||
dac_irq, // 34
|
||||
clkd_status, // 32
|
||||
gpio_bd})); // 0
|
||||
|
||||
system_wrapper i_system_wrapper (
|
||||
.DDR3_addr (DDR3_addr),
|
||||
.DDR3_ba (DDR3_ba),
|
||||
.DDR3_cas_n (DDR3_cas_n),
|
||||
.DDR3_ck_n (DDR3_ck_n),
|
||||
.DDR3_ck_p (DDR3_ck_p),
|
||||
.DDR3_cke (DDR3_cke),
|
||||
.DDR3_cs_n (DDR3_cs_n),
|
||||
.DDR3_dm (DDR3_dm),
|
||||
.DDR3_dq (DDR3_dq),
|
||||
.DDR3_dqs_n (DDR3_dqs_n),
|
||||
.DDR3_dqs_p (DDR3_dqs_p),
|
||||
.DDR3_odt (DDR3_odt),
|
||||
.DDR3_ras_n (DDR3_ras_n),
|
||||
.DDR3_reset_n (DDR3_reset_n),
|
||||
.DDR3_we_n (DDR3_we_n),
|
||||
.DDR_addr (DDR_addr),
|
||||
.DDR_ba (DDR_ba),
|
||||
.DDR_cas_n (DDR_cas_n),
|
||||
.DDR_ck_n (DDR_ck_n),
|
||||
.DDR_ck_p (DDR_ck_p),
|
||||
.DDR_cke (DDR_cke),
|
||||
.DDR_cs_n (DDR_cs_n),
|
||||
.DDR_dm (DDR_dm),
|
||||
.DDR_dq (DDR_dq),
|
||||
.DDR_dqs_n (DDR_dqs_n),
|
||||
.DDR_dqs_p (DDR_dqs_p),
|
||||
.DDR_odt (DDR_odt),
|
||||
.DDR_ras_n (DDR_ras_n),
|
||||
.DDR_reset_n (DDR_reset_n),
|
||||
.DDR_we_n (DDR_we_n),
|
||||
.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn),
|
||||
.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp),
|
||||
.FIXED_IO_mio (FIXED_IO_mio),
|
||||
.FIXED_IO_ps_clk (FIXED_IO_ps_clk),
|
||||
.FIXED_IO_ps_porb (FIXED_IO_ps_porb),
|
||||
.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb),
|
||||
.GPIO_I (gpio_i),
|
||||
.GPIO_O (gpio_o),
|
||||
.GPIO_T (gpio_t),
|
||||
.adc_clk (adc_clk),
|
||||
.adc_data_0 (adc_data_0),
|
||||
.adc_data_1 (adc_data_1),
|
||||
.adc_ddata (adc_ddata),
|
||||
.adc_dsync (adc_dsync),
|
||||
.adc_dwr (adc_dwr),
|
||||
.adc_enable_0 (adc_enable_0),
|
||||
.adc_enable_1 (adc_enable_1),
|
||||
.adc_valid_0 (adc_valid_0),
|
||||
.adc_valid_1 (adc_valid_1),
|
||||
.dac_clk (dac_clk),
|
||||
.dac_ddata (dac_ddata),
|
||||
.dac_ddata_0 (dac_ddata_0),
|
||||
.dac_ddata_1 (dac_ddata_1),
|
||||
.dac_ddata_2 (dac_ddata_2),
|
||||
.dac_ddata_3 (dac_ddata_3),
|
||||
.dac_drd (dac_drd),
|
||||
.dac_enable_0 (dac_enable_0),
|
||||
.dac_enable_1 (dac_enable_1),
|
||||
.dac_enable_2 (dac_enable_2),
|
||||
.dac_enable_3 (dac_enable_3),
|
||||
.dac_valid_0 (dac_valid_0),
|
||||
.dac_valid_1 (dac_valid_1),
|
||||
.dac_valid_2 (dac_valid_2),
|
||||
.dac_valid_3 (dac_valid_3),
|
||||
.hdmi_data (hdmi_data),
|
||||
.hdmi_data_e (hdmi_data_e),
|
||||
.hdmi_hsync (hdmi_hsync),
|
||||
.hdmi_out_clk (hdmi_out_clk),
|
||||
.hdmi_vsync (hdmi_vsync),
|
||||
.iic_main_scl_io (iic_scl),
|
||||
.iic_main_sda_io (iic_sda),
|
||||
.rx_data_n (rx_data_n),
|
||||
.rx_data_p (rx_data_p),
|
||||
.rx_ref_clk (rx_ref_clk),
|
||||
.rx_sync (rx_sync),
|
||||
.rx_sysref (rx_sysref),
|
||||
.spdif (spdif),
|
||||
.spi_clk_i (spi_clk),
|
||||
.spi_clk_o (spi_clk),
|
||||
.spi_csn_i (1'b1),
|
||||
.spi_csn_0_o (spi_csn[0]),
|
||||
.spi_csn_1_o (spi_csn[1]),
|
||||
.spi_csn_2_o (spi_csn[2]),
|
||||
.spi_sdi_i (spi_miso),
|
||||
.spi_sdo_i (spi_mosi),
|
||||
.spi_sdo_o (spi_mosi),
|
||||
.sys_clk_clk_n (sys_clk_n),
|
||||
.sys_clk_clk_p (sys_clk_p),
|
||||
.tx_data_n (tx_data_n),
|
||||
.tx_data_p (tx_data_p),
|
||||
.tx_ref_clk (tx_ref_clk),
|
||||
.tx_sync (tx_sync),
|
||||
.tx_sysref (tx_sysref));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
Loading…
Reference in New Issue