ccpci_lvds- rev.d. xcvr pin changes
Rejeesh Kutty
parent
1cbea90bac
commit
128ca7719a
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@ -1,38 +1,36 @@
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# constraints
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# reference-only & not-effective
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# (axi_pcie_x0y0.xdc)
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set_property -dict {PACKAGE_PIN AA6} [get_ports pcie_ref_clk_p] ; ## MGTREFCLK1P_111
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set_property -dict {PACKAGE_PIN AA5} [get_ports pcie_ref_clk_n] ; ## MGTREFCLK1N_111
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set_property -dict {PACKAGE_PIN AD4} [get_ports pcie_data_rx_p[0]] ; ## MGTXRXP3_111
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set_property -dict {PACKAGE_PIN AD3} [get_ports pcie_data_rx_n[0]] ; ## MGTXRXN3_111
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set_property -dict {PACKAGE_PIN AC6} [get_ports pcie_data_rx_p[1]] ; ## MGTXRXP2_111
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set_property -dict {PACKAGE_PIN AC5} [get_ports pcie_data_rx_n[1]] ; ## MGTXRXN2_111
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set_property -dict {PACKAGE_PIN AE6} [get_ports pcie_data_rx_p[2]] ; ## MGTXRXP1_111
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set_property -dict {PACKAGE_PIN AE5} [get_ports pcie_data_rx_n[2]] ; ## MGTXRXN1_111
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set_property -dict {PACKAGE_PIN AD8} [get_ports pcie_data_rx_p[3]] ; ## MGTXRXP0_111
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set_property -dict {PACKAGE_PIN AD7} [get_ports pcie_data_rx_n[3]] ; ## MGTXRXN0_111
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set_property -dict {PACKAGE_PIN AC2} [get_ports pcie_data_tx_p[0]] ; ## MGTXTXP3_111
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set_property -dict {PACKAGE_PIN AC1} [get_ports pcie_data_tx_n[0]] ; ## MGTXTXN3_111
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set_property -dict {PACKAGE_PIN AE2} [get_ports pcie_data_tx_p[1]] ; ## MGTXTXP2_111
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set_property -dict {PACKAGE_PIN AE1} [get_ports pcie_data_tx_n[1]] ; ## MGTXTXN2_111
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set_property -dict {PACKAGE_PIN AF4} [get_ports pcie_data_tx_p[2]] ; ## MGTXTXP1_111
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set_property -dict {PACKAGE_PIN AF3} [get_ports pcie_data_tx_n[2]] ; ## MGTXTXN1_111
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set_property -dict {PACKAGE_PIN AF8} [get_ports pcie_data_tx_p[3]] ; ## MGTXTXP0_111
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set_property -dict {PACKAGE_PIN AF7} [get_ports pcie_data_tx_n[3]] ; ## MGTXTXN0_111
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set_property -dict {PACKAGE_PIN U6 } [get_ports pcie_ref_clk_p] ; ## MGTREFCLK1P_112 (JX3.2) (P2.A13)
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set_property -dict {PACKAGE_PIN U5 } [get_ports pcie_ref_clk_n] ; ## MGTREFCLK1N_112 (JX3.4) (P2.A14)
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set_property -dict {PACKAGE_PIN T4 } [get_ports pcie_data_rx_p[0]] ; ## MGTXRXP3_112 (JX1.97) (P2.B14)
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set_property -dict {PACKAGE_PIN T3 } [get_ports pcie_data_rx_n[0]] ; ## MGTXRXN3_112 (JX1.99) (P2.B15)
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set_property -dict {PACKAGE_PIN V4 } [get_ports pcie_data_rx_p[1]] ; ## MGTXRXP2_112 (JX1.92) (P2.B19)
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set_property -dict {PACKAGE_PIN V3 } [get_ports pcie_data_rx_n[1]] ; ## MGTXRXN2_112 (JX1.94) (P2.B20)
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set_property -dict {PACKAGE_PIN Y4 } [get_ports pcie_data_rx_p[2]] ; ## MGTXRXP1_112 (JX1.91) (P2.B23)
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set_property -dict {PACKAGE_PIN Y3 } [get_ports pcie_data_rx_n[2]] ; ## MGTXRXN1_112 (JX1.93) (P2.B24)
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set_property -dict {PACKAGE_PIN AB4} [get_ports pcie_data_rx_p[3]] ; ## MGTXRXP0_112 (JX1.88) (P2.B27)
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set_property -dict {PACKAGE_PIN AB3} [get_ports pcie_data_rx_n[3]] ; ## MGTXRXN0_112 (JX1.90) (P2.B28)
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set_property -dict {PACKAGE_PIN R2 } [get_ports pcie_data_tx_p[0]] ; ## MGTXTXP3_112 (JX3.19) (P2.A16)
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set_property -dict {PACKAGE_PIN R1 } [get_ports pcie_data_tx_n[0]] ; ## MGTXTXN3_112 (JX3.21) (P2.A17)
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set_property -dict {PACKAGE_PIN U2 } [get_ports pcie_data_tx_p[1]] ; ## MGTXTXP2_112 (JX3.14) (P2.A21)
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set_property -dict {PACKAGE_PIN U1 } [get_ports pcie_data_tx_n[1]] ; ## MGTXTXN2_112 (JX3.16) (P2.A22)
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set_property -dict {PACKAGE_PIN W2 } [get_ports pcie_data_tx_p[2]] ; ## MGTXTXP1_112 (JX3.13) (P2.A25)
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set_property -dict {PACKAGE_PIN W1 } [get_ports pcie_data_tx_n[2]] ; ## MGTXTXN1_112 (JX3.15) (P2.A26)
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set_property -dict {PACKAGE_PIN AA2} [get_ports pcie_data_tx_p[3]] ; ## MGTXTXP0_112 (JX3.8 ) (P2.A29)
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set_property -dict {PACKAGE_PIN AA1} [get_ports pcie_data_tx_n[3]] ; ## MGTXTXN0_112 (JX3.10) (P2.A30)
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set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS33} [get_ports pcie_rstn] ; ## IO_L19P_T3_13
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set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS33} [get_ports pcie_waken] ; ## IO_L20N_T3_13
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set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVCMOS33} [get_ports pcie_rstn_good] ; ## IO_L22N_T3_12
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# Default constraints have LVCMOS25, overwite it
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set_property -dict {IOSTANDARD LVCMOS33} [get_ports iic_scl] ; ## IO_L5P_T0_13
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set_property -dict {IOSTANDARD LVCMOS33} [get_ports iic_sda] ; ## IO_L5N_T0_13
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set_property PULLUP true [get_ports pcie_rstn]
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set_property LOC IBUFDS_GTE2_X0Y5 [get_cells i_ibufds_pcie_ref_clk]
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create_clock -name pcie_ref_clock -period 10 [get_ports pcie_ref_clk_p]
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set_property LOC GTXE2_CHANNEL_X0Y8 [get_cells -hierarchical -filter {NAME =~ *comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/gtx_channel.gtxe2_channel_i}]
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set_property LOC GTXE2_CHANNEL_X0Y9 [get_cells -hierarchical -filter {NAME =~ *comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/gtx_channel.gtxe2_channel_i}]
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set_property LOC GTXE2_CHANNEL_X0Y10 [get_cells -hierarchical -filter {NAME =~ *comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/gtx_channel.gtxe2_channel_i}]
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set_property LOC GTXE2_CHANNEL_X0Y11 [get_cells -hierarchical -filter {NAME =~ *comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtx_channel.gtxe2_channel_i}]
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