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ad_tdd_control: Remove tdd_enable_synced control line 

For a better timing and control, the valid control lines are gated with flops, instead of combinatorial logic.
This is the main reason why we do not need the tdd_enable_synced signal anymore. The out coming data is delayed by one clock cycle to keep data and control lines synced.
main
Istvan Csomortani 2015-12-03 11:13:56 +02:00
parent 5cf45b2978
commit 12c95b059d
3 changed files with 65 additions and 34 deletions
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33
library/axi_ad9361/axi_ad9361.v
View File

@ -284,6 +284,12 @@ module axi_ad9361 (
reg up_rack = 'd0;
reg [31:0] up_rdata = 'd0;
reg [15:0] adc_data_i0 = 16'b0;
reg [15:0] adc_data_q0 = 16'b0;
reg [15:0] adc_data_i1 = 16'b0;
reg [15:0] adc_data_q1 = 16'b0;
// internal clocks and resets
wire up_clk;
@ -333,6 +339,10 @@ module axi_ad9361 (
wire tdd_txnrx_s;
wire tdd_mode_s;
wire [15:0] adc_data_i0_s;
wire [15:0] adc_data_q0_s;
wire [15:0] adc_data_i1_s;
wire [15:0] adc_data_q1_s;
// signal name changes
@ -403,6 +413,21 @@ module axi_ad9361 (
// TDD interface
// additional flop to keep control and data synced
always @(posedge clk) begin
if(rst == 1) begin
adc_data_i0 <= 16'b0;
adc_data_q0 <= 16'b0;
adc_data_i1 <= 16'b0;
adc_data_q1 <= 16'b0;
end else begin
adc_data_i0 <= adc_data_i0_s;
adc_data_q0 <= adc_data_q0_s;
adc_data_i1 <= adc_data_i1_s;
adc_data_q1 <= adc_data_q1_s;
end
end
axi_ad9361_tdd_if #(.LEVEL_OR_PULSE_N(1)) i_tdd_if (
.clk (clk),
.rst (rst),
@ -478,16 +503,16 @@ module axi_ad9361 (
.delay_locked (delay_locked_s),
.adc_enable_i0 (adc_enable_i0),
.adc_valid_i0 (adc_valid_i0_s),
.adc_data_i0 (adc_data_i0),
.adc_data_i0 (adc_data_i0_s),
.adc_enable_q0 (adc_enable_q0),
.adc_valid_q0 (adc_valid_q0_s),
.adc_data_q0 (adc_data_q0),
.adc_data_q0 (adc_data_q0_s),
.adc_enable_i1 (adc_enable_i1),
.adc_valid_i1 (adc_valid_i1_s),
.adc_data_i1 (adc_data_i1),
.adc_data_i1 (adc_data_i1_s),
.adc_enable_q1 (adc_enable_q1),
.adc_valid_q1 (adc_valid_q1_s),
.adc_data_q1 (adc_data_q1),
.adc_data_q1 (adc_data_q1_s),
.adc_dovf (adc_dovf),
.adc_dunf (adc_dunf),
.up_adc_gpio_in (up_adc_gpio_in),

55
library/axi_ad9361/axi_ad9361_tdd.v
View File

@ -160,11 +160,19 @@ module axi_ad9361_tdd (
reg tdd_slave_synced = 1'b0;
reg tdd_tx_valid_i0 = 1'b0;
reg tdd_tx_valid_q0 = 1'b0;
reg tdd_tx_valid_i1 = 1'b0;
reg tdd_tx_valid_q1 = 1'b0;
reg tdd_rx_valid_i0 = 1'b0;
reg tdd_rx_valid_q0 = 1'b0;
reg tdd_rx_valid_i1 = 1'b0;
reg tdd_rx_valid_q1 = 1'b0;
// internal signals
wire rst;
wire tdd_enable_s;
wire tdd_enable_synced_s;
wire tdd_secondary_s;
wire [ 7:0] tdd_burst_count_s;
wire tdd_rx_only_s;
@ -205,25 +213,35 @@ module axi_ad9361_tdd (
// tx/rx data flow control
assign tdd_tx_valid_i0 = ((tdd_enable_synced_s & tdd_gated_tx_dmapath_s) == 1'b1) ?
(tx_valid_i0 & tdd_tx_dp_en_s) : tx_valid_i0;
assign tdd_tx_valid_q0 = ((tdd_enable_synced_s & tdd_gated_tx_dmapath_s) == 1'b1) ?
(tx_valid_q0 & tdd_tx_dp_en_s) : tx_valid_q0;
assign tdd_tx_valid_i1 = ((tdd_enable_synced_s & tdd_gated_tx_dmapath_s) == 1'b1) ?
(tx_valid_i1 & tdd_tx_dp_en_s) : tx_valid_i1;
assign tdd_tx_valid_q1 = ((tdd_enable_synced_s & tdd_gated_tx_dmapath_s) == 1'b1) ?
(tx_valid_q1 & tdd_tx_dp_en_s) : tx_valid_q1;
always @(posedge clk) begin
if((tdd_enable_s == 1) && (tdd_gated_tx_dmapath_s == 1)) begin
tdd_tx_valid_i0 <= tx_valid_i0 & tdd_tx_dp_en_s;
tdd_tx_valid_q0 <= tx_valid_q0 & tdd_tx_dp_en_s;
tdd_tx_valid_i1 <= tx_valid_i1 & tdd_tx_dp_en_s;
tdd_tx_valid_q1 <= tx_valid_q1 & tdd_tx_dp_en_s;
end else begin
tdd_tx_valid_i0 <= tx_valid_i0;
tdd_tx_valid_q0 <= tx_valid_q0;
tdd_tx_valid_i1 <= tx_valid_i1;
tdd_tx_valid_q1 <= tx_valid_q1;
end
end
assign tdd_rx_valid_i0 = ((tdd_enable_synced_s & tdd_gated_rx_dmapath_s) == 1'b1) ?
(rx_valid_i0 & tdd_rx_rf_en) : rx_valid_i0;
assign tdd_rx_valid_q0 = ((tdd_enable_synced_s & tdd_gated_rx_dmapath_s) == 1'b1) ?
(rx_valid_q0 & tdd_rx_rf_en) : rx_valid_q0;
assign tdd_rx_valid_i1 = ((tdd_enable_synced_s & tdd_gated_rx_dmapath_s) == 1'b1) ?
(rx_valid_i1 & tdd_rx_rf_en) : rx_valid_i1;
assign tdd_rx_valid_q1 = ((tdd_enable_synced_s & tdd_gated_rx_dmapath_s) == 1'b1) ?
(rx_valid_q1 & tdd_rx_rf_en) : rx_valid_q1;
always @(posedge clk) begin
if((tdd_enable_s == 1) && (tdd_gated_tx_dmapath_s == 1)) begin
tdd_rx_valid_i0 <= rx_valid_i0 & tdd_rx_rf_en;
tdd_rx_valid_q0 <= rx_valid_q0 & tdd_rx_rf_en;
tdd_rx_valid_i1 <= rx_valid_i1 & tdd_rx_rf_en;
tdd_rx_valid_q1 <= rx_valid_q1 & tdd_rx_rf_en;
end else begin
tdd_rx_valid_i0 <= rx_valid_i0;
tdd_rx_valid_q0 <= rx_valid_q0;
tdd_rx_valid_i1 <= rx_valid_i1;
tdd_rx_valid_q1 <= rx_valid_q1;
end
end
assign tdd_enabled = tdd_enable_synced_s;
assign tdd_enabled = tdd_enable_s;
assign tdd_terminal_type = ~tdd_terminal_type_s;
// instantiations
@ -284,7 +302,6 @@ module axi_ad9361_tdd (
.clk(clk),
.rst(rst),
.tdd_enable(tdd_enable_s),
.tdd_enable_synced (tdd_enable_synced_s),
.tdd_secondary(tdd_secondary_s),
.tdd_counter_init(tdd_counter_init_s),
.tdd_frame_length(tdd_frame_length_s),

11
library/common/ad_tdd_control.v
View File

@ -49,7 +49,6 @@ module ad_tdd_control(
// TDD timming signals
tdd_enable,
tdd_enable_synced,
tdd_secondary,
tdd_tx_only,
tdd_rx_only,
@ -103,7 +102,6 @@ module ad_tdd_control(
input rst;
input tdd_enable;
output tdd_enable_synced;
input tdd_secondary;
input tdd_tx_only;
input tdd_rx_only;
@ -179,7 +177,6 @@ module ad_tdd_control(
reg counter_at_tdd_tx_dp_on_2 = 1'b0;
reg counter_at_tdd_tx_dp_off_2 = 1'b0;
reg tdd_enable_synced = 1'h0;
reg tdd_last_burst = 1'b0;
reg tdd_sync_d1 = 1'b0;
@ -232,14 +229,6 @@ module ad_tdd_control(
end
end
always @(posedge clk) begin
if (rst == 1'b1) begin
tdd_enable_synced <= 1'b0;
end else begin
tdd_enable_synced <= ((~tdd_sync_d3 & tdd_sync_d2) == 1'b1) ? tdd_enable : tdd_enable_synced;
end
end
// ***************************************************************************
// tdd counter (state machine)
// ***************************************************************************