clean: Delete deprecated source files
The axi_jesd_gt was repleaced by axi_adxcvr IP, which is located at library/xilinx and library/altera. The axi_jesd_xcvr was an early version of axi_adxcvr. The register map is moved to the IP's directory.main
Istvan Csomortani
parent
f64b44c8ac
commit
12d6e46ae7
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@ -1,72 +0,0 @@
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####################################################################################
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####################################################################################
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## Copyright 2011(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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####################################################################################
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M_DEPS := axi_jesd_gt_ip.tcl
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M_DEPS += ../scripts/adi_env.tcl
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M_DEPS += ../scripts/adi_ip.tcl
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M_DEPS += ../common/ad_rst.v
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M_DEPS += ../common/ad_gt_channel.v
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M_DEPS += ../common/ad_gt_common.v
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M_DEPS += ../common/ad_gt_es.v
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M_DEPS += ../common/ad_gt_es_axi.v
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M_DEPS += ../common/ad_gt_channel_1.v
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M_DEPS += ../common/ad_gt_common_1.v
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M_DEPS += ../common/ad_jesd_align.v
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M_DEPS += ../common/up_axi.v
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M_DEPS += ../common/up_gt_channel.v
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M_DEPS += ../common/up_gt.v
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M_DEPS += axi_jesd_gt_tx_constr.xdc
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M_DEPS += axi_jesd_gt_rx_constr.xdc
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M_DEPS += axi_jesd_gt_constr.xdc
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M_DEPS += axi_jesd_gt.v
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M_DEPS += ../interfaces/if_gt_qpll.xml
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M_DEPS += ../interfaces/if_gt_qpll_rtl.xml
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M_DEPS += ../interfaces/if_gt_pll.xml
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M_DEPS += ../interfaces/if_gt_pll_rtl.xml
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M_DEPS += ../interfaces/if_gt_rx.xml
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M_DEPS += ../interfaces/if_gt_rx_rtl.xml
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M_DEPS += ../interfaces/if_gt_rx_ksig.xml
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M_DEPS += ../interfaces/if_gt_rx_ksig_rtl.xml
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M_DEPS += ../interfaces/if_gt_tx.xml
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M_DEPS += ../interfaces/if_gt_tx_rtl.xml
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M_VIVADO := vivado -mode batch -source
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M_FLIST := *.cache
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M_FLIST += *.data
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M_FLIST += *.xpr
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M_FLIST += *.log
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M_FLIST += component.xml
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M_FLIST += *.jou
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M_FLIST += xgui
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M_FLIST += *.ip_user_files
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M_FLIST += *.srcs
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M_FLIST += *.hw
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M_FLIST += *.sim
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M_FLIST += .Xil
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.PHONY: all dep clean clean-all
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all: dep axi_jesd_gt.xpr
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clean:clean-all
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clean-all:
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rm -rf $(M_FLIST)
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axi_jesd_gt.xpr: $(M_DEPS)
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-rm -rf $(M_FLIST)
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$(M_VIVADO) axi_jesd_gt_ip.tcl >> axi_jesd_gt_ip.log 2>&1
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dep:
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make -C ../interfaces
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####################################################################################
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####################################################################################
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File diff suppressed because it is too large
Load Diff
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@ -1,5 +0,0 @@
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set_property shreg_extract no [get_cells -hier -filter {name =~ *ad_rst_sync*}]
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@ -1,194 +0,0 @@
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# ip
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source ../scripts/adi_env.tcl
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source $ad_hdl_dir/library/scripts/adi_ip.tcl
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adi_ip_create axi_jesd_gt
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adi_ip_files axi_jesd_gt [list \
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"$ad_hdl_dir/library/common/ad_rst.v" \
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"$ad_hdl_dir/library/common/ad_gt_channel.v" \
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"$ad_hdl_dir/library/common/ad_gt_common.v" \
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"$ad_hdl_dir/library/common/ad_gt_es.v" \
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"$ad_hdl_dir/library/common/ad_gt_es_axi.v" \
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"$ad_hdl_dir/library/common/ad_gt_channel_1.v" \
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"$ad_hdl_dir/library/common/ad_gt_common_1.v" \
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"$ad_hdl_dir/library/common/ad_jesd_align.v" \
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"$ad_hdl_dir/library/common/up_axi.v" \
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"$ad_hdl_dir/library/common/up_gt_channel.v" \
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"$ad_hdl_dir/library/common/up_gt.v" \
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"axi_jesd_gt_tx_constr.xdc" \
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"axi_jesd_gt_rx_constr.xdc" \
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"axi_jesd_gt_constr.xdc" \
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"axi_jesd_gt.v" ]
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adi_ip_properties axi_jesd_gt
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adi_ip_infer_interfaces axi_jesd_gt
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adi_ip_constraints axi_jesd_gt [list \
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"axi_jesd_gt_tx_constr.xdc" \
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"axi_jesd_gt_rx_constr.xdc" \
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"axi_jesd_gt_constr.xdc" ]
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ipx::associate_bus_interfaces -busif m_axi -clock s_axi_aclk [ipx::current_core]
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adi_if_infer_bus ADI:user:if_gt_qpll slave gt_qpll_0 [list \
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"qpll_rst qpll0_rst "\
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"qpll_ref_clk qpll0_ref_clk_in "]
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adi_if_infer_bus ADI:user:if_gt_qpll slave gt_qpll_1 [list \
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"qpll_rst qpll1_rst "\
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"qpll_ref_clk qpll1_ref_clk_in "]
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for {set n 0} {$n < 8} {incr n} {
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adi_if_infer_bus ADI:user:if_gt_pll slave gt_pll_${n} [list \
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"cpll_rst_m cpll_rst_m_${n} "\
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"cpll_ref_clk_in cpll_ref_clk_in_${n} "]
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adi_if_infer_bus ADI:user:if_gt_rx slave gt_rx_${n} [list \
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"rx_p rx_${n}_p "\
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"rx_n rx_${n}_n "\
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"rx_rst rx_rst_${n} "\
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"rx_rst_m rx_rst_m_${n} "\
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"rx_pll_rst rx_pll_rst_${n} "\
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"rx_gt_rst rx_gt_rst_${n} "\
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"rx_gt_rst_m rx_gt_rst_m_${n} "\
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"rx_pll_locked rx_pll_locked_${n} "\
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"rx_pll_locked_m rx_pll_locked_m_${n} "\
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"rx_user_ready rx_user_ready_${n} "\
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"rx_user_ready_m rx_user_ready_m_${n} "\
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"rx_rst_done rx_rst_done_${n} "\
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"rx_rst_done_m rx_rst_done_m_${n} "\
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"rx_out_clk rx_out_clk_${n} "\
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"rx_clk rx_clk_${n} "\
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"rx_sysref rx_sysref_${n} "\
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"rx_sync rx_sync_${n} "\
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"rx_sof rx_sof_${n} "\
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"rx_data rx_data_${n} "\
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"rx_ip_rst rx_ip_rst_${n} "\
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"rx_ip_sof rx_ip_sof_${n} "\
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"rx_ip_data rx_ip_data_${n} "\
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"rx_ip_sysref rx_ip_sysref_${n} "\
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"rx_ip_sync rx_ip_sync_${n} "\
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"rx_ip_rst_done rx_ip_rst_done_${n} "]
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adi_if_infer_bus xilinx.com:display_jesd204:jesd204_rx_bus master gt_rx_ip_${n} [list \
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"rxcharisk rx_gt_charisk_${n} "\
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"rxdisperr rx_gt_disperr_${n} "\
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"rxnotintable rx_gt_notintable_${n} "\
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"rxdata rx_gt_data_${n} "]
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adi_if_infer_bus ADI:user:if_gt_rx_ksig master gt_rx_ksig_${n} [list \
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"rx_gt_ilas_f rx_gt_ilas_f_${n} "\
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"rx_gt_ilas_q rx_gt_ilas_q_${n} "\
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"rx_gt_ilas_a rx_gt_ilas_a_${n} "\
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"rx_gt_ilas_r rx_gt_ilas_r_${n} "\
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"rx_gt_cgs_k rx_gt_cgs_k_${n} "]
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adi_if_infer_bus ADI:user:if_gt_tx slave gt_tx_${n} [list \
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"tx_p tx_${n}_p "\
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"tx_n tx_${n}_n "\
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"tx_rst tx_rst_${n} "\
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"tx_rst_m tx_rst_m_${n} "\
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"tx_pll_rst tx_pll_rst_${n} "\
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"tx_gt_rst tx_gt_rst_${n} "\
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"tx_gt_rst_m tx_gt_rst_m_${n} "\
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"tx_pll_locked tx_pll_locked_${n} "\
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"tx_pll_locked_m tx_pll_locked_m_${n} "\
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"tx_user_ready tx_user_ready_${n} "\
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"tx_user_ready_m tx_user_ready_m_${n} "\
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"tx_rst_done tx_rst_done_${n} "\
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"tx_rst_done_m tx_rst_done_m_${n} "\
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"tx_out_clk tx_out_clk_${n} "\
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"tx_clk tx_clk_${n} "\
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"tx_sysref tx_sysref_${n} "\
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"tx_sync tx_sync_${n} "\
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"tx_data tx_data_${n} "\
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"tx_ip_rst tx_ip_rst_${n} "\
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"tx_ip_data tx_ip_data_${n} "\
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"tx_ip_sysref tx_ip_sysref_${n} "\
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"tx_ip_sync tx_ip_sync_${n} "\
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"tx_ip_rst_done tx_ip_rst_done_${n} "]
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adi_if_infer_bus xilinx.com:display_jesd204:jesd204_tx_bus slave gt_tx_ip_${n} [list \
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"txcharisk tx_gt_charisk_${n} "\
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"txdata tx_gt_data_${n} "]
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}
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.QPLL0_ENABLE')) == 1} \
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[ipx::get_bus_interfaces gt_qpll_0 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.QPLL1_ENABLE')) == 1} \
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[ipx::get_bus_interfaces gt_qpll_1 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 0} \
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[ipx::get_bus_interfaces gt_pll_0 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 1} \
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[ipx::get_bus_interfaces gt_pll_1 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 2} \
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[ipx::get_bus_interfaces gt_pll_2 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 3} \
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[ipx::get_bus_interfaces gt_pll_3 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 4} \
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[ipx::get_bus_interfaces gt_pll_4 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 5} \
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[ipx::get_bus_interfaces gt_pll_5 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 6} \
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[ipx::get_bus_interfaces gt_pll_6 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 7} \
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[ipx::get_bus_interfaces gt_pll_7 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \
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[ipx::get_bus_interfaces gt_rx_*0 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \
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[ipx::get_bus_interfaces gt_rx_*1 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \
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[ipx::get_bus_interfaces gt_rx_*2 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \
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[ipx::get_bus_interfaces gt_rx_*3 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \
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[ipx::get_bus_interfaces gt_rx_*4 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \
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[ipx::get_bus_interfaces gt_rx_*5 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \
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[ipx::get_bus_interfaces gt_rx_*6 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \
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[ipx::get_bus_interfaces gt_rx_*7 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0} \
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[ipx::get_bus_interfaces gt_tx_*0 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1} \
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[ipx::get_bus_interfaces gt_tx_*1 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2} \
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[ipx::get_bus_interfaces gt_tx_*2 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3} \
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[ipx::get_bus_interfaces gt_tx_*3 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4} \
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[ipx::get_bus_interfaces gt_tx_*4 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5} \
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[ipx::get_bus_interfaces gt_tx_*5 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6} \
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[ipx::get_bus_interfaces gt_tx_*6 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7} \
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[ipx::get_bus_interfaces gt_tx_*7 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \
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[ipx::get_ports *rx_*0* -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \
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[ipx::get_ports *rx_*1* -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \
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[ipx::get_ports *rx_*2* -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \
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[ipx::get_ports *rx_*3* -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \
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[ipx::get_ports *rx_*4* -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \
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[ipx::get_ports *rx_*5* -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \
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[ipx::get_ports *rx_*6* -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \
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[ipx::get_ports *rx_*7* -of_objects [ipx::current_core]]
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set_property driver_value 0 [ipx::get_ports -filter "direction==in" -of_objects [ipx::current_core]]
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ipx::save_core [ipx::current_core]
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@ -1,19 +0,0 @@
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set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_rst_done*}]
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set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_pll_locked*}]
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set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_status*}]
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set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/rx_sysref_sel*}]
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set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/rx_up_sysref*}]
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set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/rx_up_sync*}]
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set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_rst_done_m1_reg && IS_SEQUENTIAL}]
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set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_rst_done_m_m1_reg && IS_SEQUENTIAL}]
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set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_pll_locked_m1_reg && IS_SEQUENTIAL}]
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set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_pll_locked_m_m1_reg && IS_SEQUENTIAL}]
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set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_status_m1_reg && IS_SEQUENTIAL}]
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set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/rx_sysref_sel_m1_reg && IS_SEQUENTIAL}]
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set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/rx_up_sysref_m1_reg && IS_SEQUENTIAL}]
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set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/rx_up_sync_m1_reg && IS_SEQUENTIAL}]
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set_false_path -from [get_cells -hier -filter {name =~ *up_rx_preset_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *ad_rst_sync_m1_reg && IS_SEQUENTIAL}]
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@ -1,19 +0,0 @@
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set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_rst_done*}]
|
||||
set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_pll_locked*}]
|
||||
set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_status*}]
|
||||
set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/tx_sysref_sel*}]
|
||||
set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/tx_up_sysref*}]
|
||||
set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/tx_up_sync*}]
|
||||
|
||||
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_rst_done_m1_reg && IS_SEQUENTIAL}]
|
||||
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_rst_done_m_m1_reg && IS_SEQUENTIAL}]
|
||||
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_pll_locked_m1_reg && IS_SEQUENTIAL}]
|
||||
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_pll_locked_m_m1_reg && IS_SEQUENTIAL}]
|
||||
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_status_m1_reg && IS_SEQUENTIAL}]
|
||||
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/tx_sysref_sel_m1_reg && IS_SEQUENTIAL}]
|
||||
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/tx_up_sysref_m1_reg && IS_SEQUENTIAL}]
|
||||
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/tx_up_sync_m1_reg && IS_SEQUENTIAL}]
|
||||
|
||||
set_false_path -from [get_cells -hier -filter {name =~ *up_tx_preset_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *ad_rst_sync_m1_reg && IS_SEQUENTIAL}]
|
||||
|
||||
|
|
@ -1,318 +0,0 @@
|
|||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2011(c) Analog Devices, Inc.
|
||||
//
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without modification,
|
||||
// are permitted provided that the following conditions are met:
|
||||
// - Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// - Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in
|
||||
// the documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
// - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
// contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
// - The use of this software may or may not infringe the patent rights
|
||||
// of one or more patent holders. This license does not release you
|
||||
// from the requirement that you obtain separate licenses from these
|
||||
// patent holders to use this software.
|
||||
// - Use of the software either in source or binary form, must be run
|
||||
// on or directly connected to an Analog Devices Inc. component.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
|
||||
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
|
||||
// PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
//
|
||||
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
|
||||
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_jesd_xcvr (
|
||||
|
||||
rst,
|
||||
|
||||
// receive interface
|
||||
|
||||
rx_clk,
|
||||
rx_rstn,
|
||||
rx_ext_sysref_in,
|
||||
rx_ext_sysref_out,
|
||||
rx_sync,
|
||||
rx_sof,
|
||||
rx_data,
|
||||
rx_ready,
|
||||
rx_ip_sysref,
|
||||
rx_ip_sync,
|
||||
rx_ip_sof,
|
||||
rx_ip_valid,
|
||||
rx_ip_data,
|
||||
rx_ip_ready,
|
||||
|
||||
// transmit interface
|
||||
|
||||
tx_clk,
|
||||
tx_rstn,
|
||||
tx_ext_sysref_in,
|
||||
tx_ext_sysref_out,
|
||||
tx_sync,
|
||||
tx_data,
|
||||
tx_ready,
|
||||
tx_ip_sysref,
|
||||
tx_ip_sync,
|
||||
tx_ip_valid,
|
||||
tx_ip_data,
|
||||
tx_ip_ready,
|
||||
|
||||
// axi-lite (slave)
|
||||
|
||||
s_axi_aclk,
|
||||
s_axi_aresetn,
|
||||
s_axi_awvalid,
|
||||
s_axi_awaddr,
|
||||
s_axi_awprot,
|
||||
s_axi_awready,
|
||||
s_axi_wvalid,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wready,
|
||||
s_axi_bvalid,
|
||||
s_axi_bresp,
|
||||
s_axi_bready,
|
||||
s_axi_arvalid,
|
||||
s_axi_araddr,
|
||||
s_axi_arprot,
|
||||
s_axi_arready,
|
||||
s_axi_rvalid,
|
||||
s_axi_rdata,
|
||||
s_axi_rresp,
|
||||
s_axi_rready);
|
||||
|
||||
parameter ID = 0;
|
||||
parameter DEVICE_TYPE = 0;
|
||||
parameter TX_NUM_OF_LANES = 4;
|
||||
parameter RX_NUM_OF_LANES = 4;
|
||||
|
||||
localparam TX_LANECNT = (TX_NUM_OF_LANES == 0) ? 1 : TX_NUM_OF_LANES;
|
||||
localparam RX_LANECNT = (RX_NUM_OF_LANES == 0) ? 1 : RX_NUM_OF_LANES;
|
||||
|
||||
output rst;
|
||||
|
||||
// receive interface
|
||||
|
||||
input rx_clk;
|
||||
output rx_rstn;
|
||||
input rx_ext_sysref_in;
|
||||
output rx_ext_sysref_out;
|
||||
output rx_sync;
|
||||
output [((RX_LANECNT* 1)-1):0] rx_sof;
|
||||
output [((RX_LANECNT*32)-1):0] rx_data;
|
||||
input [((RX_LANECNT* 1)-1):0] rx_ready;
|
||||
output rx_ip_sysref;
|
||||
input rx_ip_sync;
|
||||
input [ 3:0] rx_ip_sof;
|
||||
input rx_ip_valid;
|
||||
input [((RX_LANECNT*32)-1):0] rx_ip_data;
|
||||
output rx_ip_ready;
|
||||
|
||||
// transmit interface
|
||||
|
||||
input tx_clk;
|
||||
output tx_rstn;
|
||||
input tx_ext_sysref_in;
|
||||
output tx_ext_sysref_out;
|
||||
input tx_sync;
|
||||
input [((TX_LANECNT*32)-1):0] tx_data;
|
||||
input [((TX_LANECNT* 1)-1):0] tx_ready;
|
||||
output tx_ip_sysref;
|
||||
output tx_ip_sync;
|
||||
output tx_ip_valid;
|
||||
output [((TX_LANECNT*32)-1):0] tx_ip_data;
|
||||
input tx_ip_ready;
|
||||
|
||||
// axi interface
|
||||
|
||||
input s_axi_aclk;
|
||||
input s_axi_aresetn;
|
||||
input s_axi_awvalid;
|
||||
input [ 31:0] s_axi_awaddr;
|
||||
input [ 2:0] s_axi_awprot;
|
||||
output s_axi_awready;
|
||||
input s_axi_wvalid;
|
||||
input [ 31:0] s_axi_wdata;
|
||||
input [ 3:0] s_axi_wstrb;
|
||||
output s_axi_wready;
|
||||
output s_axi_bvalid;
|
||||
output [ 1:0] s_axi_bresp;
|
||||
input s_axi_bready;
|
||||
input s_axi_arvalid;
|
||||
input [ 31:0] s_axi_araddr;
|
||||
input [ 2:0] s_axi_arprot;
|
||||
output s_axi_arready;
|
||||
output s_axi_rvalid;
|
||||
output [ 31:0] s_axi_rdata;
|
||||
output [ 1:0] s_axi_rresp;
|
||||
input s_axi_rready;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire up_rstn;
|
||||
wire up_clk;
|
||||
wire [ 7:0] status_s;
|
||||
wire [ 3:0] rx_ip_sof_s;
|
||||
wire [((RX_LANECNT*32)-1):0] rx_ip_data_s;
|
||||
wire [ 7:0] rx_status_s;
|
||||
wire [ 7:0] tx_status_s;
|
||||
wire up_wreq_s;
|
||||
wire [ 13:0] up_waddr_s;
|
||||
wire [ 31:0] up_wdata_s;
|
||||
wire up_wack_s;
|
||||
wire up_rreq_s;
|
||||
wire [ 13:0] up_raddr_s;
|
||||
wire [ 31:0] up_rdata_s;
|
||||
wire up_rack_s;
|
||||
|
||||
// variables
|
||||
|
||||
genvar n;
|
||||
|
||||
// assignments
|
||||
|
||||
assign status_s = 8'hff;
|
||||
assign up_rstn = s_axi_aresetn;
|
||||
assign up_clk = s_axi_aclk;
|
||||
|
||||
assign rx_ip_ready = 1'b1;
|
||||
assign rx_ip_sysref = rx_ext_sysref_out;
|
||||
|
||||
assign rx_ip_sof_s[3] = rx_ip_sof[0];
|
||||
assign rx_ip_sof_s[2] = rx_ip_sof[1];
|
||||
assign rx_ip_sof_s[1] = rx_ip_sof[2];
|
||||
assign rx_ip_sof_s[0] = rx_ip_sof[3];
|
||||
|
||||
generate
|
||||
for (n = 0; n < RX_LANECNT; n = n + 1) begin: g_rx_swap
|
||||
assign rx_ip_data_s[((n*32) + 31):((n*32) + 24)] = rx_ip_data[((n*32) + 7):((n*32) + 0)];
|
||||
assign rx_ip_data_s[((n*32) + 23):((n*32) + 16)] = rx_ip_data[((n*32) + 15):((n*32) + 8)];
|
||||
assign rx_ip_data_s[((n*32) + 15):((n*32) + 8)] = rx_ip_data[((n*32) + 23):((n*32) + 16)];
|
||||
assign rx_ip_data_s[((n*32) + 7):((n*32) + 0)] = rx_ip_data[((n*32) + 31):((n*32) + 24)];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate
|
||||
if (RX_LANECNT < 8) begin
|
||||
assign rx_status_s[7:RX_LANECNT] = status_s[7:RX_LANECNT];
|
||||
assign rx_status_s[(RX_LANECNT-1):0] = rx_ready;
|
||||
end else begin
|
||||
assign rx_status_s = rx_ready[7:0];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate
|
||||
for (n = 0; n < RX_LANECNT; n = n + 1) begin: g_rx_align
|
||||
ad_jesd_align i_jesd_align (
|
||||
.rx_clk (rx_clk),
|
||||
.rx_ip_sof (rx_ip_sof_s),
|
||||
.rx_ip_data (rx_ip_data_s[n*32+31:n*32]),
|
||||
.rx_sof (rx_sof[n]),
|
||||
.rx_data (rx_data[n*32+31:n*32]));
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign tx_ip_valid = 1'b1;
|
||||
assign tx_ip_sysref = tx_ext_sysref_out;
|
||||
|
||||
generate
|
||||
for (n = 0; n < TX_LANECNT; n = n + 1) begin: g_tx_swap
|
||||
assign tx_ip_data[((n*32) + 31):((n*32) + 24)] = tx_data[((n*32) + 7):((n*32) + 0)];
|
||||
assign tx_ip_data[((n*32) + 23):((n*32) + 16)] = tx_data[((n*32) + 15):((n*32) + 8)];
|
||||
assign tx_ip_data[((n*32) + 15):((n*32) + 8)] = tx_data[((n*32) + 23):((n*32) + 16)];
|
||||
assign tx_ip_data[((n*32) + 7):((n*32) + 0)] = tx_data[((n*32) + 31):((n*32) + 24)];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate
|
||||
if (TX_LANECNT < 8) begin
|
||||
assign tx_status_s[7:TX_LANECNT] = status_s[7:TX_LANECNT];
|
||||
assign tx_status_s[(TX_LANECNT-1):0] = tx_ready;
|
||||
end else begin
|
||||
assign tx_status_s = tx_ready[7:0];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// processor
|
||||
|
||||
up_xcvr #(
|
||||
.ID(ID),
|
||||
.DEVICE_TYPE(DEVICE_TYPE))
|
||||
i_up_xcvr (
|
||||
.rst (rst),
|
||||
.rx_clk (rx_clk),
|
||||
.rx_rstn (rx_rstn),
|
||||
.rx_ext_sysref (rx_ext_sysref_in),
|
||||
.rx_sysref (rx_ext_sysref_out),
|
||||
.rx_ip_sync (rx_ip_sync),
|
||||
.rx_sync (rx_sync),
|
||||
.rx_status (rx_status_s),
|
||||
.tx_clk (tx_clk),
|
||||
.tx_rstn (tx_rstn),
|
||||
.tx_ext_sysref (tx_ext_sysref_in),
|
||||
.tx_sysref (tx_ext_sysref_out),
|
||||
.tx_sync (tx_sync),
|
||||
.tx_ip_sync (tx_ip_sync),
|
||||
.tx_status (tx_status_s),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq_s),
|
||||
.up_waddr (up_waddr_s),
|
||||
.up_wdata (up_wdata_s),
|
||||
.up_wack (up_wack_s),
|
||||
.up_rreq (up_rreq_s),
|
||||
.up_raddr (up_raddr_s),
|
||||
.up_rdata (up_rdata_s),
|
||||
.up_rack (up_rack_s));
|
||||
|
||||
// axi interface
|
||||
|
||||
up_axi i_up_axi (
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_axi_awvalid (s_axi_awvalid),
|
||||
.up_axi_awaddr (s_axi_awaddr),
|
||||
.up_axi_awready (s_axi_awready),
|
||||
.up_axi_wvalid (s_axi_wvalid),
|
||||
.up_axi_wdata (s_axi_wdata),
|
||||
.up_axi_wstrb (s_axi_wstrb),
|
||||
.up_axi_wready (s_axi_wready),
|
||||
.up_axi_bvalid (s_axi_bvalid),
|
||||
.up_axi_bresp (s_axi_bresp),
|
||||
.up_axi_bready (s_axi_bready),
|
||||
.up_axi_arvalid (s_axi_arvalid),
|
||||
.up_axi_araddr (s_axi_araddr),
|
||||
.up_axi_arready (s_axi_arready),
|
||||
.up_axi_rvalid (s_axi_rvalid),
|
||||
.up_axi_rresp (s_axi_rresp),
|
||||
.up_axi_rdata (s_axi_rdata),
|
||||
.up_axi_rready (s_axi_rready),
|
||||
.up_wreq (up_wreq_s),
|
||||
.up_waddr (up_waddr_s),
|
||||
.up_wdata (up_wdata_s),
|
||||
.up_wack (up_wack_s),
|
||||
.up_rreq (up_rreq_s),
|
||||
.up_raddr (up_raddr_s),
|
||||
.up_rdata (up_rdata_s),
|
||||
.up_rack (up_rack_s));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
|
@ -1,12 +0,0 @@
|
|||
|
||||
set_false_path -from [get_registers *up_xcvr:i_up_xcvr|up_rx_sysref_sel*] -to [get_registers *up_xcvr:i_up_xcvr|rx_sysref_sel_m1*]
|
||||
set_false_path -from [get_registers *up_xcvr:i_up_xcvr|up_rx_sysref*] -to [get_registers *up_xcvr:i_up_xcvr|rx_up_sysref_m1*]
|
||||
set_false_path -from [get_registers *up_xcvr:i_up_xcvr|up_rx_sync*] -to [get_registers *up_xcvr:i_up_xcvr|rx_up_sync_m1*]
|
||||
set_false_path -from [get_registers *up_xcvr:i_up_xcvr|up_tx_sysref_sel*] -to [get_registers *up_xcvr:i_up_xcvr|tx_sysref_sel_m1*]
|
||||
set_false_path -from [get_registers *up_xcvr:i_up_xcvr|up_tx_sysref*] -to [get_registers *up_xcvr:i_up_xcvr|tx_up_sysref_m1*]
|
||||
set_false_path -from [get_registers *up_xcvr:i_up_xcvr|up_tx_sync*] -to [get_registers *up_xcvr:i_up_xcvr|tx_up_sync_m1*]
|
||||
set_false_path -from [get_registers *up_xcvr:i_up_xcvr|rx_sync*] -to [get_registers *up_xcvr:i_up_xcvr|up_rx_status_m1*]
|
||||
set_false_path -from [get_registers *up_xcvr:i_up_xcvr|tx_ip_sync*] -to [get_registers *up_xcvr:i_up_xcvr|up_tx_status_m1*]
|
||||
set_false_path -from [get_registers *up_xcvr:i_up_xcvr|up_rx_reset*] -to [get_registers *up_xcvr:i_up_xcvr|ad_rst:i_rx_rst_reg|ad_rst_sync_m1*]
|
||||
set_false_path -from [get_registers *up_xcvr:i_up_xcvr|up_tx_reset*] -to [get_registers *up_xcvr:i_up_xcvr|ad_rst:i_tx_rst_reg|ad_rst_sync_m1*]
|
||||
|
||||
|
|
@ -1,142 +0,0 @@
|
|||
|
||||
|
||||
package require -exact qsys 13.0
|
||||
source ../scripts/adi_env.tcl
|
||||
source ../scripts/adi_ip_alt.tcl
|
||||
|
||||
set_module_property NAME axi_jesd_xcvr
|
||||
set_module_property DESCRIPTION "AXI JESD XCVR Interface"
|
||||
set_module_property VERSION 1.0
|
||||
set_module_property GROUP "Analog Devices"
|
||||
set_module_property DISPLAY_NAME axi_jesd_xcvr
|
||||
set_module_property ELABORATION_CALLBACK p_axi_jesd_xcvr
|
||||
|
||||
# files
|
||||
|
||||
add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
|
||||
set_fileset_property quartus_synth TOP_LEVEL axi_jesd_xcvr
|
||||
add_fileset_file ad_rst.v VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v
|
||||
add_fileset_file ad_jesd_align.v VERILOG PATH $ad_hdl_dir/library/common/ad_jesd_align.v
|
||||
add_fileset_file up_axi.v VERILOG PATH $ad_hdl_dir/library/common/up_axi.v
|
||||
add_fileset_file up_xcvr.v VERILOG PATH $ad_hdl_dir/library/common/up_xcvr.v
|
||||
add_fileset_file axi_jesd_xcvr.v VERILOG PATH axi_jesd_xcvr.v TOP_LEVEL_FILE
|
||||
add_fileset_file axi_jesd_xcvr_constr.sdc SDC PATH axi_jesd_xcvr_constr.sdc
|
||||
|
||||
# parameters
|
||||
|
||||
add_parameter ID INTEGER 0
|
||||
set_parameter_property ID DEFAULT_VALUE 0
|
||||
set_parameter_property ID DISPLAY_NAME ID
|
||||
set_parameter_property ID TYPE INTEGER
|
||||
set_parameter_property ID UNITS None
|
||||
set_parameter_property ID HDL_PARAMETER true
|
||||
|
||||
add_parameter DEVICE_TYPE INTEGER 0
|
||||
set_parameter_property DEVICE_TYPE DEFAULT_VALUE 0
|
||||
set_parameter_property DEVICE_TYPE DISPLAY_NAME DEVICE_TYPE
|
||||
set_parameter_property DEVICE_TYPE TYPE INTEGER
|
||||
set_parameter_property DEVICE_TYPE UNITS None
|
||||
set_parameter_property DEVICE_TYPE HDL_PARAMETER true
|
||||
|
||||
add_parameter TX_NUM_OF_LANES INTEGER 0
|
||||
set_parameter_property TX_NUM_OF_LANES DEFAULT_VALUE 4
|
||||
set_parameter_property TX_NUM_OF_LANES DISPLAY_NAME TX_NUM_OF_LANES
|
||||
set_parameter_property TX_NUM_OF_LANES TYPE INTEGER
|
||||
set_parameter_property TX_NUM_OF_LANES UNITS None
|
||||
set_parameter_property TX_NUM_OF_LANES HDL_PARAMETER true
|
||||
|
||||
add_parameter RX_NUM_OF_LANES INTEGER 0
|
||||
set_parameter_property RX_NUM_OF_LANES DEFAULT_VALUE 4
|
||||
set_parameter_property RX_NUM_OF_LANES DISPLAY_NAME RX_NUM_OF_LANES
|
||||
set_parameter_property RX_NUM_OF_LANES TYPE INTEGER
|
||||
set_parameter_property RX_NUM_OF_LANES UNITS None
|
||||
set_parameter_property RX_NUM_OF_LANES HDL_PARAMETER true
|
||||
|
||||
# axi4 slave
|
||||
|
||||
add_interface s_axi_clock clock end
|
||||
add_interface_port s_axi_clock s_axi_aclk clk Input 1
|
||||
|
||||
add_interface s_axi_reset reset end
|
||||
set_interface_property s_axi_reset associatedClock s_axi_clock
|
||||
add_interface_port s_axi_reset s_axi_aresetn reset_n Input 1
|
||||
|
||||
add_interface s_axi axi4lite end
|
||||
set_interface_property s_axi associatedClock s_axi_clock
|
||||
set_interface_property s_axi associatedReset s_axi_reset
|
||||
add_interface_port s_axi s_axi_awvalid awvalid Input 1
|
||||
add_interface_port s_axi s_axi_awaddr awaddr Input 16
|
||||
add_interface_port s_axi s_axi_awprot awprot Input 3
|
||||
add_interface_port s_axi s_axi_awready awready Output 1
|
||||
add_interface_port s_axi s_axi_wvalid wvalid Input 1
|
||||
add_interface_port s_axi s_axi_wdata wdata Input 32
|
||||
add_interface_port s_axi s_axi_wstrb wstrb Input 4
|
||||
add_interface_port s_axi s_axi_wready wready Output 1
|
||||
add_interface_port s_axi s_axi_bvalid bvalid Output 1
|
||||
add_interface_port s_axi s_axi_bresp bresp Output 2
|
||||
add_interface_port s_axi s_axi_bready bready Input 1
|
||||
add_interface_port s_axi s_axi_arvalid arvalid Input 1
|
||||
add_interface_port s_axi s_axi_araddr araddr Input 16
|
||||
add_interface_port s_axi s_axi_arprot arprot Input 3
|
||||
add_interface_port s_axi s_axi_arready arready Output 1
|
||||
add_interface_port s_axi s_axi_rvalid rvalid Output 1
|
||||
add_interface_port s_axi s_axi_rresp rresp Output 2
|
||||
add_interface_port s_axi s_axi_rdata rdata Output 32
|
||||
add_interface_port s_axi s_axi_rready rready Input 1
|
||||
|
||||
# transceiver interface
|
||||
|
||||
ad_alt_intf reset rst output 1 s_axi_clock s_axi_reset
|
||||
|
||||
proc p_axi_jesd_xcvr {} {
|
||||
|
||||
set p_num_of_rx_lanes [get_parameter_value "RX_NUM_OF_LANES"]
|
||||
set p_num_of_tx_lanes [get_parameter_value "TX_NUM_OF_LANES"]
|
||||
|
||||
if {$p_num_of_rx_lanes > 0} {
|
||||
|
||||
ad_alt_intf clock rx_clk input 1
|
||||
ad_alt_intf reset-n rx_rstn output 1 if_rx_clk s_axi_reset
|
||||
ad_alt_intf signal rx_ext_sysref_in input 1
|
||||
ad_alt_intf signal rx_ext_sysref_out output 1
|
||||
ad_alt_intf signal rx_sync output 1
|
||||
ad_alt_intf signal rx_sof output $p_num_of_rx_lanes
|
||||
ad_alt_intf signal rx_data output $p_num_of_rx_lanes*32 data
|
||||
ad_alt_intf signal rx_ready input $p_num_of_rx_lanes rx_ready
|
||||
ad_alt_intf signal rx_ip_sysref output 1 export
|
||||
ad_alt_intf signal rx_ip_sync input 1 export
|
||||
ad_alt_intf signal rx_ip_sof input 4 export
|
||||
|
||||
add_interface if_rx_ip_avl avalon_streaming sink
|
||||
add_interface_port if_rx_ip_avl rx_ip_data data input $p_num_of_rx_lanes*32
|
||||
add_interface_port if_rx_ip_avl rx_ip_valid valid input 1
|
||||
add_interface_port if_rx_ip_avl rx_ip_ready ready output 1
|
||||
|
||||
set_interface_property if_rx_ip_avl associatedClock if_rx_clk
|
||||
set_interface_property if_rx_ip_avl associatedReset if_rx_rstn
|
||||
set_interface_property if_rx_ip_avl dataBitsPerSymbol [expr ($p_num_of_rx_lanes*32)]
|
||||
}
|
||||
|
||||
if {$p_num_of_tx_lanes > 0} {
|
||||
|
||||
ad_alt_intf clock tx_clk input 1
|
||||
ad_alt_intf reset-n tx_rstn output 1 if_tx_clk s_axi_reset
|
||||
ad_alt_intf signal tx_ext_sysref_in input 1
|
||||
ad_alt_intf signal tx_ext_sysref_out output 1
|
||||
ad_alt_intf signal tx_sync input 1
|
||||
ad_alt_intf signal tx_data input $p_num_of_tx_lanes*32 data
|
||||
ad_alt_intf signal tx_ready input $p_num_of_tx_lanes tx_ready
|
||||
ad_alt_intf signal tx_ip_sysref output 1 export
|
||||
ad_alt_intf signal tx_ip_sync output 1 export
|
||||
|
||||
add_interface if_tx_ip_avl avalon_streaming source
|
||||
add_interface_port if_tx_ip_avl tx_ip_data data output $p_num_of_tx_lanes*32
|
||||
add_interface_port if_tx_ip_avl tx_ip_valid valid output 1
|
||||
add_interface_port if_tx_ip_avl tx_ip_ready ready input 1
|
||||
|
||||
set_interface_property if_tx_ip_avl associatedClock if_tx_clk
|
||||
set_interface_property if_tx_ip_avl associatedReset if_tx_rstn
|
||||
set_interface_property if_tx_ip_avl dataBitsPerSymbol [expr ($p_num_of_tx_lanes*32)]
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1,344 +0,0 @@
|
|||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2011(c) Analog Devices, Inc.
|
||||
//
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without modification,
|
||||
// are permitted provided that the following conditions are met:
|
||||
// - Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// - Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in
|
||||
// the documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
// - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
// contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
// - The use of this software may or may not infringe the patent rights
|
||||
// of one or more patent holders. This license does not release you
|
||||
// from the requirement that you obtain separate licenses from these
|
||||
// patent holders to use this software.
|
||||
// - Use of the software either in source or binary form, must be run
|
||||
// on or directly connected to an Analog Devices Inc. component.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
|
||||
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
|
||||
// PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
//
|
||||
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
|
||||
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module up_xcvr (
|
||||
|
||||
// common reset
|
||||
|
||||
rst,
|
||||
|
||||
// receive interface
|
||||
|
||||
rx_clk,
|
||||
rx_rstn,
|
||||
rx_ext_sysref,
|
||||
rx_sysref,
|
||||
rx_ip_sync,
|
||||
rx_sync,
|
||||
rx_status,
|
||||
|
||||
// transmit interface
|
||||
|
||||
tx_clk,
|
||||
tx_rstn,
|
||||
tx_ext_sysref,
|
||||
tx_sysref,
|
||||
tx_sync,
|
||||
tx_ip_sync,
|
||||
tx_status,
|
||||
|
||||
// bus interface
|
||||
|
||||
up_rstn,
|
||||
up_clk,
|
||||
up_wreq,
|
||||
up_waddr,
|
||||
up_wdata,
|
||||
up_wack,
|
||||
up_rreq,
|
||||
up_raddr,
|
||||
up_rdata,
|
||||
up_rack);
|
||||
|
||||
// parameters
|
||||
|
||||
localparam PCORE_VERSION = 32'h00060162;
|
||||
parameter ID = 0;
|
||||
parameter DEVICE_TYPE = 0;
|
||||
|
||||
// common reset
|
||||
|
||||
output rst;
|
||||
|
||||
// receive interface
|
||||
|
||||
input rx_clk;
|
||||
output rx_rstn;
|
||||
input rx_ext_sysref;
|
||||
output rx_sysref;
|
||||
input rx_ip_sync;
|
||||
output rx_sync;
|
||||
input [ 7:0] rx_status;
|
||||
|
||||
// transmit interface
|
||||
|
||||
input tx_clk;
|
||||
output tx_rstn;
|
||||
input tx_ext_sysref;
|
||||
output tx_sysref;
|
||||
input tx_sync;
|
||||
output tx_ip_sync;
|
||||
input [ 7:0] tx_status;
|
||||
|
||||
// bus interface
|
||||
|
||||
input up_rstn;
|
||||
input up_clk;
|
||||
input up_wreq;
|
||||
input [13:0] up_waddr;
|
||||
input [31:0] up_wdata;
|
||||
output up_wack;
|
||||
input up_rreq;
|
||||
input [13:0] up_raddr;
|
||||
output [31:0] up_rdata;
|
||||
output up_rack;
|
||||
|
||||
// internal registers
|
||||
|
||||
reg up_reset = 'd1;
|
||||
reg up_rx_reset = 'd1;
|
||||
reg up_tx_reset = 'd1;
|
||||
reg up_wack = 'd0;
|
||||
reg [31:0] up_scratch = 'd0;
|
||||
reg up_resetn = 'd0;
|
||||
reg up_rx_sysref_sel = 'd0;
|
||||
reg up_rx_sysref = 'd0;
|
||||
reg up_rx_sync = 'd0;
|
||||
reg up_rx_resetn = 'd0;
|
||||
reg up_tx_sysref_sel = 'd0;
|
||||
reg up_tx_sysref = 'd0;
|
||||
reg up_tx_sync = 'd0;
|
||||
reg up_tx_resetn = 'd0;
|
||||
reg up_rack = 'd0;
|
||||
reg [31:0] up_rdata = 'd0;
|
||||
reg rx_rstn = 'd0;
|
||||
reg rx_sysref_sel_m1 = 'd0;
|
||||
reg rx_sysref_sel = 'd0;
|
||||
reg rx_up_sysref_m1 = 'd0;
|
||||
reg rx_up_sysref = 'd0;
|
||||
reg rx_sysref = 'd0;
|
||||
reg rx_up_sync_m1 = 'd0;
|
||||
reg rx_up_sync = 'd0;
|
||||
reg rx_sync = 'd0;
|
||||
reg tx_rstn = 'd0;
|
||||
reg tx_sysref_sel_m1 = 'd0;
|
||||
reg tx_sysref_sel = 'd0;
|
||||
reg tx_up_sysref_m1 = 'd0;
|
||||
reg tx_up_sysref = 'd0;
|
||||
reg tx_sysref = 'd0;
|
||||
reg tx_up_sync_m1 = 'd0;
|
||||
reg tx_up_sync = 'd0;
|
||||
reg tx_ip_sync = 'd0;
|
||||
reg [ 8:0] up_rx_status_m1 = 'd0;
|
||||
reg [ 8:0] up_rx_status = 'd0;
|
||||
reg [ 8:0] up_tx_status_m1 = 'd0;
|
||||
reg [ 8:0] up_tx_status = 'd0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire rx_rst;
|
||||
wire tx_rst;
|
||||
wire up_wreq_s;
|
||||
wire up_rreq_s;
|
||||
|
||||
// decode block select
|
||||
|
||||
assign up_wreq_s = (up_waddr[13:8] == 6'h00) ? up_wreq : 1'b0;
|
||||
assign up_rreq_s = (up_raddr[13:8] == 6'h00) ? up_rreq : 1'b0;
|
||||
|
||||
// processor write interface
|
||||
|
||||
always @(negedge up_rstn or posedge up_clk) begin
|
||||
if (up_rstn == 0) begin
|
||||
up_reset <= 1'b1;
|
||||
up_rx_reset <= 1'b1;
|
||||
up_tx_reset <= 1'b1;
|
||||
up_wack <= 'd0;
|
||||
up_scratch <= 'd0;
|
||||
up_resetn <= 'd0;
|
||||
up_rx_sysref_sel <= 'd0;
|
||||
up_rx_sysref <= 'd0;
|
||||
up_rx_sync <= 'd0;
|
||||
up_rx_resetn <= 'd0;
|
||||
up_tx_sysref_sel <= 'd0;
|
||||
up_tx_sysref <= 'd0;
|
||||
up_tx_sync <= 'd0;
|
||||
up_tx_resetn <= 'd0;
|
||||
end else begin
|
||||
up_reset <= ~up_resetn;
|
||||
up_rx_reset <= ~(up_resetn & up_rx_resetn);
|
||||
up_tx_reset <= ~(up_resetn & up_tx_resetn);
|
||||
up_wack <= up_wreq_s;
|
||||
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
|
||||
up_scratch <= up_wdata;
|
||||
end
|
||||
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h03)) begin
|
||||
up_resetn <= up_wdata[0];
|
||||
end
|
||||
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin
|
||||
up_rx_sysref_sel <= up_wdata[1];
|
||||
up_rx_sysref <= up_wdata[0];
|
||||
end
|
||||
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
|
||||
up_rx_sync <= up_wdata[0];
|
||||
end
|
||||
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h13)) begin
|
||||
up_rx_resetn <= up_wdata[0];
|
||||
end
|
||||
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h20)) begin
|
||||
up_tx_sysref_sel <= up_wdata[1];
|
||||
up_tx_sysref <= up_wdata[0];
|
||||
end
|
||||
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h21)) begin
|
||||
up_tx_sync <= up_wdata[0];
|
||||
end
|
||||
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h23)) begin
|
||||
up_tx_resetn <= up_wdata[0];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// processor read interface
|
||||
|
||||
always @(negedge up_rstn or posedge up_clk) begin
|
||||
if (up_rstn == 0) begin
|
||||
up_rack <= 'd0;
|
||||
up_rdata <= 'd0;
|
||||
end else begin
|
||||
up_rack <= up_rreq_s;
|
||||
if (up_rreq_s == 1'b1) begin
|
||||
case (up_raddr[7:0])
|
||||
8'h00: up_rdata <= PCORE_VERSION;
|
||||
8'h01: up_rdata <= ID;
|
||||
8'h02: up_rdata <= up_scratch;
|
||||
8'h03: up_rdata <= {31'd0, up_resetn};
|
||||
8'h10: up_rdata <= {30'd0, up_rx_sysref_sel, up_rx_sysref};
|
||||
8'h11: up_rdata <= {31'd0, up_rx_sync};
|
||||
8'h12: up_rdata <= {23'd0, up_rx_status};
|
||||
8'h13: up_rdata <= {31'd0, up_rx_resetn};
|
||||
8'h20: up_rdata <= {30'd0, up_tx_sysref_sel, up_tx_sysref};
|
||||
8'h21: up_rdata <= {31'd0, up_tx_sync};
|
||||
8'h22: up_rdata <= {23'd0, up_tx_status};
|
||||
8'h23: up_rdata <= {31'd0, up_tx_resetn};
|
||||
8'h30: up_rdata <= DEVICE_TYPE;
|
||||
default: up_rdata <= 0;
|
||||
endcase
|
||||
end else begin
|
||||
up_rdata <= 32'd0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// resets
|
||||
|
||||
assign rst = up_reset;
|
||||
|
||||
ad_rst i_rx_rst_reg (.preset(up_rx_reset), .clk(rx_clk), .rst(rx_rst));
|
||||
ad_rst i_tx_rst_reg (.preset(up_tx_reset), .clk(tx_clk), .rst(tx_rst));
|
||||
|
||||
// rx sysref & sync
|
||||
|
||||
always @(posedge rx_clk or posedge rx_rst) begin
|
||||
if (rx_rst == 1'b1) begin
|
||||
rx_rstn <= 'd0;
|
||||
rx_sysref_sel_m1 <= 'd0;
|
||||
rx_sysref_sel <= 'd0;
|
||||
rx_up_sysref_m1 <= 'd0;
|
||||
rx_up_sysref <= 'd0;
|
||||
rx_sysref <= 'd0;
|
||||
rx_up_sync_m1 <= 'd0;
|
||||
rx_up_sync <= 'd0;
|
||||
rx_sync <= 'd0;
|
||||
end else begin
|
||||
rx_rstn <= 1'd1;
|
||||
rx_sysref_sel_m1 <= up_rx_sysref_sel;
|
||||
rx_sysref_sel <= rx_sysref_sel_m1;
|
||||
rx_up_sysref_m1 <= up_rx_sysref;
|
||||
rx_up_sysref <= rx_up_sysref_m1;
|
||||
if (rx_sysref_sel == 1'b1) begin
|
||||
rx_sysref <= rx_ext_sysref;
|
||||
end else begin
|
||||
rx_sysref <= rx_up_sysref;
|
||||
end
|
||||
rx_up_sync_m1 <= up_rx_sync;
|
||||
rx_up_sync <= rx_up_sync_m1;
|
||||
rx_sync <= rx_up_sync & rx_ip_sync;
|
||||
end
|
||||
end
|
||||
|
||||
// tx sysref & sync
|
||||
|
||||
always @(posedge tx_clk or posedge tx_rst) begin
|
||||
if (tx_rst == 1'b1) begin
|
||||
tx_rstn <= 'd0;
|
||||
tx_sysref_sel_m1 <= 'd0;
|
||||
tx_sysref_sel <= 'd0;
|
||||
tx_up_sysref_m1 <= 'd0;
|
||||
tx_up_sysref <= 'd0;
|
||||
tx_sysref <= 'd0;
|
||||
tx_up_sync_m1 <= 'd0;
|
||||
tx_up_sync <= 'd0;
|
||||
tx_ip_sync <= 'd0;
|
||||
end else begin
|
||||
tx_rstn <= 1'd1;
|
||||
tx_sysref_sel_m1 <= up_tx_sysref_sel;
|
||||
tx_sysref_sel <= tx_sysref_sel_m1;
|
||||
tx_up_sysref_m1 <= up_tx_sysref;
|
||||
tx_up_sysref <= tx_up_sysref_m1;
|
||||
if (tx_sysref_sel == 1'b1) begin
|
||||
tx_sysref <= tx_ext_sysref;
|
||||
end else begin
|
||||
tx_sysref <= tx_up_sysref;
|
||||
end
|
||||
tx_up_sync_m1 <= up_tx_sync;
|
||||
tx_up_sync <= tx_up_sync_m1;
|
||||
tx_ip_sync <= tx_up_sync & tx_sync;
|
||||
end
|
||||
end
|
||||
|
||||
// status
|
||||
|
||||
always @(negedge up_rstn or posedge up_clk) begin
|
||||
if (up_rstn == 0) begin
|
||||
up_rx_status_m1 <= 'd0;
|
||||
up_rx_status <= 'd0;
|
||||
up_tx_status_m1 <= 'd0;
|
||||
up_tx_status <= 'd0;
|
||||
end else begin
|
||||
up_rx_status_m1 <= {rx_sync, rx_status};
|
||||
up_rx_status <= up_rx_status_m1;
|
||||
up_tx_status_m1 <= {tx_ip_sync, tx_status};
|
||||
up_tx_status <= up_tx_status_m1;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
Loading…
Reference in New Issue