zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

motcon2_fmc: Updated constraint files and fixed reset connection

main
Adrian Costina 2015-02-24 12:14:04 +02:00
parent 9c04491e1b
commit 12d8461159
2 changed files with 9 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
projects/motcon2_fmc/common/motcon2_fmc_bd.tcl
View File

@ -555,8 +555,9 @@
# ethernet # ethernet
connect_bd_net -net sys_200m_clk [get_bd_ports refclk] [get_bd_pins sys_ps7/FCLK_CLK1] connect_bd_net -net sys_200m_clk [get_bd_ports refclk] [get_bd_pins sys_ps7/FCLK_CLK1]
connect_bd_net -net sys_rstgen_peripheral_reset [get_bd_ports refclk_rst] connect_bd_net -net sys_rstgen_peripheral_reset [get_bd_ports refclk_rst] [get_bd_pins sys_rstgen/peripheral_reset]
connect_bd_net -net sys_100m_resetn [get_bd_ports eth_phy_rst_n] connect_bd_net -net sys_100m_resetn [get_bd_ports eth_phy_rst_n]
connect_bd_net [get_bd_pins /sys_ps7/ENET0_MDIO_MDC] [get_bd_ports eth_mdio_mdc] connect_bd_net [get_bd_pins /sys_ps7/ENET0_MDIO_MDC] [get_bd_ports eth_mdio_mdc]
connect_bd_net [get_bd_pins /sys_ps7/ENET0_MDIO_O] [get_bd_ports eth_mdio_o] connect_bd_net [get_bd_pins /sys_ps7/ENET0_MDIO_O] [get_bd_ports eth_mdio_o]
@ -565,7 +566,8 @@
# phy 1 # phy 1
connect_bd_intf_net -intf_net sys_ps7_GMII_ETHERNET_1 [get_bd_intf_pins gmii_to_rgmii_eth1/gmii] [get_bd_intf_pins sys_ps7/GMII_ETHERNET_0] connect_bd_intf_net -intf_net sys_ps7_GMII_ETHERNET_1 [get_bd_intf_pins gmii_to_rgmii_eth1/gmii] [get_bd_intf_pins sys_ps7/GMII_ETHERNET_0]
connect_bd_intf_net -intf_net gmii_to_rgmii_eth1_rgmii [get_bd_intf_ports eth1_rgmii] [get_bd_intf_pins gmii_to_rgmii_eth1/rgmii] connect_bd_intf_net -intf_net gmii_to_rgmii_eth1_rgmii [get_bd_intf_ports eth1_rgmii] [get_bd_intf_pins gmii_to_rgmii_eth1/rgmii]
connect_bd_net -net sys_rstgen_peripheral_reset [get_bd_pins gmii_to_rgmii_eth1/reset] connect_bd_net -net sys_rstgen_peripheral_reset [get_bd_pins gmii_to_rgmii_eth1/reset] [get_bd_pins sys_rstgen/peripheral_reset]
connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins gmii_to_rgmii_eth1/clk_20m] [get_bd_pins sys_audio_clkgen/clk_out4] connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins gmii_to_rgmii_eth1/clk_20m] [get_bd_pins sys_audio_clkgen/clk_out4]
connect_bd_net -net sys_audio_clkgen_clk_out3 [get_bd_pins gmii_to_rgmii_eth1/clk_25m] [get_bd_pins sys_audio_clkgen/clk_out3] connect_bd_net -net sys_audio_clkgen_clk_out3 [get_bd_pins gmii_to_rgmii_eth1/clk_25m] [get_bd_pins sys_audio_clkgen/clk_out3]
connect_bd_net -net sys_audio_clkgen_clk_out4 [get_bd_pins gmii_to_rgmii_eth1/clk_125m] [get_bd_pins sys_audio_clkgen/clk_out2] connect_bd_net -net sys_audio_clkgen_clk_out4 [get_bd_pins gmii_to_rgmii_eth1/clk_125m] [get_bd_pins sys_audio_clkgen/clk_out2]
@ -575,7 +577,7 @@
# phy 2 # phy 2
connect_bd_intf_net -intf_net sys_ps7_GMII_ETHERNET_2 [get_bd_intf_pins gmii_to_rgmii_eth2/gmii] [get_bd_intf_pins sys_ps7/GMII_ETHERNET_1] connect_bd_intf_net -intf_net sys_ps7_GMII_ETHERNET_2 [get_bd_intf_pins gmii_to_rgmii_eth2/gmii] [get_bd_intf_pins sys_ps7/GMII_ETHERNET_1]
connect_bd_intf_net -intf_net gmii_to_rgmii_eth2_rgmii [get_bd_intf_ports eth2_rgmii] [get_bd_intf_pins gmii_to_rgmii_eth2/rgmii] connect_bd_intf_net -intf_net gmii_to_rgmii_eth2_rgmii [get_bd_intf_ports eth2_rgmii] [get_bd_intf_pins gmii_to_rgmii_eth2/rgmii]
connect_bd_net -net sys_rstgen_peripheral_reset [get_bd_pins gmii_to_rgmii_eth2/reset] connect_bd_net -net sys_rstgen_peripheral_reset [get_bd_pins gmii_to_rgmii_eth2/reset] [get_bd_pins sys_rstgen/peripheral_reset]
connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins gmii_to_rgmii_eth2/clk_20m] [get_bd_pins sys_audio_clkgen/clk_out4] connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins gmii_to_rgmii_eth2/clk_20m] [get_bd_pins sys_audio_clkgen/clk_out4]
connect_bd_net -net sys_audio_clkgen_clk_out3 [get_bd_pins gmii_to_rgmii_eth2/clk_25m] [get_bd_pins sys_audio_clkgen/clk_out3] connect_bd_net -net sys_audio_clkgen_clk_out3 [get_bd_pins gmii_to_rgmii_eth2/clk_25m] [get_bd_pins sys_audio_clkgen/clk_out3]
connect_bd_net -net sys_audio_clkgen_clk_out4 [get_bd_pins gmii_to_rgmii_eth2/clk_125m] [get_bd_pins sys_audio_clkgen/clk_out2] connect_bd_net -net sys_audio_clkgen_clk_out4 [get_bd_pins gmii_to_rgmii_eth2/clk_125m] [get_bd_pins sys_audio_clkgen/clk_out2]

8
projects/motcon2_fmc/zed/system_constr.xdc
View File

@ -136,9 +136,9 @@ create_clock -period 8.000 -name rgmii_rxc1 [get_ports eth1_rgmii_rxc]
create_clock -name eth1_rx_clk_vir -period 8 create_clock -name eth1_rx_clk_vir -period 8
set_property IDELAY_VALUE 18 [get_cells */*/gmii_to_rgmii_eth1/inst/*delay_rgmii_rx_ctl] set_property IDELAY_VALUE 18 [get_cells */*/gmii_to_rgmii_eth1/inst/*delay_rgmii_rx_ctl]
set_property IDELAY_VALUE 18 [get_cells -hier -filter {name =~ *gmii_to_rgmii_eth1*/*delay_rgmii_rxd*}] set_property IDELAY_VALUE 18 [get_cells -hier -filter {name =~ *gmii_to_rgmii_eth1*/*delay_rgmii_rd*}]
set_property IODELAY_GROUP eth_idelay_grp [get_cells */*/gmii_to_rgmii_eth1/inst/*delay_rgmii_rx_ctl] set_property IODELAY_GROUP eth_idelay_grp [get_cells */*/gmii_to_rgmii_eth1/inst/*delay_rgmii_rx_ctl]
set_property IODELAY_GROUP eth_idelay_grp [get_cells -hier -filter {name =~*gmii_to_rgmii_eth1*/*delay_rgmii_rxd*}] set_property IODELAY_GROUP eth_idelay_grp [get_cells -hier -filter {name =~*gmii_to_rgmii_eth1*/*delay_rgmii_rd*}]
set_input_delay -clock [get_clocks eth1_rx_clk_vir] -max -1.2 [get_ports {eth1_rgmii_rd[*] eth1_rgmii_rx_ctl}] set_input_delay -clock [get_clocks eth1_rx_clk_vir] -max -1.2 [get_ports {eth1_rgmii_rd[*] eth1_rgmii_rx_ctl}]
set_input_delay -clock [get_clocks eth1_rx_clk_vir] -min -2.8 [get_ports {eth1_rgmii_rd[*] eth1_rgmii_rx_ctl}] set_input_delay -clock [get_clocks eth1_rx_clk_vir] -min -2.8 [get_ports {eth1_rgmii_rd[*] eth1_rgmii_rx_ctl}]
@ -170,9 +170,9 @@ set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets i_system_wrapper/system_i/gmi
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets i_system_wrapper/system_i/sys_audio_clkgen/inst/clk_out3] set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets i_system_wrapper/system_i/sys_audio_clkgen/inst/clk_out3]
set_property IDELAY_VALUE 18 [get_cells */*/gmii_to_rgmii_eth2/inst/*delay_rgmii_rx_ctl] set_property IDELAY_VALUE 18 [get_cells */*/gmii_to_rgmii_eth2/inst/*delay_rgmii_rx_ctl]
set_property IDELAY_VALUE 18 [get_cells -hier -filter {name =~ *gmii_to_rgmii_eth2*/*delay_rgmii_rxd*}] set_property IDELAY_VALUE 18 [get_cells -hier -filter {name =~ *gmii_to_rgmii_eth2*/*delay_rgmii_rd*}]
set_property IODELAY_GROUP eth_idelay_grp [get_cells */*/gmii_to_rgmii_eth2/inst/*delay_rgmii_rx_ctl] set_property IODELAY_GROUP eth_idelay_grp [get_cells */*/gmii_to_rgmii_eth2/inst/*delay_rgmii_rx_ctl]
set_property IODELAY_GROUP eth_idelay_grp [get_cells -hier -filter {name =~*gmii_to_rgmii_eth2*/*delay_rgmii_rxd*}] set_property IODELAY_GROUP eth_idelay_grp [get_cells -hier -filter {name =~*gmii_to_rgmii_eth2*/*delay_rgmii_rd*}]
set_input_delay -clock [get_clocks eth2_rx_clk_vir] -max -1.2 [get_ports {eth2_rgmii_rd[*] eth2_rgmii_rx_ctl}] set_input_delay -clock [get_clocks eth2_rx_clk_vir] -max -1.2 [get_ports {eth2_rgmii_rd[*] eth2_rgmii_rx_ctl}]
set_input_delay -clock [get_clocks eth2_rx_clk_vir] -min -2.8 [get_ports {eth2_rgmii_rd[*] eth2_rgmii_rx_ctl}] set_input_delay -clock [get_clocks eth2_rx_clk_vir] -min -2.8 [get_ports {eth2_rgmii_rd[*] eth2_rgmii_rx_ctl}]