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make signaltap/timing part of the flow

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Rejeesh Kutty 2014-04-02 10:52:37 -04:00
parent d0a8b4a63c
commit 12e5cc91bd
3 changed files with 11 additions and 14 deletions
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2
projects/fmcjesdadc1/a5gt/system_project.tcl
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@ -9,7 +9,6 @@ set_global_assignment -name DEVICE 5AGTFD7K3F40I5
set_global_assignment -name TOP_LEVEL_ENTITY system_top
set_global_assignment -name SDC_FILE system_constr.sdc
set_global_assignment -name QSYS_FILE system_bd.qsys
set_global_assignment -name QIP_FILE system_adc_mon.qip
set_global_assignment -name VERILOG_FILE $ad_hdl_dir/library/common/altera/ad_jesd_align.v
set_global_assignment -name VERILOG_FILE $ad_hdl_dir/library/common/altera/ad_xcvr_rx_rst.v
set_global_assignment -name VERILOG_FILE ../common/fmcjesdadc1_spi.v
@ -69,6 +68,7 @@ set_global_assignment -name ENABLE_ADVANCED_IO_TIMING ON
set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER ON
set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
set_global_assignment -name TIMEQUEST_REPORT_SCRIPT system_timing.tcl
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
execute_flow -compile

8
projects/fmcjesdadc1/a5gt/system_timing.tcl
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@ -1,11 +1,3 @@
package require ::quartus::flow
project_open fmcjesdadc1_a5gt
execute_module -tool fit
create_timing_netlist
read_sdc system_constr.sdc
update_timing_netlist
report_timing -detail path_only -npaths 20 -file timing_impl.log

15
projects/fmcjesdadc1/a5gt/system_top.v
View File

@ -235,6 +235,16 @@ module system_top (
rx_sysref <= rx_sysref_m2 & ~rx_sysref_m3;
end
sld_signaltap #(
.sld_data_bits (112),
.sld_mem_address_bits (10),
.sld_sample_depth (1024),
.sld_trigger_bits (2))
i_signaltap (
.acq_clk (rx_clk),
.acq_data_in ({rx_sysref, rx_sync, adc1_mon_data_s, adc0_mon_data_s}),
.acq_trigger_in ({rx_sysref, rx_sync}));
genvar n;
generate
for (n = 0; n < 4; n = n + 1) begin: g_align_1
@ -254,11 +264,6 @@ module system_top (
assign rx_xcvr_status_s[ 7: 4] = rx_cdr_locked_s;
assign rx_xcvr_status_s[ 3: 0] = rx_cal_busy_s;
system_adc_mon i_adc_mon (
.acq_clk (rx_clk),
.acq_data_in ({adc1_mon_data_s, adc0_mon_data_s}),
.acq_trigger_in ({adc1_mon_valid_s, adc0_mon_valid_s}));
ad_xcvr_rx_rst #(.NUM_OF_LANES (4)) i_xcvr_rx_rst (
.rx_clk (rx_clk),
.rx_rstn (sys_resetn),