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ccusb_lvds: Initial commit

main
Adrian Costina 2016-10-25 16:32:44 +03:00
parent 5731ba3300
commit 138eeebc9b
7 changed files with 467 additions and 0 deletions
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3
projects/pzsdr/Makefile
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@ -11,6 +11,7 @@ all:
-make -C ccbrk_cmos all -make -C ccbrk_cmos all
-make -C ccfmc all -make -C ccfmc all
-make -C ccpci all -make -C ccpci all
-make -C ccusb_lvds all
-make -C ccbox_lvds all -make -C ccbox_lvds all
-make -C ccbrk all -make -C ccbrk all
-make -C ccbrk_cmos all -make -C ccbrk_cmos all
@ -21,6 +22,7 @@ clean:
make -C ccbrk_cmos clean make -C ccbrk_cmos clean
make -C ccfmc clean make -C ccfmc clean
make -C ccpci clean make -C ccpci clean
make -C ccusb_lvds clean
make -C ccbox_lvds clean make -C ccbox_lvds clean
make -C ccbrk clean make -C ccbrk clean
make -C ccbrk_cmos clean make -C ccbrk_cmos clean
@ -31,6 +33,7 @@ clean-all:
make -C ccbrk_cmos clean-all make -C ccbrk_cmos clean-all
make -C ccfmc clean-all make -C ccfmc clean-all
make -C ccpci clean-all make -C ccpci clean-all
make -C ccusb_lvds clean-all
make -C ccbox_lvds clean-all make -C ccbox_lvds clean-all
make -C ccbrk clean-all make -C ccbrk clean-all
make -C ccbrk_cmos clean-all make -C ccbrk_cmos clean-all

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projects/pzsdr/ccusb_lvds/Makefile Normal file
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@ -0,0 +1,82 @@
####################################################################################
####################################################################################
## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
####################################################################################
M_DEPS += system_top.v
M_DEPS += system_project.tcl
M_DEPS += system_constr.xdc
M_DEPS += system_bd.tcl
M_DEPS += ../common/ccusb_lvds_bd.tcl
M_DEPS += ../../scripts/adi_project.tcl
M_DEPS += ../../scripts/adi_env.tcl
M_DEPS += ../../scripts/adi_board.tcl
M_DEPS += ../../fmcomms2/common/fmcomms2_bd.tcl
M_DEPS += ../../common/xilinx/sys_wfifo.tcl
M_DEPS += ../../common/pzsdr/pzsdr_system_ps7.tcl
M_DEPS += ../../common/pzsdr/pzsdr_system_constr.xdc
M_DEPS += ../../common/pzsdr/pzsdr_system_bd.tcl
M_DEPS += ../../common/pzsdr/pzsdr_lvds_system_constr.xdc
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
M_DEPS += ../../../library/axi_usb_fx3/axi_usb_fx3.xpr
M_DEPS += ../../../library/util_cpack/util_cpack.xpr
M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
M_DEPS += ../../../library/util_upack/util_upack.xpr
M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
M_VIVADO := vivado -mode batch -source
M_FLIST := *.cache
M_FLIST += *.data
M_FLIST += *.xpr
M_FLIST += *.log
M_FLIST += *.jou
M_FLIST += xgui
M_FLIST += *.runs
M_FLIST += *.srcs
M_FLIST += *.sdk
M_FLIST += *.hw
M_FLIST += *.sim
M_FLIST += .Xil
M_FLIST += *.ip_user_files
.PHONY: all lib clean clean-all
all: lib ccusb_lvds_pzsdr.sdk/system_top.hdf
clean:
rm -rf $(M_FLIST)
clean-all:clean
make -C ../../../library/axi_ad9361 clean
make -C ../../../library/axi_dmac clean
make -C ../../../library/axi_usb_fx3 clean
make -C ../../../library/util_cpack clean
make -C ../../../library/util_tdd_sync clean
make -C ../../../library/util_upack clean
make -C ../../../library/util_wfifo clean
ccusb_lvds_pzsdr.sdk/system_top.hdf: $(M_DEPS)
-rm -rf $(M_FLIST)
$(M_VIVADO) system_project.tcl >> ccusb_lvds_pzsdr_vivado.log 2>&1
lib:
make -C ../../../library/axi_ad9361
make -C ../../../library/axi_dmac
make -C ../../../library/axi_usb_fx3
make -C ../../../library/util_cpack
make -C ../../../library/util_tdd_sync
make -C ../../../library/util_upack
make -C ../../../library/util_wfifo
####################################################################################
####################################################################################

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projects/pzsdr/ccusb_lvds/system_bd.tcl Normal file
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source $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_bd.tcl
source ../common/ccusb_lvds_bd.tcl

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projects/pzsdr/ccusb_lvds/system_constr.xdc Normal file
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# USB_FX3
set_property -dict {PACKAGE_PIN J11 IOSTANDARD LVCMOS18} [get_ports data[0]] ; ## IO_L01_34_JX4_P
set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS18} [get_ports data[1]] ; ## IO_L01_34_JX4_N
set_property -dict {PACKAGE_PIN H9 IOSTANDARD LVCMOS18} [get_ports data[2]] ; ## IO_L03_34_JX4_P
set_property -dict {PACKAGE_PIN G9 IOSTANDARD LVCMOS18} [get_ports data[3]] ; ## IO_L03_34_JX4_N
set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVCMOS18} [get_ports data[4]] ; ## IO_L05_34_JX4_P
set_property -dict {PACKAGE_PIN J9 IOSTANDARD LVCMOS18} [get_ports data[5]] ; ## IO_L05_34_JX4_N
set_property -dict {PACKAGE_PIN F5 IOSTANDARD LVCMOS18} [get_ports data[6]] ; ## IO_L07_34_JX4_P
set_property -dict {PACKAGE_PIN E5 IOSTANDARD LVCMOS18} [get_ports data[7]] ; ## IO_L07_34_JX4_N
set_property -dict {PACKAGE_PIN F9 IOSTANDARD LVCMOS18} [get_ports data[8]] ; ## IO_L09_34_JX4_P
set_property -dict {PACKAGE_PIN E8 IOSTANDARD LVCMOS18} [get_ports data[9]] ; ## IO_L09_34_JX4_N
set_property -dict {PACKAGE_PIN F8 IOSTANDARD LVCMOS18} [get_ports data[10]] ; ## IO_L11_SRCC_34_JX4_P
set_property -dict {PACKAGE_PIN E7 IOSTANDARD LVCMOS18} [get_ports data[11]] ; ## IO_L11_SRCC_34_JX4_N
set_property -dict {PACKAGE_PIN C8 IOSTANDARD LVCMOS18} [get_ports data[12]] ; ## IO_L13_MRCC_34_JX4_P
set_property -dict {PACKAGE_PIN C7 IOSTANDARD LVCMOS18} [get_ports data[13]] ; ## IO_L13_MRCC_34_JX4_N
set_property -dict {PACKAGE_PIN C9 IOSTANDARD LVCMOS18} [get_ports data[14]] ; ## IO_L15_34_JX4_P
set_property -dict {PACKAGE_PIN B9 IOSTANDARD LVCMOS18} [get_ports data[15]] ; ## IO_L15_34_JX4_N
set_property -dict {PACKAGE_PIN J8 IOSTANDARD LVCMOS18} [get_ports data[16]] ; ## IO_L06_34_JX4_P
set_property -dict {PACKAGE_PIN H8 IOSTANDARD LVCMOS18} [get_ports data[17]] ; ## IO_L06_34_JX4_N
set_property -dict {PACKAGE_PIN D9 IOSTANDARD LVCMOS18} [get_ports data[18]] ; ## IO_L08_34_JX4_P
set_property -dict {PACKAGE_PIN D8 IOSTANDARD LVCMOS18} [get_ports data[19]] ; ## IO_L08_34_JX4_N
set_property -dict {PACKAGE_PIN E6 IOSTANDARD LVCMOS18} [get_ports data[20]] ; ## IO_L10_34_JX4_P
set_property -dict {PACKAGE_PIN D5 IOSTANDARD LVCMOS18} [get_ports data[21]] ; ## IO_L10_34_JX4_N
set_property -dict {PACKAGE_PIN G7 IOSTANDARD LVCMOS18} [get_ports data[22]] ; ## IO_L12_MRCC_34_JX4_P
set_property -dict {PACKAGE_PIN F7 IOSTANDARD LVCMOS18} [get_ports data[23]] ; ## IO_L12_MRCC_34_JX4_N
set_property -dict {PACKAGE_PIN D6 IOSTANDARD LVCMOS18} [get_ports data[24]] ; ## IO_L14_SRCC_34_JX4_P
set_property -dict {PACKAGE_PIN C6 IOSTANDARD LVCMOS18} [get_ports data[25]] ; ## IO_L14_SRCC_34_JX4_N
set_property -dict {PACKAGE_PIN B10 IOSTANDARD LVCMOS18} [get_ports data[26]] ; ## IO_L16_34_JX4_P
set_property -dict {PACKAGE_PIN A10 IOSTANDARD LVCMOS18} [get_ports data[27]] ; ## IO_L16_34_JX4_N
set_property -dict {PACKAGE_PIN B7 IOSTANDARD LVCMOS18} [get_ports data[28]] ; ## IO_L18_34_JX4_P
set_property -dict {PACKAGE_PIN A7 IOSTANDARD LVCMOS18} [get_ports data[29]] ; ## IO_L18_34_JX4_N
set_property -dict {PACKAGE_PIN B5 IOSTANDARD LVCMOS18} [get_ports data[30]] ; ## IO_L20_34_JX4_P
set_property -dict {PACKAGE_PIN B4 IOSTANDARD LVCMOS18} [get_ports data[31]] ; ## IO_L20_34_JX4_N
set_property -dict {PACKAGE_PIN A9 IOSTANDARD LVCMOS18} [get_ports pclk] ; ## IO_L17_34_JX4_P
set_property -dict {PACKAGE_PIN G6 IOSTANDARD LVCMOS18} [get_ports addr[0]] ; ## IO_L02_34_JX4_P
set_property -dict {PACKAGE_PIN AD18 IOSTANDARD LVCMOS18} [get_ports addr[1]] ; ## IO_L17_13_JX2_P
#set_property -dict {PACKAGE_PIN AD29 IOSTANDARD LVCMOS18} [get_ports addr[2]] ; ## G34 FMC_LPC_LA31_N
#set_property -dict {PACKAGE_PIN AC29 IOSTANDARD LVCMOS18} [get_ports addr[3]] ; ## G33 FMC_LPC_LA31_P
#set_property -dict {PACKAGE_PIN AF25 IOSTANDARD LVCMOS18} [get_ports addr[4]] ; ## G31 FMC_LPC_LA29_N
set_property -dict {PACKAGE_PIN A8 IOSTANDARD LVCMOS18} [get_ports slcs_n] ; ## IO_L17_34_JX4_N
set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS18} [get_ports slwr_n] ; ## IO_L19_34_JX4_P
set_property -dict {PACKAGE_PIN C3 IOSTANDARD LVCMOS18} [get_ports sloe_n] ; ## IO_L19_34_JX4_N
set_property -dict {PACKAGE_PIN B6 IOSTANDARD LVCMOS18} [get_ports slrd_n] ; ## IO_L21_34_JX4_P
set_property -dict {PACKAGE_PIN AD20 IOSTANDARD LVCMOS18} [get_ports pktend_n] ; ## IO_L13_MRCC_13_JX2_P
set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVCMOS18} [get_ports usb_fx3_uart_tx] ; ## IO_L14_SRCC_13_JX2_N
set_property -dict {PACKAGE_PIN AE20 IOSTANDARD LVCMOS18} [get_ports usb_fx3_uart_rx] ; ## IO_L16_13_JX2_P
set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS18} [get_ports fifo_rdy[0]] ; ## IO_L21_34_JX4_N
set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS18} [get_ports fifo_rdy[1]] ; ## IO_L11_SRCC_13_JX2_P
set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS18} [get_ports fifo_rdy[2]] ; ## IO_L11_SRCC_13_JX2_N
set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS18} [get_ports fifo_rdy[3]] ; ## IO_L13_MRCC_13_JX2_N
set_property -dict {PACKAGE_PIN G5 IOSTANDARD LVCMOS18} [get_ports pmode[0]] ; ## IO_L02_34_JX4_N
set_property -dict {PACKAGE_PIN H7 IOSTANDARD LVCMOS18} [get_ports pmode[1]] ; ## IO_L04_34_JX4_P

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projects/pzsdr/ccusb_lvds/system_project.tcl Normal file
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@ -0,0 +1,16 @@
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project_create ccusb_lvds_pzsdr
adi_project_files ccusb_lvds_pzsdr [list \
"system_top.v" \
"system_constr.xdc"\
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
"$ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc" \
"$ad_hdl_dir/projects/common/pzsdr/pzsdr_lvds_system_constr.xdc" ]
adi_project_run ccusb_lvds_pzsdr

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projects/pzsdr/ccusb_lvds/system_top.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
inout [14:0] ddr_addr,
inout [ 2:0] ddr_ba,
inout ddr_cas_n,
inout ddr_ck_n,
inout ddr_ck_p,
inout ddr_cke,
inout ddr_cs_n,
inout [ 3:0] ddr_dm,
inout [31:0] ddr_dq,
inout [ 3:0] ddr_dqs_n,
inout [ 3:0] ddr_dqs_p,
inout ddr_odt,
inout ddr_ras_n,
inout ddr_reset_n,
inout ddr_we_n,
inout fixed_io_ddr_vrn,
inout fixed_io_ddr_vrp,
inout [53:0] fixed_io_mio,
inout fixed_io_ps_clk,
inout fixed_io_ps_porb,
inout fixed_io_ps_srstb,
inout iic_scl,
inout iic_sda,
input rx_clk_in_p,
input rx_clk_in_n,
input rx_frame_in_p,
input rx_frame_in_n,
input [ 5:0] rx_data_in_p,
input [ 5:0] rx_data_in_n,
output tx_clk_out_p,
output tx_clk_out_n,
output tx_frame_out_p,
output tx_frame_out_n,
output [ 5:0] tx_data_out_p,
output [ 5:0] tx_data_out_n,
output enable,
output txnrx,
input clk_out,
inout gpio_clksel,
inout gpio_resetb,
inout gpio_sync,
inout gpio_en_agc,
inout [ 3:0] gpio_ctl,
inout [ 7:0] gpio_status,
input usb_fx3_uart_tx,
output usb_fx3_uart_rx,
input [ 3:0] fifo_rdy,
inout [31:0] data,
output [1:0] addr,
output pclk,
output slcs_n,
output slrd_n,
output sloe_n,
output slwr_n,
output pktend_n,
output [ 1:0] pmode,
output spi_csn,
output spi_clk,
output spi_mosi,
input spi_miso);
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
// assignments
assign pmode = 2'b11;
// instantiations
ad_iobuf #(.DATA_WIDTH(16)) i_iobuf (
.dio_t ({gpio_t[51], gpio_t[46:32]}),
.dio_i ({gpio_o[51], gpio_o[46:32]}),
.dio_o ({gpio_i[51], gpio_i[46:32]}),
.dio_p ({ gpio_clksel, // 51:51
gpio_resetb, // 46:46
gpio_sync, // 45:45
gpio_en_agc, // 44:44
gpio_ctl, // 43:40
gpio_status})); // 39:32
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.enable (enable),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.otg_vbusoc (1'b0),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.ps_intr_15 (1'b0),
.rx_clk_in_n (rx_clk_in_n),
.rx_clk_in_p (rx_clk_in_p),
.rx_data_in_n (rx_data_in_n),
.rx_data_in_p (rx_data_in_p),
.rx_frame_in_n (rx_frame_in_n),
.rx_frame_in_p (rx_frame_in_p),
.spi0_clk_i (1'b0),
.spi0_clk_o (spi_clk),
.spi0_csn_0_o (spi_csn),
.spi0_csn_1_o (),
.spi0_csn_2_o (),
.spi0_csn_i (1'b1),
.spi0_sdi_i (spi_miso),
.spi0_sdo_i (1'b0),
.spi0_sdo_o (spi_mosi),
.spi1_clk_i (1'b0),
.spi1_clk_o (),
.spi1_csn_0_o (),
.spi1_csn_1_o (),
.spi1_csn_2_o (),
.spi1_csn_i (1'b1),
.spi1_sdi_i (1'b0),
.spi1_sdo_i (1'b0),
.spi1_sdo_o (),
.tdd_sync_i (1'b0),
.tdd_sync_o (),
.tdd_sync_t (),
.tx_clk_out_n (tx_clk_out_n),
.tx_clk_out_p (tx_clk_out_p),
.tx_data_out_n (tx_data_out_n),
.tx_data_out_p (tx_data_out_p),
.tx_frame_out_n (tx_frame_out_n),
.tx_frame_out_p (tx_frame_out_p),
.txnrx (txnrx),
.up_enable (gpio_o[47]),
.up_txnrx (gpio_o[48]),
.usb_fx3_uart_tx(usb_fx3_uart_tx),
.usb_fx3_uart_rx(usb_fx3_uart_rx),
.dma_rdy(),
.dma_wmk(),
.fifo_rdy(fifo_rdy),
.pclk(pclk),
.data(data),
.addr(addr),
.slcs_n(slcs_n),
.slrd_n(slrd_n),
.sloe_n(sloe_n),
.slwr_n(slwr_n),
// .epswitch_n(epswitch_n),
.pktend_n(pktend_n)
);
endmodule
// ***************************************************************************
// ***************************************************************************

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projects/pzsdr/common/ccusb_lvds_bd.tcl Normal file
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create_bd_port -dir I usb_fx3_uart_tx
create_bd_port -dir O usb_fx3_uart_rx
create_bd_port -dir I dma_rdy
create_bd_port -dir I dma_wmk
create_bd_port -dir I -from 3 -to 0 fifo_rdy
create_bd_port -dir O pclk
create_bd_port -dir IO -from 31 -to 0 data
create_bd_port -dir O -from 1 -to 0 addr
create_bd_port -dir O slcs_n
create_bd_port -dir O slrd_n
create_bd_port -dir O sloe_n
create_bd_port -dir O slwr_n
create_bd_port -dir O pktend_n
create_bd_port -dir O epswitch_n
set axi_uart [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uart]
set_property -dict [list CONFIG.C_BAUDRATE {115200}] $axi_uart
set axi_usb_fx3 [create_bd_cell -type ip -vlnv analog.com:user:axi_usb_fx3:1.0 axi_usb_fx3]
set axi_usb_fx3_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_usb_fx3_dma]
set_property -dict [list CONFIG.c_sg_include_stscntrl_strm {0}] $axi_usb_fx3_dma
set_property -dict [list CONFIG.c_mm2s_burst_size {256}] $axi_usb_fx3_dma
set_property -dict [list CONFIG.c_s2mm_burst_size {256}] $axi_usb_fx3_dma
set_property -dict [list CONFIG.c_sg_length_width {16}] $axi_usb_fx3_dma
set usb_fx3_rx_axis_fifo [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:1.1 usb_fx3_rx_axis_fifo ]
ad_connect axi_usb_fx3/s_axis axi_usb_fx3_dma/M_AXIS_MM2S
ad_connect sys_cpu_clk usb_fx3_rx_axis_fifo/s_axis_aclk
ad_connect sys_cpu_resetn usb_fx3_rx_axis_fifo/s_axis_aresetn
ad_connect axi_usb_fx3/m_axis usb_fx3_rx_axis_fifo/S_AXIS
ad_connect axi_usb_fx3_dma/S_AXIS_S2MM usb_fx3_rx_axis_fifo/M_AXIS
ad_connect axi_uart/rx usb_fx3_uart_tx
ad_connect axi_uart/tx usb_fx3_uart_rx
ad_connect sys_cpu_clk axi_usb_fx3/s_axi_aclk
ad_connect sys_cpu_resetn axi_usb_fx3/s_axi_aresetn
ad_connect axi_usb_fx3/dma_rdy dma_rdy
ad_connect axi_usb_fx3/dma_wmk dma_wmk
ad_connect axi_usb_fx3/fifo_rdy fifo_rdy
ad_connect axi_usb_fx3/pclk pclk
ad_connect axi_usb_fx3/data data
ad_connect axi_usb_fx3/addr addr
ad_connect axi_usb_fx3/slcs_n slcs_n
ad_connect axi_usb_fx3/slrd_n slrd_n
ad_connect axi_usb_fx3/sloe_n sloe_n
ad_connect axi_usb_fx3/slwr_n slwr_n
ad_connect axi_usb_fx3/pktend_n pktend_n
ad_connect axi_usb_fx3/epswitch_n epswitch_n
ad_cpu_interrupt ps-13 mb-12 axi_usb_fx3/irq
ad_cpu_interrupt ps-12 mb-13 axi_usb_fx3_dma/mm2s_introut
ad_cpu_interrupt ps-11 mb-14 axi_usb_fx3_dma/s2mm_introut
ad_cpu_interrupt ps-10 mb-15 axi_uart/interrupt
ad_cpu_interconnect 0x50000000 axi_usb_fx3
ad_cpu_interconnect 0x40400000 axi_usb_fx3_dma
ad_cpu_interconnect 0x40600000 axi_uart
ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
ad_mem_hp3_interconnect sys_cpu_clk axi_usb_fx3_dma/M_AXI_SG
ad_mem_hp3_interconnect sys_cpu_clk axi_usb_fx3_dma/M_AXI_MM2S
ad_mem_hp3_interconnect sys_cpu_clk axi_usb_fx3_dma/M_AXI_S2MM