zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

library: local constraints

main
Rejeesh Kutty 2014-08-11 16:34:26 -04:00
parent 39bb7ca231
commit 1396a215e5
10 changed files with 79 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
library/axi_ad9144/axi_ad9144_constr.xdc Normal file
View File

@ -0,0 +1,8 @@
set ip_dac_clk [get_clocks -of_objects [get_ports dac_clk]]
set ip_cpu_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
set_false_path -from $ip_dac_clk -to $ip_cpu_clk
set_false_path -from $ip_cpu_clk -to $ip_dac_clk

2
library/axi_ad9144/axi_ad9144_ip.tcl
View File

@ -23,6 +23,8 @@ adi_ip_files axi_ad9144 [list \
"axi_ad9144.v" ]
adi_ip_properties axi_ad9144
adi_ip_constraints axi_ad9144 [list \
"axi_ad9144_constr.xdc" ]
ipx::save_core [ipx::current_core]

8
library/axi_ad9680/axi_ad9680_constr.xdc Normal file
View File

@ -0,0 +1,8 @@
set ip_adc_clk [get_clocks -of_objects [get_ports adc_clk]]
set ip_cpu_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
set_false_path -from $ip_adc_clk -to $ip_cpu_clk
set_false_path -from $ip_cpu_clk -to $ip_adc_clk

2
library/axi_ad9680/axi_ad9680_ip.tcl
View File

@ -22,6 +22,8 @@ adi_ip_files axi_ad9680 [list \
"axi_ad9680.v" ]
adi_ip_properties axi_ad9680
adi_ip_constraints axi_ad9680 [list \
"axi_ad9680_constr.xdc" ]
ipx::save_core [ipx::current_core]

30
library/axi_dmac/axi_dmac_constr.xdc Normal file
View File

@ -0,0 +1,30 @@
set ip_device_wr_clk [get_clocks -of_objects [get_ports fifo_wr_clk]]
set ip_dma_wr_clk [get_clocks -of_objects [get_ports m_dest_axi_aclk]]
set ip_device_rd_clk [get_clocks -of_objects [get_ports fifo_rd_clk]]
set ip_dma_rd_clk [get_clocks -of_objects [get_ports m_src_axi_aclk]]
set ip_cpu_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
set_false_path -from $ip_cpu_clk -to $ip_device_wr_clk
set_false_path -from $ip_cpu_clk -to $ip_dma_wr_clk
set_false_path -from $ip_cpu_clk -to $ip_device_rd_clk
set_false_path -from $ip_cpu_clk -to $ip_dma_rd_clk
set_false_path -from $ip_device_wr_clk -to $ip_cpu_clk
set_false_path -from $ip_device_wr_clk -to $ip_dma_wr_clk
set_false_path -from $ip_device_wr_clk -to $ip_device_rd_clk
set_false_path -from $ip_device_wr_clk -to $ip_dma_rd_clk
set_false_path -from $ip_dma_wr_clk -to $ip_device_wr_clk
set_false_path -from $ip_dma_wr_clk -to $ip_cpu_clk
set_false_path -from $ip_dma_wr_clk -to $ip_device_rd_clk
set_false_path -from $ip_dma_wr_clk -to $ip_dma_rd_clk
set_false_path -from $ip_device_rd_clk -to $ip_device_wr_clk
set_false_path -from $ip_device_rd_clk -to $ip_dma_wr_clk
set_false_path -from $ip_device_rd_clk -to $ip_cpu_clk
set_false_path -from $ip_device_rd_clk -to $ip_dma_rd_clk
set_false_path -from $ip_dma_rd_clk -to $ip_device_wr_clk
set_false_path -from $ip_dma_rd_clk -to $ip_dma_wr_clk
set_false_path -from $ip_dma_rd_clk -to $ip_device_rd_clk
set_false_path -from $ip_dma_rd_clk -to $ip_cpu_clk

2
library/axi_dmac/axi_dmac_ip.tcl
View File

@ -30,6 +30,8 @@ adi_ip_files axi_dmac [list \
"axi_repack.v" ]
adi_ip_properties axi_dmac
adi_ip_constraints axi_dmac [list \
"axi_dmac_constr.xdc" ]
set_property physical_name {s_axi_aclk} [ipx::get_port_map CLK \
[ipx::get_bus_interface s_axi_signal_clock [ipx::current_core]]]

4
library/axi_hdmi_tx/axi_hdmi_tx.v
View File

@ -106,8 +106,8 @@ module axi_hdmi_tx (
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_EMBEDDED_SYNC = 0;
parameter C_S_AXI_MIN_SIZE = 32'hffff;
parameter C_BASEADDR = 32'hffffffff;
parameter C_HIGHADDR = 32'h00000000;
parameter C_HIGHADDR = 32'hffffffff;
parameter C_BASEADDR = 32'h00000000;
localparam XILINX_7SERIES = 0;
localparam XILINX_ULTRASCALE = 1;

13
library/axi_hdmi_tx/axi_hdmi_tx_constr.xdc Normal file
View File

@ -0,0 +1,13 @@
set ip_hdmi_clk [get_clocks -of_objects [get_ports hdmi_clk]]
set ip_dma_clk [get_clocks -of_objects [get_ports m_axis_mm2s_clk]]
set ip_cpu_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
set_false_path -from $ip_hdmi_clk -to $ip_cpu_clk
set_false_path -from $ip_hdmi_clk -to $ip_dma_clk
set_false_path -from $ip_dma_clk -to $ip_hdmi_clk
set_false_path -from $ip_dma_clk -to $ip_cpu_clk
set_false_path -from $ip_cpu_clk -to $ip_hdmi_clk
set_false_path -from $ip_cpu_clk -to $ip_dma_clk

5
library/axi_hdmi_tx/axi_hdmi_tx_ip.tcl
View File

@ -19,9 +19,12 @@ adi_ip_files axi_hdmi_tx [list \
"$ad_hdl_dir/library/common/up_hdmi_tx.v" \
"axi_hdmi_tx_vdma.v" \
"axi_hdmi_tx_core.v" \
"axi_hdmi_tx.v" ]
"axi_hdmi_tx.v" \
"axi_hdmi_tx_constr.xdc" ]
adi_ip_properties axi_hdmi_tx
adi_ip_constraints axi_hdmi_tx [list \
"axi_hdmi_tx_constr.xdc" ]
ipx::save_core [ipx::current_core]

8
library/scripts/adi_ip.tcl
View File

@ -16,6 +16,14 @@ proc adi_ip_files {ip_name ip_files} {
set_property "top" "$ip_name" $proj_fileset
}
proc adi_ip_constraints {ip_name ip_constr_files} {
set proj_filegroup [ipx::get_file_group xilinx_verilogsynthesis [ipx::current_core]]
ipx::add_file $ip_constr_files $proj_filegroup
set_property type {{xdc}} [ipx::get_file $ip_constr_files $proj_filegroup]
set_property library_name {} [ipx::get_file $ip_constr_files $proj_filegroup]
}
proc adi_ip_properties {ip_name} {
ipx::package_project -root_dir .