From 13a35f7a2af1830519aa02c66390155123013efb Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Fri, 16 Sep 2016 14:20:39 +0300 Subject: [PATCH] altera/ad_serdes_clk: The IO_PLL reset is active heigh --- library/altera/alt_serdes/alt_serdes_hw.tcl | 4 ++-- library/altera/common/ad_serdes_clk.v | 5 +++-- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/library/altera/alt_serdes/alt_serdes_hw.tcl b/library/altera/alt_serdes/alt_serdes_hw.tcl index 56fdd9586..3aa7a5374 100644 --- a/library/altera/alt_serdes/alt_serdes_hw.tcl +++ b/library/altera/alt_serdes/alt_serdes_hw.tcl @@ -90,8 +90,8 @@ proc p_alt_serdes {} { add_connection alt_serdes_pll_reconfig.reconfig_to_pll alt_serdes_pll.reconfig_to_pll add_interface drp_clk clock sink set_interface_property drp_clk EXPORT_OF alt_serdes_pll_reconfig.mgmt_clk - add_interface drp_rstn reset sink - set_interface_property drp_rstn EXPORT_OF alt_serdes_pll_reconfig.mgmt_reset + add_interface drp_rst reset sink + set_interface_property drp_rst EXPORT_OF alt_serdes_pll_reconfig.mgmt_reset add_interface pll_reconfig avalon slave set_interface_property pll_reconfig EXPORT_OF alt_serdes_pll_reconfig.mgmt_avalon_slave } diff --git a/library/altera/common/ad_serdes_clk.v b/library/altera/common/ad_serdes_clk.v index 75492f68d..6ba9770e4 100644 --- a/library/altera/common/ad_serdes_clk.v +++ b/library/altera/common/ad_serdes_clk.v @@ -77,13 +77,14 @@ module ad_serdes_clk ( reg up_drp_locked_int = 'd0; // internal signals - + wire up_drp_reset; wire [31:0] up_drp_rdata_int_s; wire up_drp_busy_int_s; wire up_drp_locked_int_s; // defaults + assign up_drp_reset = ~up_rstn; assign out_clk = div_clk; assign up_drp_rdata = up_drp_rdata_int; assign up_drp_ready = up_drp_ready_int; @@ -144,7 +145,7 @@ module ad_serdes_clk ( .loaden_loaden (loaden), .ls_clk_clk (div_clk), .drp_clk_clk (up_clk), - .drp_rstn_reset (up_rstn), + .drp_rst_reset (up_drp_reset), .pll_reconfig_waitrequest (up_drp_busy_int_s), .pll_reconfig_read (up_drp_rd_int), .pll_reconfig_write (up_drp_wr_int),