From 14e23b106c2c5210ca1eeff47cf8485ba57eb610 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Fri, 8 May 2015 17:43:10 +0300 Subject: [PATCH] axi_ad9361: changed device interface module for Altera to have the same inputs as the one for Xilinx --- library/axi_ad9361/axi_ad9361_dev_if_alt.v | 2 ++ 1 file changed, 2 insertions(+) diff --git a/library/axi_ad9361/axi_ad9361_dev_if_alt.v b/library/axi_ad9361/axi_ad9361_dev_if_alt.v index 9e8b66c11..6c1516caf 100644 --- a/library/axi_ad9361/axi_ad9361_dev_if_alt.v +++ b/library/axi_ad9361/axi_ad9361_dev_if_alt.v @@ -73,6 +73,7 @@ module axi_ad9361_dev_if ( adc_data, adc_status, adc_r1_mode, + adc_ddr_edgesel, // transmit data path interface @@ -134,6 +135,7 @@ module axi_ad9361_dev_if ( output [47:0] adc_data; output adc_status; input adc_r1_mode; + input adc_ddr_edgesel; // transmit data path interface