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axi_ad9361: changed device interface module for Altera to have the same inputs as the one for Xilinx

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Adrian Costina 2015-05-08 17:43:10 +03:00
parent 91279253ef
commit 14e23b106c
1 changed files with 2 additions and 0 deletions
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library/axi_ad9361/axi_ad9361_dev_if_alt.v
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@ -73,6 +73,7 @@ module axi_ad9361_dev_if (
adc_data, adc_data,
adc_status, adc_status,
adc_r1_mode, adc_r1_mode,
adc_ddr_edgesel,
// transmit data path interface // transmit data path interface
@ -134,6 +135,7 @@ module axi_ad9361_dev_if (
output [47:0] adc_data; output [47:0] adc_data;
output adc_status; output adc_status;
input adc_r1_mode; input adc_r1_mode;
input adc_ddr_edgesel;
// transmit data path interface // transmit data path interface