diff --git a/library/axi_dmac/axi_dmac_constr.ttcl b/library/axi_dmac/axi_dmac_constr.ttcl
index d90bf4982..a0c03bbd1 100644
--- a/library/axi_dmac/axi_dmac_constr.ttcl
+++ b/library/axi_dmac/axi_dmac_constr.ttcl
@@ -8,9 +8,27 @@
 <: set async_src_dest [getBooleanValue "ASYNC_CLK_SRC_DEST"] :>
 <: set disable_debug_registers [getBooleanValue "DISABLE_DEBUG_REGISTERS"] :>
 
-set req_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
-set src_clk [get_clocks -of_objects [get_ports -quiet {fifo_wr_clk s_axis_aclk m_src_axi_aclk}]]
-set dest_clk [get_clocks -of_objects [get_ports -quiet {fifo_rd_clk m_axis_aclk m_dest_axi_aclk}]]
+set req_clk_ports_base {s_axi_aclk}
+set src_clk_ports_base {fifo_wr_clk s_axis_aclk m_src_axi_aclk}
+set dest_clk_ports_base {fifo_rd_clk m_axis_aclk m_dest_axi_aclk}
+set req_clk_ports $req_clk_ports_base
+set src_clk_ports $src_clk_ports_base
+set dest_clk_ports $dest_clk_ports_base
+<: if {[expr {!$async_req_src}]} { :>
+set req_clk_ports "$req_clk_ports $src_clk_ports_base"
+set src_clk_ports "$src_clk_ports $req_clk_ports_base"
+<: } :>
+<: if {[expr {!$async_src_dest}]} { :>
+set src_clk_ports "$src_clk_ports $dest_clk_ports_base"
+set dest_clk_ports "$dest_clk_ports $src_clk_ports_base"
+<: } :>
+<: if {[expr {!$async_dest_req}]} { :>
+set req_clk_ports "$req_clk_ports $dest_clk_ports_base"
+set dest_clk_ports "$dest_clk_ports $req_clk_ports_base"
+<: } :>
+set req_clk [get_clocks -of_objects [get_ports -quiet $req_clk_ports]]
+set src_clk [get_clocks -of_objects [get_ports -quiet $src_clk_ports]]
+set dest_clk [get_clocks -of_objects [get_ports -quiet $dest_clk_ports]]
 
 <: if {$async_req_src || $async_src_dest || $async_dest_req} { :>
 set_property ASYNC_REG TRUE \
diff --git a/library/axi_dmac/request_arb.v b/library/axi_dmac/request_arb.v
index c0eb6d40c..06a4091bc 100644
--- a/library/axi_dmac/request_arb.v
+++ b/library/axi_dmac/request_arb.v
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
+// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -309,7 +309,6 @@ module request_arb #(
   wire [ID_WIDTH+3-1:0] rewind_req_data;
 
   reg src_throttler_enabled = 1'b1;
-  wire src_throttler_enable;
   wire rewind_state;
 
   /* Unused for now
@@ -772,6 +771,26 @@ module request_arb #(
     .m_axis_level(),
     .m_axis_empty());
 
+  wire src_throttler_enable;
+
+  sync_event #(
+    .ASYNC_CLK(ASYNC_CLK_REQ_SRC)
+  ) sync_rewind (
+    .in_clk(req_clk),
+    .in_event(rewind_state),
+    .out_clk(src_clk),
+    .out_event(src_throttler_enable));
+
+  always @(posedge src_clk) begin
+    if (src_resetn == 1'b0) begin
+      src_throttler_enabled <= 'b1;
+    end else if (rewind_req_valid) begin
+      src_throttler_enabled <= 'b0;
+    end else if (src_throttler_enable) begin
+      src_throttler_enabled <= 'b1;
+    end
+  end
+
   end else begin
 
   assign s_axis_ready = 1'b0;
@@ -878,24 +897,6 @@ module request_arb #(
     end
   endfunction
 
-  sync_event #(
-    .ASYNC_CLK(ASYNC_CLK_REQ_SRC)
-  ) sync_rewind (
-    .in_clk(req_clk),
-    .in_event(rewind_state),
-    .out_clk(src_clk),
-    .out_event(src_throttler_enable));
-
-  always @(posedge src_clk) begin
-    if (src_resetn == 1'b0) begin
-      src_throttler_enabled <= 'b1;
-    end else if (rewind_req_valid) begin
-      src_throttler_enabled <= 'b0;
-    end else if (src_throttler_enable) begin
-      src_throttler_enabled <= 'b1;
-    end
-  end
-
   /*
    * Make sure that we do not request more data than what fits into the
    * store-and-forward burst memory.